Integrated assembly

Abstract

This application relates to an integrated assembly. Some embodiments include an integrated assembly having a first word line and a second word line coupled to a driver circuit. The first word line has a first end remote from the driver circuit, and the second word line has a second end remote from the driver circuit. A switch is adjacent to the first end and is configured to couple the first end to one or both of the second end and a low voltage reference source (e.g., VNWL power supply) during a transition of the first word line from an "on" state to an "off" state.

Description

Technical Field

[0001] A memory array (e.g., a DRAM array). The integrated assembly includes vertically stacked levels. Background Art

[0002] Memory is utilized in modern computing architectures to store data. One type of memory is dynamic random access memory (DRAM). Compared to alternative types of memory, DRAM can offer advantages of simple structure, low cost, and high speed.

[0003] DRAM can utilize memory cells that have a capacitor and a transistor (so-called 1T-1C memory cells), where the capacitor is coupled to the source / drain region of the transistor. An example 1T-1C memory cell 2 is shown in FIG. 1, where the transistor is labeled T and the capacitor is labeled C. The capacitor has a node coupled to the source / drain region of the transistor and has another node coupled to a common plate CP. The common plate can be coupled to any suitable voltage, such as a voltage in the range from greater than or equal to ground to less than or equal to VCC (i.e., ground ≤ CP ≤ VCC). In some applications, the common plate is at a voltage of approximately one-half VCC (i.e., approximately VCC / 2). The transistor has a gate coupled to a word line WL (i.e., an access line, a routing line, a first linear structure, etc.) and has a source / drain region coupled to a bit line BL (i.e., a digital line, a sense line, a second linear structure, etc.). In operation, an electric field generated by a voltage along the word line can selectively couple the bit line to the capacitor during a read / write operation.

[0004] Another prior art 1T-1C memory cell configuration is shown in FIG. 2. The configuration of FIG. 2 shows two memory cells 2a and 2b; where memory cell 2a includes transistor T1 and capacitor C1, and memory cell 2b includes transistor T2 and capacitor C2. Word lines WL0 and WL1 are electrically coupled to the gates of transistors T1 and T2, respectively. The connection to bit line BL is shared by memory cells 2a and 2b.

[0005] The memory cells described above can be incorporated into a memory array, and in some applications the memory array can have an open bit line arrangement. An example integrated assembly 9 with an open bit line architecture is shown in FIG. 3. Assembly 9 includes two laterally adjacent memory arrays ("Array-1" and "Array-2"), each of which contains memory cells of the type described in FIG. 2 (not labeled in FIG. 3 to simplify the drawing). Word lines WL0-WL7 extend across the arrays and are coupled to a word line driver. Digital lines D0-D8 are associated with the first array (Array-1), and digital lines D0*-D8* are associated with the second array (Array-2). Sense amplifiers SA0-SA8 are provided between the first and second arrays. Digital lines at the same height are paired with each other and compared via a sense amplifier (e.g., digital line D0 and D0* are paired with each other and compared with sense amplifier SA0). In a read operation, one of the paired digital lines can act as a reference for determining the electrical characteristics (e.g., voltage) of the other of the paired digital lines.

[0006] An ongoing goal in integrated circuit fabrication is to increase the packaging density and thus the level of integration. There is a need to develop a three-dimensional arrangement of memories with a tight packaging. Another ongoing goal is to read / write quickly from / to the memory cells of a memory array. A limitation on the speed of the read / write operation can be the speed at which a word line can transition from "on" to "off". Summary of the Invention

[0007] In one aspect, the present application provides an integrated assembly, comprising: a first word line coupled to a driver circuit and having a first end remote from the driver circuit; a second word line coupled to the driver circuit and having a second end remote from the driver circuit; and a switch adjacent to the first end and configured to couple the first end to one or both of the second end and a low voltage reference source during a transition of the first word line from an "on" state to an "off" state.

[0008] In another aspect, the present application further provides an integrated assembly, comprising: a first word line coupled to a first sub-driver circuit and having a first end remote from the first sub-driver circuit; a second word line coupled to a second sub-driver circuit and having a second end remote from the second sub-driver circuit; the second word line being vertically offset relative to the first word line; the first sub-driver circuit and the second sub-driver circuit being vertically offset relative to the first word line and the second word line; a first switch adjacent to the first end and configured to couple the first end to a low voltage reference source during a transition of the first word line from an "on" state to an "off" state; and a second switch adjacent to the second end and configured to couple the second end to the low voltage reference source during a transition of the second word line from an "on" state to an "off" state.

[0009] In yet another aspect, the present application further provides an integrated assembly, comprising: a substrate including a control circuit, a first sub-driver circuit, and a second sub-driver circuit; a first layer above the substrate; the first layer including a first portion of a first array of first memory cells and including a first portion of a second array of second memory cells; a second layer above the first layer; the second layer including a second portion of the first array of first memory cells and including a second portion of the second array of second memory cells; a first word line associated with the first array, the first word line having a first end proximate to the first sub-driver circuit and having a second end remote from the first sub-driver circuit and along the first layer; a second word line associated with the first array, the second word line having a third end proximate to the second sub-driver circuit and having a fourth end remote from the second sub-driver circuit and along the second layer; and a transistor adjacent to one of the second end and the fourth end and configured to couple one of the second end and the fourth end to a low voltage reference source and one or both of the other of the second end and the fourth end during a transition of one of the first word line and the second word line from an "on" state to an "off" state; the transistor including a vertically extending channel region and a gate operatively proximate to the channel region; the gate being coupled to the control circuit. Description of the Drawings

[0010] FIG. 1 is a schematic diagram of a prior art memory cell having one transistor and one capacitor.

[0011] FIG. 2 is a schematic diagram of a pair of prior art memory cells each having one transistor and one capacitor and sharing a bit line connection.

[0012] FIG. 3 is a schematic diagram of a prior art integrated assembly having an open bit line architecture.

[0013] Figure 4 is a schematic diagram of an example integrated assembly having multiple levels vertically shifted relative to each other.

[0014] Figure 5A and 5B is a schematic operational view of an example layout including a pair of word lines within an arrangement of vertically stacked levels.

[0015] Figure 6 is a schematic side view of an example layout including a pair of word lines within an arrangement of vertically stacked levels.

[0016] Figure 7 is a schematic side view of an example multi-level assembly showing an example arrangement of example circuit components. The example circuit components include memory cells. Figure 7A is Figure 7 a schematic side view of one of the example memory cells.

[0017] Figure 8 is a diagram of an example layout including a number of word lines.

[0018] Figure 8A is a diagram of an example layout including a word line.

[0019] Figure 9 is a schematic side view of an example multi-level assembly showing an example arrangement of example circuit components.

[0020] Figure 10 is a schematic side view of an example multi-level assembly showing an example arrangement of example circuit components. DETAILED DESCRIPTION

[0021] Some embodiments include an integrated assembly that includes word lines having ends selectively shunted to a low voltage. Such configurations can rapidly transition from an “on” mode to an “off” mode. Refer to Figures 4 - 10 for a description of example embodiments.

[0022] Refer to Figure 4 , the integrated assembly 10 includes a substrate 12, a first level 14 above the substrate, and a second level 16 above the first level. Structures 12, 14, and 16 are vertically stacked with respect to each other. Substrate 12, first level 14, and second level 16 can be regarded as examples of tiers stacked with respect to each other. The tiers can be within different semiconductor dies, or at least two of the tiers can be within the same semiconductor die.

[0023] The first layer 14 and the second layer 16 each have a memory region 18 and 22 respectively. The first memory array and the second memory array (arrays - 1 and - 2 similar to those shown in FIG. 3) are supported by the first layer 14 and the second layer 16, where each of the memory arrays has a first portion along the first (lower) layer 14 and a second portion along the second (upper) layer 16. The first memory array includes first memory cells 20a, and the second memory array includes second memory cells 20b. The memory cells are schematically illustrated as circular. The first and second memory arrays may include any suitable number of memory cells, and in some embodiments, may include hundreds, thousands, millions, etc. of memory cells. The memory cells may be DRAM cells, and in some embodiments, the memory cells may be configured in an arrangement of the type described above with reference to the prior art FIGS. 1 - 3 (i.e., arrays - 1 and - 2 may be DRAM arrays).

[0024] In some embodiments, the first layer 14 and the second layer 16 may be referred to as the first memory layer and the second memory layer respectively.

[0025] The substrate 12 may include semiconductor material; and may include, for example, single - crystal silicon, consist essentially of single - crystal silicon, or be composed of single - crystal silicon. The substrate 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any structure that includes semiconductor material, including but not limited to bulk semiconductor material, such as a semiconductor wafer (alone or in a combination including other materials), and a layer of semiconductor material (alone or in a combination including other materials). The term "substrate" refers to any support structure, including but not limited to the semiconductor substrates described above. In some applications, the substrate 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc. Each of the layers 14 and 16 may also include semiconductor material.

[0026] In the illustrated embodiment, the substrate 12 includes a sense amplifier circuit (SA) and a word line driver circuit (WD).

[0027] The sense amplifier circuit includes a region labeled "SA - E" to identify it as associated with the "even" part of the circuit, and a region labeled "SA - O" to identify it as associated with the "odd" part of the circuit. The terms "even" and "odd" are arbitrary and are used to distinguish different sense amplifier circuits. The illustrated configuration has sense amplifier circuits SA - O and SA - E that are paired with each other and distributed as structures (blocks) 24.

[0028] The word line driver circuit (i.e., the row driver circuit) includes a region 31 labeled SWD-L and a region 33 labeled SWD-U. The acronym SWD stands for sub-word line driver and is used to emphasize that components SWD-L and SWD-U are part of a common word line driver circuit. In other words, components SWD-L and SWD-U can be regarded as sub-drivers (or sub-driver circuits) relative to the common word line driver circuit. In the illustrated embodiment, the sub-driver circuit SWD-L is utilized during the operation of memory cells associated with the lower level 14, and the sub-driver circuit SWD-U is utilized during the operation of memory cells associated with the upper level 16.

[0029] The illustrated configuration has sub-driver circuits SWD-L and SWD-U that are paired with each other and distributed as a structure (block) 30. In some embodiments, one of the sub-driver circuits SWD-L and SWD-U may be referred to as the first sub-driver circuit, and the other may be referred to as the second sub-driver circuit.

[0030] Blocks 24 and 30 can be regarded as forming a patch area. The patch area can be regarded as together forming a quilting arrangement of circuit sub-units along the substrate 12.

[0031] The first digital lines D0, D1, and D2 are associated with a first memory array (Array-1). The first digital lines D0, D1, and D2 extend along the first memory array (Array-1) and are coupled to first memory cells 20a of the first memory array. The digital lines D0, D1, and D2 are laterally spaced apart from each other and may represent a number of substantially identical digital lines extending across the first memory array; where the term "substantially identical" means identical within reasonable tolerances of manufacturing and measurement. The first digital lines alternate between even first digital lines and odd first digital lines, where digital lines D0 and D2 represent even first digital lines, and digital line D1 represents an odd first digital line. The even first digital lines (e.g., D0) are coupled to a first sense amplifier circuit 26 (i.e., SA-E), and the odd first digital lines (e.g., D1) are coupled to a second sense amplifier circuit 28 (i.e., SA-O). The first digital lines D0, D1, and D2 have a first portion along the first level 14 and a second portion along the second level 16.

[0032] The second digital lines D0*, D1*, and D2* are associated with a second memory array (Array-2). The second digital lines D0*, D1*, and D2* extend along the second memory array and are coupled to second memory cells 20b of the second memory array (Array-2). The digital lines D0*, D1*, and D2* are laterally spaced apart from each other and may represent a plurality of substantially identical digital lines extending across the second memory array. The second digital lines alternate between even second digital lines and odd second digital lines, where the digital lines D0* and D2* represent even second digital lines, and the digital line D1* represents an odd second digital line. The even second digital lines (e.g., D0*) are coupled to a first sense amplifier circuit 26 (i.e., SA-E), and the odd second digital lines (e.g., D1*) are coupled to a second sense amplifier circuit 28 (i.e., SA-O). The second digital lines D0*, D1*, and D2* have a first portion along the first level 14 and a second portion along the second level 16.

[0033] The even first digital lines D0 and D2 are comparably coupled to the even second digital lines D0* and D2* via a first sense amplifier circuit 26 (SA-E); and the odd first digital line D1 is comparably coupled to the odd second digital line D1* via a second sense amplifier circuit 28 (SA-O). For purposes of understanding the present disclosure and the following claims, a first digital line is "comparably coupled" to a second digital line via a sense amplifier circuit if the sense amplifier circuit is configured to compare the electrical characteristics (e.g., voltage) of the first digital line and the second digital line to each other.

[0034] Two digital lines comparably coupled to each other via a sense amplifier circuit may be considered complementary to each other. For example, the digital lines D0 and D0* are complementary to each other, as are the digital lines D1 and D1*. In some embodiments, complementary digital lines may be considered to form complementary digital line pairs. Thus, the digital lines D0 and D0* may be considered to form a first complementary pair, and the digital lines D1 and D1* may be considered to form a second complementary pair.

[0035] In Figure 4 the illustrated embodiment, the digital lines D0, D0*, D1, D1*, D2, and D2* are all vertically shifted with respect to the first sense amplifier circuit SA-E and the second sense amplifier circuit SA-O. Also, the digital lines D0, D0*, D1, D1*, D2, and D2* are all laterally shifted with respect to each other.

[0036] In some embodiments, the digital lines along the first memory array (Array-1) may be referred to as a first set of digital lines, and the digital lines along the second memory (Array-2) may be referred to as a second set of digital lines. The digital lines are also identified by the general reference numeral 23.

[0037] Still referring toFigure 4 The word line 32 extends along a first memory array and a second memory array (Array-1 and Array-2).

[0038] Each of the first memory cells 20a in the first memory array (Array-1) is uniquely addressed by one of the digit lines (e.g., one of digit lines D0, D1, and D2) extending along the first memory array and one of the word lines 32. Similarly, each of the memory cells 20b in the second memory array (Array-2) is uniquely addressed by one of the digit lines (e.g., one of digit lines D0*, D1*, and D2*) extending along the second memory array and one of the word lines 32.

[0039] Figure 4 The advantage of this configuration is that all sense amplifier circuits and all word line driver circuits are disposed directly below the memory arrays (Array-1 and Array-2), which enables a tight packaging of the memory arrays across the semiconductor substrate; or in other words, compared to a configuration in which at least some of the sense amplifier circuits and / or at least some of the word line driver circuits are not directly below the memory arrays, this can save valuable semiconductor footprint area. The vertical stacking of regions of the memory arrays (Array-1 and Array-2) can further save valuable semiconductor footprint area.

[0040] Some embodiments include methods for increasing the rate (speed) for transitioning a word line from an “on” state to an “off” state. The word line can be considered to include a first end proximate to a sub-driver circuit and a second end remote from the first end. The example embodiments described herein can include coupling the second end of the word line to one or more low voltage sources (power supplies) during the switching of the word line from an “on” state to an “off” state, which can generally improve the speed of word line switching compared to conventional methods in which the ends of the word line are electrically floating. The low voltage source can include, for example, a low voltage reference source (e.g., a source at a negative word line voltage VNWL), a word line that is already in an “off” state, etc. Figure 4 An example orientation of shows the distal ends of two of the word lines selectively coupled to VNWL via switches 40. Only two of the word lines are shown as having distal ends selectively coupled to VNWL to simplify the drawing. In practice, the distal ends of all word lines can be coupled to VNWL (and / or to other suitable low voltage sources).

[0041] Reference Figures 5A - 10 describes an example assembly having distal ends of word lines coupled to one or more suitable low voltage sources.

[0042] Reference Figure 5A and 5B , which schematically illustrates a multi-level assembly 50. The multi-level assembly includes a substrate 12, similar to that referred to above with referenceFigure 4 The first layer 14 and the second layer 16 of those described layers. The sub-driver circuits SWD-L 31 and SWD-U 33 are associated with the substrate 12, and the low voltage reference source 52 is also associated with the substrate 12. In the illustrated embodiment, the low voltage reference source 52 corresponds to VNWL, but in other embodiments, it may correspond to another suitable voltage level (power supply). In some embodiments, the word lines of the memory array may have an on voltage that is higher than the threshold voltage of the access devices (e.g., transistors) adjacent to the word lines, and may have an off voltage that is lower than the threshold voltage of the access devices. The low voltage reference source may be at a voltage level that is less than or equal to the off-state voltage of the word lines. For example, VNWL may be less than or equal to about -0.3 volts (V).

[0043] The assembly 50 includes a pair of word lines 32, where the word lines are labeled 32a and 32b such that they can be distinguished from each other. The word line 32a has a proximal end 51a coupled to the sub-driver circuit SWD-L, and has a distal end 53a adjacent to the switch 40a. The word line 32b has a proximal end 51b coupled to the sub-driver circuit SWD-U, and has a distal end 53b adjacent to the switch 40b. The word lines 32a and 32b extend along the first layer 14 and the second layer 16, respectively. In some embodiments, one of the word lines 32a and 32b may be referred to as the first word line, and the other may be referred to as the second word line. In some embodiments, the word line 32a may be referred to as the lower word line, and the word line 32b may be referred to as the upper word line.

[0044] Figure 5A An operation phase is shown in which the upper word line 32b is in the on operation state (mode), and Figure 5B An operation phase is shown in which the upper word line 32b transitions from the on operation state (mode) to the off operation state (mode). The switch 40b is open at the Figure 5A operation phase such that the word line 32b is normally used to access the memory cells. However, the switch 40b is closed at the Figure 5B operation phase such that the low voltage reference source 52 is coupled to the distal end 53b of the word line 32b. Such coupling of the word line to the low voltage reference source 52 can substantially increase the rate of transition of the word line 32b from the on mode to the off mode as compared to a conventional configuration lacking a connection of the distal end to the low voltage reference source 52.

[0045] The switch 40a associated with the lower word line 32a may operate similarly to the switch 40b associated with the upper word line 32b, and specifically, may be operable to couple the distal end 53a of the word line 32a to the low voltage reference source 52 during the transition of the word line 32a from the on mode to the off mode.

[0046] The switches 40a and 40b can have any suitable configuration. In some embodiments, such switches can correspond to transistors. Figure 6 shown in a configuration where switches 40a and 40b correspond to transistors 56a and 56b, respectively Figure 5A and 5B assembly 50.

[0047] Each of the transistors 56 has a first source / drain region 54 coupled to the distal end 53 of the associated word line, and has a second source / drain region 58 coupled to the low voltage reference source 52. The transistor 56 also includes a gate 60 configured to selectively couple the source / drain regions 54 and 58 to each other. The gate 60 is coupled to the control circuit 62. The control circuit can be configured to selectively turn on the selected transistor and thereby couple the distal end 53 of one of the word lines 32 to the low voltage reference source 52, or turn off the selected transistor and thereby decouple the distal end from the low voltage reference source 52.

[0048] Figure 7 A more detailed view of an example arrangement of the word lines 32a and 32b and the control transistors 56a and 56b within the assembly 50 is provided. An example memory cell 20a of Array-1 is shown along the heights corresponding to levels 14 and 16. Each of the memory cells 20a is uniquely addressed by a digit line 23 and a word line 32a or 32b. The word lines are shown in a dashed (dotted) view to indicate their out-of-plane in the Figure 7 cross-sectional plane.

[0049] Levels 14 and 16 can each include portions of a first memory cell array (Array-1) and a second memory cell (Array-2), as described above with reference to Figure 4 described. Figure 7 Only a portion of the first memory cell array (Array-1) is shown to simplify the drawing, but it should be understood that the second memory cell array (Array-2) can be modified similar to the Figure 7 modifications described in; and in this regard, it can also be modified similar to the modifications described below with reference to Figures 8 - 10 described.

[0050] The illustrated embodiment includes sub-driver circuits 31 and 33 (SWD-L and SWD-U), a low voltage reference source 52 (VNWL), and a control circuit 62. The circuits 31, 33, 52, and 62 can be supported by a substrate 12 and can be below the first level 14 and the second level 16.

[0051] In Figure 7AThe enlarged view in [reference] shows an example memory cell 20 to simplify the labeling of the components of the memory cell. The memory cell 20 includes a transistor T coupled to a capacitor C. The transistor T includes a vertically extending pillar 70 of a semiconductor material 72. The semiconductor material 72 can include any suitable composition; and in some embodiments can include, consist essentially of, or consist of one or more of: silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; where the term III / V semiconductor material refers to a semiconductor material that includes elements selected from Group III and Group V of the periodic table (where Group III and Group V are the old nomenclature and are now referred to as Group 13 and Group 15).

[0052] A gate dielectric material (insulating material) 74 is adjacent to the sidewalls of the pillar 70, and a conductive gate material 76 is adjacent to the gate dielectric material.

[0053] The gate dielectric material 74 can include any suitable composition, and in some embodiments, can include, consist essentially of, or consist of silicon dioxide.

[0054] The conductive gate material 76 can include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0055] The conductive gate material 76 forms the transistor gate of the transistor T. The transistor includes a first source / drain region 86 in the upper region of the pillar 70, a second source / drain region 88 in the lower region of the pillar 70, and a channel region 90 between the first source / drain region 86 and the second source / drain region 88. In operation, an electric field generated by a voltage in the gate material 76 (i.e., the voltage along the Figure 7A word line 32 as illustrated in [reference]) can couple the source / drain regions 86 and 88 to each other in a gated manner through the channel region 90. When the term "gated coupling" is used herein, this can refer to the controlled coupling / de-coupling of the source / drain regions of a transistor that can be caused by the electrical activation / de-activation of the gate of the transistor.

[0056] The capacitor C includes a first conductive node 78, a second conductive node 80, and an insulating material (capacitor dielectric material) 82 between the first conductive node and the second conductive node.

[0057] The first conductive node 78 and the second conductive node 80 may comprise any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). The first conductive node and the second conductive node may comprise the same composition as each other, or may comprise different compositions relative to each other.

[0058] The insulating material 82 may comprise any suitable composition and, in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide.

[0059] In the illustrated embodiment, the lower conductive node 78 is configured as an upwardly open container. In other embodiments, the lower conductive node may have another suitable shape.

[0060] The lower conductive node 78 may be referred to as a storage node, and the upper conductive node 80 may be referred to as a plate electrode. In some embodiments, the plate electrodes may all be coupled to each other, as Figure 7 shown.

[0061] Capacitor C is an example storage element coupled to transistor T. In other embodiments, other suitable storage elements may be utilized in place of capacitor C. A suitable storage element may be a device having at least two detectable states; and in some embodiments, a suitable storage element may be, for example, a resistive memory device, a conductive bridging device, a phase change memory (PCM) device, a programmable metallization cell (PMC), etc.

[0062] Referring Figure 7 to, one of word lines 32a and 32b may be referred to as a first word line, and the other may be referred to as a second word line. Word lines 32a and 32b have ends 51a and 51b proximate to driver circuit 64, where this driver is shown to include first sub-driver circuit 31 and second sub-driver circuit 33.

[0063] In some embodiments, one of word lines 32a and 32b may be considered to have a first end remote from driver circuit 64, and the other of the word lines may be considered to have a second end remote from driver circuit 64. For example, in some embodiments, end 53a may be referred to as a first distal end, and end 53b may be referred to as a second distal end.

[0064] In some embodiments, the ends 51a, 51b, 53a, and 53b may be referred to as a first end, a second end, a third end, and a fourth end to distinguish them from each other. For example, the ends 51a and 53a may be referred to as the first end and the second end, and the ends 51b and 53b may be referred to as the third end and the fourth end.

[0065] The transistors 56a and 56b are example switches 40a and 40b that are adjacent to the distal ends 53a and 53b and are configured to selectively couple such distal ends to the low voltage reference source 52 during a transition of the associated word line from an on state to an off state.

[0066] The illustrated transistors 56a and 56b are similar to the transistor T referenced above Figure 7A described. Specifically, the transistors have vertically extending pillars 92 of semiconductor material 94. The semiconductor material pillars 92 may each include an upper source / drain region 58 and a lower source / drain region 54, and a channel region 95 vertically between the source / drain region 58 and the source / drain region 54. The transistors 56a and 56b have a gate dielectric material 96 adjacent to the channel region 95 and have a conductive gate material 98 adjacent to the gate dielectric material 96. The conductive gate material 98 is coupled to the control circuit 62. An electric field generated by the control circuit 62 within the gate material 98 (i.e., within the transistor gate) may selectively couple the source / drain region 54 and the drain region 58 to each other through the channel region 95.

[0067] In some embodiments, one of the transistors 56a and 56b may be referred to as a first transistor (or more generally, a first switch), and the other may be referred to as a second transistor (or more generally, a second switch). The transistor 56 may be configured identically to Figure 7A the transistor T (i.e., the transistor associated with the memory cell 20). Thus, the transistor 56 may be fabricated simultaneously and using the same process steps and materials as the transistors associated with the memory cells 20a and 20b.

[0068] In the illustrated embodiment, the conductive interconnects 97 and 99 are adjacent to the source / drain regions 58 and 54 and electrically couple such source / drain regions to the low voltage reference source 52 and the distal end 53, respectively. The conductive interconnects 97 and 99 may include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0069] In the illustrated embodiments, the word lines 32a and 32b are vertically offset relative to each other and vertically offset relative to the circuits 52, 62, and 64.

[0070] In operation, when an individual word line transitions from an on operating state to an off operating state, the transistors 56a and 56b can be used to couple the distal ends 53a and 53b of the word lines 32a and 32b to the low voltage reference source 52. Arrows 66a and 66b are provided to schematically illustrate the discharge facilitated by the transistors 56a and 56b during the transition of an adjacent word line 32a or 32b from an on operating state to an off operating state. The transistors 56a and 56b are configured to operate independently of each other such that the discharge 66a can be controlled independently relative to the discharge 66b.

[0071] In some embodiments, the word lines along each of the levels 14 and 16 can be arranged as a series of parallel word lines extending in a first direction. For example, Figure 8 schematically illustrates the word line 32 along one of the levels 14 and 16 and shows such word lines extending in a first direction corresponding to the illustrated x-axis direction.

[0072] The transistor 56 is along the distal end 53 of the word line 32 and is arranged as a series of transistors. Each of the transistors within such series is provided to be electrically between the distal end 53 of the word line 32 and the low voltage reference source 52.

[0073] The transistor 56 has a gate 60 coupled to the control circuit 62. A wire 91 extends along the gate 60 and is used to electrically couple the gate to the control circuit 62. The wire 91 is shown extending in a second direction (the illustrated y-axis direction) that is generally orthogonal to the first direction of the word line 32. The term "generally orthogonal" means orthogonal within reasonable tolerances of manufacturing and measurement. In some embodiments, the wire 91 can extend in the same direction as Figure 7 the digital line 23 (i.e., in and out of the page with respect to the cross-sectional view of Figure 7 ).

[0074] Figure 7 and 8 shows a switch 40 including only a single transistor. In other embodiments, an individual switch can include two or more transistors. For example, Figure 8A shows an embodiment in which the switch 40 includes three of the transistors 56. Figure 8A The embodiment of

[0075] In some embodiments, the discharge at the distal end of a word line transitioning from an on operating state to an off operating state can be directed to a word line that is already in the "off operating state". Figure 9 Show assembly 50 configured to utilize lower word line 32a to facilitate discharge from the distal end 53b of upper word line 32b when upper word line transitions from an on state to an off state. Figure 9 The configuration of is similar to that referenced above Figure 7 described. However, Figure 9 The embodiment of eliminates the coupling of the distal end 53 to a low voltage reference source and instead couples the distal end 53b of the upper word line 32b to the distal end 53a of the lower word line 32a through transistor 56 (more generally, switch 40). The lower word line 32a is shown in an off operating state and the upper word line 32b is shown transitioning from an on operating state to an off operating state. Discharge from the distal end 53b of the upper word line 32b during the transition to the off state is facilitated by coupling the distal end 53b to the distal end 53a via transistor 56 (switch 40), which can generally reduce the time required to transition the word line 32b to the off state compared to a similar device lacking the facilitated discharge through the distal end 53b. Arrow 66 schematically illustrates the facilitated discharge from the distal end 53b through transistor 56 (switch 40) to the off state lower word line 32a.

[0076] Although Figure 9 the device of is described as utilizing the distal end 53a of the lower word line 32a to facilitate discharge from the distal end 53b of the upper word line 32b, it should be understood that the device can operate in the opposite direction such that the distal end 53b of the upper word line 32b is used to facilitate discharge from the distal end 53a of the lower word line 32a in an application where the upper word line is in an off state and the lower word line is transitioning from an on state to an off state.

[0077] Figure 7 Show an application where a low voltage reference source 52 is used to facilitate discharge from the distal end of a word line during the transition of the word line to an off state, and Figure 9 show an application where an off state word line is used to facilitate discharge from the distal end of an adjacent word line during the transition of the adjacent word line to an off state. In some embodiments, Figure 7 and 9 the applications of can be combined to facilitate discharge from the distal end of a word line during the transition of the word line to an off state. Figure 10 Show assembly 50 in a configuration similar to Figure 7 and 9 However, Figure 10 the configuration of has two transistors 56a and 56b for different purposes relative to each other.

[0078] The transistors 56a and 56b are coupled to each other through the lower source / drain region 54 of the upper transistor 56b and the upper source / drain region 58 of the lower transistor 56a. In addition, the upper source / drain region 58 of the upper transistor 56b is coupled to the low voltage reference source 52, and the lower source / drain region 54 of the lower transistor 56a is coupled to the lower word line 32a. In the illustrated embodiment, the lower word line 32a is in an off state, and the upper word line 32b is transitioning from an on state to an off state. The transistor 56b can facilitate the discharge from the upper word line 32b by coupling such upper word line to the low voltage reference source 52, and the transistor 56a can simultaneously facilitate the discharge from the upper word line 32b by coupling such upper word line to the off-state lower word line 32a. The arrows 66a and 66b schematically indicate the facilitated discharges through the transistors 56a and 56b, respectively.

[0079] Although Figure 10 the embodiments specifically show the upper word line 32b having a discharge facilitated through the distal end 53b, it should be understood that in other embodiments, a configuration similar to Figure 10 the configuration of

[0080] Although the embodiments described herein indicate that there are two memory levels (14, 16) above the substrate 12, it should be understood that in other embodiments, there may be more than two memory levels above the substrate.

[0081] In some applications, the embodiments described herein can reduce the time for a word line to transition from an on state to an off state by at least about 3 nanoseconds (ns), or even at least about 5 ns.

[0082] The assemblies and structures discussed above can be utilized within an integrated circuit (the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and can be incorporated into an electronic system. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems: such as cameras, wireless devices, displays, chip sets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular telephones, personal computers, automobiles, industrial control systems, airplanes, etc.

[0083] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method known now or to be developed, which methods include, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0084] The terms "dielectric" and "insulating" can be used to describe materials having insulating electrical properties. The terms are regarded as synonymous in this disclosure. In some cases the term "dielectric" and in other cases the term "insulating" (or "electrically insulating") can be used within this disclosure to provide linguistic variation to simplify the underlying basis within the following claims, rather than to indicate any significant chemical or electrical differences.

[0085] The terms "electrically connected" and "electrically coupled" can both be used in this disclosure. The terms are regarded as synonymous. In some cases using one term and in other cases using the other term may be for providing linguistic variation within this disclosure to simplify the underlying basis within the following claims. The term "couple (couple, coupling, coupled, etc.)" can refer to an electrical connection.

[0086] The specific orientation of the various embodiments in the figures is for illustrative purposes only, and in some applications, the embodiments can be rotated relative to the shown orientation. The description provided herein and the following claims relate to any structure having the described relationship between the various features, whether the structure is in the specific orientation of the respective figures or rotated relative to such orientation.

[0087] Unless otherwise specified, the cross-sectional views in the accompanying description only show the features within the cross-sectional plane and do not show the materials behind the cross-sectional plane, so as to simplify the figures.

[0088] When a structure is referred to as "on another structure", "adjacent to another structure" or "abut against another structure", the structure can be directly on the other structure or there may also be an intervening structure. In contrast, when a structure is referred to as "directly on another structure", "directly adjacent to another structure" or "directly abut against another structure", there is no intervening structure. The terms "directly below", "directly above", etc. do not indicate direct physical contact (unless explicitly stated otherwise), but instead indicate vertical alignment.

[0089] A structure (e.g., a layer, a material, etc.) can be referred to as "vertically extending" to indicate that the structure generally extends upward from an underlying substrate (e.g., a wafer). A vertically extending structure can generally extend orthogonally to the upper surface of the substrate, or may not extend orthogonally to the upper surface of the substrate.

[0090] Some embodiments include an integrated assembly having a first word line coupled to a driver circuit and a second word line coupled to the driver circuit. The first word line has a first end remote from the driver circuit, and the second word line has a second end remote from the driver circuit. A switch is adjacent to the first end and is configured to couple the first end to one or both of the second end and a low voltage reference source during a transition of the first word line from an “on” state to an “off” state.

[0091] Some embodiments include an integrated assembly that includes a first word line coupled to a first sub-driver circuit and having a first end remote from the first sub-driver circuit. The assembly also includes a second word line coupled to a second sub-driver circuit and having a second end remote from the second sub-driver circuit. The second word line is vertically offset relative to the first word line. The first sub-driver circuit and the second sub-driver circuit are vertically offset relative to the first word line and the second word line. A first switch is adjacent to the first end and is configured to couple the first end to a low voltage reference source during a transition of the first word line from an “on” state to an “off” state. A second switch is adjacent to the second end and is configured to couple the second end to a low voltage reference source during a transition of the second word line from an “on” state to an “off” state.

[0092] Some embodiments include an integrated assembly having a substrate that includes a control circuit, a first sub-driver circuit, and a second sub-driver circuit. A first layer is above the substrate. The first layer includes a first portion of a first array of first memory cells and includes a first portion of a second array of second memory cells. A second layer is above the first layer. The second layer includes a second portion of the first array of first memory cells and includes a second portion of the second array of second memory cells. A first word line is associated with the first array. The first word line has a first end proximate to the first sub-driver circuit and has a second end remote from the first sub-driver circuit and along the first layer. A second word line is associated with the first array. The second word line has a third end proximate to the second sub-driver circuit and has a fourth end remote from the second sub-driver circuit and along the second layer. A transistor is adjacent to one of the second end and the fourth end and is configured to couple the one of the second end and the fourth end to one or both of a low voltage reference source and the other of the second end and the fourth end during a transition of one of the first word line and the second word line from an “on” state to an “off” state. The transistor includes a vertically extending channel region and a gate operatively proximate to the channel region. The gate is coupled to the control circuit.

[0093] As provided, the subject matter disclosed herein has been described in more specific or less specific language with respect to structural and method features. However, it should be understood that the claims are not limited to the specific features shown and described, as the devices disclosed herein include example embodiments. Accordingly, the claims have the full scope as set forth in writing and should be construed appropriately in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly, comprising: A first word line coupled to a driver circuit and having a first end remote from the driver circuit; A second word line coupled to the driver circuit and having a second end remote from the driver circuit; And A switch adjacent to the first end and configured to selectively couple the first end to the second end and selectively couple the first end to a low voltage reference source during a transition of the first word line from an "on" state to an "off" state.

2. The integrated assembly according to claim 1, wherein the second word line is vertically offset from the first word line.

3. The integrated assembly according to claim 2, wherein the driver circuit includes a first sub-driver circuit and a second sub-driver circuit, and wherein the first word line and the second word line are respectively coupled to the first sub-driver circuit and the second sub-driver circuit.

4. The integrated assembly according to claim 2, wherein the switch is a transistor.

5. The integrated assembly according to claim 4, wherein the transistor has a vertically extending channel region.

6. The integrated assembly according to claim 1, wherein the switch is configured to couple the first end to the second end during the transition of the first word line from an "on" state to an "off" state and when the second word line is in the "off" state.

7. The integrated assembly according to claim 1, wherein the switch is a first switch and is configured to couple the first end to the low voltage reference source; and the integrated assembly further includes a second switch between the first end and the second end and configured to couple the first end to the second end during the transition of the first word line from an "on" state to an "off" state and when the second word line is in the "off" state.

8. An integrated assembly, comprising: A first word line coupled to a first sub-driver circuit and having a first end remote from the first sub-driver circuit; A second word line coupled to a second sub-driver circuit and having a second end remote from the second sub-driver circuit; the second word line is vertically offset relative to the first word line; The first sub-driver circuit and the second sub-driver circuit are vertically offset relative to the first word line and the second word line; A first switching transistor adjacent to the first end and configured to couple the first end to a low voltage reference source during a transition of the first word line from an "on" state to an "off" state, the first switching transistor having a first source / drain region coupled to the first end and a second source / drain region coupled to the low voltage reference source; And A second switching transistor, adjacent to the second terminal and configured to couple the second terminal to the low voltage reference source during a transition of the second word line from an "on" state to an "off" state, the second switching transistor having a third source / drain region coupled to the second terminal and a fourth source / drain region coupled to the low voltage reference source.

9. The integrated assembly of claim 8, wherein the low voltage reference source is at a negative word line voltage VNWL.

10. The integrated assembly of claim 8, wherein the first switching transistor and the second switching transistor have gates coupled to a control circuit; and wherein the control circuit is under the first word line and the second word line.

11. The integrated assembly of claim 8, wherein the first switching transistor and the second switching transistor include vertically extending channel regions.

12. The integrated assembly of claim 8, wherein the first switching transistor is one of a series of transistors disposed between the first terminal and the low voltage reference source, the series of transistors having gates coupled to a control circuit.

13. The integrated assembly of claim 12, wherein the control circuit is vertically offset from the first word line and the second word line.

14. The integrated assembly of claim 12, wherein the control circuit is under the first word line and the second word line.

15. An integrated assembly, comprising: a substrate including a control circuit, a first sub-driver circuit, and a second sub-driver circuit; a first layer over the substrate; the first layer including a first portion of a first array of first memory cells and including a first portion of a second array of second memory cells; a second layer over the first layer; the second layer including a second portion of the first array of first memory cells and including a second portion of the second array of second memory cells; a first word line associated with the first array, the first word line having a first end proximate to the first sub-driver circuit and having a second end remote from the first sub-driver circuit and along the first layer; a second word line associated with the first array, the second word line having a third end proximate to the second sub-driver circuit and having a fourth end remote from the second sub-driver circuit and along the second layer; and a transistor adjacent to one of the second end and the fourth end and configured to couple one of the second end and the fourth end to the low voltage reference source and one or both of the other of the second end and the fourth end during a transition of one of the first word line and the second word line from an "on" state to an "off" state; the transistor being between a first source / drain region and a second source / drain region and including a vertically extending channel region and a gate operatively proximate to the channel region. The gate is coupled to the control circuit, and the one of the second terminal and the fourth terminal that is adjacent to the transistor is coupled to the first source / drain region.

16. The integrated assembly according to claim 15, wherein the low voltage reference source is at a negative word line voltage VNWL.

17. The integrated assembly according to claim 15, wherein the transistor is adjacent to the second terminal and is configured to couple the second terminal to one or both of the low voltage reference source and the fourth terminal during a transition of the first word line from an "on" state to an "off" state.

18. The integrated assembly according to claim 17, wherein the first word line is one of a series of first word lines along the first layer, wherein the transistor is one of a series of transistors, wherein each of the first word lines in the series of the first word lines is adjacent to one of the transistors in the series of the transistors; wherein each transistor in the series of the transistors has a gate coupled to the control circuit, wherein a wire extends along the gate and is used for the coupling of the gate to the control circuit; wherein the first word line extends along a first direction; and wherein the wire extends along a second direction orthogonal to the first direction.

19. The integrated assembly according to claim 17, wherein the transistor is a first transistor, and the integrated assembly further includes a second transistor, the second transistor is adjacent to the fourth terminal and is configured to couple the fourth terminal to the low voltage reference source during a transition of the second word line from an "on" state to an "off" state.

20. The integrated assembly according to claim 15, wherein the first memory cell and the second memory cell include capacitors, and wherein a bottom electrode of the capacitor is configured as an upwardly open container.

21. The integrated assembly according to claim 15, wherein the transistor is configured to couple the second terminal to the low voltage reference source.

22. The integrated assembly according to claim 15, wherein the transistor is configured to couple the fourth terminal to the low voltage reference source.

23. The integrated assembly according to claim 15, wherein the transistor is configured to couple the second terminal to the fourth terminal during the transition of the first word line from an "on" state to an "off" state and when the second word line is in the "off" state.

24. The integrated assembly according to claim 15, wherein the transistor is configured to couple the fourth terminal to the second terminal during the transition of the second word line from an "on" state to an "off" state and when the first word line is in the "off" state.

25. The integrated assembly according to claim 15, wherein the transistor is a first transistor and is configured to couple the second terminal to the low voltage reference source, and the integrated assembly further includes a second transistor, the second transistor being between the second terminal and the fourth terminal and being configured to couple the second terminal to the fourth terminal during the transition of the first word line from the "on" state to the "off" state and when the second word line is in the "off" state.

26. The integrated assembly according to claim 15, wherein the transistor is a first transistor and is configured to couple the fourth terminal to the low voltage reference source, and the integrated assembly further includes a second transistor, the second transistor being between the fourth terminal and the second terminal and being configured to couple the fourth terminal to the second terminal during the transition of the second word line from the "on" state to the "off" state and when the first word line is in the "off" state.

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