Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device, comprising a display area and a non-display area; the display area comprises a plurality of pixel circuits and a first fixed potential line, the first fixed potential line being electrically connected to the pixel circuits; the non-display area comprises a first signal line and a first pin, the first signal line being electrically connected to the first fixed potential line, one side of the first pin being electrically connected to the first signal line and the other side being electrically connected to a first flexible printed circuit board; wherein the non-display area comprises a first region and a second region, the first region and the second region being located on different sides of the display area; the first pin being disposed in the first region, and the first signal line extending from the first region to the second region; and the portion of the first signal line located in the second region being connected to the first fixed potential line. The first pin electrically connected to the first signal line is disposed in the first region, and the first signal line extending from the first region to the second region and then connected to the first fixed potential line in the display area can reduce the width of the first region.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] As consumers' demand for displays increases, full-screen displays have become a focus of current research. Full-screen displays have an extremely high screen-to-body ratio and can greatly improve user experience.

[0003] However, in existing technologies, the display panel frame requires circuits and peripheral wiring, printed circuit board bonding, and encapsulation adhesive. This is especially true in the lower frame of the display panel, where circuits, various signal lines, and bonding pins are located, which poses a significant challenge to the implementation of full-screen displays. Therefore, reducing the frame is a key issue in achieving full-screen displays.

[0004] Application Contents

[0005] In view of this, embodiments of the present application provide a display panel and a display device to solve the above problems.

[0006] In a first aspect, the present application provides a display panel comprising a display area and a non-display area; the display area comprises a plurality of pixel circuits and a first fixed potential line, the first fixed potential line being electrically connected to the pixel circuit; the non-display area comprises a first signal line and a first pin, the first signal line being electrically connected to the first fixed potential line, one side of the first pin being electrically connected to the first signal line, and the other side being electrically connected to a first flexible printed circuit board; wherein the non-display area comprises a first region and a second region, the first region and the second region being located on different sides of the display area; the first pin being arranged in the first region, and the first signal line extending from the first region to the second region; the portion of the first signal line located in the second region being connected to the first fixed potential line.

[0007] In an implementation of the first aspect, the display area also includes a first electrode; the non-display area includes a second signal line, the second signal line is electrically connected to the first electrode, and the second signal line provides a second fixed potential signal to the second electrode; wherein the absolute value of the second fixed potential signal is smaller than the absolute value of the first fixed potential signal, and the second signal line is located on a side of the first signal line away from the display area.

[0008] In an implementation of the first aspect, the display area also includes multiple data lines, which are electrically connected to the pixel circuit; the non-display area also includes multiple third signal lines and multiple third pins, and the multiple third signal lines and the multiple third pins are located in the first area; the third signal line is electrically connected to the data line, and one side of the third pin is electrically connected to the second signal line; wherein the first pin is located on a side of the multiple third pins away from the center of the first area, and the portion of the first signal line arranged in the first area is located on a side of the multiple third signal lines away from the center of the first area.

[0009] In an implementation of the first aspect, the third pin and the first pin are electrically connected to the same first flexible printed circuit board.

[0010] In an implementation of the first aspect, the other side of the third pin is electrically connected to a second flexible printed circuit board on which a display integrated circuit board is provided; and the first flexible printed circuit board is electrically connected to the main board.

[0011] In an implementation of the first aspect, the first region includes at least two first pins; wherein, at least one first pin is arranged on one side of the plurality of third pins, and the other first pins are arranged on the other side of the plurality of third pins.

[0012] In an implementation of the first aspect, the first pin located on one side of the plurality of third pins is electrically connected to one first flexible printed circuit board, and the first pin located on the other side of the plurality of third pins is electrically connected to another first flexible printed circuit board.

[0013] In an implementation of the first aspect, the first area and the display area are arranged along a first direction, the second area and the display area are arranged along a second direction, and the first direction intersects the second direction.

[0014] In an implementation of the first aspect, the first area and the second area are located on opposite sides of the display area.

[0015] In an implementation of the first aspect, part of the second area and the first area are arranged on opposite sides of the display area along a first direction, and another part of the second area and the display area are arranged along a second direction, and the first direction intersects the second direction.

[0016] In a second aspect, the present application provides a display device, comprising the display panel provided in the first aspect.

[0017] In this embodiment of the present application, although the first pin electrically connected to the first signal line is located in the first region, the first signal line extends from the first region to the second region and then connects to the first fixed potential line in the display area. This prevents the first signal line and the first fixed potential line from being electrically connected in the first region, which would increase the width of the first region. Furthermore, the first pin in the first region is electrically connected to the first flexible printed circuit board, further reducing the width of the first region. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 A schematic diagram of a display panel provided in accordance with an embodiment of the present application;

[0020] Figure 2 is an equivalent circuit diagram of a pixel circuit related to the present application;

[0021] Figure 3 A schematic diagram of another display panel provided in one embodiment of the present application;

[0022] Figure 4 A schematic diagram of another display panel provided in accordance with an embodiment of the present application;

[0023] Figure 5 A schematic diagram of a display panel provided in another embodiment of the present application;

[0024] Figure 6 A schematic diagram of another display panel provided in another embodiment of the present application;

[0025] Figure 7 A schematic diagram of a display panel provided in yet another embodiment of the present application;

[0026] Figure 8 for Figure 7 A corresponding cross-sectional schematic diagram;

[0027] Figure 9 A schematic diagram of another display panel provided in yet another embodiment of the present application;

[0028] Figure 10 for Figure 9 A corresponding cross-sectional schematic diagram;

[0029] Figure 11 A schematic diagram of a display panel provided in yet another embodiment of the present application;

[0030] Figure 12 A schematic diagram of another display panel provided in yet another embodiment of the present application;

[0031] Figure 13 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0033] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0034] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0035] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0036] In the description of this specification, it is necessary to understand that the words "substantially", "approximately", "approximately", "about", "roughly", "generally" and the like described in the claims and embodiments of this application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0037] It should be understood that although the terms "first," "second," and "third," etc. may be used in embodiments of the present application to describe signal lines, pins, etc., these signal lines, pins, etc. should not be limited to these terms. These terms are merely used to distinguish signal lines, pins, etc. from one another. For example, a first signal line may also be referred to as a second signal line, and similarly, a second signal line may also be referred to as a first signal line, without departing from the scope of the embodiments of the present application.

[0038] The applicant in this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0039] Figure 1 A schematic diagram of a display panel provided according to an embodiment of the present application.

[0040] like Figure 1 As shown, the display panel provided in the embodiment of the present application includes a display area AA and a non-display area BB, and the non-display area BB can surround the display area AA. The display area AA is mainly used for light-emitting display, and the non-display area BB is mainly used for setting peripheral circuits and packaging.

[0041] The display area AA includes a plurality of pixel circuits CT, which are configured to provide a light-emitting driving voltage or a light-emitting driving current to the light-emitting devices in the display area AA. For example, when the light-emitting devices in the display area AA are organic light-emitting diodes, the pixel circuits CT may provide a light-emitting driving current to the light-emitting devices.

[0042] The display area AA further includes a plurality of first fixed potential lines VL, which are electrically connected to the pixel circuits CT and are used to transmit first fixed potential signals provided to the pixel circuits CT.

[0043] Figure 2 is an equivalent circuit diagram of a pixel circuit related to the present application.

[0044] like Figure 2 As shown, the pixel circuit CT includes a light-emitting driving transistor T0, a first reset transistor T1, a second reset transistor T2, a data voltage writing transistor T3, a threshold grabbing transistor T4, a power supply voltage writing transistor T5, a light-emitting control transistor T6 and a capacitor C0.

[0045] One plate of the capacitor C0 is electrically connected to the gate of the light-emitting driving transistor T0 , and the other plate is electrically connected to the input end of the power supply voltage writing transistor T5 .

[0046] An input terminal of the first reset transistor T1 receives a reset signal Vref, and an output terminal is electrically connected to the gate of the light emitting driving transistor T0 , so as to reset the gate of the light emitting driving transistor T0 .

[0047] The second reset transistor T2 has an input terminal receiving a reset signal Vref and an output terminal electrically connected to the light emitting device OLED, and is used for resetting the anode or cathode of the light emitting device OLED.

[0048] The data voltage write transistor T3 has an input terminal that receives the data voltage Vdata, and an output terminal that is electrically connected to the input terminal of the light-emitting driver transistor T0. The threshold capture transistor T4 has an input terminal that is electrically connected to the output terminal of the light-emitting driver transistor T0, and an output terminal that is electrically connected to the gate of the light-emitting driver transistor T0. The data voltage write transistor T3 and the threshold capture transistor T4 cooperate to write the data voltage Vdata to the gate of the light-emitting driver transistor T0.

[0049] The input terminal of the power supply voltage writing transistor T5 receives the first power supply voltage VDD, and the output terminal is electrically connected to the input terminal of the light emitting driving transistor T0 for writing the first power supply voltage VDD into the input terminal of the light emitting driving transistor T0.

[0050] The input end of the light emitting control transistor T6 is electrically connected to the output end of the light emitting driving transistor T0 , and the output end is electrically connected to the light emitting device OLED, for transmitting the light emitting driving current generated by the light emitting driving transistor T0 to the light emitting device OLED.

[0051] In the embodiment of the present application, the first fixed potential line VL can be electrically connected to the input terminal of the power supply voltage writing transistor T5. The first fixed potential line VL is used to transmit the first power supply voltage VDD to the input terminal of the light-emitting driving transistor T0. In other words, the first fixed potential signal transmitted by the first fixed potential line VL can specifically be the first power supply voltage VDD.

[0052] The non-display area BB includes a first signal line S1 electrically connected to the first fixed potential line VL. That is, the first signal line S1 in the non-display area BB is used to transmit a first fixed potential signal to the first fixed potential line VL in the display area AA.

[0053] The non-display area BB also includes a first pin P1, one side of which is electrically connected to the first signal line S1 and the other side to the first flexible printed circuit board F1. This means that the first fixed potential signal transmitted from the first signal line S1 to the first fixed potential line VL can be obtained from the outside of the display panel via the first pin P1 and the first flexible printed circuit board F1. The first flexible printed circuit board F1 can be electrically connected to the mainboard, and the mainboard transmits the first fixed potential signal to the display panel via the first flexible printed circuit board F1.

[0054] Furthermore, the non-display area BB includes a first area B1 and a second area B2, and the first area B1 and the second area B2 are located on different sides of the display area AA. Figure 1 As shown, the first area B1 is located at the lower side of the display area AA, and the second area B2 is located at the upper side of the display area AA.

[0055] The first pin P1 is disposed in the first region B1 , and the first signal line S1 extends from the first region B1 to the second region B2 . The portion of the first signal line S1 in the second region B2 is connected to the first fixed potential line VL.

[0056] It can be understood that the first pin P1 is disposed in the first area B1, which is the area where the display panel's binding area is located. This area includes not only the pins but also fan-out wiring, multiple output selection circuitry, and other components. In the embodiment of the present application, although the first pin P1 electrically connected to the first signal line S1 is disposed in the first area B1, the first signal line S1 extends from the first area B1 to the second area B2 before connecting to the first fixed potential line VL in the display area AA. This prevents the first signal line S1 from electrically connecting to the first fixed potential line VL in the first area B1, which would increase the width of the first area B1. Furthermore, the first pin P1 in the first area B1 is electrically connected to the first flexible printed circuit board F1, further reducing the width of the first area B1.

[0057] Figure 3 A schematic diagram of another display panel provided in one embodiment of the present application is shown. Figure 4 A schematic diagram of another display panel provided according to an embodiment of the present application.

[0058] In one embodiment of the present application, Figure 1 As shown, the first region B1 and the second region B2 are located on opposite sides of the display area AA. In other words, the first signal line S1 extends from the first region B1, where the first pin P1 is located, to the second region B2, which is opposite the first region B1. For example, the first region B1 is located below the display area AA, and the second region B2 is located above the display area AA. The first signal line S1 is electrically connected to the first pin P1 in the first region B1 and to the first fixed potential line VL in the second region B2, which is opposite the first region B1.

[0059] It should be noted that the first area B1 and the second area B2 are located on opposite sides of the display area AA, and the portion of the first signal line S1 located between the first area B1 and the second area B2 is also disposed in the non-display area BB. Figure 1 It can be seen that when the first area B1 and the second area B2 are respectively located on the upper and lower sides of the display area AA, the first signal line S1 extends from the first area B1 to the second area B2 through the non-display area BB on the left and / or right side of the display area AA.

[0060] In one embodiment of the present application, Figure 3As shown, the first region B1 and the display area AA are arranged along a first direction Y, and the second region B2 and the display area AA are arranged along a second direction X, with the first direction Y intersecting the second direction X. That is, the second region B2 and the first region B1 are not oriented in the same direction as the display area AA. For example, the first region B1 is located below the display area AA, and the second region is located to the left and / or right of the display area AA. The first signal line S1 is electrically connected to the first pin P1 in the first region B1 below the display area AA, and is electrically connected to the first fixed potential line VL in the second regions B2 on the left and right sides of the display area AA.

[0061] In one embodiment of the present application, Figure 4 As shown, part of the second area B2 and the first area B1 are arranged on opposite sides of the display area AA along the first direction Y, and another part of the second area B2 and the display area AA are arranged along the second direction X, and the first direction Y intersects the second direction X. In other words, the second area B2 includes parts located outside the display area AA in different directions. For example, Figure 4 As shown, the first area B1 is arranged on the lower side of the display area AA, and the second area B2 includes a portion located on the upper side of the display area AA, and also includes a portion located on the left and / or right side of the display area AA. The first signal line S1 is electrically connected to the first fixed potential line VL in the second areas B2 on the left and right sides of the display area AA and the second area B2 on the upper side.

[0062] Figure 5 A schematic diagram of a display panel provided in another embodiment of the present application is shown. Figure 6 A schematic diagram of another display panel provided in accordance with another embodiment of the present application.

[0063] In one embodiment of the present application, Figure 5 and Figure 6 As shown, the display area AA further includes a first electrode EL, the output end of the pixel circuit CT is electrically connected to one end of the light emitting device and the first electrode EL is electrically connected to the other end of the light emitting device. The first electrode EL is used to provide a second fixed potential signal to the light emitting device.

[0064] For example, Figure 5 and Figure 6 As shown, the output end of the pixel circuit CT is electrically connected to the anode of the light-emitting device OLED, and the first electrode EL is electrically connected to the cathode of the light-emitting device. The pixel circuit CT provides a signal to the anode of the light-emitting device OLED, and the first electrode EL provides a second fixed potential signal to the cathode of the light-emitting device OLED.

[0065] The non-display area BB includes a second signal line S2, which is electrically connected to the first electrode EL. That is, the second signal line S2 in the non-display area BB is used to transmit a second fixed potential signal to the first electrode EL in the display area AA.

[0066] The first region B1 of the non-display area BB also includes a second pin P2. One side of the second pin P2 is electrically connected to the second signal line S2, and the other side is electrically connected to the first flexible printed circuit board F1. In other words, the second fixed potential signal transmitted by the second signal line S2 to the first electrode EL can be obtained from the outside of the display panel via the second pin P2 and the first flexible printed circuit board F1. The adjacent first pin P1 and second pin P2 can be electrically connected to the same first flexible printed circuit board F1.

[0067] Furthermore, the absolute value of the second fixed potential signal transmitted by the second signal line S2 is smaller than the absolute value of the first fixed potential signal transmitted by the first signal line S1, and the second signal line S2 is arranged on a side of the first signal line S1 away from the display area AA. Since the potential signal transmitted by the second signal line S2 is lower, static electricity around the display panel can be effectively shielded.

[0068] In a technical solution corresponding to this embodiment, as Figure 5 As shown, the first signal line S1 and the second signal line S2 are electrically connected to the first fixed potential line VL and the first electrode EL respectively in the second area B2 of the non-display area BB.

[0069] In another technical solution corresponding to this embodiment, as Figure 6 As shown, the first signal line S2 is electrically connected to the first fixed potential line VL in the second area B2 of the non-display area BB, and the second signal line S2 is electrically connected to the first electrode EL in other areas of the non-display area BB except the first area B1 and the second area B2.

[0070] Figure 7 A schematic diagram of a display panel provided in yet another embodiment of the present application is shown. Figure 8 for Figure 7 A corresponding cross-sectional diagram, Figure 9 A schematic diagram of another display panel provided in yet another embodiment of the present application is shown. Figure 10 for Figure 9 A corresponding cross-sectional schematic diagram.

[0071] In one implementation of this embodiment, Figure 7 As shown, the first signal line S1 and the first auxiliary signal line 10 are arranged in different layers and connected in parallel. The first auxiliary signal line 10 and the first signal line S1 are connected in parallel to reduce the resistance of the first fixed potential signal transmission path and ensure the accuracy of the first fixed potential signal.

[0072] Among them, such as Figure 8As shown, the pixel circuit CT includes a transistor, which includes a gate CT0 and a source / drain CT1. The gate CT0 can be provided on the same layer as the scan line, and the source / drain CT1 can be provided on the same layer as the data line DL. The light-emitting device OLED includes a first electrode EL, a second electrode AL, and a light-emitting layer LL located between the first and second electrodes EL. The first electrode EL is electrically connected to the second signal line S2, and the second electrode AL is electrically connected to the pixel circuit CT.

[0073] In this implementation, if Figure 8 As shown, the first signal line S1 and the data line DL are provided on the same layer, the first auxiliary signal line 10 and the second electrode AL are provided on the same layer, and the first auxiliary signal line 10 and the second electrode AL are electrically connected through a via.

[0074] In another implementation of this embodiment, Figure 9 As shown, the second signal line S2 and the second auxiliary signal line 20 are arranged in different layers and connected in parallel. The parallel connection of the second auxiliary signal line 20 and the second signal line S2 can reduce the resistance of the second fixed potential signal transmission path. Furthermore, because the second signal line S2 transmits a low-potential signal and is located at the edge of the non-display area BB away from the display area AA, it can work together with the second auxiliary signal line 20 to provide electrostatic protection for the display panel.

[0075] In this implementation, if Figure 9 As shown, the second signal line S2 is provided on the same layer as the scan line, the second auxiliary signal line 20 is provided on the same layer as the second electrode AL and / or the first electrode EL, and the second auxiliary signal line 20 is electrically connected to the second electrode AL and / or the first electrode EL through a via.

[0076] The second signal line S2 also extends from the first area B1 to other areas of the non-display area BB, and the via holes electrically connecting the second auxiliary signal line 20 to the second electrode AL and / or the first electrode EL can be located in the first area. In particular, when the display panel includes a rounded-corner display panel, the via holes electrically connecting the second auxiliary signal line 20 to the second electrode AL and / or the first electrode EL can be located in the first area near the rounded corner area.

[0077] Figure 11 A schematic diagram of a display panel provided in yet another embodiment of the present application is shown. Figure 12 A schematic diagram of another display panel provided in yet another embodiment of the present application.

[0078] In one embodiment of the present application, Figure 11 and Figure 12As shown, the display area AA further includes a plurality of data lines DL. The data lines DL are electrically connected to the pixel circuits CT and are used to transmit the data voltage Vdata provided to the pixel circuits CT. Specifically, the data lines DL can be electrically connected to the input terminal of the data voltage write transistor T3 of the pixel circuits CT. The data lines DL are used to transmit the data voltage Vdata to the input terminal of the data voltage write transistor T3. Furthermore, the data voltage Vdata transmitted by the data lines DL can be written into the gate of the light-emitting driving transistor T0.

[0079] The non-display area BB includes a plurality of third signal lines S3, which are electrically connected to the data lines DL. That is, the third signal lines S3 in the non-display area BB are used to transmit data voltages Vdata to the data lines DL in the display area AA.

[0080] The non-display area BB further includes a plurality of third pins P3, one side of which is electrically connected to the data line DL. In other words, the data voltage Vdata transmitted from the third signal line S3 to the data line DL can be obtained from the outside of the display panel through the third pins P3.

[0081] The plurality of third signal lines S3 and the plurality of third pins P3 included in the non-display area BB are located in the first region B1 , and the third signal lines S3 are electrically connected to the data lines DL in the first region B1 .

[0082] Optionally, the first region B1 includes a multi-channel output selection circuit DM, the third signal line S2 is electrically connected to the input of the multi-channel output selection circuit DM, and the data line DL is electrically connected to the output of the multi-channel output selection circuit DM. When a switch in the multi-channel output selection circuit DM is turned on, the corresponding third signal line S3 is electrically connected to the corresponding data line DL. In other words, in the first region B1, the third signal line S3 is electrically connected to the data line DL through the multi-channel output selection circuit DM.

[0083] In the embodiments of this application, Figure 5 and Figure 6 As shown, the first pin P1 is located on a side of the plurality of third pins P3 away from the center of the first area B1, and the portion of the first signal line S1 disposed in the first area B1 is located on a side of the plurality of third signal lines S3 away from the center of the first area B1. Figure 5 and Figure 6 As shown, the third pins P3 are arranged along the second direction X, and along the second direction X, the first pin P1 is located on one side of the plurality of third pins P3; the third signal lines S3 are arranged along the second direction X, and along the second direction X, the first signal line S1 is located on one side of the plurality of third signal lines S3.

[0084] Optionally, all third pins P3 included in the first area B1 are regarded as a second pin group, and the first pin P1 is located on a side of the third pin group away from the center of the first area B1; all third signal lines S3 included in the second area B1 are regarded as a third signal line group, and the third signal line S3 is located on a side of the third signal line group away from the center of the first area B1.

[0085] In other words, the first pin P1 is closer to the edge of the first area B1 than the third pin P3, and the first signal line S1 is closer to the edge of the first area B1 than the third signal line S3. This facilitates routing the first signal line S1 in the first area B1, preventing it from winding within the first area B1 and ensuring a smaller width for the first area B1. Furthermore, this helps minimize the need for the first signal line S1 to travel through a smaller path from the first area B1 to the second area B2, reducing load and signal interference on the first signal line S1 and ensuring the accuracy of the first fixed potential signal.

[0086] It should be noted that when the non-display area also includes a second pin P2 and a second signal line S2, the second pin P2 is located on the side of the first pin P1 away from the third pin P3, and the portion of the second signal line S2 located in the first area B1 is located on the side of the portion of the first signal line S1 located in the first area B1 away from the third signal line S3.

[0087] It should be noted that, in the present application, the first area B1 may further include other signal lines in addition to the first signal line S1 and the third signal line S3 , and may also include other pins in addition to the first pin P1 and the third pin P3 .

[0088] Furthermore, if Figure 11 and Figure 12 As shown, the first region B1 may include at least two first pins P1. At least one first pin P1 is disposed on one side of the plurality of third pins P3, while the other first pins P1 are disposed on the other side of the plurality of third pins P3. In other words, the at least two first pins P1 included in the first region B1 are disposed separately on opposite sides of the third pin group.

[0089] In one implementation of this embodiment, Figure 11 As shown, the third pin P3 and the first pin P1 are electrically connected to the same first flexible printed circuit board F1. In other words, the third pin P3 is also electrically connected to the flexible printed circuit board, and the flexible printed circuit board electrically connected to the first pin P1 and the second pin P2 is the same first flexible printed circuit board F1.

[0090] It should be noted that in a technical solution corresponding to this implementation, if the first area B1 also includes other pins, for example, the second pin P2, then these other pins can also be electrically connected to the same first flexible printed circuit board F1 as the first pin P1 and the third pin P3.

[0091] In another implementation of this embodiment, Figure 12 As shown, the other side of the third pin P3 is electrically connected to the second flexible printed circuit board F2. That is, the first pin P1 and the third pin P3 are electrically connected to different flexible printed circuit boards.

[0092] The first flexible printed circuit board (F1) is electrically connected to the motherboard. The motherboard can provide a first fixed potential signal to the first signal line S1 via the first flexible printed circuit board (F1) and the first pin (P1). The second flexible printed circuit board (F2) is provided with a display integrated circuit board. The display integrated circuit board can provide a display data voltage to the third signal line S3 via the second flexible printed circuit board (F2) and the third pin (P3).

[0093] This implementation can reduce the influence of the first fixed potential signal on other signals.

[0094] One technical solution corresponding to this implementation is that the first pins P1 located on one side of the plurality of third pins P3 are electrically connected to one first flexible printed circuit board F1, and the first pins P1 located on the other side of the plurality of third pins P3 are electrically connected to another first flexible printed circuit board F1. In other words, the first pins P1 located on both sides of the third pin group are respectively connected to the first flexible printed circuit board F1.

[0095] Figure 13 A schematic diagram of a display device provided in an embodiment of the present application.

[0096] The embodiment of the present application provides a display device, such as Figure 13 As shown, it includes a display panel 01 provided in any of the above embodiments. The display device provided in the embodiment of the present application can be a mobile phone. In addition, the display device provided in the embodiment of the present application can also be a display device such as a computer or a television.

[0097] In the display device provided herein, although the first pin electrically connected to the first signal line is disposed in the first region, the first signal line extends from the first region to the second region and then connects to the first fixed potential line in the display area. This prevents the first signal line and the first fixed potential line from being electrically connected in the first region, which would increase the width of the first region. Furthermore, the first pin in the first region is electrically connected to the first flexible printed circuit board, further reducing the width of the first region.

[0098] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: The display area includes: a plurality of pixel circuits; a first fixed potential line, the first fixed potential line being electrically connected to the pixel circuit; The non-display area includes: a first signal line electrically connected to the first fixed potential line; a first pin, wherein one side of the first pin is electrically connected to the first signal line, and the other side of the first pin is electrically connected to the first flexible printed circuit board; The non-display area includes a first area and a second area, the first area and the second area are located on different sides of the display area; the first pin is provided in the first area, and the first signal line extends from the first area to the second area; the portion of the first signal line located in the second area is connected to the first fixed potential line; The display area further includes a plurality of data lines, and the data lines are electrically connected to the pixel circuit; The non-display area further includes a plurality of third signal lines and a plurality of third pins, wherein the plurality of third signal lines and the plurality of third pins are located in the first area; the third signal lines are electrically connected to the data lines, and one side of the third pins is electrically connected to the data lines; The first pin is located on a side of the plurality of third pins away from the center of the first area, and the portion of the first signal line arranged in the first area is located on a side of the plurality of third signal lines away from the center of the first area.

2. The display panel according to claim 1, wherein: The display area further includes a first electrode; The non-display area includes a second signal line, the second signal line is electrically connected to the first electrode, and the second signal line provides a second fixed potential signal to the first electrode; The first fixed potential line is used to transmit a first fixed potential signal provided to the pixel circuit, the absolute value of the second fixed potential signal is smaller than the absolute value of the first fixed potential signal, and the second signal line is located on a side of the first signal line away from the display area.

3. The display panel according to claim 1, wherein The third pin and the first pin are electrically connected to the same first flexible printed circuit board.

4. The display panel according to claim 1, wherein: The other side of the third pin is electrically connected to a second flexible printed circuit board, on which a display integrated circuit board is provided; The first flexible printed circuit board is electrically connected to the main board.

5. The display panel according to claim 1, wherein: The first area includes at least two first pins; At least one of the first pins is arranged on one side of the plurality of third pins, and the other first pins are arranged on the other side of the plurality of third pins.

6. The display panel according to claim 5, wherein: The first pins located on one side of the plurality of third pins are electrically connected to one of the first flexible printed circuit boards, and the first pins located on the other side of the plurality of third pins are electrically connected to another of the first flexible printed circuit boards.

7. The display panel according to claim 1, wherein: The first area and the display area are arranged along a first direction, the second area and the display area are arranged along a second direction, and the first direction intersects the second direction.

8. The display panel according to claim 1, wherein: The first area and the second area are located on two opposite sides of the display area.

9. The display panel according to claim 1, wherein: Part of the second area and the first area are arranged on opposite sides of the display area along a first direction, and another part of the second area and the display area are arranged along a second direction, and the first direction intersects the second direction.

10. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 9.

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