Memory cell and method of making the same, three-dimensional memory and method of operating the same

Abstract

The present disclosure provides a memory cell, comprising: a stack layer laminated on a substrate, comprising: a plurality of channel holes penetrating through the stack layer and part of the substrate; wherein at least one second laminated material layer in the stack layer after forming the plurality of channel holes is etched to form a ring-shaped limiting structure; a gate dielectric layer located on the surface of the plurality of channel holes after the ring-shaped limiting structure is etched; a channel layer located on the surface of the gate dielectric layer; a resistance variable layer located on the surface of the channel layer corresponding to the ring-shaped limiting structure; wherein the gate voltage applied to the at least one second laminated material layer and the bit line pulse signal connected with the channel layer are controlled to change the resistance state of the resistance variable layer, so as to realize the reading, writing or erasing operation of the memory cell on the resistance variable layer. The present disclosure also provides a preparation method of the memory cell, a three-dimensional memory and an operation method thereof.

Description

Technical Field

[0001] This disclosure relates to the field of three-dimensional memory technology, specifically to a memory cell and its fabrication method, and a three-dimensional memory and its operation method. Background Technology

[0002] As the stacking layers of 3D memory continue to increase, for example from 32 layers to 64 layers to 256 layers, the word line spacing of 3D memory also continues to decrease, for example from 25nm to 17nm. The continued stacking of traditional charge-trapping and / or floating-gate 3D memory based on the gate all-round configuration will face two physical limits: (1) Traditional 3D memory uses P-type or undoped polysilicon (e.g., polysilicon) channels. As the channel length increases, the channel current will decrease until it falls below the lower limit of the drive read current, resulting in read failure; (2) The continuous reduction of word line (WL) spacing will lead to continuous enhancement of word line coupling until adjacent WLs interfere with each other, causing charge-trapping cells or floating-gate cells to fail.

[0003] The vertical stacking capability of 3D memory continues to expand, with requirements such as 512 layers and 1024 layers, while the shrinking channel gap (WL) is an unavoidable process requirement. Using highly conductive N-type polycrystalline semiconductors as the channel material can greatly increase the channel current intensity and expand the vertical scalability of 3D memory. However, the N-type channel results in a very small effective threshold window (Vth window), making it unsuitable for traditional 3D memory. Resistive switching memory cells controlled by channel current or potential difference can eliminate the WL coupling effect, and the WL is only used for cell selection; lowering the WL voltage further reduces the risk of WL breakdown. However, thin-film resistive switching memory cells currently cannot achieve majority bit (2-bit, 3-bit, or 4-bit per cell) storage technology. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a storage unit and its preparation method, a three-dimensional memory and its operation method, which solves the above technical problems by setting a limiting structure in the storage unit.

[0005] The first aspect of this disclosure provides a memory cell comprising: a stacked layer, stacked on a substrate, including: a plurality of channel vias penetrating the stacked layer and a portion of the substrate; wherein at least one second stacked material layer in the stacked layer after forming the plurality of channel vias is etched to form an annular confinement structure; a gate dielectric layer located on the surface of the plurality of channel vias after being etched to form the annular confinement structure; a channel layer located on the surface of the gate dielectric layer; and a resistive switching layer located on the surface of the channel layer corresponding to the annular confinement structure; wherein controlling the gate voltage applied to at least one second stacked material layer and a bit line pulse signal connected to the channel layer changes the resistance state of the resistive switching layer, thereby enabling the memory cell to perform read, write, or erase operations on the resistive switching layer.

[0006] Furthermore, the stacked layer includes multiple stacked pairs, each stacked pair including a first stacked material layer and a second stacked material layer, wherein the first stacked material layer and the second stacked material layer are sequentially stacked on the substrate.

[0007] Furthermore, the first stacked material layer is an insulating layer, and the second stacked material layer is a metal dielectric layer, which is a word line layer.

[0008] Furthermore, the number of layers in the second stacked material layer is positively correlated with the number of layers in the memory cell.

[0009] Furthermore, the resistive switching layer is composed of resistive switching materials or phase change materials.

[0010] Furthermore, an array of common sources is formed by multiple channel holes penetrating the stacked layers and part of the substrate.

[0011] Furthermore, the channel layer is an N-type semiconductor channel layer, and the substrate is an N-type substrate.

[0012] Furthermore, the channel layer is an N-type polycrystalline or single-crystal semiconductor channel layer.

[0013] Furthermore, the storage unit also includes an insulating material layer, located inside the multiple channel holes where no material layer is provided.

[0014] Furthermore, the memory cell is configured such that when performing a data read operation on the three-dimensional cell, current flows from the drain layer of the memory cell to the substrate.

[0015] Furthermore, the memory cell is configured such that when performing a data read operation on the memory cell, a bias voltage is applied to the drain layer and the substrate is grounded; the gate layer of the unselected memory cell is grounded and a negative gate voltage is applied to the gate layer of the selected memory cell; the resistance state of the resistive switching layer of the selected memory cell is sensed to determine the data state of the memory cell.

[0016] Furthermore, the memory cell is configured such that when performing a data write operation on the memory cell, the gate layer of the unselected memory cell is grounded, a negative gate voltage is applied to the gate layer of the selected memory cell, the substrate is grounded, and a write pulse is applied to the drain layer of the memory cell, the write pulse being sufficient to cause the memory cell to tunnel, so that electrons are stored in the memory cell.

[0017] Furthermore, the memory cell is configured such that when performing an erase operation on the memory cell, the drain layer of the memory cell is floated or grounded, and an erase pulse is applied to the drain layer of the memory cell, which is sufficient to cause the three-dimensional memory to tunnel.

[0018] A second aspect of this disclosure provides a method for fabricating a memory cell, comprising: forming a stacked layer on a substrate; fabricating a plurality of channel vias on the stacked layer and a portion of the substrate, and etching at least one sacrificial layer in the stacked layer after forming the plurality of channel vias to form an annular confinement structure; sequentially forming a gate dielectric layer, a channel layer, and a resistive switching layer on the surface of each channel via after the annular confinement structure is etched; filling the interior of each channel via where no material layer is disposed with an insulating material layer; forming a bit line lead at a portion of the top of the channel layer; etching the sacrificial layer in the stacked layer and replacing it to form a second stacked material layer; wherein, controlling the gate voltage applied to at least one second stacked material layer and the bit line pulse signal connected to the channel layer changes the resistance state of the resistive switching layer, thereby enabling the memory cell to perform read, write, or erase operations on the resistive switching layer.

[0019] A third aspect of this disclosure provides a three-dimensional memory comprising: a memory cell as shown in the first aspect of this disclosure.

[0020] A third aspect of this disclosure provides a method for operating a three-dimensional memory, comprising: controlling the voltage bias applied to the substrate, drain layer and gate layer of a portion of the memory cells in the three-dimensional memory, and performing data writing, reading and erasing operations on the portion of the memory cells in the three-dimensional memory respectively.

[0021] Furthermore, data reading operations are performed on some memory cells in the three-dimensional memory, including: triggering a data reading program; applying a negative gate voltage to the gate layer of the selected memory cell to turn off its corresponding channel; grounding the gate layer and substrate of the unselected memory cells; applying a bias voltage to the drain layer of the memory cell; and sensing the resistance state of the resistive switching layer of the selected memory cell to determine the data state of the memory cell.

[0022] Furthermore, data writing operations are performed on some memory cells in the three-dimensional memory, including: triggering a data writing program; grounding the gate layer of the unselected memory cells and applying a negative gate voltage to the gate layer of the selected memory cells; grounding the substrate; and applying a write pulse to the drain layer of the memory cells, the write pulse being sufficient to cause the memory cells to tunnel, so that electrons are stored in the memory cells.

[0023] Furthermore, a data erasure operation is performed on some memory cells in the three-dimensional memory, including: triggering a data erasure program; grounding the gate layer of the unselected memory cells and applying a negative gate voltage to the gate layer of the selected memory cells; and applying an erase pulse to the drain layer of the memory cells, the erase pulse being sufficient to cause the three-dimensional memory to tunnel.

[0024] This disclosure has at least the following advantages over the prior art:

[0025] (1) The present disclosure provides a memory cell that uses an N-type semiconductor channel and selects the memory cell by turning off the corresponding channel through word line negative voltage.

[0026] (2) By forming a ring-shaped confinement structure inside the channel hole, a resistive switching ring structure is formed after the resistive switching layer is deposited. The corresponding resistive switching ring resistance state can be read by reading the channel current.

[0027] (3) In the resistive variable ring structure, the majority bit storage writing is achieved by means of the sudden drop pulse, and page writing is supported.

[0028] (4) In the resistive variable ring structure, the erasure operation is achieved by means of the slow-falling pulse, and the area erasure is supported. Attached Figure Description

[0029] To gain a more complete understanding of this disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 The diagram schematically illustrates a partial structural schematic of a cross-section of a storage cell according to an embodiment of the present disclosure;

[0031] Figure 2 The illustration shows a partial structural schematic diagram of a cross-section of a storage cell according to another embodiment of the present disclosure;

[0032] Figure 3 The intention shows according to Figure 1 A schematic diagram showing the current flow direction when a storage unit performs data reading or writing operations;

[0033] Figure 4 It shows that according to Figure 1 A schematic diagram showing the current flow direction during data erasure operations in a storage unit;

[0034] Figures 5A to 5H The diagram illustrates the structural schematics corresponding to each step of a method for fabricating a memory cell according to an embodiment of the present disclosure.

[0035] Figure 6 This illustration schematically shows a flowchart of a data reading operation method of a data manipulation method for a three-dimensional memory according to an embodiment of the present disclosure;

[0036] Figure 7 The flowchart illustrating a data writing operation method of a data manipulation method for a three-dimensional memory according to an embodiment of the present disclosure is shown in the illustration.

[0037] Figure 8 The flowchart illustrating the data erasure operation method of a data manipulation method for a three-dimensional memory according to an embodiment of the present disclosure is shown in the illustration. Detailed Implementation

[0038] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0039] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0040] In describing the embodiments of this disclosure in detail, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure. Furthermore, in actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0041] Embodiments of this disclosure provide a memory cell, including: a stacked layer, stacked on a substrate, including: a plurality of channel vias penetrating the stacked layer and a portion of the substrate; wherein, at least one second stacked material layer in the stacked layer after forming the plurality of channel vias is etched to form an annular confinement structure; a gate dielectric layer, located on the surface of the plurality of channel vias after being etched to form the annular confinement structure; a channel layer, located on the surface of the gate dielectric layer; and a resistive switching layer, located on the surface of the channel layer corresponding to the annular confinement structure; wherein, by controlling the gate voltage applied to at least one second stacked material layer and the bit line pulse signal connected to the channel layer, the resistance state of the resistive switching layer is changed, thereby enabling the memory cell to perform read, write, or erase operations on the resistive switching layer.

[0042] Embodiments of this disclosure provide a memory cell that forms a ring-shaped confinement structure inside a channel via, thereby creating a resistive switching ring structure after the resistive switching layer is deposited. The resistance state of the resistive switching ring can be read by reading the channel current. In the resistive switching ring structure, a sudden drop pulse can be used to achieve majority-bit memory writing and support page writing; a gradual drop pulse can also be used to achieve erase operations and support region erasure.

[0043] The technical solution of this disclosure will be described in detail below with reference to the structure of the storage unit in a specific embodiment of this disclosure. It should be understood that... Figure 1 The material layers, shapes, and structures of the various parts of the storage cell shown are merely exemplary to help those skilled in the art understand the technical solutions of this disclosure, and are not intended to limit the scope of protection of this disclosure.

[0044] Figure 1 The diagram illustrates a partial structural schematic of a cross-section of a storage cell according to an embodiment of the present disclosure.

[0045] like Figure 1 As shown, the storage unit structure of this embodiment includes:

[0046] Substrate 10, which can be a conductive substrate, such as an N-type substrate.

[0047] The stacked layer 20 is stacked on the substrate 10 and includes a plurality of channel holes penetrating the stacked layer 20 and a portion of the substrate 10; wherein, at least one second stacked material layer 202 in the stacked layer after the plurality of channel holes are formed is etched to form a ring-shaped confinement structure.

[0048] The gate dielectric layer 30 is located on the surface of multiple channel holes after being etched to form a ring-shaped confinement structure.

[0049] The channel layer 40 is located on the surface of the gate dielectric layer 30.

[0050] The resistive switching layer 50 is located on the surface of the channel layer 40 corresponding to the annular confinement structure.

[0051] Specifically, by controlling the gate voltage applied to at least one second stacked material layer 202 and the bit line pulse signal connected to the channel layer 40, the resistance state of the resistive switching layer 50 is changed, thereby enabling the memory cell to perform read, write, or erase operations on the resistive switching layer 50.

[0052] According to embodiments of this disclosure, the stacked layer 20 includes multiple stacked pairs, each stacked pair including a first stacked material layer 201 and a second stacked material layer 202, wherein the first stacked material layer 201 and the second stacked material layer 202 are sequentially stacked on the substrate 10. In one example, the first stacked material layer 201 is an insulating layer, such as OX, and the second stacked material layer 202 is a metal dielectric layer, which is a word line layer. The word line layer closest to the substrate 10 in the stacked layer 20 is the lower select layer, and the word line layer furthest from the substrate 10 is the upper select layer. Specifically, an array of vias is formed on the stacked layer 20 by etching. The sacrificial layers corresponding to the lower and upper selective layers can be made of silicon nitride doped with carbon, so that the sacrificial layers corresponding to the lower and upper selective layers are not etched to form a ring-shaped confinement structure during the etching process. The sacrificial layers of the other metal dielectric layers in the second stack material layer 202 can be made of silicon nitride, and are all etched to form a ring-shaped confinement structure during the etching process.

[0053] In embodiments of this disclosure, such as Figure 1 As shown, a gate dielectric layer 30, a channel layer 40, and a resistive switching layer 50 are sequentially grown on the surface of multiple channel holes after etching to form a ring-shaped confinement structure. The resistive switching layer 50 is located on the surface of the channel layer 40 corresponding to the ring-shaped confinement structure to form a resistive switching ring structure. This resistive switching ring exhibits different resistance states under different pulse excitations. The resistive switching layer 50 is composed of a resistive switching material or a phase change material, such as GST or HfO2.

[0054] Specifically, the channel layer 40 is an N-type semiconductor channel layer, which can be an N-type polycrystalline or single-crystal semiconductor channel layer. The channel layer 40 is composed of materials such as silicon, germanium, germanium-silicon, or III-V group semiconductors, or other materials with semiconductor switching characteristics, such as NZO or graphene. It forms a MOS structure with the word line layer through an insulating layer. Figure 1 As shown, each channel hole penetrates the stacked layer 20 and a portion of the substrate 10, forming an array of common sources.

[0055] In embodiments of this disclosure, an insulating layer 202 is filled in the channel after the growth of the resistive switching layer 50, the insulating layer 202 serving as an isolation layer.

[0056] The number of layers in the storage unit is positively correlated with the number of layers in the second stacked material layer. That is, the more layers in the second stacked material layer, the more layers the storage unit has. The specific number of layers is not limited in the embodiments disclosed herein, and can be 512 layers, 1024 layers, etc., and can be set according to the actual application requirements.

[0057] In the embodiments of this disclosure, both the word line layer and the bit line layer are small-sized metal lines, such as... Figure 1 As shown, the word line layer 202 is in the same direction as the substrate 10 in the y-axis direction, and it can cover multiple strings in the x-axis direction, such as 9 strings, 16 strings, 19 strings, etc. The word line layer 202 is connected to the gate dielectric layer 30 and is used to provide a bias voltage to the gate dielectric layer 30. The bit line 60 is connected to the drain layer of the memory cell and provides a pulse signal to the drain layer. Each bit line 60 can control one or more strings at the same time. The embodiments of this disclosure do not limit this.

[0058] like Figure 2 The diagram shown is another structural schematic of the storage unit according to an embodiment of this disclosure. This structure is similar to... Figure 1 The difference in the storage cell structure shown is that a resistive switching thin film connection layer (i.e., a partial residual resistive switching layer 50) is left in the area outside the resistive switching ring. This connection layer is a process residue and is always in a high-resistivity state. Moreover, this connection layer does not participate in data reading, writing or erasing operations.

[0059] Figure 3 The intention shows according to Figure 1 A schematic diagram showing the current flow direction when a storage unit performs data reading or writing operations.

[0060] like Figure 3 As shown, when performing a data read operation, the memory cell is configured to: ground the gate layer of unselected memory cells, apply a negative gate voltage to the gate layer of selected memory cells (such as the memory cell selected in region 100), apply a bias voltage to the drain layer (such as the memory cell selected in region 200), ground the substrate, and sense the resistance state change of the resistive switching layer of the selected memory cell to read data, specifically reading the channel current I. ds The data state of the selected memory cell is given. Preferably, the negative gate voltage range is below -3V, and the bias voltage applied to the drain layer can be 0.5V to 1.5V.

[0061] Specifically, by applying a negative gate voltage to the gate layer of the selected memory cell, the negative gate voltage in the corresponding memory cell shuts down the channel corresponding to the resistive switching ring (e.g., Figure 3(As indicated by "A" in the diagram, the channel is closed). When an unselected memory cell is grounded, all corresponding channels are open, and the current read is determined by the state of the selected resistor ring. For example, when the resistor ring is in a high-resistance state, the read current is 0, 00, or 000; when the resistor ring is in a certain resistance state, the read current is a corresponding numerical value, such as 01, 10, 010, 011, or 0111; when the resistor ring is in the lowest resistance state, the read current is 1, 11, or 111. It should be noted that the number of bits representing the specific current state is related to the number of bits in the memory cell. When the memory cell is a multi-bit memory cell, the read current value is also multi-bit. The memory cells provided in the embodiments of this disclosure support multi-bit storage.

[0062] like Figure 3 As shown, when the memory cell performs a data write operation, the word line selection of the memory cell is as follows: when performing a data read operation, the gate layer of the unselected memory cell is grounded, a negative gate voltage is applied to the gate layer of the selected memory cell (such as the memory cell selected in region 100), a write pulse is applied to the drain layer (such as the memory cell selected in region 200), and the substrate is grounded. The write pulse is sufficient to cause the memory cell to tunnel, so that electrons are stored in the memory cell.

[0063] Specifically, the write pulse is a current pulse or a potential difference pulse, which changes the resistance state of the reverse converter by rapidly decreasing the channel current pulse or potential difference pulse. For example, the write pulse can be a current pulse with an amplitude of 2.0 mA and a waveform of 5 / 60 / 5 ns or 5 / 45 / 3 ns. Under this pulse, the corresponding resistance state of the reverse converter can be 10. 3 Ω, corresponding to a data level of 00, and other data levels in the same memory cell are formed by a resistor of approximately 10. 4 Ω, 10 5 Ω and 3×10 5 Ω, which correspond to data levels 01, 10, and 11, respectively. Embodiments of this disclosure support page writing by connecting write pulses via bit lines and simultaneously selecting multiple bit lines.

[0064] When performing data writing operations, the storage cell provided in the embodiments of this disclosure does not limit the amplitude of the current pulse, which can also be 2.8mA, 3.1mA, or 3.5mA, etc., and the waveform is not limited to 5 / 60 / 5ns or 5 / 45 / 3ns, etc. Furthermore, the data level corresponding to the resistive state of the aforementioned resistive switching ring is merely an example and does not constitute a limitation of the embodiments of this disclosure. Its specific value depends on the resistive switching ring material, the applied pulse size, and the number of bits of the writable storage cell in actual application. The embodiments of this disclosure do not limit this.

[0065] like Figure 4As shown, when the memory cell performs a data erase operation, the word line selection of the memory cell is as follows: when implementing a data read operation, the gate layer of the unselected memory cell is grounded, a negative gate voltage is applied to the gate layer of the selected memory cell (such as the memory cell selected in region 100), and an erase pulse is applied to the drain layer of the memory cell. The erase pulse is sufficient to cause the three-dimensional memory to tunnel.

[0066] Specifically, the erase pulse is a current pulse or a potential difference pulse. By gradually decreasing the channel current pulse or potential difference pulse, all resistive switching rings on the same word line layer can be erased simultaneously, supporting block erase. For example, the erase pulse can be a positive voltage pulse with an amplitude of 1.5V and a waveform of 5 / 50 / 5ns. Under this pulse, all programmed data states are erased, such as erasing 00, 01, and 10 to form data state 11 (SET state), etc.

[0067] In the embodiments of this disclosure, the resistive switching rings formed by the resistive switching layer 50 are physically isolated and do not interfere with each other. By using negative voltage operation on the word lines, there is no write interference to non-corresponding resistive switching rings, thus achieving no coupling interference between word lines.

[0068] The storage unit provided in the embodiments of this disclosure does not limit the amplitude of the voltage pulse during data erasure operations; it can also be a voltage pulse of other amplitudes and waveforms. Furthermore, the resistance state of the resistor-variable ring to be erased described above is merely illustrative and does not constitute a limitation of the embodiments of this disclosure. The specific values ​​to be erased and the number of bits of the erasable storage unit are set according to the actual application process, and the embodiments of this disclosure do not limit this.

[0069] The storage unit provided in the embodiments of this disclosure can realize the selection of word lines and bit lines and the setting of applied voltage bias or pulse signals through the logic control unit, thereby efficiently realizing operations such as area erasure and page writing.

[0070] Figures 5A to 5H The schematic diagram illustrates the structure corresponding to each step of a method for fabricating a memory cell according to an embodiment of the present disclosure. The structure of the memory cell fabricated by this method is as follows: Figure 1 or Figure 2 As shown.

[0071] like Figures 5A to 5H As shown, the method for fabricating this memory cell includes:

[0072] Step 501, as follows Figure 5A As shown, multiple channel holes are fabricated in the stacked layer 20 above the substrate 10. The number of channel holes can be multiple, and can be any number of 1, 2, 3, ...

[0073] Step 502, as follows Figure 5BAs shown, in the stacked layers after forming multiple channel holes, at least one sacrificial layer is etched to form a ring-shaped confinement structure.

[0074] Specifically, such as Figure 5B As shown, the stacked layer 20 includes multiple stacked layers, each stacked layer including a first stacked material layer 201 and a second stacked material layer 202'. The first stacked material layer 201 is an insulating layer, and the second stacked material layer 202' is a sacrificial layer. The word line layer in the second stacked material layer 202' that is closest to the substrate 10 is used as the lower select layer, and the word line layer that is farthest from the substrate 10 is used as the upper select layer. The sacrificial layers corresponding to the lower select layer and the upper select layer can be made of silicon nitride doped with carbon, so that the sacrificial layers corresponding to the lower select layer and the upper select layer are not etched to form a ring-shaped confinement structure during the etching process. The other sacrificial layers in the second stacked material layer 202', except for the lower select layer and the upper select layer, can be made of silicon nitride, and they are all etched to form a ring-shaped confinement structure.

[0075] Step 503, as follows Figure 5C As shown, a gate dielectric layer 30, a channel layer 40, and a resistive switching layer 50 are sequentially formed on the surface of each channel hole after being etched to form a ring-shaped confinement structure.

[0076] Step 504, as follows Figure 5D As shown, the resistive switching layer 50 is removed except for the resistive switching layer 50 corresponding to the annular confinement structure, so that the resistive switching layer 50 is provided only at the location corresponding to the annular confinement structure, and the resistive switching layer 50 forms a resistive switching ring structure.

[0077] In the embodiments of this disclosure, the fabrication process of the storage cell may also omit step 504. Since the resistive switching thin film connecting layer (i.e., the partially residual resistive switching layer 50) is left on the area outside the resistive switching ring, the connecting layer is always in a high-resistivity state and does not participate in data reading, writing or erasing operations. That is, step 504 may or may not be set.

[0078] Step 505, as follows Figure 5E As shown, an insulating material layer 201 is filled inside each channel hole without a material layer.

[0079] Step 506, as follows Figure 5F As shown, bit line leads are formed at the top of a portion of the channel layer 40.

[0080] Step 507, as follows Figure 5G As shown, the sacrificial layer 202' in the stacked layer 20 is etched and replaced to form a second stacked material layer 202, which is a metal dielectric layer and is a word line layer.

[0081] Step 508, as follows Figure 5HAs shown, metal is deposited and bit lines 60 are formed, completing the fabrication of the memory cell.

[0082] Figure 5H The schematic diagram is as follows: Figure 1 The structural diagram shown is illustrated. Figure 5H In this context, it is understandable that the process for removing parts of the structure is not limited to the wet etching and photolithography processes mentioned above. It can be a combination of the two or other dry or wet etching processes.

[0083] It should be noted that the structure of the memory cell prepared by the above-described process in the embodiments of this disclosure is as follows: Figure 1 As shown, the specific layer thickness is set according to the actual application. Furthermore, the embodiments of the above steps are merely examples illustrating how to fabricate the memory cell of this disclosure on existing conventional device structures. In this disclosure, any fabrication process capable of forming the various structural components and their relative positions of the aforementioned memory cell is within the scope of protection of this disclosure.

[0084] In another exemplary embodiment of this disclosure, a three-dimensional memory is provided, comprising any of the memory cells mentioned in this disclosure.

[0085] In this embodiment, the three-dimensional memory further includes a logic control unit, the memory cell being interfaced with the front side of the logic control unit. The three-dimensional memory can be a three-dimensional NAND flash memory.

[0086] In this embodiment, the selection of word lines and bit lines, as well as the setting of applied voltage bias or pulse signals, can be realized through the logic control unit, thereby realizing operations such as area erasure and page writing respectively.

[0087] In yet another exemplary embodiment of this disclosure, a method for operating a three-dimensional memory as described above is provided, comprising: controlling the voltage bias applied to the substrate, drain layer and gate layer of a portion of the memory cells in the three-dimensional memory, and performing data writing, reading and erasing operations on the portion of the memory cells in the three-dimensional memory respectively.

[0088] The operation method includes a data reading operation method, a data erasing operation method, and a data writing operation method. There is no fixed execution order among the data reading operation method, the data erasing operation method, and the data writing operation method.

[0089] like Figure 6 As shown, the data reading operation method includes the following steps:

[0090] Step S601: Trigger the data reading program.

[0091] Step S602: Apply a negative gate voltage to the gate layer of the selected memory cell to turn off its corresponding channel; ground the gate layer and substrate of the unselected memory cell.

[0092] Step S603: Apply a bias voltage to the drain layer of the memory cell.

[0093] Step S604: Sensing the resistance state of the resistive switching layer of the selected memory cell to determine the data state of the memory cell.

[0094] In this embodiment, when performing data read operations on the memory, the configuration of each drain layer, substrate, and gate layer is as shown in the above embodiment, and will not be described in detail here.

[0095] like Figure 7 As shown, the data writing operation method includes the following steps:

[0096] Step S701: Trigger the data writing program.

[0097] In step S702, the gate layer of the unselected memory cell is grounded, and a negative gate voltage is applied to the gate layer of the selected memory cell.

[0098] Step S703: Ground the substrate.

[0099] Step S704: A write pulse is applied to the drain layer of the memory cell. The write pulse is sufficient to cause the memory cell to tunnel, so that electrons are stored in the memory cell.

[0100] In this embodiment, when performing data writing operations on the memory, the configuration of each drain layer, substrate, and gate layer is as shown in the above embodiment, and will not be described in detail here.

[0101] like Figure 8 As shown, the data erasure operation method includes the following steps:

[0102] Step S801: Trigger the data erasure procedure.

[0103] In step S802, the gate layer of the unselected memory cell is grounded, and a negative gate voltage is applied to the gate layer of the selected memory cell.

[0104] Step S803: An erase pulse is applied to the drain layer of the memory cell, and the erase pulse is sufficient to cause the three-dimensional memory to tunnel.

[0105] In this embodiment, when performing a data erasure operation on the memory, the configuration of each drain layer, substrate, and gate layer is as shown in the above embodiment, and will not be described in detail here.

[0106] It should be noted that the operation method is not limited to these steps, and other steps that are omitted can be adjusted according to the actual situation.

[0107] As can be seen from the above description, the embodiments of this disclosure achieve at least the following technical effects:

[0108] 1) The present disclosure provides a memory cell that uses an N-type semiconductor channel and selects the memory cell by turning off the corresponding channel through word line negative voltage.

[0109] 2) By forming a ring-shaped confinement structure inside the channel hole, a resistive switching ring structure is formed after the resistive switching layer is deposited. The corresponding resistive switching ring resistance state can be read by reading the channel current.

[0110] 3) In the resistive variable ring structure, the majority bit storage writing is achieved by means of a sudden drop pulse, and page writing is also supported.

[0111] 4) In the resistive variable ring structure, the erasure operation is achieved by means of a slow-falling pulse, as well as the erasure of the support area.

[0112] Although the present disclosure has been illustrated and described in detail in the accompanying drawings and the foregoing description, such illustrations and descriptions should be considered illustrative or exemplary rather than limiting.

[0113] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0114] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents.

Claims

1. A storage unit, characterized in that, include: A stacked layer, stacked on a substrate, includes: a plurality of channel holes penetrating the stacked layer and a portion of the substrate; wherein, at least one second stacked material layer in the stacked layer after the plurality of channel holes are formed is etched to form a ring-shaped confinement structure; A gate dielectric layer is located on the surface of the plurality of channel holes after the annular confinement structure has been etched to form the annular confinement structure; The channel layer is located on the surface of the gate dielectric layer; A resistive switching layer is located on the surface of the channel layer corresponding to the annular confinement structure; The channel layer is an N-type semiconductor channel layer, and the substrate is an N-type substrate; Specifically, by controlling the negative gate voltage applied to the at least one second-layer stacked material layer and the bit line pulse signal connected to the channel layer, the resistance state of the resistive switching layer is changed, thereby enabling the memory cell to perform read, write, or erase operations on the resistive switching layer; the selection of the memory cell is achieved by turning off the corresponding channel through word line negative voltage.

2. The storage unit according to claim 1, characterized in that, The stacked layer includes multiple stacked pairs, each stacked pair including a first stacked material layer and a second stacked material layer, wherein the first stacked material layer and the second stacked material layer are sequentially stacked on the substrate.

3. The storage unit according to claim 2, characterized in that, The first stacked material layer is an insulating layer, and the second stacked material layer is a metal dielectric layer, which is a word line layer.

4. The storage unit according to claim 1, characterized in that, The number of layers in the second stacked material layer is positively correlated with the number of layers in the storage cell.

5. The storage unit according to claim 1, characterized in that, The resistive switching layer is composed of resistive switching material or phase change material.

6. The storage unit according to claim 1, characterized in that, An array of common sources formed by multiple channel holes penetrating the stacked layers and part of the substrate.

7. The storage unit according to claim 1, characterized in that, The channel layer is an N-type polycrystalline or monocrystalline semiconductor channel layer.

8. The storage unit according to claim 1, characterized in that, Also includes: An insulating material layer is located inside the plurality of channel holes where no material layer is provided.

9. The storage unit according to claim 1, characterized in that, The storage cell is configured such that, when performing a data read operation on the three-dimensional cell, current flows from the drain layer of the storage cell to the substrate.

10. The storage unit according to claim 9, characterized in that, The storage unit is configured as follows: When performing a data read operation on the memory cell, a bias voltage is applied to the drain layer and the substrate is grounded; The gate layer of the unselected memory cell is grounded, and a negative gate voltage is applied to the gate layer of the selected memory cell. The resistance state of the resistive switching layer of the selected memory cell is sensed to determine the data state of the memory cell.

11. The storage unit according to claim 1, characterized in that, The storage unit is configured as follows: When performing a data write operation on the memory cell, the gate layer of the unselected memory cell is grounded, and a negative gate voltage is applied to the gate layer of the selected memory cell. Ground the substrate; A write pulse is applied to the drain layer of the memory cell, the write pulse being sufficient to cause the memory cell to tunnel, thereby storing electrons in the memory cell.

12. The storage unit according to claim 1, characterized in that, The storage unit is configured as follows: When performing an erase operation on the memory cell, the drain layer of the memory cell is floated or grounded, and an erase pulse is applied to the drain layer of the memory cell. The erase pulse is sufficient to cause the three-dimensional memory to tunnel.

13. A method for fabricating a memory cell, characterized in that, include: A stacked layer is formed on the substrate; Multiple channel holes are formed on the stacked layers and a portion of the substrate, and at least one sacrificial layer in the stacked layers after the multiple channel holes are formed is etched to form a ring-shaped confinement structure; On the surface of each channel hole after the ring-shaped confinement structure is etched, a gate dielectric layer, a channel layer, and a resistive switching layer are sequentially formed. The interior of each channel hole, where no material layer is provided, is filled with an insulating material layer; A bit line lead-out end is formed at the top of a portion of the channel layer; The sacrificial layer in the stacked layers is etched and replaced to form the second stacked material layer; The channel layer is an N-type semiconductor channel layer, and the substrate is an N-type substrate; Specifically, by controlling the negative gate voltage applied to the at least one second-layer stacked material layer and the bit line pulse signal connected to the channel layer, the resistance state of the resistive switching layer is changed, thereby enabling the memory cell to perform read, write, or erase operations on the resistive switching layer; the selection of the memory cell is achieved by turning off the corresponding channel through word line negative voltage.

14. A three-dimensional memory, characterized in that, include: The storage unit as described in any one of claims 1 to 12.

15. A method for operating a three-dimensional memory as described in claim 14, characterized in that, include: The voltage bias applied to the substrate, drain layer and gate layer of some memory cells in the three-dimensional memory is controlled, and data writing, reading and erasing operations are performed on some memory cells in the three-dimensional memory respectively.

16. The operating method according to claim 15, characterized in that, The data reading operation on a portion of the storage units in the three-dimensional memory includes: Trigger the data reading program; A negative gate voltage is applied to the gate layer of the selected memory cell to turn off its corresponding channel; The gate layer and the substrate of the unselected memory cell are grounded; A bias voltage is applied to the drain layer of the memory cell; The resistance state of the resistive switching layer of the selected memory cell is sensed to determine the data state of the memory cell.

17. The operating method according to claim 15, characterized in that, The data writing operation to a portion of the storage cells in the three-dimensional memory includes: Trigger the data writing program; The gate layer of the unselected memory cell is grounded, and a negative gate voltage is applied to the gate layer of the selected memory cell. Ground the substrate; A write pulse is applied to the drain layer of the memory cell, the write pulse being sufficient to cause the memory cell to tunnel, thereby storing electrons in the memory cell.

18. The operating method according to claim 15, characterized in that, The data erasure operation on a portion of the storage cells in the three-dimensional memory includes: Trigger the data erasure procedure; The gate layer of the unselected memory cell is grounded, and a negative gate voltage is applied to the gate layer of the selected memory cell. An erase pulse is applied to the drain layer of the memory cell, the erase pulse being sufficient to induce a tunneling effect in the three-dimensional memory.

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