Apparatus for programming of electronic devices

Abstract

An apparatus (10; 14; 16; 18) for programming an electronic device (12) (particularly for ISP, ICP or PP programming) includes: an electronic processing unit (20; 45) adapted to process and manage at least one programming algorithm of the electronic device (12); a programming unit (11) connected to the processing unit (20; 45) and the electronic device (12) for receiving programming data from the processing unit (20; 45) and sending the programming data to the electronic device (12) via a predetermined communication protocol; an interface unit (25) associated with the processing unit (20; 45) and the electronic device (12); and a non-volatile electronic storage unit (23; 22) adapted to exchange data with the electronic processing unit (20; 45) via at least one bidirectional data communication line (32, 31).

Description

Technical Field

[0001] This invention relates to an apparatus for programming electronic devices and related programming methods.

[0002] In particular, the apparatus according to the invention can be used for ICP (In-Circuit Programming), ISP (In-System Programming), or PP (Pre-Programming) type programming of electronic devices, such as microcontrollers, microprocessors, non-volatile memory, flash memory, serial memory, or other memories, which may have been: assembled (ICP, ISP) on the electronic device, such as, but not limited to, mobile phones, electronic control units, and digital cameras; or not assembled (PP), as will be explicitly referred to below without loss of generality. Background Technology

[0003] Known programming devices are used, for example but not limited to, ICP, ISP or PP programming in the prototyping stage or final production stage (by downloading an application or predetermined dataset onto a microcontroller, microprocessor and / or nonvolatile electronic memory that has been assembled on a printed circuit or electronic device or has not yet been assembled).

[0004] Such known programming devices include at least one processing unit or CPU (central processing unit), typically a microprocessor or microcontroller, designed to process and manage electronic device programming algorithms based on its specific type or family. In effect, the first processing unit is programmed with specific code specifically designed to program a predetermined type of device (e.g., a specific family of microprocessors or non-volatile memory). Therefore, the programming algorithm is implemented based on the specific hardware architecture of the electronic device to be programmed, such as the specific internal structure of the memory address space (in the case of a microcontroller, microprocessor, or memory), or the device's addresses, such as serial ports, I2C ports, ADC ports, counters, or hardware or other "timers" (in the case of a microcontroller or microprocessor).

[0005] The programming device also includes at least one field-programmable device or FPD (Field Programmable Device), such as an FPGA (Field Programmable Gate Array) device, which is connected to the processing unit on one side and to at least one programming port on the other side for ISP, ICP or PP programming, which can be selectively connected to an electronic board or electronic device, thereby connecting to the electronic device to be programmed.

[0006] As an example, but not limited to, it is possible to use a processing unit consisting of a microprocessor unit or Hard Processor System (HPS) unit and a programmable unit or FPD unit (FPGA) in a single electronic component. This allows for limiting the necessary space on the printed circuitry of the programming system and provides a very fast and efficient communication channel between the two component units.

[0007] The FPGA portion of the processing unit is configured to receive programming data from the electronic device from the HPS portion of the processing unit, for example, in block order, and transmit it to the electronic device to be programmed via a programming port based on a predetermined ICP, ISP, or PP communication protocol. Therefore, the FPGA portion of the processing unit is specifically programmed to manage the communication protocol and associated data streams and control signals.

[0008] This programming device also provides a connection to an electronic processor equipped with a suitable user interface for selecting one or more files related to the program or programming data of the electronic device to be programmed and transmitting them to the device itself. This connection is typically achieved via a data communication line, such as an RS232 serial line, parallel line, USB line, Ethernet line, or other line connected to the processing unit.

[0009] A known drawback of programming devices is that, in applications requiring high programming speeds, a communication line of finite length and well-defined electrical characteristics must be provided between the programming system and the device to be programmed. This may also necessitate modifications to the characteristics of the communication line based on the device to be programmed and the board on which it is mounted. This results in high costs and long integration times for the programming system.

[0010] Another drawback of known programming devices is that, in cases where large amounts of configuration data need to be downloaded into the device to be programmed, the programming system must provide non-volatile memory capacity commensurate with such data volume. In fact, a lack of non-volatile memory capacity may necessitate the exchange of large amounts of data between the electronic processor and the programming system, leading to increased programming time. Summary of the Invention

[0011] Therefore, the object of the present invention is to overcome the significant limitations of the known art devices highlighted above.

[0012] In particular, the object of this invention is an architecture for the entire programming system capable of supporting various communication possibilities between processing units and interface blocks. This allows the programming system to be easily integrated and adapted to production environments and constantly changing operating conditions.

[0013] Another object of the present invention is to improve the transmission speed of data sent from the processing unit to the interface block and from the interface block to the processing unit. This results in a reduction in device programming time.

[0014] Another objective of this invention is to protect the integrity of data sent from the processing unit to the interface block and data sent from the interface block to the processing unit. This translates into greater robustness of the programming system.

[0015] Another object of the present invention is to allow large amounts of data to be stored within the programming system, so as to allow faster and more efficient access to the data to be downloaded to the device to be programmed.

[0016] According to the present invention, an apparatus for programming an electronic device is provided, particularly for ISP, ICP, or PP programming. The apparatus includes: a processing unit suitable for processing and managing at least one programming algorithm of the electronic device; an electronic processor connected to the processing unit and the electronic device, the electronic processor being configured to receive programming data from the processing unit and to transmit the programming data to the electronic device via a predetermined communication protocol; and a non-volatile electronic memory adapted to exchange data with the processing unit via at least one bidirectional data communication line. The apparatus further includes: a first communication block configured to communicate via a set of bidirectional single-ended lines. The communication interface exchanges data with the processing unit; and a secondary external unit, which can be connected to the first communication block via another communication interface consisting of bidirectional differential data lines, and which can be connected to the electronic device via a data communication line; the secondary external unit includes a second communication block and an interface block connected together by bidirectional single-ended lines; wherein, the first communication block is configured to convert the bidirectional single-ended lines of the communication interface into the bidirectional differential data lines of the other communication interface, and the second communication block is configured to convert the bidirectional differential data lines of the other communication interface into the bidirectional single-ended lines connecting the second communication block and the interface block together. Attached Figure Description

[0017] The structural and functional features of the present invention and its advantages over known technologies will become more apparent from the following description, which is made with reference to the accompanying drawings illustrating some preferred but non-limiting embodiments of a device for programming electronic devices, in which:

[0018] - Figure 1 This is a block diagram schematically illustrating an implementation where the device to be programmed is connected to the programming system via a bidirectional single-ended wire;

[0019] - Figure 2 This is a block diagram schematically illustrating an implementation where the device to be programmed is connected to the programming system via bidirectional differential parallel lines;

[0020] - Figure 3 This is a block diagram schematically illustrating an implementation method in which the device to be programmed is connected to the programming system via a bidirectional differential high-speed serial line;

[0021] - Figure 4 This is a block diagram schematically illustrating an implementation where the device to be programmed is connected to a programming system via a bidirectional differential high-speed serial line; in the latter implementation, the high-speed serialization / deserialization procedure is integrated into the processing unit of the programming system. Detailed Implementation

[0022] In accordance with the above objectives, an apparatus for programming electronic devices, particularly for ISP, ICP, or PP programming, includes an HPS processing unit that prepares one or more programming algorithms for processing and managing the corresponding electronic device to be programmed.

[0023] The programming apparatus according to the invention further includes a programmable field unit or FPD, such as an FPGA unit, which is connected to or forms part of the HPS processing unit and is operatively associated with at least one electronic device to be programmed. The FPGA unit is arranged to receive processed programming data from the HPS processing unit and to transmit it to the electronic device to be programmed based on a predetermined communication protocol.

[0024] The device also includes at least one interface block associated with a relevant programming interface of the processing unit for connecting electronic devices to be programmed.

[0025] According to one aspect of the invention, the field-programmable unit or FPD (especially the programmable FPGA unit) is provided with a plurality of logic ports, which are selectively programmed and / or dynamically programmable to manage the one or more algorithms to be programmed via an output interface using ICP, ISP or PP (depending on the specific electronic device to be programmed).

[0026] Therefore, using an FPD unit (especially an FPGA unit) that is programmed as needed to act as a predetermined processing unit for managing at least one specific programming algorithm allows the same circuit to be maintained as a programming board to perform programming of electronic devices (even completely different electronic devices) at different times.

[0027] According to a variant of the invention, the programming device further includes an auxiliary processing unit associated with the programmable type unit or FPD unit, which is arranged to load predetermined configuration data thereon. This configuration data relates at least to the desired programming of the logic ports of the FPD unit and one or more programming algorithms.

[0028] According to another aspect of the invention, each output interface is connected to the auxiliary processing unit to be selectively programmed by it according to specific operating parameters depending on the electronic device.

[0029] The following falls within the spirit of the invention: a programming device includes a reading unit connected to a processing unit, and a non-volatile electronic storage unit selectively associated with the processing unit, in which configuration data is stored. Therefore, by association, i.e., by selectively inserting a storage unit such as an SD flash card or micro SD into the reading unit, it is possible to configure (possibly each time power is applied) the desired configuration data for the programming device to allow programming of a particular electronic device.

[0030] According to another variation, the programming device includes a volatile electronic storage unit connected to the processing unit for temporarily storing the configuration data.

[0031] According to another variation, the programming device includes a non-volatile electronic storage unit with a large storage capacity and the possibility of accessing it for high-speed read and write. The non-volatile electronic storage unit is connected to the processing unit, particularly to the FPGA section, for storing the configuration data.

[0032] According to another variation, the programming device includes at least one input interface associated with the processing unit for connecting to an electronic processor to receive from it at least data relating to one or more programming algorithms and programming data for the electronic device to be programmed.

[0033] In this way, it is possible, for example, to dynamically select the pre-defined file, specific programming algorithm, and associated programming interface related to the program of the electronic device to be programmed through the user interface of the electronic processor.

[0034] According to a variation of the invention, when the relevant interface block is running near the programmable unit, each programming interface (particularly the FPGA portion) on the processing unit can be directly connected to the relevant interface block via a bidirectional single-ended line. As a non-limiting example, this applies when the interface block is located on the same printed circuit board as the programmable unit or FPD unit.

[0035] According to a variation of the invention, after appropriately converting bidirectional single-ended lines to bidirectional differential lines, each programming interface on a programmable type unit or FPD unit can be connected to a secondary external unit via a connecting cable. The secondary unit consists of a block for converting bidirectional differential lines to bidirectional single-ended lines and an associated interface block connected to the device to be programmed. As a non-limiting example, the connecting cable consists of bidirectional differential data lines from lines carrying one or more power supply voltages and a ground line. According to a variation of the invention, each programming interface on a programmable type unit or FPD unit can take the form of at least one high-speed bidirectional differential serial line connected to the secondary external unit. As a non-limiting example, this is permitted by a particular type of programmable unit or FPD unit that integrates a high-speed serialization and deserialization system coupled to the high-speed bidirectional differential line. As a non-limiting example, the connecting cable to the secondary external unit consists of at least one bidirectional differential high-speed serial data line, lines carrying one or more power supply voltages, and a ground line. The secondary unit consists of a block for converting high-speed bidirectional differential serial lines to bidirectional single-ended lines and an associated interface block connected to the device to be programmed.

[0036] According to a variation of the invention, each programming interface on a programmable type unit or FPD unit can be connected to a high-speed serialization and deserialization unit via a parallel bus consisting of single-ended bidirectional lines. As a non-limiting example, the high-speed serialization and deserialization unit can consist of another programmable unit or FPD unit integrating a high-speed serialization and deserialization system, which allows connection to a secondary external unit via a high-speed bidirectional differential serial line. As a non-limiting example, the connection cable to the secondary external unit consists of at least one bidirectional differential high-speed serial data line, a line carrying one or more power supply voltages, and a ground line. The secondary unit consists of a block for converting the high-speed bidirectional differential serial line to bidirectional single-ended lines and an associated interface block connected to the device to be programmed. The invention also covers a programming method for electronic devices, particularly for ICP, ISP, or PP type programming of microprocessors, microcontrollers, serial memories, flash memory, etc.

[0037] The process according to the invention includes a programming step, wherein at least one predetermined programming algorithm associated with programming data of a specific electronic device to be programmed is processed and managed by a processing unit. In this stage, the programming data processed by the algorithm is sent to a programmable FPGA portion of the processing unit, which is operatively associated with the electronic device to be programmed. The programming data is transmitted from the FPGA unit to the associated electronic device via its associated output interface, based on a predetermined and specific communication protocol (depending on the type of device to be programmed).

[0038] According to one aspect of the invention, the programming method includes an initialization step, wherein a processing unit (particularly an FPGA portion) is selectively programmed in the field such that at least a portion of its logic ports is configured to simulate the desired and specific operation of a microcontroller or microprocessor arranged to manage and process the programming algorithm.

[0039] According to a variation of the invention, at least the configuration data is unloaded during the initialization step via a non-volatile electronic storage unit operatively connected to the processing unit.

[0040] According to a further variation, the configuration data is read by a reading unit connected to a processing unit, and a non-volatile electronic storage unit is selectively associated with the reading unit, in which the configuration data is stored.

[0041] Now let's get into the specific details; please refer to the attached document. Figure 1 , Figure 2 , Figure 3 and Figure 4 The device 10 according to the invention can be used to program electronic devices in at least one electronic device 12, particularly for programming of the type of In-System Programming (ISP), In-Circuit Programming (ICP), or Pre-Programming (PP), such electronic devices as microcontrollers, microprocessors, serial flash memory, etc., which can be programmed directly on the circuit or electronic board 13 of electronic devices such as cellular phones, electronic control units, cameras or digital cameras in the case of ISP and ICP, or unassembled in the case of PP.

[0042] The device in question can be advantageously, but not exclusively, used during the prototyping phase of a new device to allow for any reprogramming of the application code in the device to be programmed.

[0043] The following will describe Figure 1 The implementation method is shown. In Figure 2 , Figure 3 and Figure 4 In the other embodiments shown, the differences from the previous embodiments will be described.

[0044] The device 10 includes a processing unit 20, a programmable type unit 25 or an auxiliary unit, a first volatile electronic memory 21, a second non-volatile electronic memory 22, a third non-volatile electronic memory 23 and at least one interface block 25.

[0045] Processing unit 20 integrates a processor section (HPS) and an FPD section (FPGA). The FPD section (FPGA) of unit 20 is a programmable field cell whose logic ports can be selectively programmed in a dynamic manner, as will be better described below, in order to emulate a specific CPU (central processing unit) that can manage specific algorithms related to programming data for a specific electronic device 12 to be programmed each time.

[0046] Processing unit 20 is connected to different components of device 10, as described below:

[0047] - Connected to the first electronic memory 21 via a bidirectional data communication line 30, which may be, for example, SRAM (Static Random Access Memory) or SDRAM (Synchronous Dynamic Random Access Memory), which has fast access capability for temporary storage of programming data or specific data user parameters used during programming;

[0048] - Connected to a second electronic memory 22 via a bidirectional data communication line 31, which may be, for example, a fast-access eMMC (embedded multimedia card) for non-volatile storage of programming data or specific user parameters used during programming.

[0049] - Connected to a third electronic memory 23 via a bidirectional data communication line 32, which may be, for example, a non-volatile SD or micro SD for storing configuration data, programming data, or specific user parameters used during programming of the programmable unit FPD;

[0050] - Connected to interface block 25 via bidirectional data bus 29 for sending or receiving data based on a predetermined communication protocol, which is dynamically determined based on the programmed electronic device 12;

[0051] - Connected to the auxiliary programmable unit 24 via data bus 33, for sending configuration parameters dynamically selected based on the programmed electronic device 12 to the interface block 25.

[0052] The processing unit 20 can also be selectively connected to the electronic processor 11, such as a personal computer, laptop computer, etc., via a serial line UART (Universal Asynchronous Receiver-Transmitter) 27 or a proprietary communication line 28. The electronic processor 11 is provided with sufficient user interfaces.

[0053] The second electronic memory 22 is a non-volatile memory with high storage capacity and high read / write access speed. Preemptive loading of programming data into this memory allows access to the programming data during the programming phase of the electronic device 12 without the need for communication lines 27 and 28 to the electronic processor. This results in a reduction in the programming time of the electronic device 12.

[0054] The third electronic memory 23 is a selectively removable, non-volatile type of electronic memory, such as an SD (Storage Device) or microSD memory (not labeled) inserted into a corresponding slot, and is arranged for specific configuration parameters of the storage device 10, particularly specific configuration parameters of the FPD programmable portion of unit 20. Therefore, the removal of memory 23 and its reprogramming, or replacement with a different memory 15 having different storage content, makes it possible to substantially modify the device's configuration parameters based on the programmable electronics 12 each time power is applied.

[0055] Interface block 25 is arranged to define the correct levels of electrical signals and specific signal lines for programming a particular device 12. In practice, interface block 25 is connected to processing unit 20 on one side and to the electronic device 12 to be programmed via communication line 26 on the other side.

[0056] The communication line 26 includes a set of predetermined electrical conductors, the number of which may vary depending on the type of electronic device 12 being programmed each time. Advantageously, the communication line 26 is connected to an electrical and mechanical adapter (not shown), which in turn is physically connected to the electronic device 12 to be programmed, allowing the definition of desired and specific electrical programming signals compatible with the electronic device 12.

[0057] Interface block 25 includes, in particular, a set of unindicated predetermined elements that can be selectively and dynamically configured by processing unit 20 via interface 29 to establish predetermined electrical connections with electronics 12 during operation in the direction of a specific programmed signal.

[0058] Interface block 25 also includes a dynamically configurable system for the processing unit 20 to select the input and output voltage levels of a specific programming signal (not shown) via interface 29, so as to establish a predetermined electrical connection with the electronics 12 depending on the voltage level of the specific programming signal.

[0059] Interface block 25 also includes a system for defining the input and output behavior of a specific programming signal (not shown), which can be selectively and dynamically configured by programmable unit 24 via interface 34 to establish a predetermined electrical connection with electronics 12 depending on the configuration of pull-up or pull-down conditions of the specific programming signal.

[0060] As described below, the processing unit 20 is programmed (as described below) to define different functional blocks, as follows:

[0061] - The first block 101 manages data communication via UART serial line 27;

[0062] - The second block 102 manages data communication via proprietary communication line 28;

[0063] - Communication between the HPS processor section of the third 103 management processing unit and the FPD programmable section of the processing unit;

[0064] - The fourth block 104 simulates the operation of a predetermined microprocessor, which is dynamically selected based on the programmed electronic device 12; the fourth block 104 processes and manages specific programming algorithms and sends programming data to the interface block 25, and thus to the electronic device 12; the fourth block 104 is replicated according to the number of programming channels supported by the programming system 10 (i.e., the number of devices that can be programmed in parallel);

[0065] - The fifth block 105 manages data exchange with the electronic memory 23 via the bidirectional data communication line 32;

[0066] -The sixth block 106 manages data exchange with the electronic memory 21 via the bidirectional data communication line 30;

[0067] - The seventh block 107 manages data exchange with the electronic memory 22 via the bidirectional data communication line 31;

[0068] - The eighth block 108 manages communication with the programmable unit 24 via line 33, and therefore manages communication with the interface block 25 via line 34;

[0069] - The ninth block 109 manages the dynamic loading of the configuration of the FPD programmable part of the processing unit 20 through the HPS processor part of the processing unit 20.

[0070] The aforementioned functional blocks can be dynamically modified by reprogramming the programmable portion of the processing unit 20, depending on the electronic device 12 to be programmed. In particular, depending on possible modifications to the hardware architecture, block 104 can be frequently reprogrammed via block 109.

[0071] Therefore, even if any modifications and / or changes are made to the specific device being programmed, there is no need to replace or redesign the device 10 itself, and therefore no need to replace or redesign the entire related functional application code.

[0072] The operation of the device 10 described so far is described below. When powered on, the device 10 is initialized by a series of operations that allow configuration of the different components of the device before it can be used to program the electronics 12; a preferred initialization sequence is described below. It should be understood that this sequence should not be construed as limiting, as other sequences are possible depending on the presence of other and different components.

[0073] During the initialization phase, the HPS processor portion of processing unit 20 accesses non-volatile memory 23 via bidirectional data communication line 32 to read operating system-related files and activate the boot sequence. The operating system management based on the HPS processor portion of processing unit 20 corresponds to the aforementioned functional blocks numbered 101, 102, 103, 105, 106, 107, and 109.

[0074] During the initialization phase, the electronic processor sends data and programming parameters related to the electronic device 12 to the HPS processor section of the processing unit 20 via interface 27 or 28. This data and programming parameters are then stored in memory 23. The HPS processor section of the processing unit 20 accesses the non-volatile memory 23 via function block 109 and programs the FPD programmable section of the processing unit 20 based on settings received from the user interface present on the electronic processor 11 via interface 27 or 28. This final process allows dynamic modification of function block 104. Function block 104 of the processing unit 20 then configures interface block 25, specifically based on settings received from the HPS processor section of the processing unit 20, to assign signals, their directions (input / output), and their voltage levels. Function block 104 of the processing unit 20 also transmits signal configurations to the programmable unit 24 when signals are not driven (pull-up or pull-down conditions) based on settings received from the HPS processor section of the processing unit 20. Programmable unit 24 then configures interface block 25.

[0075] During programming of electronic device 12, the HPS processor portion of processing unit 20, supported by memory 21 or memory 22, reads programming data blocks of electronic device 12 from memory 23. This data is sent to the FPD programmable portion of processing unit 20, which in turn sends it to interface block 25, and thus to the electronic device 12 to be programmed. This programming step is performed in a manner known per se and therefore will not be described further here.

[0076] refer to Figure 2 The device 14, which represents the evolution of the device 10 defined above, is connected to the secondary external unit 15 of the programming system 14 via a communication line 38.

[0077] The device 14 includes a processing unit 20, a first volatile electronic memory 21, a second non-volatile electronic memory 22, a third non-volatile electronic memory 23, and at least one communication block 35.

[0078] The secondary external unit 15 consists of a communication block 36 and an interface block 25.

[0079] The communication block 35 of device 14 is connected in the following manner:

[0080] - It is connected to the processing unit 20 via the communication interface 37 for sending or receiving data based on a predetermined communication protocol, which is dynamically determined based on the programmed electronic device 12;

[0081] - A communication block 36 connected to the secondary external unit 15 via a bidirectional data bus 38 is used to send or receive data based on a predetermined communication protocol, which is dynamically determined based on the programmed electronic device 12.

[0082] Communication block 35 exchanges data with processing unit 20 through communication interface 37, which consists of a set of bidirectional single-ended lines. Communication block 35 performs the following action: converting the single-ended lines of communication interface 37 into bidirectional differential lines of communication line 38.

[0083] Communication line 38 consists of bidirectional data lines and power lines in differential format (but not exclusively).

[0084] The communication block 36 of the secondary external unit 15 is connected in the following manner:

[0085] - A communication block 35 connected to the programming system 14 via a bidirectional data bus 38 is used to send or receive data based on a predetermined communication protocol, which is dynamically determined based on the programmed electronic device 12.

[0086] - An interface block 25 connected to the secondary external unit 15 via a bidirectional data bus 39 is used to send or receive data based on a predetermined communication protocol, which is dynamically determined based on electronic devices 12 programmed via communication line 26.

[0087] The communication block 36 of the secondary external unit 15 exchanges data with the communication block 35 of the programming system 14 through a communication interface 38 consisting of a set of differential bidirectional data lines. The communication block 36 performs the following action: converting the differential lines of the interface 38 into bidirectional single-ended lines of the communication line 39. The communication line 39 consists of single-ended bidirectional data lines and power lines (but not exclusively).

[0088] refer to Figure 3 The two sides of device 16, which represents the evolution of the devices 10 to 14 defined above, are secondary external units 17 connected to the programming system 16 via communication lines 43.

[0089] The device 16 includes a processing unit 20, a first volatile electronic memory 21, a second non-volatile electronic memory 22, a third non-volatile electronic memory 23, and at least one communication block 40.

[0090] The secondary external unit 17 consists of a communication block 41 and an interface block 25.

[0091] The communication block 40 of device 16 is connected in the following manner:

[0092] - Connected to the processing unit 20 via a bidirectional data bus 42 for sending or receiving data based on a predetermined communication protocol, which is dynamically determined based on the programmed electronic device 12;

[0093] - A communication block 41 connected to a secondary external unit 17 via a bidirectional data bus 43 is used to send or receive data based on a predetermined communication protocol, which is dynamically determined based on the programmed electronic device 12.

[0094] Communication block 40 exchanges data with processing unit 20 through communication interface 42, which consists of a set of bidirectional single-ended lines. Communication block 40 performs the following: conversion and serialization / deserialization of the single-ended lines of interface 42 in one or more high-speed bidirectional differential serial lines of communication line 43.

[0095] The communication line 43 consists of one or more high-speed differential bidirectional serial data lines and power lines. As a non-limiting example, they can be used as a means of transmitting Ethernet cables by utilizing differential lines for high-speed data transmission and PowerOn Ethernet (POE) technology for power transmission.

[0096] The communication block 41 of the secondary external unit 17 is connected:

[0097] - A communication block 40 connected to the programming system 16 via a bidirectional data bus 43 is used to send or receive data based on a predetermined communication protocol, which is dynamically determined based on the programmed electronic device 12.

[0098] - An interface block 25 connected to the secondary external unit 17 via a bidirectional data bus 44 is used to send or receive data based on a predetermined communication protocol, which is dynamically determined based on electronic devices 12 programmed via communication line 26.

[0099] The communication block 41 of the secondary external unit 17 exchanges data with the communication block 40 of the programming system 16 through a communication interface 43 consisting of one or more high-speed differential serial lines. The communication block 41 performs the following: converting and serializing / deserializing the high-speed differential serial lines of the interface 43 into single-ended bidirectional lines of the communication line 44.

[0100] Communication line 44 consists of a single-ended bidirectional data line and a power line (but not exclusively).

[0101] As a non-limiting example, communication blocks 40 and 41, which exist in programming system 16 and secondary external unit 17 respectively, can be implemented using a programmable FPGA device with an integrated high-speed SERDES transceiver type serialization and deserialization system.

[0102] refer to Figure 4 The two sides of the device 18, which represents the evolution of the device 16 defined above, are secondary external units 17 connected to the programming system 18 via communication lines 43.

[0103] The changes introduced in programming system 18 compared to the previous programming system 16 involve: eliminating communication block 40 and interface 42, and replacing processing unit 20 with processing unit 45. The functions performed by communication block 40 and interface 42 are integrated into processing unit 45.

[0104] As an example, but not limited to, it may eventually be possible to use a processing unit within a single electronic component, consisting of a microprocessor unit or Hard Processor System (HPS) unit, a programmable unit or FPD unit (FPGA), and one or more high-speed SERDES transceivers. This allows for limiting the necessary space on printed circuit boards and providing very fast and efficient communication channels between component units.

Claims

1. An apparatus for programming an electronic device, the apparatus comprising: A processing unit suitable for processing and managing at least one programming algorithm of the electronic device; An electronic processor connected to the processing unit and the electronic device of the device, the electronic processor being configured to receive programming data from the processing unit and to transmit the programming data to the electronic device via a predetermined communication protocol; A non-volatile electronic memory, adapted to exchange data with the processing unit via at least one bidirectional data communication line; The device further includes: A first communication block is configured to exchange data with the processing unit via a communication interface consisting of a set of bidirectional single-ended lines; and A secondary external unit is connected to the first communication block via another communication interface consisting of bidirectional differential data lines, and is connected to the electronic device via a data communication line; the secondary external unit includes a second communication block and an interface block connected together via bidirectional single-ended lines; The first communication block is configured to convert the bidirectional single-ended line of the communication interface into the bidirectional differential data line of the other communication interface, and the second communication block is configured to convert the bidirectional differential data line of the other communication interface into the bidirectional single-ended line that connects the second communication block and the interface block together.

2. The apparatus according to claim 1, wherein, The non-volatile electronic memory includes interchangeable units and fixed units.

3. The apparatus according to claim 1 or 2, wherein, The device also includes a fixed electronic unit for volatile storage, which is adapted to exchange data with the processing unit via a bidirectional data communication line.

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