Semiconductor device

Abstract

For example, a semiconductor device has an output electrode configured to be connected to an inductive load, a ground electrode configured to be connected to a ground terminal, a first transistor and a second transistor configured to be connected in parallel between the output electrode and the ground electrode, an active clamp circuit configured to be connected to a gate of the first transistor, and a gate control circuit configured to control the gates of the first transistor and the second transistor in such a manner that the first transistor and the second transistor are turned on in a first operation state and the first transistor and the second transistor are turned off in a second operation state, the gate control circuit short-circuiting the gate and the source of the second transistor after the transition from the first operation state to the second operation state and before the active clamp circuit operates.

Description

Technical Field

[0001] This invention relates to a semiconductor device having an insulated gate transistor. Background Technology

[0002] Patent Document 1 discloses a planar gate type semiconductor device as an example of a semiconductor device having an insulated gate type transistor. The semiconductor device includes: a semiconductor layer having a main surface; a gate insulating layer formed on the main surface; a gate electrode formed on the gate insulating layer; and a channel on the surface of the semiconductor layer that faces the gate electrode across the gate insulating layer.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2015-70193 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] Semiconductor devices equipped with insulated-gate transistors are sometimes connected to inductive loads as an example of their application. In this case, excellent on-resistance and excellent active clamping tolerance are required as electrical characteristics. On-resistance is the resistance value of the semiconductor device during normal operation. Active clamping tolerance is the tolerance of the transistor when it is actively clamped.

[0008] Specifically, active clamping withstand capability is the transistor's withstand capability relative to the back electromotive force (EMF) generated by the energy stored in the inductive load during the transition from the on state to the off state. Active clamping action is an action of the transistor that dissipates (absorbs) the back EMF.

[0009] As an example, the on-resistance and active clamping tolerance are adjusted based on the area of ​​the transistor's channel. Increasing the channel area increases the current path during normal operation, thus reducing the on-resistance. However, in this case, the active clamping tolerance decreases due to the sharp temperature rise caused by the back electromotive force during active clamping operation.

[0010] Conversely, reducing the channel area shortens the current path during normal operation, thus increasing the on-resistance. However, in this case, the sharp temperature rise caused by back electromotive force during active clamping can be suppressed, thereby improving the active clamping tolerance. Thus, the channel area-based adjustment method involves a trade-off, making it difficult to simultaneously achieve excellent on-resistance and excellent active clamping tolerance.

[0011] One embodiment of the present invention provides a semiconductor device that can achieve both excellent on-resistance and excellent active clamping tolerance.

[0012] Solution for solving the problem

[0013] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor layer; an insulated-gate type first transistor formed on the semiconductor layer; an insulated-gate type second transistor formed on the semiconductor layer; and a control wiring formed on the semiconductor layer in a manner electrically connected to the first transistor and the second transistor, for transmitting a control signal that controls the first transistor and the second transistor to be in an on state during normal operation, and controls the first transistor to be in an off state and the second transistor to be in an on state during active clamping operation.

[0014] According to this semiconductor device, during normal operation, current can flow using both the first and second transistors. This reduces the on-resistance. Conversely, during active clamping operation, current can flow using the second transistor while the first transistor is stopped. This suppresses the sharp temperature rise caused by back electromotive force (EMF), and the second transistor dissipates (absorbs) the back EMF. Consequently, the active clamping tolerance is improved. Therefore, both excellent on-resistance and excellent active clamping tolerance can be achieved.

[0015] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor layer; an insulated-gate type first transistor formed on the semiconductor layer; an insulated-gate type second transistor formed on the semiconductor layer; and a control circuit formed on the semiconductor layer in a manner electrically connected to the first transistor and the second transistor, wherein the first transistor and the second transistor are controlled to be turned on during normal operation, and the first transistor is controlled to be turned off and the second transistor is controlled to be turned on during active clamping operation.

[0016] According to this semiconductor device, during normal operation, current can flow using both the first and second transistors. This reduces the on-resistance. Conversely, during active clamping operation, current can flow using the second transistor while the first transistor is stopped. This suppresses the sharp temperature rise caused by back electromotive force (EMF), and the second transistor dissipates (absorbs) the back EMF. Consequently, the active clamping tolerance is improved. Therefore, both excellent on-resistance and excellent active clamping tolerance can be achieved.

[0017] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor layer; an insulated-gate type first transistor including a first channel and formed on the semiconductor layer; an insulated-gate type second transistor including a second channel and formed on the semiconductor layer; and a control wiring formed on the semiconductor layer in a manner electrically connected to the first transistor and the second transistor, transmitting a control signal for controlling the first transistor and the second transistor in such a manner that the utilization rates of the first channel and the second channel during active clamping operation are greater than zero and less than the utilization rates of the first channel and the second channel during normal operation.

[0018] According to this semiconductor device, during normal operation, the utilization rates of the first and second channels are relatively increased. This results in a relatively increased current path, thereby reducing the on-resistance. On the other hand, during active clamping operation, the utilization rates of the first and second channels are relatively decreased. This suppresses the sharp temperature rise caused by back electromotive force, thus improving the active clamping tolerance. Therefore, a balance between excellent on-resistance and excellent active clamping tolerance can be achieved.

[0019] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor layer; an insulated-gate type first transistor including a first channel and formed in the semiconductor layer; an insulated-gate type second transistor including a second channel and formed in the semiconductor layer; and a control circuit formed in the semiconductor layer in an electrically connected manner to the first transistor and the second transistor, for controlling the first transistor and the second transistor in such a manner that the utilization rates of the first channel and the second channel during active clamping operation are greater than zero and less than the utilization rates of the first channel and the second channel during normal operation.

[0020] According to this semiconductor device, during normal operation, the utilization rates of the first and second channels are relatively increased. This results in a relatively increased current path, thereby reducing the on-resistance. On the other hand, during active clamping operation, the utilization rates of the first and second channels are relatively decreased. This suppresses the sharp temperature rise caused by back electromotive force, thereby improving the active clamping tolerance. Therefore, a balance between excellent on-resistance and excellent active clamping tolerance can be achieved.

[0021] One embodiment of the present invention provides a semiconductor device comprising: a first transistor and a second transistor connected in parallel; an active clamping circuit connected to the gate of the first transistor; and a gate control circuit that controls the gates of the first transistor and the second transistor respectively in a manner that turns on the first transistor and the second transistor in a first operating state and turns off the first transistor and the second transistor in a second operating state, wherein the gate control circuit short-circuits the gate-source of the second transistor after transitioning from the first operating state to the second operating state and before the active clamping circuit is activated.

[0022] According to this semiconductor device, the active clamping tolerance can be improved with a simple circuit structure. Therefore, it is possible to achieve both excellent on-resistance and excellent active clamping tolerance. Attached Figure Description

[0023] Figure 1 This is a perspective view of the semiconductor device according to the first embodiment of the present invention, viewed from one direction.

[0024] Figure 2 It means Figure 1 The diagram shows a block circuit diagram illustrating the electrical structure of a semiconductor device.

[0025] Figure 3 It is used for explanation Figure 1 The circuit diagram shown illustrates the normal operation of the semiconductor device and the active clamping operation.

[0026] Figure 4 yes Figure 3 The circuit diagram shown is a waveform diagram of the main electrical signals used.

[0027] Figure 5 yes Figure 1 The cross-sectional perspective of region V shown.

[0028] Figure 6 From Figure 5 A three-dimensional cross-sectional view after the electrodes have been removed.

[0029] Figure 7 From Figure 6 The cross-sectional perspective view after removing the structure above the semiconductor layer is a cross-sectional perspective view showing the channel structure including the first embodiment.

[0030] Figure 8 yes Figure 7 Top view.

[0031] Figure 9 It includes Figure 5 Enlarged cross-sectional views of the regions of the first trench gate structure and the second trench gate structure shown.

[0032] Figure 10 yes Figure 5 An enlarged cross-sectional view of the first trench gate configuration shown.

[0033] Figure 11 yes Figure 5 An enlarged cross-sectional view of the second trench gate structure shown.

[0034] Figure 12A Is with Figure 7 The cross-sectional perspective view of the corresponding region is a cross-sectional perspective view showing the channel construction method including the second example.

[0035] Figure 12B Is with Figure 7 The cross-sectional perspective view of the corresponding region is a cross-sectional perspective view showing the channel construction method including the third example.

[0036] Figure 13 It is a chart that investigates the relationship between active clamping withstand capacity and areal resistivity through actual measurements.

[0037] Figure 14A It is used for explanation Figure 1 A cross-sectional perspective view of the normal operation of a first control example of the semiconductor device shown.

[0038] Figure 14B It is used for explanation Figure 1 A cross-sectional perspective view of the active clamping operation of the first control example of the semiconductor device shown.

[0039] Figure 15A It is used for explanation Figure 1 A cross-sectional perspective view of the normal operation of a second control example of the semiconductor device shown.

[0040] Figure 15B It is used for explanation Figure 1 A cross-sectional perspective view of the active clamping operation of the second control example of the semiconductor device shown.

[0041] Figure 16 Is with Figure 7 The cross-sectional perspective view of the corresponding region is a perspective view showing the semiconductor device according to the second embodiment of the present invention.

[0042] Figure 17A It is used for explanation Figure 16 A cross-sectional perspective view of the normal operation of a first control example of the semiconductor device shown.

[0043] Figure 17B It is used for explanation Figure 16 A cross-sectional perspective view of the active clamping operation of the first control example of the semiconductor device shown.

[0044] Figure 18A It is used for explanation Figure 16 A cross-sectional perspective view of the normal operation of a second control example of the semiconductor device shown.

[0045] Figure 18B It is used for explanation Figure 16 A cross-sectional perspective view of the active clamping operation of the second control example of the semiconductor device shown.

[0046] Figure 19A It is used for explanation Figure 16 A cross-sectional perspective view of the normal operation of the third control example of the semiconductor device shown.

[0047] Figure 19B It is used for explanation Figure 16 A cross-sectional perspective view of the active clamping operation of the third control example of the semiconductor device shown.

[0048] Figure 20 This is a perspective view of the semiconductor device according to the third embodiment of the present invention, viewed from one direction.

[0049] Figure 21 yes Figure 20 The cross-sectional perspective view of region XXI shown.

[0050] Figure 22 From Figure 21 A three-dimensional cross-sectional view after the electrodes have been removed.

[0051] Figure 23 From Figure 22 A cross-sectional perspective view after removing the structure above the semiconductor layer.

[0052] Figure 24A It is used for explanation Figure 23 A cross-sectional perspective view of the normal operation of the semiconductor device shown.

[0053] Figure 24B It is used for explanation Figure 23 A cross-sectional perspective view of the active clamping action of the semiconductor device shown.

[0054] Figure 25 Is with Figure 21 The cross-sectional perspective view of the corresponding region is a cross-sectional perspective view of the semiconductor device according to the fourth embodiment of the present invention.

[0055] Figure 26 From Figure 25 A cross-sectional perspective view of the structure above the semiconductor layer.

[0056] Figure 27A It is used for explanation Figure 25 A cross-sectional perspective view of the normal operation of the semiconductor device shown.

[0057] Figure 27B It is used for explanation Figure 25 A cross-sectional perspective view of the active clamping action of the semiconductor device shown.

[0058] Figure 28 Is with Figure 25 The cross-sectional perspective view of the corresponding region is a cross-sectional perspective view of the semiconductor device according to the fifth embodiment of the present invention.

[0059] Figure 29A It is used for explanation Figure 28 A cross-sectional perspective view of the normal operation of a first control example of the semiconductor device shown.

[0060] Figure 29B It is used for explanation Figure 28 A cross-sectional perspective view of the active clamping operation of the first control example of the semiconductor device shown.

[0061] Figure 30A It is used for explanation Figure 28 A cross-sectional perspective view of the normal operation of a second control example of the semiconductor device shown.

[0062] Figure 30B It is used for explanation Figure 28 A cross-sectional perspective view of the active clamping operation of the second control example of the semiconductor device shown.

[0063] Figure 31 Is with Figure 7 The cross-sectional perspective view of the corresponding region is a cross-sectional perspective view of the semiconductor device according to the sixth embodiment of the present invention.

[0064] Figure 32A It is used for explanation Figure 31 A cross-sectional perspective view of the normal operation of the semiconductor device shown.

[0065] Figure 32B It is used for explanation Figure 31 A cross-sectional perspective view of the active clamping action of the semiconductor device shown.

[0066] Figure 33 Is with Figure 7 The cross-sectional perspective view of the corresponding region is a perspective view showing the semiconductor device according to the seventh embodiment of the present invention.

[0067] Figure 34A It is used for explanation Figure 33 A cross-sectional perspective view of the normal operation of the semiconductor device shown.

[0068] Figure 34B It is used for explanation Figure 33 A cross-sectional perspective view of the active clamping action of the semiconductor device shown.

[0069] Figure 35 Is with Figure 7 The cross-sectional perspective view of the corresponding region is a partial cut-off cross-sectional perspective view of the semiconductor device according to the eighth embodiment of the present invention.

[0070] Figure 36A It is used for explanation Figure 35 A cross-sectional perspective view of the normal operation of the semiconductor device shown.

[0071] Figure 36B It is used for explanation Figure 35 A cross-sectional perspective view of the active clamping action of the semiconductor device shown.

[0072] Figure 37 This is a perspective view of the semiconductor device according to the ninth embodiment of the present invention, viewed from one direction.

[0073] Figure 38 It means Figure 37 The diagram shows a block circuit diagram illustrating the electrical structure of a semiconductor device.

[0074] Figure 39 It is used for explanation Figure 37 The circuit diagram shown illustrates the normal operation of the semiconductor device and the active clamping operation.

[0075] Figure 40 yes Figure 39 The circuit diagram shown is a waveform diagram of the main electrical signals used.

[0076] Figure 41 It is a three-dimensional representation of a semiconductor package through encapsulating resin.

[0077] Figure 42 yes Figure 41 Top view.

[0078] Figure 43 This is a top view showing a portion of the circuit module of the first example.

[0079] Figure 44 This is a top view showing a portion of the circuit module in the second example.

[0080] Figure 45 This is a block circuit diagram showing a semiconductor device according to the tenth embodiment of the present invention (i.e., in the case of a high-side switch semiconductor device, an electrical configuration for performing the first half-on control of a power MISFET during active clamping operation).

[0081] Figure 46 It is Figure 45 The power MISFET is represented by the equivalent circuit diagram of the first MISFET and the second MISFET.

[0082] Figure 47 It means Figure 45 A circuit diagram of an example configuration of the gate control circuit and the active clamping circuit.

[0083] Figure 48 This is a timing diagram showing the first half-on control of a power MISFET during active clamping when the semiconductor device is a high-side switch.

[0084] Figure 49 This is a block circuit diagram showing the semiconductor device of the eleventh embodiment of the present invention (i.e., the electrical configuration for performing the first half-on control of the power MISFET during active clamping operation when the semiconductor device is a low-side switch).

[0085] Figure 50 It is Figure 49 The power MISFET is represented by the equivalent circuit diagram of the first MISFET and the second MISFET.

[0086] Figure 51 It means Figure 49 A circuit diagram of an example configuration of the gate control circuit and the active clamping circuit.

[0087] Figure 52 This is a timing diagram showing the first half-on control of a power MISFET during active clamping when the semiconductor device is a low-side switch.

[0088] Figure 53 This is a diagram illustrating the startup behavior when a capacity load is connected.

[0089] Figure 54 This is a graph showing the power consumption when a capacity load is connected.

[0090] Figure 55 This is a diagram illustrating a semiconductor device (i.e., an electrical structure for performing three-mode control) according to the twelfth embodiment of the present invention.

[0091] Figure 56 This is a diagram illustrating an example of three-mode control.

[0092] Figure 57 This is a diagram illustrating an example of an overcurrent protection circuit. Detailed Implementation

[0093] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0094] <First Implementation Method>

[0095] Figure 1This is a perspective view of the semiconductor device 1 according to the first embodiment of the present invention, viewed from one direction. Hereinafter, an example of the semiconductor device 1 being a high-side switching device will be described, but the semiconductor device 1 is not limited to a high-side switching device. The semiconductor device 1 can also be provided as a low-side switching device by adjusting the electrical connection method and function of various configurations.

[0096] Reference Figure 1 Semiconductor device 1 includes semiconductor layer 2. Semiconductor layer 2 contains silicon. Semiconductor layer 2 is formed into a cuboid-shaped chip. Semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4.

[0097] The first principal surface 3 and the second principal surface 4 form a quadrilateral shape when viewed from their normal direction Z (hereinafter referred to as "top view"). Side surfaces 5A and 5C extend along the first direction X and are opposite each other in the second direction Y, which intersects the first direction X. Side surfaces 5B and 5D extend along the second direction Y and are opposite each other in the first direction X. Specifically, the second direction Y is orthogonal to the first direction X.

[0098] An output region 6 and an input region 7 are defined in semiconductor layer 2. The output region 6 is defined as the area on side 5C. The input region 7 is defined as the area on side 5A. Viewed from above, the area SOUT of the output region 6 is greater than or equal to the area SIN of the input region 7 (SIN ≤ SOUT).

[0099] The ratio of area SOUT to area SIN, SOUT / SIN, can be greater than 1 and less than 10 (1 ≤ SOUT / SIN ≤ 10). The ratio SOUT / SIN can also be greater than 1 and less than 2, greater than 2 and less than 4, greater than 4 and less than 6, greater than 6 and less than 8, or greater than 8 and less than 10. The planar shapes of input region 7 and output region 6 are arbitrary, but limited to specific shapes. Of course, the ratio SOUT / SIN can also exceed 0 and be less than 1.

[0100] Output region 6 includes a power MISFET (Metal Insulator Semiconductor Field Effect Transistor) 9, which is an example of an insulated-gate type transistor. The power MISFET 9 includes a gate, a drain, and a source.

[0101] Input area 7 includes a controller IC (Integrated Circuit) 10, which is an example of a control circuit. The controller IC 10 includes various functional circuits that implement various functions. These functional circuits include circuitry that generates gate control signals to drive the power MISFET 9 based on external electrical signals. The controller IC 10, together with the power MISFET 9, forms a so-called IPD (Intelligent Power Device). The IPD is also known as an IPM (Intelligent Power Module).

[0102] Input region 7 is electrically insulated from output region 6 through region separation structure 8. Figure 1 In the diagram, the region separation structure 8 is shown by a shading. Although a detailed description is omitted, the region separation structure 8 may also have a trench insulation structure formed by embedding an insulator in the trench.

[0103] On semiconductor layer 2, a plurality of electrodes 11, 12, 13, 14, 15, and 16 are formed. Figure 1 In the diagram, multiple electrodes 11 to 16 are shown by shaded lines. These electrodes 11 to 16 are configured as terminal electrodes for external connection via wires (e.g., bonding leads). The number, arrangement, and planar shape of the electrodes 11 to 16 are arbitrary and not limited to any particular type. Figure 1 As shown in the diagram.

[0104] The number, arrangement, and planar shape of the multiple electrodes 11-16 are adjusted according to the specifications of the power MISFET9 and the controller IC10. In this configuration, the multiple electrodes 11-16 include a drain electrode 11 (power supply electrode), a source electrode 12 (output electrode), an input electrode 13, a reference voltage electrode 14, an ENABLE electrode 15, and a SENSE electrode 16.

[0105] Drain electrode 11 is formed on the second main surface 4 of semiconductor layer 2. Drain electrode 11 is electrically connected to the second main surface 4 of semiconductor layer 2. Drain electrode 11 delivers power supply voltage VB to the drain of power MISFET 9 and various circuits of controller IC 10.

[0106] The drain electrode 11 may also include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The drain electrode 11 may also have a single-layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The drain electrode 11 may also have a stacked structure in which at least two of the Ti layer, Ni layer, Au layer, Ag layer, and Al layer are stacked in any shape.

[0107] The source electrode 12 is formed on the first main surface 3 above the output region 6. The source electrode 12 is electrically connected to the source of the power MISFET 9. The source electrode 12 transmits the electrical signal generated by the power MISFET 9 to the outside.

[0108] Input electrode 13, reference voltage electrode 14, ENABLE electrode 15, and SENSE electrode 16 are respectively formed on the first main surface 3 on the input region 7. Input electrode 13 transmits the input voltage used to drive controller IC 10.

[0109] Reference voltage electrode 14 transmits a reference voltage (e.g., ground voltage) to controller IC 10. ENABLE electrode 15 transmits an electrical signal to enable or disable some or all of the functions of controller IC 10. SENSE electrode 16 transmits an electrical signal to detect abnormalities in controller IC 10.

[0110] A gate control wiring 17, as an example of control wiring, is also formed on semiconductor layer 2. The gate control wiring 17 is selectively wound to output region 6 and input region 7. The gate control wiring 17 is electrically connected to the gate of power MISFET 9 in output region 6 and electrically connected to controller IC 10 in input region 7.

[0111] Gate control wiring 17 transmits the gate control signal generated by controller IC 10 to the gate of power MISFET 9. The gate control signal includes an on signal Von and an off signal Voff, which control the on and off states of power MISFET 9.

[0112] The turn-on signal Von is above the gate threshold voltage Vth of the power MISFET9 (Vth < Von). The turn-off signal Voff is less than the gate threshold voltage Vth of the power MISFET9 (Voff < Vth). The turn-off signal Voff can also be a reference voltage (e.g., ground voltage).

[0113] In this configuration, the gate control wiring 17 includes a first gate control wiring 17A, a second gate control wiring 17B, and a third gate control wiring 17C. The first gate control wiring 17A, the second gate control wiring 17B, and the third gate control wiring 17C are electrically insulated from each other.

[0114] In this configuration, the two first gate control lines 17A are wound to different regions. Additionally, the two second gate control lines 17B are wound to different regions. Furthermore, the two third gate control lines 17C are wound to different regions.

[0115] The first gate control line 17A, the second gate control line 17B, and the third gate control line 17C transmit the same or different gate control signals to the gate of the power MISFET 9. The number, configuration, and shape of the gate control lines 17 are arbitrary and can be adjusted according to the transmission distance of the gate control signals and the number of gate control signals to be transmitted.

[0116] The source electrode 12, input electrode 13, reference voltage electrode 14, ENABLE electrode 15, SENSE electrode 16, and gate control wiring 17 may each contain at least one of nickel, palladium, aluminum, copper, aluminum alloy, and copper alloy.

[0117] The source electrode 12, input electrode 13, reference voltage electrode 14, ENABLE electrode 15, SENSE electrode 16, and gate control wiring 17 may each contain at least one of Al-Si-Cu (aluminum-silicon-copper) alloy, Al-Si (aluminum-silicon) alloy, and Al-Cu (aluminum-copper) alloy.

[0118] The source electrode 12, input electrode 13, reference voltage electrode 14, ENABLE electrode 15, SENSE electrode 16, and gate control wiring 17 may contain the same electrode material or different electrode materials.

[0119] Figure 2 It means Figure 1 The diagram shows a block circuit illustrating the electrical structure of the semiconductor device 1. The following explanation will use the example of the semiconductor device 1 being mounted in a vehicle.

[0120] Semiconductor device 1 includes drain electrode 11, source electrode 12, input electrode 13, reference voltage electrode 14, ENABLE electrode 15, SENSE electrode 16, gate control wiring 17, power MISFET 9, and controller IC 10.

[0121] Drain electrode 11 is connected to the power supply. Drain electrode 11 provides the power supply voltage VB to the power MISFET 9 and the controller IC 10. The power supply voltage VB can also be above 10V and below 20V. Source electrode 12 is connected to the load.

[0122] Input electrode 13 can also be connected to an MCU (Micro Controller Unit), DC / DC converter, LDO (Low Dropout), etc. Input electrode 13 provides an input voltage to controller IC 10. The input voltage can be above 1V and below 10V. Reference voltage electrode 14 is connected to a reference voltage wiring. Reference voltage electrode 14 provides a reference voltage to power MISFET 9 and controller IC 10.

[0123] The ENABLE electrode 15 can also be connected to the MCU. Inputting an electrical signal to the ENABLE electrode 15 enables or disables some or all of the functions of the controller IC 10. The SENSE electrode 16 can also be connected to a resistor.

[0124] The gate of the power MISFET9 is connected to the controller IC10 (gate control circuit 25 described later) via gate control wiring 17. The drain of the power MISFET9 is connected to drain electrode 11. The source of the power MISFET9 is connected to the controller IC10 (current detection circuit 27 described later) and source electrode 12.

[0125] The controller IC10 includes a sensor MISFET21, an input circuit22, a current and voltage control circuit23, a protection circuit24, a gate control circuit25, an active clamping circuit26, a current detection circuit27, a power supply reverse connection protection circuit28, and an abnormality detection circuit29.

[0126] The gate of sensor MISFET 21 is connected to the gate control circuit 25. The drain of sensor MISFET 21 is connected to the drain electrode 11. The source of sensor MISFET 21 is connected to the current detection circuit 27.

[0127] Input circuit 22 is connected to input electrode 13 and current / voltage control circuit 23. Input circuit 22 may also include a Schmitt trigger circuit. Input circuit 22 shapes the waveform of the electrical signal applied to input electrode 13. The signal generated by input circuit 22 is input to current / voltage control circuit 23.

[0128] The current and voltage control circuit 23 is connected to the protection circuit 24, the gate control circuit 25, the power supply reverse connection protection circuit 28, and the abnormality detection circuit 29. The current and voltage control circuit 23 may also include logic circuits.

[0129] The current and voltage control circuit 23 generates various voltages based on electrical signals from the input circuit 22 and from the protection circuit 24. In this configuration, the current and voltage control circuit 23 includes a drive voltage generation circuit 30, a first constant voltage generation circuit 31, a second constant voltage generation circuit 32, and a reference voltage and reference current generation circuit 33.

[0130] The drive voltage generation circuit 30 generates a drive voltage for driving the gate control circuit 25. The drive voltage can also be set to a value obtained by subtracting a predetermined value from the power supply voltage VB. Alternatively, the drive voltage generation circuit 30 can generate a drive voltage between 5V and 15V, obtained by subtracting 5V from the power supply voltage VB. The drive voltage is input to the gate control circuit 25.

[0131] The first constant voltage generation circuit 31 generates a first constant voltage for driving the protection circuit 24. The first constant voltage generation circuit 31 may also include a Zener diode and a regulator circuit (here, a Zener diode). The first constant voltage may also be above 1V and below 5V. The first constant voltage is input to the protection circuit 24 (specifically, the load open-circuit detection circuit 35, etc., described later).

[0132] The second constant voltage generation circuit 32 generates a second constant voltage for driving the protection circuit 24. The second constant voltage generation circuit 32 may also include a Zener diode and a regulator circuit (here, a regulator circuit). The second constant voltage may also be above 1V and below 5V. The second constant voltage is input to the protection circuit 24 (specifically, the overheat protection circuit 36 ​​and the undervoltage malfunction suppression circuit 37, described later).

[0133] The reference voltage and reference current generation circuit 33 generates reference voltages and reference currents for various circuits. The reference voltage can be 1V or higher and 5V or lower. The reference current can be 1mA or higher and 1A or lower. The reference voltage and reference current are input to various circuits. In cases where various circuits include comparators, the reference voltage and reference current can also be input to the comparator.

[0134] Protection circuit 24 is connected to current and voltage control circuit 23, gate control circuit 25, abnormal detection circuit 29, the source of power MISFET 9, and the source of sensor MISFET 21. Protection circuit 24 includes overcurrent protection circuit 34, load open circuit detection circuit 35, overheat protection circuit 36, and low voltage malfunction suppression circuit 37.

[0135] Overcurrent protection circuit 34 protects power MISFET 9 from overcurrent. Overcurrent protection circuit 34 is connected to gate control circuit 25 and the source of sensor MISFET 21. Overcurrent protection circuit 34 may also include current monitoring circuit. The signal generated by overcurrent protection circuit 34 is input to gate control circuit 25 (specifically, drive signal output circuit 40 described later).

[0136] The load open-circuit detection circuit 35 detects the short-circuit and open states of the power MISFET 9. The load open-circuit detection circuit 35 is connected to the current-voltage control circuit 23 and the source of the power MISFET 9. The signal generated by the load open-circuit detection circuit 35 is input to the current-voltage control circuit 23.

[0137] The overheat protection circuit 36 ​​monitors the temperature of the power MISFET 9 and protects it from excessive temperature rise. The overheat protection circuit 36 ​​is connected to the current and voltage control circuit 23. The overheat protection circuit 36 ​​may also include temperature-sensing devices such as temperature-sensing diodes or thermistors. The signal generated by the overheat protection circuit 36 ​​is input to the current and voltage control circuit 23.

[0138] The low-voltage malfunction suppression circuit 37 suppresses malfunction of the power MISFET 9 when the power supply voltage VB is less than a predetermined value. The low-voltage malfunction suppression circuit 37 is connected to the current and voltage control circuit 23. The signal generated by the low-voltage malfunction suppression circuit 37 is input to the current and voltage control circuit 23.

[0139] The gate control circuit 25 controls the on and off states of the power MISFET 9 and the sensor MISFET 21. The gate control circuit 25 is connected to the current and voltage control circuit 23, the protection circuit 24, the gate of the power MISFET 9, and the gate of the sensor MISFET 21.

[0140] The gate control circuit 25 generates various gate control signals corresponding to the number of gate control lines 17 based on electrical signals from the current and voltage control circuit 23 and the protection circuit 24. These various gate control signals are input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control lines 17, respectively.

[0141] Specifically, the gate control circuit 25 includes an oscillation circuit 38, a charge pump circuit 39, and a drive signal output circuit 40. The oscillation circuit 38 oscillates according to the electrical signal from the current-voltage control circuit 23, generating a predetermined electrical signal. The electrical signal generated by the oscillation circuit 38 is input to the charge pump circuit 39. The charge pump circuit 39 boosts the electrical signal from the oscillation circuit 38. The boosted electrical signal from the charge pump circuit 39 is then input to the drive signal output circuit 40.

[0142] The drive signal output circuit 40 generates various gate control signals based on electrical signals from the charge pump circuit 39 and the protection circuit 24 (specifically, the overcurrent protection circuit 34). These gate control signals are input to the gates of the power MISFET 9 and the sensor MISFET 21 via the gate control wiring 17. Both the sensor MISFET 21 and the power MISFET 9 are simultaneously controlled by the gate control circuit 25.

[0143] The active clamping circuit 26 protects the power MISFET 9 from back electromotive force. The active clamping circuit 26 is connected to the drain electrode 11, the gate of the power MISFET 9, and the gate of the sensor MISFET 21. The active clamping circuit 26 may also include multiple diodes.

[0144] The active clamping circuit 26 may also include a plurality of diodes connected in sequence with bias. The active clamping circuit 26 may also include a plurality of diodes connected in reverse bias. The active clamping circuit 26 may also include a plurality of diodes connected in sequence with bias and a plurality of diodes connected in reverse bias.

[0145] The multiple diodes may also include pn-junction diodes, or Zener diodes, or a combination of pn-junction diodes and Zener diodes. The active clamping circuit 26 may also include multiple Zener diodes connected in a mutually biased manner. The active clamping circuit 26 may also include Zener diodes and pn-junction diodes connected in a reverse biased manner.

[0146] The current detection circuit 27 detects the current flowing through the power MISFET 9 and the sensor MISFET 21. The current detection circuit 27 is connected to the protection circuit 24, the anomaly detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The current detection circuit 27 generates a current detection signal based on the electrical signals generated by the power MISFET 9 and the sensor MISFET 21. This current detection signal is then input to the anomaly detection circuit 29.

[0147] The reverse connection protection circuit 28 protects the current and voltage control circuit 23, power MISFET 9, and other components from reverse voltage during a reverse connection. The reverse connection protection circuit 28 is connected to the reference voltage electrode 14 and the current and voltage control circuit 23.

[0148] Anomaly detection circuit 29 monitors the voltage of protection circuit 24. Anomaly detection circuit 29 is connected to current and voltage control circuit 23, protection circuit 24, and current detection circuit 27. In the event of an anomaly (voltage fluctuation, etc.) occurring in any of the overcurrent protection circuit 34, load open circuit detection circuit 35, overheat protection circuit 36, or undervoltage malfunction suppression circuit 37, anomaly detection circuit 29 generates an anomaly detection signal corresponding to the voltage of protection circuit 24 and outputs it externally.

[0149] Specifically, the anomaly detection circuit 29 includes a first multiplexer circuit 41 and a second multiplexer circuit 42. The first multiplexer circuit 41 includes two input sections, one output section, and a selection control input section. A protection circuit 24 and a current detection circuit 27 are respectively connected to the input sections of the first multiplexer circuit 41. The second multiplexer circuit 42 is connected to the output section of the first multiplexer circuit 41. A current and voltage control circuit 23 is connected to the selection control input section of the first multiplexer circuit 41.

[0150] The first multiplexer circuit 41 generates an anomaly detection signal based on the electrical signal from the current-voltage control circuit 23, the voltage detection signal from the protection circuit 24, and the current detection signal from the current detection circuit 27. The anomaly detection signal generated by the first multiplexer circuit 41 is input to the second multiplexer circuit 42.

[0151] The second multiplexer circuit 42 includes two input sections and one output section. The input sections of the second multiplexer circuit 42 are respectively connected to the output section and the ENABLE electrode 15. The output section of the second multiplexer circuit 42 is connected to the SENSE electrode 16.

[0152] With an MCU connected to the ENABLE electrode 15 and a resistor connected to the SENSE electrode 16, an ENABLE signal is input from the MCU to the ENABLE electrode 15, and an abnormality detection signal is derived from the SENSE electrode 16. The abnormality detection signal is converted into an electrical signal by the resistor connected to the SENSE electrode 16. An abnormality in the state of the semiconductor device 1 is detected based on this electrical signal.

[0153] Figure 3 It is used for explanation Figure 1 The circuit diagram of the active clamping action of the semiconductor device 1 shown. Figure 4 yes Figure 3 The circuit diagram shown contains the waveforms of the main electrical signals.

[0154] Here, a circuit example with an inductive load L connected to a power MISFET 9 is used to illustrate the normal operation of the semiconductor device 1 and the active clamping operation. The example utilizes a device with windings (coils) such as a solenoid, motor, transformer, or relay as the inductive load L. The inductive load L is also called an L-load.

[0155] Reference Figure 3The source of the power MISFET 9 is connected to the inductive load L. The drain of the power MISFET 9 is electrically connected to the drain electrode 11. The gate and drain of the power MISFET 9 are connected to the active clamping circuit 26. In this circuit example, the active clamping circuit 26 includes m (m is a natural number) Zener diodes DZ and n (n is a natural number) pn-junction diodes D. The pn-junction diodes D are reverse biased relative to the Zener diodes DZ.

[0156] Reference Figure 3 as well as Figure 4 If an on signal Von is input to the gate of the power MISFET9 which is in the off state, the power MISFET9 switches from the off state to the on state (normal operation). The on signal Von has a voltage greater than or equal to the gate threshold voltage Vth (Vth≤Von). The power MISFET9 remains on for a predetermined on time TON.

[0157] If the power MISFET9 switches to the ON state, the drain current ID begins to flow from the drain of the power MISFET9 towards the source. The drain current ID increases from zero to a predetermined value and then saturates. The inductive load L stores inductive energy due to the increase in drain current ID.

[0158] If an off signal Voff is input to the gate of the power MISFET9, the power MISFET9 switches from the on state to the off state. The off signal Voff has a voltage less than the gate threshold voltage Vth (Voff < Vth). The off signal Voff can also be a reference voltage (e.g., ground voltage).

[0159] During the transition of power MISFET9 from the on state to the off state, the induced energy of the inductive load L is applied to power MISFET9 as a back electromotive force. As a result, power MISFET9 enters an active clamping state (active clamping operation). If power MISFET9 enters an active clamping state, the source voltage VSS drops sharply to a negative voltage that is less than the reference voltage (ground voltage).

[0160] At this time, the source voltage VSS is limited by the operation of the active clamping circuit 26 to a voltage greater than or equal to the power supply voltage VB minus the limiting voltage VL and the clamping turn-on voltage VCLP (VSS≥VB-VL-VCLP).

[0161] In other words, if the power MISFET9 is in an active clamping state, the drain voltage VDS between the drain and source of the power MISFET9 rises sharply to the clamping voltage VDSSCL. The clamping voltage VDSSCL is limited by the power MISFET9 and the active clamping circuit 26 to a voltage below the clamping turn-on voltage VCLP and the limiting voltage VL (VDS≤VCLP+VL).

[0162] In this method, the limiting voltage VL is the sum of the inter-terminal voltage VZ of the Zener diode DZ in the active clamping circuit 26 and the inter-terminal voltage VF of the pn junction diode (VL = m·VZ + n·VF).

[0163] The clamping turn-on voltage VCLP is a positive voltage applied between the gate and source of the power MISFET9 (i.e., the gate voltage VGS). The clamping turn-on voltage VCLP is above the gate threshold voltage Vth (Vth≤VCLP). Therefore, the power MISFET9 remains on in the active clamping state.

[0164] The power MISFET9 fails when the clamping voltage VDSSCL exceeds the maximum rated drain voltage VDSS (VDSS < VDSSCL). The power MISFET9 is designed so that the clamping voltage VDSSCL is below the maximum rated drain voltage VDSS (VDSSCL ≤ VDSS).

[0165] When the clamping voltage VDSSCL is below the maximum rated drain voltage VDSS (VDSSCL≤VDSS), the drain current ID continues to flow from the drain of the power MISFET9 towards the source, and the inductive energy of the inductive load L is consumed (absorbed) in the power MISFET9.

[0166] The drain current ID is reduced to zero from its peak IAV before the power MISFET9 is turned off via the active clamping time TAV. As a result, the gate voltage VGS becomes the reference voltage (e.g., ground voltage), and the power MISFET9 switches from the on state to the off state.

[0167] The active clamping withstand capacity Eac of the power MISFET9 is defined based on the withstand capacity of the power MISFET9 during active clamping operation. Specifically, the active clamping withstand capacity Eac is defined based on the withstand capacity of the power MISFET9 relative to the back electromotive force generated by the inductive energy of the inductive load L when the power MISFET9 transitions from the on state to the off state.

[0168] More specifically, the active clamping tolerance Eac is defined based on the tolerance of the power MISFET9 relative to the energy generated by the clamping voltage VDSSCL. For example, the active clamping tolerance Eac is expressed using the limiting voltage VL, the clamping turn-on voltage VCLP, the drain current ID, and the active clamping time TAV, by the formula Eac = (VL + VCLP) × ID × TAV.

[0169] Figure 5 It means Figure 1 The cross-sectional perspective of region V shown. Figure 6 From Figure 5 A cross-sectional perspective view after removing the source electrode 12 and the gate control wiring 17. Figure 7 From Figure 6 The cross-sectional perspective view after removing the interlayer insulation layer 142 is a cross-sectional perspective view showing the channel structure including the first embodiment.

[0170] Figure 8 yes Figure 7 Top view. Figure 9 It includes Figure 5 Enlarged cross-sectional view of the regions of the first trench gate structure 60 (first gate structure) and the second trench gate structure 70 (second gate structure). Figure 10 yes Figure 5 An enlarged cross-sectional view of the first trench gate configuration 60 shown. Figure 11 yes Figure 5 An enlarged cross-sectional view of the second trench gate configuration 70 shown.

[0171] Reference Figures 5-11 In this manner, semiconductor layer 2 has n + The semiconductor layer 51 is a stacked structure of an n-type semiconductor substrate 51 and an n-type epitaxial layer 52. The second main surface 4 of the semiconductor layer 2 is formed by the semiconductor substrate 51. The first main surface 3 of the semiconductor layer 2 is formed by the epitaxial layer 52. The side surfaces 5A to 5D of the semiconductor layer 2 are formed by the semiconductor substrate 51 and the epitaxial layer 52.

[0172] The epitaxial layer 52 has an n-type impurity concentration lower than that of the semiconductor substrate 51. The n-type impurity concentration of the semiconductor substrate 51 can also be 1 × 10⁻⁶. 18 cm －3 Above and 1×10 20 cm －3 The n-type impurity concentration in epitaxial layer 52 can also be 1×10⁻⁶. 15 cm －3 Above and 1×10 18 cm －3 the following.

[0173] The epitaxial layer 52 has a thickness Tepi (Tepi < Tsub) that is less than the thickness Tsub of the semiconductor substrate 51. The thickness Tsub can also be 50 μm or more and 450 μm or less. The thickness Tsub can also be 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 350 μm or less, or 350 μm or more and 450 μm or less.

[0174] The resistance value can be reduced by decreasing the thickness Tsub. The thickness Tsub is adjusted by grinding. In this case, the second main surface 4 of the semiconductor layer 2 can also be a ground surface with grinding marks.

[0175] The thickness Tepi of the epitaxial layer 52 is preferably less than 1 / 10 of the thickness Tsub. The thickness Tepi can also be 5 μm or more and 20 μm or less. Alternatively, the thickness Tepi can be 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less. The thickness Tepi is preferably 5 μm or more and 15 μm or less.

[0176] A semiconductor substrate 51 is formed as a drain region 53 on the second main surface 4 side of the semiconductor layer 2. An epitaxial layer 52 is formed as a drift region 54 (drain drift region) on the surface portion of the first main surface 3 of the semiconductor layer 2. The bottom of the drift region 54 is formed by the boundary between the semiconductor substrate 51 and the epitaxial layer 52. Hereinafter, the epitaxial layer 52 will be referred to as the drift region 54.

[0177] In the output region 6, a p-type main region 55 is formed on the surface of the first main surface 3 of the semiconductor layer 2. The main region 55 forms the basis of the power MISFET 9. The p-type impurity concentration in the main region 55 can also be 1 × 10⁻⁶. 16 cm －3 Above and 1×10 18 cm －3 the following.

[0178] The main body region 55 is formed on the surface of the drift region 54. The bottom of the main body region 55 is formed on the side of the first main surface 3 relative to the bottom of the drift region 54. The thickness of the main body region 55 may be 0.5 μm or more and 2 μm or less. The thickness of the main body region 55 may also be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0179] The power MISFET 9 includes a first MISFET 56 (first transistor) and a second MISFET 57 (second transistor). The first MISFET 56 is electrically disconnected from the second MISFET 57 and is controlled independently. The second MISFET 57 is electrically disconnected from the first MISFET 56 and is controlled independently.

[0180] In other words, the power MISFET 9 is configured to drive both the first MISFET 56 and the second MISFET 57 in the ON state (full ON control). Alternatively, the power MISFET 9 can be configured to drive the first MISFET 56 in the ON state while the second MISFET 57 is in the OFF state (first half ON control). Furthermore, the power MISFET 9 can be configured to drive the first MISFET 56 in the OFF state while the second MISFET 57 is in the ON state (second half ON control).

[0181] In the fully on control mode, the power MISFET9 is driven with all current paths open. Therefore, the on-resistance within semiconductor layer 2 decreases relatively. Conversely, in the first half-on control or the second half-on control mode, the power MISFET9 is driven with a portion of the current paths cut off. Therefore, the on-resistance within semiconductor layer 2 increases relatively.

[0182] Specifically, the first MISFET 56 includes a plurality of first FET (Field Effect Transistor) structures 58. The plurality of first FET structures 58 are arranged at intervals along a first direction X in a top view, and extend in a strip-like manner along a second direction Y. The plurality of first FET structures 58 are collectively formed in a striped shape in a top view.

[0183] exist Figures 5-8 The figure shows a region on one end side of the first FET structure 58, while the region on the other end side of the first FET structure 58 is omitted. The structure of the region on the other end side of the first FET structure 58 is substantially the same as the structure of the region on one end side of the first FET structure 58. Hereinafter, the structure of the region on one end side of the first FET structure 58 will be described as an example, and the description of the structure of the region on the other end side of the first FET structure 58 will be omitted.

[0184] In this configuration, each first FET structure 58 includes a first trench gate structure 60. The first width WT1 of the first trench gate structure 60 may be 0.5 μm or more and 5 μm or less. The first width WT1 is the width of a direction (first direction X) orthogonal to the direction in which the first trench gate structure 60 extends (second direction Y).

[0185] The first width WT1 can also be 0.5μm or more and 1μm or less, 1μm or more and 1.5μm or less, 1.5μm or more and 2μm or less, 2μm or more and 2.5μm or less, 2.5μm or more and 3μm or less, 3μm or more and 3.5μm or less, 3.5μm or more and 4μm or less, 4μm or more and 4.5μm or less, or 4.5μm or more and 5μm or less. The first width WT1 is preferably 0.8μm or more and 1.2μm or less.

[0186] The first trench gate structure 60 extends through the main body region 55 and reaches the drift region 54. The first depth DT1 of the first trench gate structure 60 can be 1 μm or more and 10 μm or less. The first depth DT1 can also be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The first depth DT1 is preferably 2 μm or more and 6 μm or less.

[0187] The first trench gate structure 60 includes a first sidewall 61 on one side, a second sidewall 62 on the other side, and a bottom wall 63 connecting the first sidewall 61 and the second sidewall 62. Hereinafter, the first sidewall 61, the second sidewall 62, and the bottom wall 63 are sometimes collectively referred to as the "inner wall" or the "outer wall".

[0188] Within semiconductor layer 2, the absolute value of the angle (tapered angle) formed by the first sidewall 61 between it and the first main surface 3 can also be greater than 90° and less than 95° (e.g., around 91°). Within semiconductor layer 2, the absolute value of the angle (tapered angle) formed by the second sidewall 62 between it and the first main surface 3 can also be greater than 90° and less than 95° (e.g., around 91°). The first trench gate structure 60 can also be formed as a pointed shape (tapered shape) that narrows from the first main surface 3 side toward the bottom wall 63 side in cross-section.

[0189] The bottom wall 63 of the first trench gate structure 60 is located on the side of the first main surface 3 relative to the bottom of the drift region 54. The bottom wall 63 of the first trench gate structure 60 is formed as a convex bend (U-shaped) towards the bottom of the drift region 54.

[0190] The bottom wall 63 of the first trench gate structure 60 has a first gap IT1 of 1 μm or more and 10 μm or less relative to the bottom of the drift region 54, located on the side of the first main surface 3. The first gap IT1 can also be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The first gap IT1 is preferably 1 μm or more and 5 μm or less.

[0191] In this configuration, the second MISFET 57 includes a plurality of second FET structures 68. The plurality of second FET structures 68 are arranged at intervals along the first direction X in top view and extend in strips along the second direction Y.

[0192] Multiple second FET structures 68 extend in the same direction as multiple first FET structures 58. The multiple second FET structures 68 are generally formed in a striped pattern when viewed from above. In this configuration, the multiple second FET structures 68 are arranged alternately with the multiple first FET structures 58, with one first FET structure 58 spaced apart from each other.

[0193] exist Figures 5-8 The diagram shows a region on one end side of the second FET structure 68, while the diagram of the region on the other end side of the second FET structure 68 is omitted. The structure of the region on the other end side of the second FET structure 68 is substantially the same as the structure of the region on the one end side of the second FET structure 68. Hereinafter, the structure of the region on the one end side of the second FET structure 68 will be described as an example, and the description of the structure of the region on the other end side of the second FET structure 68 will be omitted.

[0194] In this configuration, each second FET structure 68 includes a second trench gate structure 70. The second width WT2 of the second trench gate structure 70 may be 0.5 μm or more and 5 μm or less. The second width WT2 is the width of a direction (first direction X) orthogonal to the direction in which the second trench gate structure 70 extends (second direction Y).

[0195] The second width WT2 can also be 0.5μm or more and 1μm or less, 1μm or more and 1.5μm or less, 1.5μm or more and 2μm or less, 2μm or more and 2.5μm or less, 2.5μm or more and 3μm or less, 3μm or more and 3.5μm or less, 3.5μm or more and 4μm or less, 4μm or more and 4.5μm or less, or 4.5μm or more and 5μm or less. The second width WT2 is preferably 0.8μm or more and 1.2μm or less.

[0196] The second width WT2 of the second trench gate structure 70 can also be greater than or equal to the first width WT1 of the first trench gate structure 60 (WT1≤WT2). The second width WT2 can also be less than or equal to the first width WT1 (WT1≥WT2). Preferably, the second width WT2 is equal to the first width WT1 (WT1=WT2).

[0197] The second trench gate structure 70 extends through the main body region 55 and reaches the drift region 54. The second depth DT2 of the second trench gate structure 70 can be 1 μm or more and 10 μm or less. The second depth DT2 can also be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The second depth DT2 is preferably 2 μm or more and 6 μm or less.

[0198] The second depth DT2 of the second trench gate structure 70 can also be greater than or equal to the first depth DT1 of the first trench gate structure 60 (DT1≤DT2). The second depth DT2 can also be less than or equal to the first depth DT1 (DT1≥DT2). Preferably, the second depth DT2 is equal to the first depth DT1 (DT1=DT2).

[0199] The second trench gate structure 70 includes a first sidewall 71 on one side, a second sidewall 72 on the other side, and a bottom wall 73 connecting the first sidewall 71 and the second sidewall 72. Hereinafter, the first sidewall 71, the second sidewall 72, and the bottom wall 73 are sometimes collectively referred to as the "inner wall" or the "outer wall".

[0200] Within semiconductor layer 2, the absolute value of the angle (tapered angle) formed by the first sidewall 71 between it and the first main surface 3 can also be greater than 90° and less than 95° (e.g., around 91°). Within semiconductor layer 2, the absolute value of the angle (tapered angle) formed by the second sidewall 72 between it and the first main surface 3 can also be greater than 90° and less than 95° (e.g., around 91°). The second trench gate structure 70 can also be formed as a pointed shape (tapered shape) that narrows in cross-section from the first main surface 3 side toward the bottom wall 73 side, with a second width WT2.

[0201] The bottom wall 73 of the second trench gate structure 70 is located on the side of the first main surface 3 relative to the bottom of the drift region 54. The bottom wall 73 of the second trench gate structure 70 is formed as a convex bend (U-shaped) towards the bottom of the drift region 54.

[0202] The bottom wall 73 of the second trench gate structure 70 has a second gap IT2 of 1 μm or more and 10 μm or less located on the side of the first main surface 3 relative to the bottom of the drift region 54. The second gap IT2 can also be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The second gap IT2 is preferably 1 μm or more and 5 μm or less.

[0203] Cell regions 75 are defined in the area between the plurality of first trench gate structures 60 and the plurality of second trench gate structures 70. The plurality of cell regions 75 are arranged at intervals along a first direction X in top view, and extend in a strip-like shape along a second direction Y. The plurality of cell regions 75 extend in the same direction as the first trench gate structures 60 and the second trench gate structures 70. The plurality of cell regions 75 are collectively formed in a stripe-like shape in top view.

[0204] A first depletion layer extends from the outer wall of the first trench gate structure 60 into the drift region 54. The first depletion layer extends from the outer wall of the first trench gate structure 60 in the direction along the first main surface 3 and the normal direction Z. Similarly, a second depletion layer extends from the outer wall of the second trench gate structure 70 into the drift region 54. The second depletion layer extends from the outer wall of the second trench gate structure 70 in the direction along the first main surface 3 and the normal direction Z.

[0205] The second trench gate structure 70 is arranged with a gap between it and the first trench gate structure 60, where the second depletion layer overlaps with the first depletion layer. Specifically, the second depletion layer overlaps with the first depletion layer in the region of the cell region 75 relative to the bottom wall 73 of the second trench gate structure 70 on the first main surface 3 side. With this configuration, electric field concentration in both the first trench gate structure 60 and the second trench gate structure 70 can be suppressed, thus suppressing the drop in breakdown voltage.

[0206] The second depletion layer preferably overlaps with the first depletion layer in the region on the bottom side of the drift region 54 relative to the bottom wall 73 of the second trench gate structure 70. With this configuration, the electric field concentration on the bottom wall 63 of the first trench gate structure 60 and the bottom wall 73 of the second trench gate structure 70 can be suppressed, thus appropriately suppressing the drop in breakdown voltage.

[0207] The spacing PS between the sidewalls of the first trench gate structure 60 and the second trench gate structure 70 can also be 0.2 μm or more and 2 μm or less. The spacing PS is the distance between the first sidewall 61 (second sidewall 62) of the first trench gate structure 60 and the second sidewall 72 (first sidewall 71) of the second trench gate structure 70, in a direction orthogonal to the direction in which the first trench gate structure 60 and the second trench gate structure 70 extend (second direction Y) (first direction X).

[0208] The spacing PS can also be 0.2μm or more and 0.4μm or less, 0.4μm or more and 0.6μm or less, 0.6μm or more and 0.8μm or less, 0.8μm or more and 1.0μm or less, 1.0μm or more and 1.2μm or less, 1.2μm or more and 1.4μm or less, 1.4μm or more and 1.6μm or less, 1.6μm or more and 1.8μm or less, or 1.8μm or more and 2.0μm or less. The spacing PS is preferably 0.3μm or more and 1.5μm or less.

[0209] The spacing PC between the central portions of the first trench gate structure 60 and the second trench gate structure 70 can be 1 μm or more and 7 μm or less. The spacing PC is the distance between the central portions of the first trench gate structure 60 and the central portions of the second trench gate structure 70 in a direction orthogonal to the direction in which the first trench gate structure 60 and the second trench gate structure 70 extend (second direction Y) (first direction X).

[0210] The spacing PC can also be 1μm or more and 2μm or less, 2μm or more and 3μm or less, 3μm or more and 4μm or less, 4μm or more and 5μm or less, 5μm or more and 6μm or less, or 6μm or more and 7μm or less. The spacing PC is preferably 1μm or more and 3μm or less.

[0211] Reference Figure 9 as well as Figure 10 Specifically, the first trench gate structure 60 includes a first gate trench 81, a first insulating layer 82, and a first electrode 83. The first gate trench 81 is formed by excavating the first main surface 3 toward the second main surface 4.

[0212] The first gate trench 81 divides the first sidewall 61, the second sidewall 62, and the bottom wall 63 of the first trench gate structure 60. Hereinafter, the first sidewall 61, the second sidewall 62, and the bottom wall 63 of the first trench gate structure 60 are also referred to as the first sidewall 61, the second sidewall 62, and the bottom wall 63 of the first gate trench 81.

[0213] The first insulating layer 82 is formed in a film shape along the inner wall of the first gate trench 81. The first insulating layer 82 divides a concave space within the first gate trench 81. The portion of the first insulating layer 82 that covers the bottom wall 63 of the first gate trench 81 is formed along the bottom wall 63 of the first gate trench 81. Thus, the first insulating layer 82 divides a U-shaped recessed space within the first gate trench 81.

[0214] The first insulating layer 82 comprises at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0215] The first insulating layer 82 may also have a stacked structure comprising SiN layers and SiO2 layers sequentially stacked from the semiconductor layer 2 side. Alternatively, the first insulating layer 82 may have a stacked structure comprising SiO2 layers and SiN layers sequentially stacked from the semiconductor layer 2 side. The first insulating layer 82 may also have a monolayer structure composed of either a SiO2 layer or a SiN layer. In this embodiment, the first insulating layer 82 has a monolayer structure composed of a SiO2 layer.

[0216] The first insulating layer 82 includes a first bottom-side insulating layer 84 and a first opening-side insulating layer 85 formed sequentially from the bottom wall 63 side of the first gate trench 81 toward the first main surface 3 side.

[0217] A first bottom-side insulating layer 84 covers the inner wall of the bottom wall 63 side of the first gate trench 81. Specifically, the first bottom-side insulating layer 84 covers the inner wall of the bottom wall 63 side of the first gate trench 81 relative to the bottom of the main body region 55. The first bottom-side insulating layer 84 divides a U-shaped space on the bottom wall 63 side of the first gate trench 81. The first bottom-side insulating layer 84 has a smooth inner wall surface dividing the U-shaped space. The first bottom-side insulating layer 84 is in contact with the drift region 54. A portion of the first bottom-side insulating layer 84 may also be in contact with the main body region 55.

[0218] The first opening-side insulating layer 85 covers the inner wall of the opening side of the first gate trench 81. Specifically, the first opening-side insulating layer 85 covers the first sidewall 61 and the second sidewall 62 of the first gate trench 81 in the opening side region of the first gate trench 81 relative to the bottom of the main body region 55. The first opening-side insulating layer 85 is in contact with the main body region 55. A portion of the first opening-side insulating layer 85 may also be in contact with the drift region 54.

[0219] The first bottom-side insulating layer 84 has a first thickness T1. The first opening-side insulating layer 85 has a second thickness T2 (T2 < T1) that is less than the first thickness T1. The first thickness T1 is the thickness of the first bottom-side insulating layer 84 along the normal direction of the inner wall of the first gate trench 81. The second thickness T2 is the thickness of the first opening-side insulating layer 85 along the normal direction of the inner wall of the first gate trench 81.

[0220] The first ratio T1 / WT1 relative to the first width WT1 of the first gate trench 81 can also be 0.1 or more and 0.4 or less. The first ratio T1 / WT1 can also be 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.3 or more and 0.35 or less, or 0.35 or more and 0.4 or less. The first ratio T1 / WT1 is preferably 0.25 or more and 0.35 or less.

[0221] The first thickness T1 of the first bottom insulating layer 84 can also be... The above and Below. The first thickness T1 can also be... The above and the following, The above and the following, The above and the following, The above and The following, or The above and The following is a preferred first thickness T1. The above and the following.

[0222] The first thickness T1 can also be adjusted according to the first width WT1 of the first gate trench 81. The above and Below. The first thickness T1 can also be... The above and the following, The above and the following, The above and the following, The above and the following, The above and the following, The above and the following, The above and The following, or The above and In this case, the withstand voltage of the semiconductor device 1 can be improved by thickening the first bottom-side insulating layer 84.

[0223] The second thickness T2 of the first opening-side insulating layer 85 can also be more than 1 / 100 and less than 1 / 10 of the first thickness T1 of the first bottom-side insulating layer 84. The second thickness T2 can also be... The above and Below. The second thickness T2 can also be... The above and the following, The above and the following, The above and The following, or The above and The second thickness T2 is preferably as follows. The above and the following.

[0224] The first bottom-side insulating layer 84 is formed in a shape in which the first thickness T1 decreases from the portion covering the first sidewall 61 and the second sidewall 62 of the first gate trench 81 toward the portion covering the bottom wall 63 of the first gate trench 81.

[0225] The thickness of the portion of the first bottom insulating layer 84 covering the bottom wall 63 of the first gate trench 81 is smaller than the thickness of the portions of the first sidewall 61 and the second sidewall 62 of the first bottom insulating layer 84 covering the first gate trench 81. The opening width on the bottom wall side of the U-shaped space defined by the first bottom insulating layer 84 expands by an amount equivalent to the reduction in the first thickness T1. This suppresses the narrowing of the U-shaped space. Such a U-shaped space is formed, for example, by etching the inner wall of the first bottom insulating layer 84 (e.g., wet etching).

[0226] The first electrode 83 is embedded in the first gate trench 81 through the first insulating layer 82. A first gate control signal (first control signal) including an on signal Von and an off signal Voff is applied to the first electrode 83. In this configuration, the first electrode 83 has an insulatingly separated electrode structure including a first bottom-side electrode 86, a first opening-side electrode 87, and a first intermediate insulating layer 88.

[0227] The first bottom-side electrode 86 is embedded in the bottom wall 63 side of the first gate trench 81, separated by the first insulating layer 82. Specifically, the first bottom-side electrode 86 is embedded in the bottom wall 63 side of the first gate trench 81, separated by the first bottom-side insulating layer 84. The first bottom-side electrode 86 is opposite to the drift region 54, separated by the first bottom-side insulating layer 84. A portion of the first bottom-side electrode 86 may also be opposite to the main body region 55, separated by the first bottom-side insulating layer 84.

[0228] The first bottom-side electrode 86 includes a first upper end portion 86A, a first lower end portion 86B, and a first wall portion 86C. The first upper end portion 86A is located on the opening side of the first gate trench 81. The first lower end portion 86B is located on the bottom wall 63 side of the first gate trench 81. The first wall portion 86C connects the first upper end portion 86A and the first lower end portion 86B, and extends in a wall-like manner along the inner wall of the first gate trench 81.

[0229] The first upper portion 86A protrudes from the first bottom insulating layer 84. The first upper portion 86A protrudes toward the first main surface 3 relative to the first bottom insulating layer 84. Thus, the first bottom electrode 86 has an inverted recessed groove in cross-section on the opening side of the first gate trench 81 and between the first bottom insulating layer 84 and the first opening-side insulating layer 85. The width of the first upper portion 86A is smaller than the width of the first wall portion 86C.

[0230] The first lower end portion 86B is formed as a convex bend toward the bottom wall 63 of the first gate trench 81. Specifically, the first lower end portion 86B is formed along the bottom wall of the U-shaped space divided by the first bottom side insulating layer 84, and is formed as a smooth convex bend toward the bottom wall 63 of the first gate trench 81.

[0231] According to this configuration, local electric field concentration relative to the first bottom electrode 86 can be suppressed, thus suppressing the drop in breakdown voltage. In particular, by embedding the first bottom electrode 86 in the U-shaped space after the expansion of the first bottom insulating layer 84, it is possible to appropriately suppress the first bottom electrode 86 from the first upper end portion 86A toward the first lower end portion 86B to become tapered. As a result, local electric field concentration relative to the first lower end portion 86B of the first bottom electrode 86 can be appropriately suppressed.

[0232] The first bottom-side electrode 86 may also comprise at least one of conductive polycrystalline silicon, tungsten, aluminum, copper, aluminum alloys, and copper alloys. In this embodiment, the first bottom-side electrode 86 comprises conductive polycrystalline silicon. The conductive polycrystalline silicon may also contain n-type or p-type impurities. Preferably, the conductive polycrystalline silicon contains n-type impurities.

[0233] The first opening-side electrode 87 is embedded in the opening side of the first gate trench 81 through the first insulating layer 82. Specifically, the first opening-side electrode 87 is embedded in the inverted recess defined in the opening side of the first gate trench 81 through the first opening-side insulating layer 85. The first opening-side electrode 87 is opposite to the main body region 55 through the first opening-side insulating layer 85. A portion of the first opening-side electrode 87 may also be opposite to the drift region 54 through the first opening-side insulating layer 85.

[0234] The first opening-side electrode 87 may also comprise at least one of conductive polycrystalline silicon, tungsten, aluminum, copper, aluminum alloys, and copper alloys. Preferably, the first opening-side electrode 87 comprises the same type of conductive material as the first bottom-side electrode 86. In this embodiment, the first opening-side electrode 87 comprises conductive polycrystalline silicon. The conductive polycrystalline silicon may also contain n-type or p-type impurities. Preferably, the conductive polycrystalline silicon contains n-type impurities.

[0235] A first intermediate insulating layer 88 is located between the first bottom-side electrode 86 and the first opening-side electrode 87, electrically insulating the first bottom-side electrode 86 and the first opening-side electrode 87. Specifically, the first intermediate insulating layer 88 covers the first bottom-side electrode 86 exposed from the first bottom-side insulating layer 84 in the region between the first bottom-side electrode 86 and the first opening-side electrode 87. The first intermediate insulating layer 88 covers the first upper end portion 86A (specifically, the protrusion) of the first bottom-side electrode 86. The first intermediate insulating layer 88 is connected to the first insulating layer 82 (first bottom-side insulating layer 84).

[0236] The first intermediate insulating layer 88 has a third thickness T3. The third thickness T3 is less than the first thickness T1 of the first bottom insulating layer 84 (T3 < T1). The third thickness T3 can also be greater than 1 / 100 and less than 1 / 10 of the first thickness T1. The above and The third thickness T3 can also be... The above and the following, The above and the following, The above and The following, or The above and The following is a preferred third thickness T3. The above and the following.

[0237] The first intermediate insulating layer 88 comprises at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3). In this embodiment, the first intermediate insulating layer 88 has a monolayer structure composed of a SiO2 layer.

[0238] In this configuration, the exposed portion of the first opening-side electrode 87, protruding from the first gate trench 81, is located on the bottom wall 63 side of the first gate trench 81 relative to the first main surface 3. The exposed portion of the first opening-side electrode 87 is formed in a curved shape toward the bottom wall 63 of the first gate trench 81.

[0239] The exposed portion of the first opening-side electrode 87 is covered by a first cover insulating layer 89 formed as a film. The first cover insulating layer 89 is connected to the first insulating layer 82 (first opening-side insulating layer 85) within the first gate trench 81. The first cover insulating layer 89 may also contain silicon oxide (SiO2).

[0240] Each first FET configuration 58 also includes a p-type first channel region 91 (first channel). The first channel region 91 is formed in the body region 55 in a region opposite to the first electrode 83 (first opening-side electrode 87) separated by the first insulating layer 82 (first opening-side insulating layer 85).

[0241] The first channel region 91 is formed along the first sidewall 61 or the second sidewall 62 of the first trench gate structure 60, or both the first sidewall 61 and the second sidewall 62. In this configuration, the first channel region 91 is formed along the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60.

[0242] Each first FET structure 58 also includes an n-type surface portion formed in the main body region 55. +The first source region 92 is a type 1 source region. The first source region 92 defines a first channel region 91 between the main body region 55 and the drift region 54. The n-type impurity concentration in the first source region 92 exceeds the n-type impurity concentration in the drift region 54. The n-type impurity concentration in the first source region 92 can also be 1 × 10⁻⁶. 19 cm －3 Above and 1×10 21 cm －3 the following.

[0243] In this configuration, each first FET structure 58 includes a plurality of first source regions 92. The plurality of first source regions 92 are formed spaced apart along the first trench gate structure 60 on the surface portion of the body region 55. Specifically, the plurality of first source regions 92 are formed along a first sidewall 61 or a second sidewall 62, or both the first sidewall 61 and the second sidewall 62, of the first trench gate structure 60. In this configuration, the plurality of first source regions 92 are formed spaced apart along the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60.

[0244] The bottoms of the plurality of first source regions 92 are located on the side of the first main surface 3 relative to the bottom of the main body region 55. Thus, the plurality of first source regions 92 are positioned opposite the first electrode 83 (first opening-side electrode 87) through the first insulating layer 82 (first opening-side insulating layer 85). In this way, the first channel region 91 of the first MISFET 56 is formed in the main body region 55 within the region enclosed by the plurality of first source regions 92 and the drift region 54.

[0245] Each first FET structure 58 also includes a p-type layer formed on the surface portion of the body region 55. + The first contact region 93 of the type. The p-type impurity concentration in the first contact region 93 exceeds the p-type impurity concentration in the main body region 55. The p-type impurity concentration in the first contact region 93 can also be 1×10⁻⁶. 19 cm －3 Above and 1×10 21 cm －3 the following.

[0246] In this configuration, each first FET structure 58 includes a plurality of first contact regions 93. The plurality of first contact regions 93 are formed at intervals along the first trench gate structure 60 on the surface portion of the body region 55. Specifically, the plurality of first contact regions 93 are formed along the first sidewall 61 or the second sidewall 62 of the first trench gate structure 60, or along both the first sidewall 61 and the second sidewall 62.

[0247] In this configuration, a plurality of first contact regions 93 are formed spaced apart along the first sidewall 61 and the second sidewall 62 of the first trench gate configuration 60. Specifically, the plurality of first contact regions 93 are formed on the surface portion of the main body region 55 in an alternating arrangement relative to the plurality of first source regions 92. The bottom of the plurality of first contact regions 93 is located on the side of the first main surface 3 relative to the bottom of the main body region 55.

[0248] Reference Figure 9 as well as Figure 11 The second trench gate structure 70 includes a second gate trench 101, a second insulating layer 102, and a second electrode 103. The second gate trench 101 is formed by excavating the first main surface 3 toward the second main surface 4.

[0249] The second gate trench 101 divides the second trench gate structure 70 into a first sidewall 71, a second sidewall 72, and a bottom wall 73. Hereinafter, the first sidewall 71, the second sidewall 72, and the bottom wall 73 of the second trench gate structure 70 are also referred to as the first sidewall 71, the second sidewall 72, and the bottom wall 73 of the second gate trench 101.

[0250] The second insulating layer 102 is formed in a film shape along the inner wall of the second gate trench 101. The second insulating layer 102 divides a concave space within the second gate trench 101. The portion of the second insulating layer 102 covering the bottom wall 73 of the second gate trench 101 is formed along the bottom wall 73 of the second gate trench 101. Thus, the second insulating layer 102 divides a U-shaped recessed space within the second gate trench 101.

[0251] The second insulating layer 102 comprises at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0252] The second insulating layer 102 may also have a stacked structure comprising SiN layers and SiO2 layers sequentially stacked from the semiconductor layer 2 side. Alternatively, the second insulating layer 102 may have a stacked structure comprising SiO2 layers and SiN layers sequentially stacked from the semiconductor layer 2 side. The second insulating layer 102 may also have a monolayer structure composed of either SiO2 layers or SiN layers. In this embodiment, the second insulating layer 102 has a monolayer structure composed of SiO2 layers.

[0253] The second insulating layer 102 includes a second bottom-side insulating layer 104 and a second opening-side insulating layer 105 formed sequentially from the bottom wall 73 side of the second gate trench 101 toward the first main surface 3 side.

[0254] The second bottom insulating layer 104 covers the inner wall of the bottom wall 73 side of the second gate trench 101. Specifically, the second bottom insulating layer 104 covers the inner wall of the bottom wall 73 side of the second gate trench 101 relative to the bottom of the main body region 55. The second bottom insulating layer 104 divides a U-shaped space on the bottom wall 73 side of the second gate trench 101. The second bottom insulating layer 104 has a smooth inner wall surface dividing the U-shaped space. The second bottom insulating layer 104 is in contact with the drift region 54. A portion of the second bottom insulating layer 104 may also be in contact with the main body region 55.

[0255] The second opening-side insulating layer 105 covers the inner wall of the opening side of the second gate trench 101. Specifically, the second opening-side insulating layer 105 covers the first sidewall 71 and the second sidewall 72 of the second gate trench 101 in the opening-side region of the second gate trench 101 relative to the bottom of the main region 55. The second opening-side insulating layer 105 is in contact with the main region 55. A portion of the second opening-side insulating layer 105 may also be in contact with the drift region 54.

[0256] The second bottom-side insulating layer 104 has a fourth thickness T4. The second opening-side insulating layer 105 has a fifth thickness T5 (T5 < T4) that is less than the fourth thickness T4. The fourth thickness T4 is the thickness of the second bottom-side insulating layer 104 in the normal direction along the inner wall of the second gate trench 101. The fifth thickness T5 is the thickness of the second opening-side insulating layer 105 in the normal direction along the inner wall of the second gate trench 101.

[0257] The second ratio T4 / WT2 of the fourth thickness T4 relative to the second width WT2 of the second gate trench 101 can also be 0.1 or more and 0.4 or less. The second ratio T4 / WT2 can also be 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.3 or more and 0.35 or less, or 0.35 or more and 0.4 or less. The second ratio T4 / WT2 is preferably 0.25 or more and 0.35 or less.

[0258] The second ratio T4 / WT2 can also be less than or equal to the first ratio T1 / WT1 (T4 / WT2 ≤ T1 / WT1). The second ratio T4 / WT2 can also be greater than or equal to the first ratio T1 / WT1 (T4 / WT2 ≥ T1 / WT1). The second ratio T4 / WT2 can also be equal to or equal to the first ratio T1 / WT1 (T4 / WT2 = T1 / WT1).

[0259] The fourth thickness T4 of the second bottom insulating layer 104 can also be The above and Below. The fourth thickness T4 can also be... The above and the following, The above and the following, The above and the following, The above and The following, or The above and The fourth thickness T4 is preferably... The above and the following.

[0260] The fourth thickness T4 is determined according to the second width WT2 of the second gate trench 101. The above and Below. The fourth thickness T4 can also be... The above and the following, The above and the following, The above and the following, The above and the following, The above and the following, The above and the following, The above and The following, or The above and In this case, the withstand voltage of the semiconductor device 1 can be improved by thickening the second bottom insulating layer 104.

[0261] The fourth thickness T4 can also be less than or equal to the first thickness T1 (T4≤T1). The fourth thickness T4 can also be greater than or equal to the first thickness T1 (T4≥T1). The fourth thickness T4 can also be equal to or equal to the first thickness T1 (T4=T1).

[0262] The fifth thickness T5 of the second opening-side insulating layer 105 can also be less than the fourth thickness T4 of the second bottom-side insulating layer 104 (T5 < T4). The fifth thickness T5 can also be more than 1 / 100 and less than 1 / 10 of the fourth thickness T4. The above and Below. The fifth thickness, T5, can also be... The above and the following, The above and the following, The above and The following, or The above and Below. The fifth thickness T5 is preferably... The above and the following.

[0263] The fifth thickness T5 can also be less than or equal to the second thickness T2 (T5≤T2). The fifth thickness T5 can also be greater than or equal to the second thickness T2 (T5≥T2). The fifth thickness T5 can also be equal to or equal to the second thickness T2 (T5=T2).

[0264] The second bottom-side insulating layer 104 is formed in a shape in which the fourth thickness T4 decreases from the portion covering the first sidewall 71 and the second sidewall 72 of the second gate trench 101 toward the portion covering the bottom wall 73 of the second gate trench 101.

[0265] The thickness of the portion of the second bottom insulating layer 104 covering the bottom wall 73 of the second gate trench 101 is smaller than the thickness of the portions of the second bottom insulating layer 104 covering the first sidewall 71 and the second sidewall 72 of the second gate trench 101. The expansion of the opening width on the bottom wall side of the U-shaped space defined by the second bottom insulating layer 104 corresponds to a reduction in the fourth thickness T4. This suppresses the narrowing of the U-shaped space. This U-shaped space is formed, for example, by etching the inner wall of the second bottom insulating layer 104 (e.g., wet etching).

[0266] The second electrode 103 is embedded in the second gate trench 101 through the second insulating layer 102. A predetermined second gate control signal (second control signal) including an on signal Von and an off signal Voff is applied to the second electrode 103.

[0267] In this configuration, the second electrode 103 has an insulatingly separated electrode structure comprising a second bottom-side electrode 106, a second opening-side electrode 107, and a second intermediate insulating layer 108. In this configuration, the second bottom-side electrode 106 is electrically connected to the first bottom-side electrode 86. The second opening-side electrode 107 is electrically insulated from the first opening-side electrode 87.

[0268] The second bottom-side electrode 106 is embedded in the bottom wall 73 side of the second gate trench 101 through the second insulating layer 102. Specifically, the second bottom-side electrode 106 is embedded in the bottom wall 73 side of the second gate trench 101 through the second bottom-side insulating layer 104. The second bottom-side electrode 106 is opposite to the drift region 54 through the second bottom-side insulating layer 104. A portion of the second bottom-side electrode 106 may also be opposite to the main body region 55 through the second bottom-side insulating layer 104.

[0269] The second bottom electrode 106 includes a second upper end portion 106A, a second lower end portion 106B, and a second wall portion 106C. The second upper end portion 106A is located on the opening side of the second gate trench 101. The second lower end portion 106B is located on the bottom wall 73 side of the second gate trench 101. The second wall portion 106C connects the second upper end portion 106A and the second lower end portion 106B, and extends in a wall-like manner along the inner wall of the second gate trench 101.

[0270] The second upper portion 106A protrudes from the second bottom insulating layer 104. The second upper portion 106A protrudes toward the first main surface 3 relative to the second bottom insulating layer 104. As a result, the second bottom electrode 106 forms an inverted recessed groove in cross-section between the opening side of the second gate trench 101 and between the second bottom insulating layer 104 and the second opening side insulating layer 105. The width of the second upper portion 106A is smaller than the width of the second wall portion 106C.

[0271] The second lower end portion 106B is formed in a convex curved shape toward the bottom wall 73 of the second gate trench 101. Specifically, the second lower end portion 106B is formed along the bottom wall of the U-shaped space divided by the second bottom insulating layer 104, and is formed in a smooth convex curved shape toward the bottom wall 73 of the second gate trench 101.

[0272] According to this configuration, local electric field concentration relative to the second bottom electrode 106 can be suppressed, thereby suppressing the drop in breakdown voltage. In particular, by embedding the second bottom electrode 106 in the U-shaped space after the expansion of the second bottom insulating layer 104, it is possible to appropriately suppress the second bottom electrode 106 from the second upper end portion 106A toward the second lower end portion 106B from becoming tapered. Thus, local electric field concentration relative to the second lower end portion 106B of the second bottom electrode 106 can be appropriately suppressed.

[0273] The second bottom electrode 106 may also comprise at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloys, and copper alloys. In this embodiment, the second bottom electrode 106 may also comprise conductive polysilicon. The conductive polysilicon may also contain n-type or p-type impurities. Preferably, the conductive polysilicon contains n-type impurities.

[0274] The second opening-side electrode 107 is embedded in the opening side of the second gate trench 101 through the second insulating layer 102. Specifically, the second opening-side electrode 107 is embedded in the inverted recess defined on the opening side of the second gate trench 101 through the second opening-side insulating layer 105. The second opening-side electrode 107 is opposite to the main body region 55 through the second opening-side insulating layer 105. A portion of the second opening-side electrode 107 may also be opposite to the drift region 54 through the second opening-side insulating layer 105.

[0275] The second opening-side electrode 107 may also comprise at least one of conductive polycrystalline silicon, tungsten, aluminum, copper, aluminum alloys, and copper alloys. Preferably, the second opening-side electrode 107 comprises the same type of conductive material as the second bottom-side electrode 106. In this embodiment, the second opening-side electrode 107 comprises conductive polycrystalline silicon. The conductive polycrystalline silicon may also contain n-type or p-type impurities. Preferably, the conductive polycrystalline silicon comprises n-type impurities.

[0276] The second intermediate insulating layer 108 is located between the second bottom-side electrode 106 and the second opening-side electrode 107, electrically insulating the second bottom-side electrode 106 and the second opening-side electrode 107. Specifically, the second intermediate insulating layer 108 covers the area of ​​the second bottom-side electrode 106 exposed from the second bottom-side insulating layer 104 in the region between the second bottom-side electrode 106 and the second opening-side electrode 107. The second intermediate insulating layer 108 covers the second upper end portion 106A (specifically, the protrusion) of the second bottom-side electrode 106. The second intermediate insulating layer 108 is connected to the second insulating layer 102 (the second bottom-side insulating layer 104).

[0277] The second intermediate insulating layer 108 has a sixth thickness T6. The sixth thickness T6 is less than the fourth thickness T4 of the second bottom insulating layer 104 (T6 < T4). The sixth thickness T6 can also be greater than 1 / 100 and less than 1 / 10 of the fourth thickness T4. The above and The following. The sixth thickness, T6, can also be... The above and the following, The above and the following, The above and The following, or The above and The following is a preferred sixth thickness T6. The above and the following.

[0278] The sixth thickness T6 can also be less than or equal to the third thickness T3 (T6≤T3). The sixth thickness T6 can also be greater than or equal to the third thickness T3 (T6≥T3). The sixth thickness T6 can also be equal to or equal to the third thickness T3 (T6=T3).

[0279] The second intermediate insulating layer 108 comprises at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3). In this embodiment, the second intermediate insulating layer 108 has a monolayer structure composed of a SiO2 layer.

[0280] In this configuration, the exposed portion of the second opening-side electrode 107, protruding from the second gate trench 101, is located on the bottom wall 73 side of the second gate trench 101 relative to the first main surface 3. The exposed portion of the second opening-side electrode 107 is formed in a curved shape toward the bottom wall 73 of the second gate trench 101.

[0281] The exposed portion of the second opening-side electrode 107 is covered by a second cover insulating layer 109 formed as a film. The second cover insulating layer 109 is connected to the second insulating layer 102 (second opening-side insulating layer 105) within the second gate trench 101. The second cover insulating layer 109 may also contain silicon oxide (SiO2).

[0282] Each second FET configuration 68 also has a p-type second channel region 111 (second channel). Specifically, the second channel region 111 is formed in the body region 55 in a region opposite to the second electrode 103 (second opening-side electrode 107) separated by the second insulating layer 102 (second opening-side insulating layer 105).

[0283] Specifically, the second channel region 111 is formed along the first sidewall 71 or the second sidewall 72 of the second trench gate structure 70, or both the first sidewall 71 and the second sidewall 72. In this configuration, the second channel region 111 is formed along the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70.

[0284] Each second FET structure 68 also includes n formed on the surface portion of the main body region 55. + The second source region 112 of the type. The second source region 112 defines a second channel region 111 within the main region 55 and between the drift region 54.

[0285] The n-type impurity concentration in the second source region 112 exceeds that in the drift region 54. The n-type impurity concentration in the second source region 112 can also be 1 × 10⁻⁶. 19 cm －3 Above and 1×10 21 cm －3 The n-type impurity concentration in the second source region 112 is preferably equal to the n-type impurity concentration in the first source region 92.

[0286] In this configuration, each second FET structure 68 includes a plurality of second source regions 112. The plurality of second source regions 112 are formed spaced apart along the second trench gate structure 70 on the surface portion of the body region 55. Specifically, the plurality of second source regions 112 are formed along a first sidewall 71 or a second sidewall 72, or both, of the second trench gate structure 70. In this configuration, the plurality of second source regions 112 are formed spaced apart along the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70.

[0287] In this configuration, each second source region 112 is positioned opposite each first source region 92 along the first direction X. Each second source region 112 and each first source region 92 are integrally formed. Figure 7 as well as Figure 8In the diagram, the first source region 92 and the second source region 112 are distinguished by boundary lines, but in reality, there is no clear boundary line between the first source region 92 and the second source region 112.

[0288] Each second source region 112 can also be formed offset from each first source region 92 along the second direction Y, in a manner that is partially or completely opposite to each first source region 92 along the first direction X. That is, the plurality of first source regions 92 and the plurality of second source regions 112 can also be arranged in an alternating manner when viewed from above.

[0289] The bottoms of the plurality of second source regions 112 are located on the side of the first main surface 3 relative to the bottom of the main body region 55. Thus, the plurality of second source regions 112 are positioned opposite the second electrode 103 (second opening-side electrode 107) through the second insulating layer 102 (second opening-side insulating layer 105). In this way, the second channel region 111 of the second MISFET 57 is formed in the main body region 55 within the region enclosed by the plurality of second source regions 112 and the drift region 54.

[0290] Each second FET structure 68 also includes a p-type layer formed on the surface of the main body region 55. + The second contact region 113 is a type of [type of contact region]. The p-type impurity concentration in the second contact region 113 exceeds the p-type impurity concentration in the main region 55. The p-type impurity concentration in the second contact region 113 can also be 1 × 10⁻⁶. 19 cm －3 Above and 1×10 21 cm －3 The p-type impurity concentration in the second contact region 113 is preferably equal to the p-type impurity concentration in the first contact region 93.

[0291] In this configuration, each second FET structure 68 includes a plurality of second contact regions 113. The plurality of second contact regions 113 are formed spaced apart along the second trench gate structure 70 on the surface portion of the main body region 55. Specifically, the plurality of second contact regions 113 are formed along a first sidewall 71 or a second sidewall 72, or both, of the second trench gate structure 70. The bottom of the plurality of second contact regions 113 is located on the side of the first main surface 3 relative to the bottom of the main body region 55.

[0292] In this configuration, a plurality of second contact regions 113 are formed with gaps along the first sidewall 71 and the second sidewall 72 of the second trench gate configuration 70. Specifically, the plurality of second contact regions 113 are formed on the surface portion of the main body region 55 in an alternating arrangement relative to the plurality of second source regions 112.

[0293] Reference Figure 7 as well as Figure 8 In this configuration, each second contact area 113 is positioned opposite each first contact area 93 along the first direction X. Each second contact area 113 and each first contact area 93 are integrally formed.

[0294] exist Figure 7 In order to distinguish it from the first source region 92 and the second source region 112, the first contact region 93 and the second contact region 113 are uniformly referred to as "p". + It is indicated by the symbol "". Additionally, in Figure 8 In the diagram, the first contact area 93 and the second contact area 113 are distinguished by boundary lines, but in reality, there is no clear boundary line between the area between the first contact area 93 and the second contact area 113.

[0295] Each second contact area 113 can also be formed offset from each first contact area 93 along the second direction Y, in a manner that is opposite to a portion or all of each first contact area 93 along the first direction X. That is, the plurality of first contact areas 93 and the plurality of second contact areas 113 can also be arranged in an alternating manner when viewed from above.

[0296] Reference Figure 7 as well as Figure 8 In this configuration, the main body region 55 is exposed in the first main surface 3 of the semiconductor layer 2 in the region between one end of the first trench gate structure 60 and one end of the second trench gate structure 70. The first source region 92, the first contact region 93, the second source region 112, and the second contact region 113 may also be formed in the first main surface 3 in the region between one end of the first trench gate structure 60 and one end of the second trench gate structure 70.

[0297] Similarly, although not illustrated, in this configuration, the main body region 55 is exposed in the region between the other end of the first trench gate structure 60 and the other end of the second trench gate structure 70 in the first main surface 3 of the semiconductor layer 2. The first source region 92, the first contact region 93, the second source region 112, and the second contact region 113 may also be formed in the region between the other end of the first trench gate structure 60 and the other end of the second trench gate structure 70.

[0298] Reference Figures 5-8 Multiple (in this case, two) trench contact structures 120 are formed on the first main surface 3 of the semiconductor layer 2. The multiple trench contact structures 120 include a trench contact structure 120 on one side and a trench contact structure 120 on the other side.

[0299] One side of the trench contact structure 120 is located in the region at one end of the first trench gate structure 60 and one end of the second trench gate structure 70. The other side of the trench contact structure 120 is located in the region at the other end of the first trench gate structure 60 and the other end of the second trench gate structure 70.

[0300] The groove contact structure 120 on the other side has a structure that is substantially the same as that on one side. Hereinafter, the structure on the side of the groove contact structure 120 on one side will be described as an example, and a detailed description of the structure on the side of the groove contact structure 120 on the other side will be omitted.

[0301] The trench contact structure 120 is connected to one end of the first trench gate structure 60 and one end of the second trench gate structure 70. In this configuration, the trench contact structure 120 extends in a strip shape along the first direction X when viewed from above.

[0302] The width WTC of the trench contact structure 120 can be greater than 0.5 μm and less than 5 μm. The width WTC is the width in a direction orthogonal to the direction in which the trench contact structure 120 extends (the first direction X) (the second direction Y).

[0303] The width WTC can also be 0.5μm or more and 1μm or less, 1μm or more and 1.5μm or less, 1.5μm or more and 2μm or less, 2μm or more and 2.5μm or less, 2.5μm or more and 3μm or less, 3μm or more and 3.5μm or less, 3.5μm or more and 4μm or less, 4μm or more and 4.5μm or less, or 4.5μm or more and 5μm or less. The width WTC is preferably 0.8μm or more and 1.2μm or less.

[0304] The width WTC is preferably equal to the first width WT1 of the first trench gate structure 60 (WTC = WT1). The width WTC is preferably equal to the second width WT2 of the second trench gate structure 70 (WTC = WT2).

[0305] The trench contact structure 120 penetrates the main body region 55 and reaches the drift region 54. The depth DTC of the trench contact structure 120 can be 1 μm or more and 10 μm or less. The depth DTC can also be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The depth DTC is preferably 2 μm or more and 6 μm or less.

[0306] The depth DTC is preferably equal to the first depth DT1 of the first trench gate structure 60 (DTC = DT1). The depth DTC is preferably equal to the second depth DT2 of the second trench gate structure 70 (DTC = DT2).

[0307] The trench contact structure 120 includes a first sidewall 121 on one side, a second sidewall 122 on the other side, and a bottom wall 123 connecting the first sidewall 121 and the second sidewall 122. Hereinafter, the first sidewall 121, the second sidewall 122, and the bottom wall 123 are collectively referred to as the "inner wall". The first sidewall 121 is the connection surface that connects to the first trench gate structure 60 and the second trench gate structure 70.

[0308] The first sidewall 121, the second sidewall 122, and the bottom wall 123 are located within the drift region 54. The first sidewall 121 and the second sidewall 122 extend along the normal direction Z. The first sidewall 121 and the second sidewall 122 may also be formed perpendicular to the first main surface 3.

[0309] Within semiconductor layer 2, the absolute value of the angle (tapered angle) formed by the first sidewall 121 between it and the first main surface 3 can also be greater than 90° and less than 95° (e.g., around 91°). Within semiconductor layer 2, the absolute value of the angle (tapered angle) formed by the second sidewall 122 between it and the first main surface 3 can also be greater than 90° and less than 95° (e.g., around 91°). The trench contact structure 120 can also be formed as a pointed shape (tapered shape) that narrows in width WTC from the first main surface 3 side of semiconductor layer 2 toward the bottom wall 123 side in cross-section.

[0310] The bottom wall 123 is located on the side of the first main surface 3 relative to the bottom of the drift region 54. The bottom wall 123 is formed in a convex curved shape toward the bottom of the drift region 54. The bottom wall 123 is located on the side of the first main surface 3 with an interval of 1 μm or more and 10 μm or less relative to the bottom of the drift region 54. The interval ITC can also be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The interval ITC is preferably 1 μm or more and 5 μm or less.

[0311] The ITC spacing is preferably equal to the first spacing IT1 of the first trench gate structure 60 (ITC = IT1). The ITC spacing is preferably equal to the second spacing IT2 of the second trench gate structure 70 (ITC = IT2).

[0312] The trench contact structure 120 includes a contact trench 131, a contact insulating layer 132, and a contact electrode 133. The contact trench 131 is formed by excavating the first main surface 3 of the semiconductor layer 2 toward the second main surface 4.

[0313] The contact groove 131 divides the groove contact structure 120 into a first sidewall 121, a second sidewall 122, and a bottom wall 123. Hereinafter, the first sidewall 121, the second sidewall 122, and the bottom wall 123 of the groove contact structure 120 are also referred to as the first sidewall 121, the second sidewall 122, and the bottom wall 123 of the contact groove 131.

[0314] The first sidewall 121 of the contact trench 131 communicates with the first sidewall 61 and the second sidewall 62 of the first gate trench 81. The first sidewall 121 of the contact trench 131 communicates with the first sidewall 71 and the second sidewall 72 of the second gate trench 101. The contact trench 131 forms a trench between the first gate trench 81 and the second gate trench 101.

[0315] The contact insulating layer 132 is formed as a film along the inner wall of the contact groove 131. The contact insulating layer 132 divides concave spaces within the contact groove 131. The portion of the contact insulating layer 132 that covers the bottom wall 123 of the contact groove 131 is formed along the bottom wall 123 of the contact groove 131.

[0316] The contact insulating layer 132 divides the contact trench 131 into U-shaped recesses with the same shape as the first bottom insulating layer 84 (second bottom insulating layer 104). That is, the contact insulating layer 132 divides the area on the bottom wall 123 side of the contact trench 131 into U-shaped recesses that are both widened and narrowed. Such U-shaped spaces are formed, for example, by etching the inner wall of the contact insulating layer 132 (e.g., wet etching).

[0317] The contact insulation layer 132 has a seventh thickness T7. The seventh thickness T7 can also be... The above and Below. The seventh thickness, T7, can also be... The above and the following, The above and the following, The above and the following, The above and The following, or The above and The following is a preferred seventh thickness T7. The above and the following.

[0318] The seventh thickness T7 can also be determined based on the width WTC of the 120 groove contact structure. The above and Below. The seventh thickness, T7, can also be... The above and the following, The above and the following, The above and the following, The above and the following, The above and the following, The above and the following, The above and The following, or The above and In this case, the withstand voltage of the semiconductor device 1 can be improved by increasing the thickness of the contact insulating layer 132.

[0319] The seventh thickness T7 is preferably equal to the first thickness T1 of the first bottom-side insulating layer 84 (T7 = T1). The seventh thickness T7 is preferably equal to the fourth thickness T4 of the second bottom-side insulating layer 104 (T7 = T4).

[0320] The contact insulating layer 132 comprises at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0321] The contact insulating layer 132 may also have a stacked structure comprising SiN layers and SiO2 layers sequentially stacked from the semiconductor layer 2 side. Alternatively, the contact insulating layer 132 may have a stacked structure comprising SiO2 layers and SiN layers sequentially stacked from the semiconductor layer 2 side. The contact insulating layer 132 may also have a single-layer structure composed of either SiO2 layers or SiN layers. In this embodiment, the contact insulating layer 132 has a single-layer structure composed of SiO2 layers. Preferably, the contact insulating layer 132 is made of the same insulating material as the first insulating layer 82 (second insulating layer 102).

[0322] The contact insulating layer 132 is integrally formed with the first insulating layer 82 in the connecting portion between the first gate trench 81 and the contact trench 131. The contact insulating layer 132 is integrally formed with the second insulating layer 102 in the connecting portion between the second gate trench 101 and the contact trench 131.

[0323] In this configuration, the contact insulating layer 132 has an outgoing insulating layer 132A extending to one end of the first gate trench 81 and one end of the second gate trench 101. The outgoing insulating layer 132A traverses the connecting portion and covers the inner wall of one end of the first gate trench 81. The outgoing insulating layer 132A traverses the connecting portion and covers the inner wall of one end of the second gate trench 101.

[0324] The lead-out insulating layer 132A is integrally formed with the first bottom-side insulating layer 84 and the first opening-side insulating layer 85 within the first gate trench 81. The lead-out insulating layer 132A, together with the first bottom-side insulating layer 84, divides a U-shaped space in the inner wall of one end of the first gate trench 81.

[0325] The lead-out insulating layer 132A is integrally formed with the second bottom-side insulating layer 104 and the second opening-side insulating layer 105 within the second gate trench 101. The lead-out insulating layer 132A, together with the second bottom-side insulating layer 104, divides a U-shaped space in the inner wall of one end of the second gate trench 101.

[0326] The contact electrode 133 is embedded in the contact trench 131 through the contact insulating layer 132. Unlike the first electrode 83 and the second electrode 103, the contact electrode 133 is embedded in the contact trench 131 as a single unit. The contact electrode 133 has an upper end exposed from the contact trench 131 and a lower end connected to the contact insulating layer 132.

[0327] The lower end of the contact electrode 133 is formed in the same shape as the first bottom side electrode 86 (second bottom side electrode 106), with a convex bend towards the bottom wall 123 of the contact trench 131. Specifically, the lower end of the contact electrode 133 is formed along the bottom wall of the U-shaped space divided by the contact insulating layer 132, and is formed in a smooth convex bend towards the bottom wall 123.

[0328] According to this configuration, local electric field concentration relative to the contact electrode 133 can be suppressed, thereby suppressing the drop in breakdown voltage. In particular, by embedding the contact electrode 133 in the U-shaped space after the expansion of the contact insulation layer 132, it is possible to appropriately suppress the contact electrode 133 from becoming tapered from the upper end to the lower end. Thus, local electric field concentration relative to the lower end of the contact insulation layer 132 can be appropriately suppressed.

[0329] Contact electrode 133 is electrically connected to the first bottom-side electrode 86 in the connection between the first gate trench 81 and the contact trench 131. Contact electrode 133 is electrically connected to the second bottom-side electrode 106 in the connection between the second gate trench 101 and the contact trench 131. Thus, the second bottom-side electrode 106 is electrically connected to the first bottom-side electrode 86.

[0330] Specifically, the contact electrode 133 has a lead-out electrode 133A extending to one end of the first gate trench 81 and one end of the second gate trench 101. The lead-out electrode 133A traverses the connection between the first gate trench 81 and the contact trench 131 and is located within the first gate trench 81. The lead-out electrode 133A also traverses the connection between the second gate trench 101 and the contact trench 131 and is located within the second gate trench 101.

[0331] The lead electrode 133A is embedded in the U-shaped space defined by the contact insulating layer 132 within the first gate trench 81. The lead electrode 133A is integrally formed with the first bottom-side electrode 86 within the first gate trench 81. Thus, the contact electrode 133 is electrically connected to the first bottom-side electrode 86.

[0332] Within the first gate trench 81, a first intermediate insulating layer 88 is located between the contact electrode 133 and the first opening-side electrode 87. Thus, the contact electrode 133 is electrically insulated from the first opening-side electrode 87 within the first gate trench 81.

[0333] The lead-out electrode 133A is embedded within the U-shaped space defined by the contact insulating layer 132 in the second gate trench 101. The lead-out electrode 133A is integrally formed with the second bottom-side electrode 106 within the second gate trench 101. Thus, the contact electrode 133 is electrically connected to the second bottom-side electrode 106.

[0334] Within the second gate trench 101, a second intermediate insulating layer 108 is located between the contact electrode 133 and the second opening-side electrode 107. Thus, the contact electrode 133 is electrically insulated from the second opening-side electrode 107 within the second gate trench 101.

[0335] The contact electrode 133 may also comprise at least one of conductive polycrystalline silicon, tungsten, aluminum, copper, aluminum alloys, and copper alloys. In this embodiment, the contact electrode 133 comprises conductive polycrystalline silicon. The conductive polycrystalline silicon may also contain n-type impurities or p-type impurities. The conductive polycrystalline silicon preferably contains n-type impurities. The contact electrode 133 preferably comprises the same conductive material as the first bottom-side electrode 86 and the second bottom-side electrode 106.

[0336] In this configuration, the exposed portion of the contact electrode 133 protruding from the contact trench 131 is located on the bottom wall 123 side of the contact trench 131 relative to the first main surface 3. The exposed portion of the contact electrode 133 is formed in a curved shape toward the bottom wall 123 of the contact trench 131.

[0337] The exposed portion of the contact electrode 133 is covered by a third cover insulating layer 139 formed in the form of a film. The third cover insulating layer 139 is connected to the contact insulating layer 132 within the contact trench 131. The third cover insulating layer 139 may also contain silicon oxide (SiO2).

[0338] Reference Figures 5-11A main surface insulating layer 141 is formed on the first main surface 3 of the semiconductor layer 2. The main surface insulating layer 141 selectively covers the first main surface 3. The main surface insulating layer 141 is connected to the first insulating layer 82, the second insulating layer 102, and the contact insulating layer 132. The main surface insulating layer 141 comprises at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0339] The main insulating layer 141 has a stacked structure including SiN layers and SiO2 layers sequentially stacked from the semiconductor layer 2 side. The main insulating layer 141 may also have a stacked structure including SiO2 layers and SiN layers sequentially stacked from the semiconductor layer 2 side. The main insulating layer 141 may also have a single-layer structure composed of SiO2 layers or SiN layers. In this embodiment, the main insulating layer 141 has a single-layer structure composed of SiO2 layers. The main insulating layer 141 is preferably made of the same insulating material as the first insulating layer 82, the second insulating layer 102, and the contact insulating layer 132.

[0340] An interlayer insulating layer 142 is formed on the main insulating layer 141. The interlayer insulating layer 142 may also have a thickness exceeding that of the main insulating layer 141. The interlayer insulating layer 142 covers substantially the entire area of ​​the main insulating layer 141. The interlayer insulating layer 142 comprises at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0341] In this configuration, the interlayer insulating layer 142 includes a USG (Undoped Silica Glass) layer, such as silicon oxide. The interlayer insulating layer 142 may also have a single-layer structure composed of the USG layer. The interlayer insulating layer 142 may also have a planarized main surface. The main surface of the interlayer insulating layer 142 may also be a polished surface produced using CMP (Chemical Mechanical Polishing).

[0342] The interlayer insulating layer 142 may also include PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass), which are examples of silicon oxide. The interlayer insulating layer 142 may also have a stacked structure comprising PSG layers and BPSG layers sequentially stacked from the semiconductor layer 2 side. The interlayer insulating layer 142 may also have a stacked structure comprising BPSG layers and PSG layers sequentially stacked from the first main surface 3 side.

[0343] Reference Figure 5 as well as Figure 6In the output region 6, a first plug electrode 143, a second plug electrode 144, a third plug electrode 145, and a fourth plug electrode 146 are embedded in the interlayer insulating layer 142. In this configuration, multiple first plug electrodes 143, multiple second plug electrodes 144, multiple third plug electrodes 145, and multiple fourth plug electrodes 146 are embedded in the interlayer insulating layer 142. The first plug electrodes 143, second plug electrodes 144, third plug electrodes 145, and fourth plug electrodes 146 may also each contain tungsten.

[0344] Multiple first plug electrodes 143 are embedded in portions of the first opening-side electrodes 87 of the first trench gate structure 60 within the interlayer insulating layer 142. In this configuration, the multiple first plug electrodes 143 penetrate the interlayer insulating layer 142 in a region at one end of the first trench gate structure 60 and are connected to the multiple first opening-side electrodes 87 in a one-to-one correspondence.

[0345] Of course, multiple first plug electrodes 143 can also be connected relative to a first opening side electrode 87. Although not shown in the figure, multiple first plug electrodes 143 are also embedded in the interlayer insulating layer 142 in the portion of the region covering the other end side of the first trench gate structure 60, in the same form as the region on one end side.

[0346] In this configuration, multiple first plug electrodes 143 are arranged in a row with gaps along the first direction X. Each first plug electrode 143 can also be formed into a polygonal shape, such as a triangle, quadrilateral, pentagon, or hexagon, or a circle or ellipse when viewed from above. In this configuration, each first plug electrode 143 is formed into a quadrilateral shape when viewed from above.

[0347] Multiple second plug electrodes 144 are embedded in portions of the second opening-side electrodes 107 of the second trench gate structure 70 within the interlayer insulating layer 142. In this configuration, the multiple second plug electrodes 144 penetrate the interlayer insulating layer 142 in a region at one end of the second trench gate structure 70 and are connected to the multiple second opening-side electrodes 107 in a one-to-one correspondence.

[0348] Of course, multiple second plug electrodes 144 can also be connected relative to a second opening side electrode 107. Although not shown in the figure, multiple second plug electrodes 144 are also embedded in the portion of the other end side region of the second trench gate configuration 70 in the interlayer insulating layer 142, in the same form as the region on one end side.

[0349] In this configuration, multiple second plug electrodes 144 are arranged in a row with spacing along the first direction X. Each second plug electrode 144 can also be formed into a polygonal shape, such as a triangle, quadrilateral, pentagon, or hexagon, or a circle or ellipse when viewed from above. In this configuration, each second plug electrode 144 is formed into a quadrilateral shape when viewed from above.

[0350] Multiple third plug electrodes 145 are embedded in portions of the interlayer insulating layer 142 that cover the contact electrode 133. The multiple third plug electrodes 145 penetrate the interlayer insulating layer 142 and are connected to the contact electrode 133.

[0351] Although the illustration is omitted, multiple third plug electrodes 145 are also embedded in the portion of the contact electrode 133 of the trench contact structure 120 covering the other side in the interlayer insulating layer 142, with the same shape as the region on one end side.

[0352] In this configuration, multiple third plug electrodes 145 are arranged in a row with spacing along the first direction X. Each third plug electrode 145 can also be formed into a polygonal shape, such as a triangle, quadrilateral, pentagon, or hexagon, or an ellipse, when viewed from above. In this configuration, each third plug electrode 145 is formed into a quadrilateral shape when viewed from above.

[0353] Multiple fourth plug electrodes 146 are embedded in portions of the interlayer insulating layer 142 that cover multiple unit regions 75. Each fourth plug electrode 146 penetrates the interlayer insulating layer 142 and is connected to each unit region 75. Specifically, each fourth plug electrode 146 is electrically connected in each unit region 75 to a first source region 92, a first contact region 93, a second source region 112, and a second contact region 113.

[0354] Each fourth plug electrode 146, when viewed from above, is formed as a strip extending along each unit region 75. The length of each fourth plug electrode 146 in the second direction Y may also be less than the length of each unit region 75 in the second direction Y.

[0355] Of course, multiple fourth plug electrodes 146 can also be connected to each unit region 75. In this case, the multiple fourth plug electrodes 146 are formed with gaps along each unit region 75. Furthermore, in this case, each fourth plug electrode 146 can also be formed into a polygonal shape, a circle or an ellipse, such as a triangle, a quadrilateral, a pentagon, or a hexagon, when viewed from above.

[0356] In output region 6, the aforementioned source electrode 12 and gate control wiring 17 are formed on interlayer insulating layer 142. The source electrode 12 is electrically connected to a plurality of fourth connector electrodes 146 on interlayer insulating layer 142. A reference voltage (e.g., ground voltage) is applied to the source electrode 12. The reference voltage is transmitted via the plurality of fourth connector electrodes 146 to the first source region 92, the first contact region 93, the second source region 112, and the second contact region 113.

[0357] The first gate control wiring 17A in the gate control wiring 17 is electrically connected to a plurality of first plug electrodes 143 above the interlayer insulating layer 142. A gate control signal from the controller IC 10 is input to the first gate control wiring 17A. The gate control signal is transmitted to the first opening-side electrode 87 via the first gate control wiring 17A and the plurality of first plug electrodes 143.

[0358] The second gate control wiring 17B in the gate control wiring 17 is electrically connected to a plurality of second plug electrodes 144 above the interlayer insulating layer 142. A gate control signal from the controller IC 10 is input to the second gate control wiring 17B. The gate control signal is transmitted to the second opening-side electrode 107 via the second gate control wiring 17B and the plurality of second plug electrodes 144.

[0359] The third gate control wiring 17C in the gate control wiring 17 is electrically connected to a plurality of third plug electrodes 145 above the interlayer insulating layer 142. A gate control signal from the controller IC 10 is input to the third gate control wiring 17C. The gate control signal is transmitted to the contact electrode 133 via the third gate control wiring 17C and the plurality of third plug electrodes 145. That is, the gate control signal from the controller IC 10 is transmitted to the first bottom-side electrode 86 and the second bottom-side electrode 106 via the contact electrode 133.

[0360] When both the first MISFET 56 (first trench gate structure 60) and the second MISFET 57 (second trench gate structure 70) are controlled to be in the off state, both the first channel region 91 and the second channel region 111 are controlled to be in the off state.

[0361] When both the first MISFET 56 and the second MISFET 57 are controlled to be in the ON state, both the first channel region 91 and the second channel region 111 are controlled to be in the ON state (full ON control).

[0362] When the first MISFET 56 is controlled to be on and the second MISFET 57 is controlled to be off, the first channel region 91 is controlled to be on and the second channel region 111 is controlled to be off (first half-on control).

[0363] When the first MISFET 56 is controlled to be off and the second MISFET 57 is controlled to be on, the first channel region 91 is controlled to be off and the second channel region 111 is controlled to be on (second half-on control).

[0364] In this way, the power MISFET9 utilizes the first MISFET56 and the second MISFET57 formed in an output region 6 to achieve various controls, including full-on control, first half-on control and second half-on control.

[0365] When the first MISFET 56 is driven (that is, when the gate is turned on), an on signal Von can also be applied to the first bottom-side electrode 86 and the first opening-side electrode 87. In this case, the first bottom-side electrode 86 and the first opening-side electrode 87 function as gate electrodes.

[0366] This suppresses the voltage drop between the first bottom electrode 86 and the first opening electrode 87, thus preventing electric field concentration between them. Furthermore, it reduces the on-resistance of the semiconductor layer 2, thereby lowering power consumption.

[0367] When the first MISFET 56 is driven (i.e., when the gate is turned on), an off signal Voff (e.g., a reference voltage) can be applied to the first bottom-side electrode 86, and an on signal Von can be applied to the first opening-side electrode 87. In this case, the first bottom-side electrode 86 functions as a field electrode, and the first opening-side electrode 87 functions as a gate electrode. This reduces parasitic capacitance, thereby increasing the switching speed.

[0368] When the second MISFET 57 is driven (that is, when the gate is turned on), an on signal Von can also be applied to the second bottom-side electrode 106 and the second opening-side electrode 107. In this case, the second bottom-side electrode 106 and the second opening-side electrode 107 function as gate electrodes.

[0369] This suppresses voltage drop between the second bottom electrode 106 and the second opening electrode 107, thereby suppressing electric field concentration between them. Furthermore, it reduces the on-resistance of the semiconductor layer 2, thus lowering power consumption.

[0370] When driving the second MISFET 57 (i.e., during gate turn-on control), an off signal Voff (reference voltage) can be applied to the second bottom-side electrode 106, and an on signal Von can be applied to the second opening-side electrode 107. In this case, the second bottom-side electrode 106 functions as a field electrode, and the second opening-side electrode 107 functions as a gate electrode. This reduces parasitic capacitance, thereby increasing switching speed.

[0371] Reference Figure 7 as well as Figure 8 The first channel region 91 is formed in each unit region 75 with a first channel area S1. The first channel area S1 is defined by the total planar area of ​​the plurality of first source regions 92 formed in each unit region 75.

[0372] The first channel region 91 is formed in each unit region 75 with a first channel ratio R1 (first ratio). The first channel ratio R1 is the proportion of the first channel area S1 in each unit region 75 when the planar area of ​​each unit region 75 is set to 100%.

[0373] The first channel ratio R1 is adjusted within the range of 0% to 50%. The first channel ratio R1 can also be 0% to 5%, 5% to 10%, 10% to 15%, 15% to 20%, 20% to 25%, 25% to 30%, 30% to 35%, 35% to 40%, 40% to 45%, or 45% to 50%. The preferred first channel ratio R1 is 10% to 35%.

[0374] When the first channel ratio R1 is 50%, a first source region 92 is formed over approximately the entire area of ​​the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. In this case, a first contact region 93 is not formed on the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. The first channel ratio R1 is preferably less than 50%.

[0375] When the first channel ratio R1 is 0%, the first source region 92 is not formed on the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. In this case, only the main region 55 and / or the first contact region 93 are formed on the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. The first channel ratio R1 is preferably greater than 0%. In this embodiment, an example of a first channel ratio R1 of 25% is shown.

[0376] The second channel region 111 is formed in each unit region 75 with a second channel area S2. The second channel area S2 is defined by the total planar area of ​​the plurality of second source regions 112 formed in each unit region 75.

[0377] The second channel region 111 is formed in each unit region 75 with a second channel ratio R2 (second ratio). The second channel ratio R2 is the proportion of the second channel area S2 in each unit region 75 when the planar area of ​​each unit region 75 is set to 100%.

[0378] The second channel ratio R2 is adjusted within the range of 0% to 50%. The second channel ratio R2 can also be 0% to 5%, 5% to 10%, 10% to 15%, 15% to 20%, 20% to 25%, 25% to 30%, 30% to 35%, 35% to 40%, 40% to 45%, or 45% to 50%. The preferred second channel ratio R2 is 10% to 35%.

[0379] When the second channel ratio R2 is 50%, a second source region 112 is formed over approximately the entire area of ​​the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70. In this case, a second contact region 113 is not formed on the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70. The second channel ratio R2 is preferably less than 50%.

[0380] When the second channel ratio R2 is 0%, the second source region 112 is not formed on the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70. In this case, only the main region 55 and / or the second contact region 113 are formed on the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70. The second channel ratio R2 is preferably greater than 0%. In this embodiment, an example of a second channel ratio R2 of 25% is shown.

[0381] Thus, the first channel region 91 and the second channel region 111 are formed in each unit region 75 with a total channel ratio RT (RT = R1 + R2) of more than 0% and less than 100% (preferably more than 0% and less than 100%).

[0382] In this method, the total channel ratio RT in each unit region 75 is 50%. In this method, all total channel ratios RT are set to an equal value. Therefore, the average channel ratio RAV within the output region 6 (per unit area) becomes 50%. The average channel ratio RAV is the number obtained by dividing the total number of total channel ratios RT by the sum of all total channel ratios RT.

[0383] Below, in Figure 12A as well as Figure 12B The example shown illustrates the situation after adjusting the average channel ratio (RAV). Figure 12A Is with Figure 7 The cross-sectional perspective view of the corresponding region is a cross-sectional perspective view showing the channel construction method including the second example. Figure 12B Is with Figure 7 The cross-sectional perspective view of the corresponding region is a cross-sectional perspective view showing the channel construction method including the third example.

[0384] Figure 12A This example illustrates a scenario where the average channel ratio (RAV) is adjusted to approximately 66%. The total channel ratio (RT) for each cell region (75) is approximately 66%. Figure 12B This example illustrates a scenario where the average channel ratio (RAV) is adjusted to 33%. The total channel ratio (RT) for each cell region (75) is 33%.

[0385] The total channel ratio RT can also be adjusted for each cell region 75. That is, multiple total channel ratios RT with different values ​​can be applied to each cell region 75. The total channel ratio RT is related to the temperature rise of semiconductor layer 2. For example, if the total channel ratio RT is increased, the temperature of semiconductor layer 2 will rise more easily. On the other hand, if the total channel ratio RT is decreased, the temperature of semiconductor layer 2 will be difficult to rise.

[0386] The above relationship can also be used to adjust the total channel ratio RT based on the temperature distribution of semiconductor layer 2. For example, the total channel ratio RT can be made smaller in regions of semiconductor layer 2 where the temperature is prone to rise, or the total channel ratio RT can be made larger in regions of semiconductor layer 2 where the temperature is difficult to rise.

[0387] The central portion of the output region 6 can be exemplified as a region in semiconductor layer 2 where the temperature is prone to rise. The peripheral portion of the output region 6 can be exemplified as a region in semiconductor layer 2 where the temperature is difficult to rise. Of course, the total channel ratio RT and the average channel ratio RAV can also be adjusted according to the temperature distribution of semiconductor layer 2.

[0388] Multiple cell regions 75 with a total channel ratio RT of 20% or more but less than 40% (e.g., 25%) can be converged in a region where the temperature is prone to rise (e.g., the central part). Multiple cell regions 75 with a total channel ratio RT of 60% or more but less than 80% (e.g., 75%) can also be converged in a region where the temperature is difficult to rise (e.g., the periphery). Multiple cell regions 75 with a total channel ratio RT of more than 40% but less than 60% (e.g., 50%) can also be converged in a region between a region where the temperature is prone to rise and a region where the temperature is difficult to rise.

[0389] Furthermore, total channel ratios RT of 20% to 40%, 40% to 60%, and 60% to 80% can also be applied to multiple cell regions 75 in a regular arrangement.

[0390] As an example, three total channel ratios RT, repeated in the order of 25% (low) → 50% (middle) → 75% (high), can also be applied to multiple cell regions 75. In this case, the average channel ratio RAV can also be adjusted to 50%. With this configuration, it is possible to suppress the formation of biases in the temperature distribution of the semiconductor layer 2 with a relatively simple design. The specific way in which this configuration is applied is shown in the following embodiments.

[0391] Figure 13 It is a graph showing the relationship between active clamping tolerance Eac and areal resistivity Ron·A investigated through actual measurements. Figure 13 The diagram illustrates the characteristics of simultaneously controlling the first MISFET 56 and the second MISFET 57 to be in the on and off states.

[0392] exist Figure 13 In the middle, the vertical axis represents the active clamping tolerance Eac [mJ / mm]. 2 The horizontal axis represents the area resistivity Ron·A [mΩ·mm]. 2 ].like Figure 3 As described above, the active clamping withstand capability Eac is the withstand capability relative to the back electromotive force. The areal resistivity Ron·A represents the on-resistivity within semiconductor layer 2 during normal operation.

[0393] Figure 13 The diagram shows the first plotting point P1, the second plotting point P2, the third plotting point P3, and the fourth plotting point P4. The first plotting point P1, the second plotting point P2, the third plotting point P3, and the fourth plotting point P4 represent the characteristics of the average channel ratio RAV (that is, the total channel ratio RT occupied by each cell region 75) when adjusted to 66%, 50%, 33%, and 25%, respectively.

[0394] When the average channel ratio RAV is increased, the area resistivity Ron·A decreases during normal operation, and the active clamping tolerance Eac decreases during active clamping operation. Conversely, when the average channel ratio RAV is decreased, the area resistivity Ron·A increases during normal operation, and the active clamping tolerance Eac increases during active clamping operation.

[0395] If the areal resistivity Ron·A is used as a reference, the average channel ratio RAV is preferably 33% or more (specifically, 33% or more and less than 100%). If the active clamping tolerance Eac is used as a reference, the average channel ratio RAV is preferably less than 33% (specifically, more than 0% and less than 33%).

[0396] The decrease in areal resistivity Ron·A due to the increase in average channel ratio RAV is because of the increased current path. The decrease in active clamping withstand capacity Eac due to the increase in average channel ratio RAV is because of the sharp temperature rise caused by the resulting back electromotive force.

[0397] In particular, when the average channel ratio RAV (total channel ratio RT) is relatively large, the possibility of a localized and sharp temperature rise increases in the region between the adjacent first trench gate structure 60 and second trench gate structure 70. It is believed that the active clamp tolerance Eac decreases due to this temperature rise.

[0398] On the other hand, the increase in areal resistivity Ron·A due to the decrease in average channel ratio RAV is because the current path is narrowed. The increase in active clamping tolerance Eac due to the decrease in average channel ratio RAV is considered to suppress localized and sharp temperature rises because the average channel ratio RAV (total channel ratio RT) is relatively small.

[0399] according to Figure 13 The results from the charts show that the adjustment method based on the average channel ratio RAV (total channel ratio RT) has a trade-off relationship, and it is difficult to get rid of this trade-off relationship to achieve both excellent areal resistivity Ron·A and excellent active clamping tolerance Eac.

[0400] On the other hand, according to Figure 13 The results from the graphs show that in the power MISFET9, during normal operation, it operates close to the first plotted point P1 (RAV = 66%), and during active clamping operation, it operates close to the fourth plotted point P4 (RAV = 25%). This achieves a balance between excellent areal resistivity Ron·A and excellent active clamping tolerance Eac. Therefore, the following control is implemented in this mode.

[0401] Figure 14A It is used for explanation Figure 1 A cross-sectional perspective view of the normal operation of the first control example of the semiconductor device 1 shown. Figure 14B It is used for explanation Figure 1 A cross-sectional perspective view of the active clamping operation of the first control example of the semiconductor device 1 shown. Figure 14A as well as Figure 14B For ease of explanation, the structure above the first main surface 3 is omitted, and the gate control wiring 17 is simplified.

[0402] Reference Figure 14A During normal operation of the power MISFET9, a first turn-on signal Von1 is input to the first gate control wiring 17A, a second turn-on signal Von2 is input to the second gate control wiring 17B, and a third turn-on signal Von3 is input to the third gate control wiring 17C.

[0403] The first turn-on signal Von1, the second turn-on signal Von2, and the third turn-on signal Von3 are input from the controller IC10. Each of these signals has a voltage greater than or equal to the gate threshold voltage Vth. Alternatively, each of these signals may have the same voltage.

[0404] In this case, the first opening-side electrode 87, the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 are all turned on. That is, the first opening-side electrode 87, the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 function as gate electrodes.

[0405] Therefore, both the first channel area 91 and the second channel area 111 are controlled to be in the connected state. Figure 14A In the image, dotted shadows indicate the first channel region 91 and the second channel region 111 in the connected state.

[0406] As a result, both the first MISFET 56 and the second MISFET 57 are driven (fully on control). The channel utilization RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. The channel utilization RU is the ratio of the first channel region 91 and the second channel region 111 that are controlled to be on.

[0407] The characteristic channel ratio RC is the value obtained by multiplying the average channel ratio RAV by the channel utilization RU (RC = RAV × RU). The characteristics of the power MISFET9 (area resistivity Ron·A and active clamping tolerance Eac) are determined based on the characteristic channel ratio RC. Therefore, the area resistivity Ron·A in Figure 13 The resistivity Ron·A in the graph is close to that shown by the second plotted point P2.

[0408] On the other hand, refer to Figure 14BWhen the power MISFET9 is in active clamping mode, a disconnect signal Voff is input to the first gate control wiring 17A, a first clamping signal VCon1 is input to the second gate control wiring 17B, and a second clamping signal VCon2 is input to the third gate control wiring 17C.

[0409] The disconnect signal Voff, the first clamp turn-on signal VCon1, and the second clamp turn-on signal VCon2 are input from the controller IC10. The disconnect signal Voff has a voltage less than the gate threshold voltage Vth (e.g., a reference voltage). The first clamp turn-on signal VCon1 and the second clamp turn-on signal VCon2 each have a voltage greater than the gate threshold voltage Vth. The first clamp turn-on signal VCon1 and the second clamp turn-on signal VCon2 may also have equal voltages. The first clamp turn-on signal VCon1 and the second clamp turn-on signal VCon2 may also have voltages below or less than the voltage during normal operation.

[0410] In this case, the first opening-side electrode 87 is in the off state, while the first bottom-side electrode 86, the second bottom-side electrode 106, and the second opening-side electrode 107 are in the on state. Therefore, the first channel region 91 is controlled to be in the off state and the second channel region 111 is controlled to be in the on state. Figure 14B In the diagram, the first channel region 91 in the disconnected state is shown by smeared shading, and the second channel region 111 in the connected state is shown by dotted shading.

[0411] As a result, the first MISFET 56 is controlled to be in the off state, while the second MISFET 57 is controlled to be in the on state (second half-on control). Thus, the channel utilization RU during active clamping operation becomes greater than zero and less than the channel utilization RU during normal operation.

[0412] The channel utilization RU during active clamping operation is 50%. Additionally, the characteristic channel ratio RC during active clamping operation is 25%. Therefore, the active clamping tolerance Eac is... Figure 13 The active clamp tolerance Eac is shown in the graph near the fourth plotted point P4.

[0413] In the first control example, an example of applying the second half-on control during active clamping operation was described. However, the first half-on control can also be applied during active clamping operation.

[0414] Figure 15A It is used for explanation Figure 1 A cross-sectional perspective view of the normal operation of the second control example of the semiconductor device 1 shown. Figure 15B It is used for explanation Figure 1A cross-sectional perspective view of the active clamping operation of the second control example of the semiconductor device 1 shown. Figure 15A as well as Figure 15B For ease of explanation, the structure above the first main surface 3 is omitted, and the gate control wiring 17 is simplified.

[0415] Reference Figure 15A During normal operation of the power MISFET9, a first turn-on signal Von1 is input to the first gate control wiring 17A, a second turn-on signal Von2 is input to the second gate control wiring 17B, and a turn-off signal Voff is input to the third gate control wiring 17C.

[0416] The first turn-on signal Von1, the second turn-on signal Von2, and the turn-off signal Voff are input from the controller IC10. The first turn-on signal Von1 and the second turn-on signal Von2 each have a voltage greater than or equal to the gate threshold voltage Vth. Alternatively, the first turn-on signal Von1 and the second turn-on signal Von2 may have equal voltages. The turn-off signal Voff has a voltage less than the gate threshold voltage Vth (e.g., a reference voltage).

[0417] In this case, the first opening-side electrode 87 and the second opening-side electrode 107 are respectively turned on, while the first bottom-side electrode 86 and the second bottom-side electrode 106 are respectively turned off. That is, the first opening-side electrode 87 and the second opening-side electrode 107 function as gate electrodes, while the first bottom-side electrode 86 and the second bottom-side electrode 106 function as field electrodes.

[0418] Therefore, both the first channel area 91 and the second channel area 111 are controlled to be in the connected state. Figure 15A In the diagram, the first channel region 91 and the second channel region 111 in the connected state are shown by dotted shadow lines.

[0419] As a result, both the first MISFET 56 and the second MISFET 57 are driven (fully on control). The channel utilization RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. Therefore, the areal resistivity Ron·A is... Figure 13 The resistivity Ron·A in the graph is close to that shown by the second plotted point P2.

[0420] On the other hand, refer to Figure 15B When the power MISFET9 is in active clamping mode, a first disconnect signal Voff1 is input to the first gate control wiring 17A, a clamping turn-on signal VCon is input to the second gate control wiring 17B, and a second disconnect signal Voff2 is input to the third gate control wiring 17C.

[0421] The first disconnect signal Voff1, the clamp turn-on signal VCon, and the second disconnect signal Voff2 are input from the controller IC10. The first disconnect signal Voff1 has a voltage less than the gate threshold voltage Vth (e.g., a reference voltage). The clamp turn-on signal VCon has a voltage greater than or equal to the gate threshold voltage Vth. The clamp turn-on signal VCon may also have a voltage less than or lower than the voltage during normal operation. The second disconnect signal Voff2 has a voltage value less than the gate threshold voltage Vth (e.g., a reference voltage).

[0422] In this case, the first opening-side electrode 87, the first bottom-side electrode 86, and the second bottom-side electrode 106 are all in an off state, while the second opening-side electrode 107 is in an on state. Therefore, the first channel region 91 is controlled to be in an off state and the second channel region 111 is controlled to be in an on state. Figure 15B In the diagram, the first channel region 91 in the disconnected state is shown by smeared shading, and the second channel region 111 in the connected state is shown by dotted shading.

[0423] As a result, the first MISFET 56 is controlled to be in the off state, while the second MISFET 57 is controlled to be in the on state (second half-on control). Thus, the channel utilization RU during active clamping operation becomes greater than zero and less than the channel utilization RU during normal operation.

[0424] The channel utilization RU during active clamping operation is 50%. Additionally, the characteristic channel ratio RC during active clamping operation is 25%. Therefore, the active clamping tolerance Eac is... Figure 13 The active clamp tolerance Eac is shown in the graph near the fourth plotted point P4.

[0425] In the second control example, an example of applying a second half-on control during active clamping operation was described. However, a first half-on control can also be applied during active clamping operation.

[0426] The semiconductor device 1 includes an IPD (Intelligent Power Device) formed on the semiconductor layer 2. The IPD includes a controller IC 10 that controls a power MISFET 9. Specifically, the power MISFET 9 includes a first MISFET 56 and a second MISFET 57. The controller IC 10 individually controls the first MISFET 56 and the second MISFET 57.

[0427] Specifically, during normal operation, the controller IC10 controls the first MISFET56 and the second MISFET57 to be turned on, and during active clamping operation, it controls the first MISFET56 to be turned off and the second MISFET57 to be turned on.

[0428] Therefore, during normal operation, current can flow using the first MISFET 56 and the second MISFET 57. This allows for a reduction in the areal resistivity Ron·A (on-resistance).

[0429] On the other hand, during active clamping, current can flow using the second MISFET 57 while the first MISFET 56 is stopped, thus the back electromotive force can be consumed (absorbed) by the second MISFET 57. This suppresses the sharp temperature rise caused by the back electromotive force, thereby improving the active clamping tolerance Eac.

[0430] Specifically, the semiconductor device 1 has a first MISFET 56 including a first FET structure 58 and a second MISFET 57 including a second FET structure 68. The first FET structure 58 includes a first trench gate structure 60 and a first channel region 91. The second FET structure 68 includes a second trench gate structure 70 and a second channel region 111.

[0431] In this case, the controller IC10 controls the first MISFET 56 and the second MISFET 57 by applying different characteristic channel ratios RC (channel area) during normal operation and during active clamping operation. Specifically, the controller IC10 controls the first MISFET 56 and the second MISFET 57 such that the channel utilization RU during active clamping operation is greater than zero and less than the channel utilization RU during normal operation.

[0432] Therefore, during normal operation, the characteristic channel ratio RC increases relatively. This increases the current path, thereby reducing the area resistivity Ron·A (on-off resistance). On the other hand, during active clamping operation, the characteristic channel ratio RC decreases relatively. This suppresses the sharp temperature rise caused by back electromotive force, thus improving the active clamping withstand capacity Eac.

[0433] Therefore, it is possible to provide a semiconductor device 1 that is detachable from... Figure 13 The trade-off shown achieves a balance between excellent areal resistivity Ron·A and excellent active clamping tolerance Eac.

[0434] <Second Implementation Method>

[0435] Figure 16 Is with Figure 7 The cross-sectional perspective view of the corresponding region is a perspective view showing the semiconductor device 151 according to the second embodiment of the present invention. Hereinafter, the same reference numerals will be used to mark the structures corresponding to the structure described for the semiconductor device 1, and the description will be omitted.

[0436] In semiconductor device 1, a plurality of first FET structures 58 and a plurality of second FET structures 68 are formed in a configuration where one first FET structure 58 and one second FET structure 68 are arranged alternately. In contrast, in semiconductor device 151, a plurality of first FET structures 58 and a plurality of second FET structures 68 are formed in a configuration where groups of a plurality of first FET structures 58 (in this configuration, two) and groups of a plurality of second FET structures 68 (in this configuration, two) are arranged alternately.

[0437] Furthermore, in semiconductor device 1, the second channel ratio R2 (second channel area S2) is equal to the first channel ratio R1 (first channel area S1). In contrast, in semiconductor device 151, the second channel ratio R2 is different from the first channel ratio R1 (R1 ≠ R2). Specifically, the second channel ratio R2 is smaller than the first channel ratio R1 (R2 < R1). The structure of semiconductor device 151 will be described in detail below.

[0438] Reference Figure 16 In this manner, the multiple unit regions 75 are respectively divided into regions between two adjacent first FET structures 58, regions between one adjacent first FET structure 58 and one adjacent second FET structure 68, and regions between two adjacent second FET structures 68.

[0439] In this method, three total channel ratios RT with mutually different values ​​are applied to multiple cell regions 75. The three total channel ratios RT include a first total channel ratio RT1, a second total channel ratio RT2, and a third total channel ratio RT3.

[0440] The first total channel ratio RT1 is applied to the region between two adjacent first FET structures 58. In the region between two adjacent first FET structures 58, no second channel region 111 is formed in its construction.

[0441] The first total channel ratio RT1 is the sum of the first channel ratios R1 of two adjacent first FET structures 58. As an example, the first total channel ratio RT1 can also be adjusted to be above 60% and below 80%. In this case, the first total channel ratio RT1 is adjusted to 75%. In the first total channel ratio RT1, the first channel ratio R1 on one side and the first channel ratio R1 on the other side are both 37.5%.

[0442] The second total channel ratio RT2 is applied to the region between a first FET structure 58 and a second FET structure 68 that are adjacent to each other. In the region between a first FET structure 58 and a second FET structure 68 that are adjacent to each other, a first channel region 91 and a second channel region 111 are formed on its structure.

[0443] The second total channel ratio RT2 is the sum of the first channel ratio R1 and the second channel ratio R2. As an example, the second total channel ratio RT2 can also be adjusted to be greater than 40% and less than 60%. In this case, the second total channel ratio RT2 is adjusted to 50%. In the second total channel ratio RT2, the first channel ratio R1 is 25%, and the second channel ratio R2 is 25%.

[0444] The third total channel ratio RT3 is applied to the region between two adjacent second FET structures 68. In the region between two adjacent second FET structures 68, the first channel region 91 is not formed in its construction.

[0445] The third total channel ratio RT3 is the sum of the second channel ratios R2 of the two adjacent second FET structures 68. As an example, the third total channel ratio RT3 can also be adjusted to be above 20% and below 40%. In this case, the third total channel ratio RT3 is adjusted to 25%. In the third total channel ratio RT3, the second channel ratio R2 on one side and the second channel ratio R2 on the other side are both 12.5%.

[0446] The first channel region 91 occupies more than 50% (1 / 2) of the total channel. In this configuration, the first channel region 91 occupies 62.5% of the total channel, and the second channel region 111 occupies 37.5% of the total channel. That is, the second channel ratio R2 is less than the first channel ratio R1 (R2 < R1). In this configuration, the average channel ratio RAV is 50%. The other structures in the semiconductor device 151 are the same as those in the semiconductor device 1. In this configuration, the control described below is implemented.

[0447] Figure 17A It is used for explanation Figure 1 A cross-sectional perspective view of the normal operation of the first control example of the semiconductor device 151 shown. Figure 17B It is used for explanation Figure 1 A cross-sectional perspective view of the active clamping operation of the first control example of the semiconductor device 151 shown. Figure 17A as well as Figure 17B For ease of explanation, the structure above the first main surface 3 is omitted, and the gate control wiring 17 is simplified.

[0448] Reference Figure 17A During normal operation of the power MISFET9, a first turn-on signal Von1 is input to the first gate control wiring 17A, a second turn-on signal Von2 is input to the second gate control wiring 17B, and a third turn-on signal Von3 is input to the third gate control wiring 17C.

[0449] The first turn-on signal Von1, the second turn-on signal Von2, and the third turn-on signal Von3 are input from the controller IC10. Each of these signals has a voltage greater than or equal to the gate threshold voltage Vth. Alternatively, each of these signals may have the same voltage.

[0450] In this case, the first opening-side electrode 87, the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 are all turned on. That is, the first opening-side electrode 87, the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 function as gate electrodes.

[0451] Therefore, both the first channel area 91 and the second channel area 111 are controlled to be in the connected state. Figure 17A In the diagram, the first channel region 91 and the second channel region 111 in the connected state are shown by dotted shadow lines.

[0452] As a result, both the first MISFET 56 and the second MISFET 57 are driven (fully on control). The channel utilization RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. Therefore, the areal resistivity Ron·A is... Figure 13 The resistivity Ron·A in the graph is close to that shown by the second plotted point P2.

[0453] On the other hand, refer to Figure 17B When the power MISFET9 is in active clamping mode, a disconnect signal Voff is input to the first gate control wiring 17A, a first clamping signal VCon1 is input to the second gate control wiring 17B, and a second clamping signal VCon2 is input to the third gate control wiring 17C.

[0454] The disconnect signal Voff, the first clamp turn-on signal VCon1, and the second clamp turn-on signal VCon2 are input from the controller IC10. The disconnect signal Voff has a voltage less than the gate threshold voltage Vth (e.g., a reference voltage). The first clamp turn-on signal VCon1 and the second clamp turn-on signal VCon2 each have a voltage greater than the gate threshold voltage Vth. The first clamp turn-on signal VCon1 and the second clamp turn-on signal VCon2 may also have equal voltages. Alternatively, the first clamp turn-on signal VCon1 and the second clamp turn-on signal VCon2 may have voltages less than or below the voltage during normal operation.

[0455] In this case, the first opening-side electrode 87 is in the off state, while the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 are in the on state. Therefore, the first channel region 91 is controlled to be in the off state and the second channel region 111 is controlled to be in the on state. Figure 17B In the diagram, the first channel region 91 in the disconnected state is shown by smeared shading, and the second channel region 111 in the connected state is shown by dotted shading.

[0456] As a result, the first MISFET 56 is controlled to be in the off state, while the second MISFET 57 is controlled to be in the on state (second half-on control). Therefore, the channel utilization RU during active clamping operation becomes greater than zero and less than the channel utilization RU during normal operation. Specifically, the first channel region 91, having a first channel ratio R1 exceeding the second channel ratio R2 (R2 < R1), is controlled to be in the off state, thus the channel utilization RU during active clamping operation is less than half of the channel utilization RU during normal operation.

[0457] The channel utilization rate RU during active clamping operation is 37.5%. Additionally, the characteristic channel ratio RC during active clamping operation is 18.75%. Therefore, the active clamping tolerance Eac is... Figure 13 The active clamping tolerance Eac is close to or exceeds the active clamping tolerance Eac shown by the fourth plotted point P4 in the chart.

[0458] Figure 18A It is used for explanation Figure 16 A cross-sectional perspective view of the normal operation of the second control example of the semiconductor device 151 shown. Figure 18B It is used for explanation Figure 16 A cross-sectional perspective view of the active clamping operation of the second control example of the semiconductor device 151 shown. Figure 18A as well as Figure 18B For ease of explanation, the structure above the first main surface 3 is omitted, and the gate control wiring 17 is simplified.

[0459] Reference Figure 18A During normal operation of the power MISFET9, a first turn-on signal Von1 is input to the first gate control wiring 17A, a second turn-on signal Von2 is input to the second gate control wiring 17B, and a turn-off signal Voff is input to the third gate control wiring 17C.

[0460] The first turn-on signal Von1, the second turn-on signal Von2, and the turn-off signal Voff are input from the controller IC10. The first turn-on signal Von1 and the second turn-on signal Von2 each have a voltage greater than or equal to the gate threshold voltage Vth. Alternatively, the first turn-on signal Von1 and the second turn-on signal Von2 may have equal voltages. The turn-off signal Voff may also be a reference voltage.

[0461] In this case, the first opening-side electrode 87 and the second opening-side electrode 107 are respectively turned on, while the first bottom-side electrode 86 and the second bottom-side electrode 106 are respectively turned off. That is, the first opening-side electrode 87 and the second opening-side electrode 107 function as gate electrodes, while the first bottom-side electrode 86 and the second bottom-side electrode 106 function as field electrodes.

[0462] Therefore, both the first channel area 91 and the second channel area 111 are controlled to be in the connected state. Figure 18A In the diagram, the first channel region 91 and the second channel region 111 in the connected state are shown by dotted shadow lines.

[0463] As a result, both the first MISFET 56 and the second MISFET 57 are driven (fully on control). The channel utilization RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. Therefore, the areal resistivity Ron·A is... Figure 13 The resistivity Ron·A in the graph is close to that shown by the second plotted point P2.

[0464] On the other hand, refer to Figure 18B When the power MISFET9 is in active clamping mode, a first disconnect signal Voff1 is input to the first gate control wiring 17A, a clamping turn-on signal VCon is input to the second gate control wiring 17B, and a second disconnect signal Voff2 is input to the third gate control wiring 17C.

[0465] The first disconnect signal Voff1, the clamp turn-on signal VCon, and the second disconnect signal Voff2 are input from the controller IC10. The first disconnect signal Voff1 has a voltage less than the gate threshold voltage Vth (e.g., a reference voltage). The clamp turn-on signal VCon has a voltage greater than or equal to the gate threshold voltage Vth. The clamp turn-on signal VCon may also have a voltage less than or lower than the voltage during normal operation. The second disconnect signal Voff2 may also be a reference voltage.

[0466] In this case, the first opening-side electrode 87, the first bottom-side electrode 86, and the second bottom-side electrode 106 are all in an off state, while the second opening-side electrode 107 is in an on state. Therefore, the first channel region 91 is controlled to be in an off state and the second channel region 111 is controlled to be in an on state. Figure 18B In the diagram, the first channel region 91 in the disconnected state is shown by smeared shading, and the second channel region 111 in the connected state is shown by dotted shading.

[0467] As a result, the first MISFET 56 is controlled to be in the off state, while the second MISFET 57 is controlled to be in the on state (second half-on control). Therefore, the channel utilization RU during active clamping operation becomes greater than zero and less than the channel utilization RU during normal operation. Specifically, the first channel region 91, having a first channel ratio R1 exceeding the second channel ratio R2 (R2 < R1), is controlled to be in the off state, thus the channel utilization RU during active clamping operation is less than half of the channel utilization RU during normal operation.

[0468] The channel utilization rate RU during active clamping operation is 37.5%. Additionally, the characteristic channel ratio RC during active clamping operation is 18.75%. Therefore, the active clamping tolerance Eac is... Figure 13 The active clamping tolerance Eac is close to or exceeds the active clamping tolerance Eac shown by the fourth plotted point P4 in the chart.

[0469] Figure 19A It is used for explanation Figure 16 A cross-sectional perspective view of the normal operation of the third control example of the semiconductor device 151 shown. Figure 19B It is used for explanation Figure 16 A cross-sectional perspective view of the active clamping operation of the third control example of the semiconductor device 151 shown. Figure 19A as well as Figure 19B For ease of explanation, the structure above the first main surface 3 is omitted, and the gate control wiring 17 is simplified.

[0470] Reference Figure 19ADuring normal operation of the power MISFET9, an on signal Von is input to the first gate control line 17A, a first off signal Voff1 is input to the second gate control line 17B, and a second off signal Voff2 is input to the third gate control line 17C.

[0471] The on signal Von, the first off signal Voff1, and the second off signal Voff2 are input from the controller IC10. The on signal Von has a voltage greater than or equal to the gate threshold voltage Vth. The first off signal Voff1 and the second off signal Voff2 may also have voltages less than the gate threshold voltage Vth (e.g., a reference voltage).

[0472] In this case, the first opening-side electrode 87 is in the ON state, while the first bottom-side electrode 86, the second bottom-side electrode 106, and the second opening-side electrode 107 are in the OFF state. That is, the first opening-side electrode 87 functions as a gate electrode, while the first bottom-side electrode 86 and the second bottom-side electrode 106 function as field electrodes.

[0473] Therefore, the first channel region 91 is controlled to be in the ON state and the second channel region 111 is controlled to be in the OFF state. Figure 19A In the diagram, the first channel region 91 in the on state is shown by dotted shadow lines, and the second channel region 111 in the off state is shown by smeared shadow lines.

[0474] As a result, the first MISFET 56 is controlled to be in the ON state, while the second MISFET 57 is controlled to be in the OFF state (first half-ON control). Consequently, the second channel region 111, which has a second channel ratio R2 (R2 < R1) that is less than the first channel ratio R1, is controlled to be in the OFF state, and therefore the characteristic channel ratio RC during normal operation is less than the average channel ratio RAV.

[0475] The channel utilization rate RU during normal operation is 62.5%. Additionally, the characteristic channel ratio RC during normal operation is 31.25%. Therefore, the areal resistivity Ron·A is... Figure 13 The resistivity Ron·A in the graph is close to that shown by the third plotted point P3.

[0476] On the other hand, refer to Figure 19B When the power MISFET9 is in active clamping mode, a first disconnect signal Voff1 is input to the first gate control wiring 17A, a clamping turn-on signal VCon is input to the second gate control wiring 17B, and a second disconnect signal Voff2 is input to the third gate control wiring 17C.

[0477] The first disconnect signal Voff1, the clamp turn-on signal VCon, and the second disconnect signal Voff2 are input from the controller IC10. The first disconnect signal Voff1 has a voltage less than the gate threshold voltage Vth (e.g., a reference voltage). The clamp turn-on signal VCon has a voltage greater than or equal to the gate threshold voltage Vth. The clamp turn-on signal VCon may also have a voltage less than or lower than the voltage during normal operation. The second disconnect signal Voff2 may also be a reference voltage.

[0478] In this case, the second opening-side electrode 107 is turned on, while the first bottom-side electrode 86, the first opening-side electrode 87, and the second bottom-side electrode 106 are turned off. That is, the second opening-side electrode 107 functions as a gate electrode, while the first bottom-side electrode 86 and the second bottom-side electrode 106 function as field electrodes.

[0479] Therefore, the first channel region 91 is controlled to be in the off state and the second channel region 111 is controlled to be in the on state. Figure 19B In the diagram, the first channel region 91 in the disconnected state is shown by smeared shading, and the second channel region 111 in the connected state is shown by dotted shading.

[0480] As a result, the first MISFET 56 is controlled to be in the off state, while the second MISFET 57 is controlled to be in the on state (second half-on control). Thus, the first channel region 91, which has a first channel ratio R1 (R2 < R1) that exceeds the second channel ratio R2, is controlled to be in the off state, so the channel utilization RU during active clamping operation becomes greater than zero and less than the channel utilization RU during normal operation.

[0481] The channel utilization rate RU during active clamping operation is 37.5%. Additionally, the characteristic channel ratio RC during active clamping operation is 18.75%. Therefore, the active clamping tolerance Eac is... Figure 13 The active clamping tolerance Eac is close to or exceeds the active clamping tolerance Eac shown by the second plotted point P2 in the chart.

[0482] In the third control example, a disconnect signal Voff is input to the third gate control wiring 17C during normal operation and active clamping operation. However, an on signal Von may also be input to the third gate control wiring 17C during normal operation and active clamping operation.

[0483] As described above, the semiconductor device 151 can achieve the same effect as that described for semiconductor device 1. In particular, according to semiconductor device 151, the second channel ratio R2 is different from the first channel ratio R1 (R1≠R2). Specifically, the second channel ratio R2 is smaller than the first channel ratio R1 (R1>R2).

[0484] In this configuration, the controller IC10 controls the first MISFET 56 and the second MISFET 57 such that the channel utilization RU during active clamping operation is greater than zero and less than the channel utilization RU during normal operation. Specifically, during active clamping operation, the controller IC10 controls the first channel region 91 to be in an off state and the second channel region 111 to be in an on state. This improves the active clamping tolerance (Eac).

[0485] Furthermore, according to the semiconductor device 151, as shown in the third control example, a first half-on control is applied during normal operation, and a second half-on control can be applied during active clamping operation. Additionally, according to the semiconductor device 151, the second half-on control can also be applied during normal operation, and the first half-on control can be applied during active clamping operation.

[0486] Therefore, according to the semiconductor device 151, by simply changing the control method, the same average channel ratio RAV can be achieved, and various area resistivity Ron·A and active clamping tolerance Eac can be realized.

[0487] Furthermore, in the semiconductor device 151, a plurality of first FET structures 58 and a plurality of second FET structures 68 are formed in a configuration in which a plurality of (two in this case) first FET structures 58 and a plurality of (two in this case) second FET structures 68 are arranged alternately.

[0488] In a configuration where multiple first FET structures 58 are adjacent to each other, a first channel region 91 can be formed in the region between the multiple adjacent first FET structures 58 without being connected to the second channel region 111. Therefore, the first channel region 91 can be appropriately formed, thereby allowing the first channel ratio R1 to be appropriately adjusted.

[0489] Similarly, in a configuration where multiple second FET structures 68 are adjacent to each other, a second channel region 111 can be formed in the region between the multiple adjacent second FET structures 68 without being connected to the first channel region 91. Therefore, the second channel region 111 can be appropriately formed, thereby allowing the second channel ratio R2 to be appropriately adjusted. As a result, the average channel ratio RAV and the characteristic channel ratio RC can be appropriately adjusted.

[0490] <Third Implementation Method>

[0491] Figure 20 This is a perspective view of the semiconductor device 161 of the third embodiment of the present invention viewed from one direction. Figure 21 yes Figure 20 The cross-sectional perspective view of region XXI shown. Figure 22From Figure 21 A cross-sectional perspective view after removing the source electrode 12 and the gate control wiring 17. Figure 23 From Figure 22 A cross-sectional perspective view after removing the interlayer insulating layer 142. Hereinafter, for structures corresponding to those described in the semiconductor device 1, the same reference numerals will be used and descriptions will be omitted.

[0492] In semiconductor device 1, gate control wiring 17 includes a first gate control wiring 17A, a second gate control wiring 17B, and a third gate control wiring 17C. In contrast, in semiconductor device 161, gate control wiring 17 does not have a third gate control wiring 17C, and only includes the first gate control wiring 17A and the second gate control wiring 17B.

[0493] Furthermore, in semiconductor device 1, the second bottom-side electrode 106 is electrically connected to the first bottom-side electrode 86. In contrast, in semiconductor device 161, the second bottom-side electrode 106 is electrically insulated from the first bottom-side electrode 86.

[0494] Specifically, the semiconductor device 161 includes a plurality of trench contact structures 120, which are connected to the first trench gate structure 60 and the second trench gate structure 70 respectively in a manner that electrically insulates the first trench gate structure 60 and the second trench gate structure 70 from each other.

[0495] The structures of the regions at the other end of the first FET structure 58 and the other end of the second FET structure 68 are the same as the structures of the regions at one end of the first FET structure 58 and the other end of the second FET structure 68. Hereinafter, the structure of the regions at one end of the first FET structure 58 and the other end of the second FET structure 68 will be described as an example, and the description of the structures of the regions at the other end of the first FET structure 58 and the other end of the second FET structure 68 will be omitted.

[0496] Reference Figures 20-23 The plurality of trench contact structures 120 include a plurality of first trench contact structures 162 and a plurality of second trench contact structures 163. The plurality of first trench contact structures 162 are respectively connected to one end of a corresponding plurality of first trench gate structures 60, spaced apart from the plurality of second trench gate structures 70. In this configuration, the first trench contact structures 162 are connected in a one-to-one correspondence with their respective first trench gate structures 60.

[0497] Multiple second trench contact structures 163 are connected to one end of corresponding multiple second trench gate structures 70, spaced apart from multiple first trench gate structures 60. In this configuration, the second trench contact structures 163 are connected in a one-to-one correspondence with their respective second trench gate structures 70.

[0498] Each first trench contact structure 162 includes a first contact trench 164, a first contact insulating layer 165, and a first contact electrode 166. The first contact trench 164, the first contact insulating layer 165, and the first contact electrode 166 correspond to the contact trench 131, the contact insulating layer 132, and the contact electrode 133, respectively.

[0499] The first contact trench 164 is connected to one end of the first gate trench 81. In the first direction X, the width WTC1 of the first contact trench 164 is equal to the first width WT1 of the first gate trench 81 (WTC1 = WT1). The first contact trench 164 forms a trench extending in the second direction Y between itself and the first gate trench 81.

[0500] The first contact insulating layer 165 is integrally formed with the first insulating layer 82 in the connecting portion between the first gate trench 81 and the first contact trench 164. Specifically, the first contact insulating layer 165 includes an outgoing insulating layer 165A extending into the first gate trench 81. The outgoing insulating layer 165A corresponds to the outgoing insulating layer 132A described above. That is, the first contact insulating layer 165 traverses the connecting portion and is integrally formed with the first bottom-side insulating layer 84 and the first opening-side insulating layer 85 within the first gate trench 81.

[0501] The first contact electrode 166 is integrally formed with the first bottom electrode 86 in the communication portion between the first gate trench 81 and the first contact trench 164. Specifically, the first contact electrode 166 includes a lead-out electrode 166A extending into the first gate trench 81. The lead-out electrode 166A corresponds to the lead-out electrode 133A described above.

[0502] That is, the first contact electrode 166 traverses the connecting portion and is electrically connected to the first bottom-side electrode 86 within the first gate trench 81. Within the first gate trench 81, the first intermediate insulating layer 88 is located between the first contact electrode 166 and the first opening-side electrode 87.

[0503] Each second trench contact structure 163 includes a second contact trench 167, a second contact insulating layer 168, and a second contact electrode 169. The second contact trench 167, the second contact insulating layer 168, and the second contact electrode 169 correspond to the contact trench 131, the contact insulating layer 132, and the contact electrode 133 mentioned above, respectively.

[0504] The second contact trench 167 is connected to one end of the second gate trench 101. In the first direction X, the width WTC2 of the second contact trench 167 is equal to the second width WT2 of the second gate trench 101 (WTC2 = WT2). The second contact trench 167 forms a trench extending in the second direction Y between itself and the second gate trench 101.

[0505] The second contact insulating layer 168 is integrally formed with the second insulating layer 102 in the communication portion between the second gate trench 101 and the second contact trench 167. Specifically, the second contact insulating layer 168 includes an outgoing insulating layer 168A extending into the second gate trench 101. The outgoing insulating layer 168A corresponds to the outgoing insulating layer 132A described above. That is, the second contact insulating layer 168 traverses the communication portion and is integrally formed with the second bottom-side insulating layer 104 and the second opening-side insulating layer 105 within the second gate trench 101.

[0506] The second contact electrode 169 is integrally formed with the second bottom-side electrode 106 in the communication portion between the second gate trench 101 and the second contact trench 167. Specifically, the second contact electrode 169 includes a lead-out electrode 169A extending into the second gate trench 101. The lead-out electrode 169A corresponds to the lead-out electrode 133A described above.

[0507] That is, the second contact electrode 169 traverses the connecting portion and is electrically connected to the second bottom side electrode 106 within the second gate trench 101. Within the second gate trench 101, the second intermediate insulating layer 108 is located between the second contact electrode 169 and the second opening side electrode 107.

[0508] The second contact electrode 169 is electrically insulated from the first contact electrode 166. Therefore, the second bottom electrode 106 is electrically insulated from the first bottom electrode 86. That is, the first bottom electrode 86 and the second bottom electrode 106 are configured to be independently controllable.

[0509] In this configuration, the plurality of third plug electrodes 145 includes a plurality of third plug electrodes 145A and a plurality of third plug electrodes 145B. The plurality of third plug electrodes 145A are respectively embedded in portions of the first contact electrode 166 that cover the first trench contact structure 162 within the interlayer insulating layer 142. The plurality of third plug electrodes 145A penetrate the interlayer insulating layer 142 and are connected to the first contact electrode 166.

[0510] Multiple third plug electrodes 145B are embedded in portions of the second contact electrode 169 that cover the second trench contact structure 163 within the interlayer insulating layer 142. The multiple third plug electrodes 145B penetrate the interlayer insulating layer 142 and are connected to the second contact electrode 169.

[0511] The first gate control wiring 17A in the gate control wiring 17 is electrically connected to the first bottom-side electrode 86 and the first opening-side electrode 87. Specifically, the first gate control wiring 17A is electrically connected to a plurality of first plug electrodes 143 and a plurality of third plug electrodes 145A on the interlayer insulating layer 142. The wiring pattern of the first gate control wiring 17A is arbitrary.

[0512] A gate control signal from the controller IC10 is input to the first gate control wiring 17A. The gate control signal is transmitted to the first bottom side electrode 86 and the first opening side electrode 87 via a plurality of first plug electrodes 143 and a plurality of third plug electrodes 145A.

[0513] Therefore, in this configuration, the first bottom-side electrode 86 and the first opening-side electrode 87 are simultaneously controlled to have the same voltage. This appropriately suppresses the formation of a potential difference between the first bottom-side electrode 86 and the first opening-side electrode 87, thus appropriately suppressing electric field concentration relative to the first intermediate insulating layer 88. As a result, the breakdown voltage of the first trench gate structure 60 can be improved.

[0514] The second gate control wiring 17B in the gate control wiring 17 is electrically connected to the second bottom-side electrode 106 and the second opening-side electrode 107. Specifically, the second gate control wiring 17B is electrically connected to a plurality of second plug electrodes 144 and a plurality of third plug electrodes 145B on the interlayer insulating layer 142. The wiring pattern of the second gate control wiring 17B is arbitrary.

[0515] A gate control signal from the controller IC10 is input to the second gate control wiring 17B. The gate control signal is transmitted to the second bottom-side electrode 106 and the second opening-side electrode 107 via a plurality of first plug electrodes 143 and a plurality of third plug electrodes 145B.

[0516] Therefore, in this configuration, the second bottom-side electrode 106 and the second opening-side electrode 107 are simultaneously controlled to have the same voltage. This appropriately suppresses the formation of a potential difference between the second bottom-side electrode 106 and the second opening-side electrode 107, thus appropriately suppressing electric field concentration relative to the second intermediate insulating layer 108. As a result, the breakdown voltage of the second trench gate structure 70 can be improved.

[0517] Figure 24A It is used for explanation Figure 23 A cross-sectional perspective view of the normal operation of the semiconductor device 161 shown. Figure 24B It is used for explanation Figure 23 A cross-sectional perspective view of the active clamping operation of the semiconductor device 161 shown. Figure 24A as well as Figure 24BFor ease of explanation, the structure above the first main surface 3 is omitted, and the gate control wiring 17 is simplified.

[0518] Reference Figure 24A During normal operation of the power MISFET 9, a first turn-on signal Von1 is input to the first gate control wiring 17A, and a second turn-on signal Von2 is input to the second gate control wiring 17B. The first turn-on signal Von1 and the second turn-on signal Von2 are respectively input from the controller IC10.

[0519] The first turn-on signal Von1 and the second turn-on signal Von2 each have a voltage greater than or equal to the gate threshold voltage Vth. Alternatively, the first turn-on signal Von1 and the second turn-on signal Von2 may each have the same voltage.

[0520] In this case, the first opening-side electrode 87, the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 are all turned on. That is, the first opening-side electrode 87, the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 function as gate electrodes.

[0521] Therefore, both the first channel area 91 and the second channel area 111 are controlled to be in the connected state. Figure 24A In the diagram, the first channel region 91 and the second channel region 111 in the connected state are shown by dotted shadow lines.

[0522] As a result, both the first MISFET 56 and the second MISFET 57 are driven (fully on control). The channel utilization RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. Therefore, the areal resistivity Ron·A is... Figure 13 The resistivity Ron·A in the graph is close to that shown by the second plotted point P2.

[0523] On the other hand, refer to Figure 24B When the power MISFET9 is in active clamping mode, a disconnect signal Voff is input to the first gate control wiring 17A, and a clamping signal VCon is input to the second gate control wiring 17B.

[0524] The disconnect signal Voff and the clamp turn-on signal VCon are input from controller IC10. The disconnect signal Voff has a voltage less than the gate threshold voltage Vth (e.g., a reference voltage). The clamp turn-on signal VCon has a voltage greater than or equal to the gate threshold voltage Vth. The clamp turn-on signal VCon may also have a voltage less than or lower than the voltage during normal operation.

[0525] In this case, the first bottom-side electrode 86 and the first opening-side electrode 87 are respectively in an off state, while the second bottom-side electrode 106 and the second opening-side electrode 107 are respectively in an on state. Therefore, the first channel region 91 is controlled to be in an off state and the second channel region 111 is controlled to be in an on state. Figure 24B In the diagram, the first channel region 91 in the disconnected state is shown by smeared shading, and the second channel region 111 in the connected state is shown by dotted shading.

[0526] As a result, the first MISFET 56 is controlled to be in the off state, while the second MISFET 57 is controlled to be in the on state (second half-on control). Thus, the channel utilization RU during active clamping operation becomes greater than zero and less than the channel utilization RU during normal operation.

[0527] The channel utilization RU during active clamping operation is 50%. Additionally, the characteristic channel ratio RC during active clamping operation is 25%. Therefore, the active clamping tolerance Eac is... Figure 13 The active clamp tolerance Eac is shown in the graph near the fourth plotted point P4.

[0528] In this control example, an example of applying a second half-on control during active clamping operation is described. However, a first half-on control can also be applied during active clamping operation.

[0529] As described above, the semiconductor device 161 can achieve the same effect as that described for the semiconductor device 1. In particular, according to the semiconductor device 161, the second bottom electrode 106 is electrically insulated from the first bottom electrode 86, and the second opening-side electrode 107 is electrically insulated from the first opening-side electrode 87.

[0530] In this configuration, the controller IC 10 simultaneously controls the first bottom-side electrode 86 and the first aperture-side electrode 87 of the first MISFET 56 with the same voltage. This appropriately suppresses the formation of a potential difference between the first bottom-side electrode 86 and the first aperture-side electrode 87 during normal operation and active clamping operation. Consequently, electric field concentration relative to the first intermediate insulating layer 88 can be appropriately suppressed, thus improving the breakdown voltage of the first trench gate configuration 60.

[0531] Furthermore, the controller IC 10 simultaneously controls the second bottom-side electrode 106 and the second opening-side electrode 107 of the second MISFET 57 with the same voltage. This appropriately suppresses the formation of a potential difference between the second bottom-side electrode 106 and the second opening-side electrode 107 during normal operation and active clamping operation. As a result, electric field concentration relative to the second intermediate insulating layer 108 can be appropriately suppressed, thus improving the breakdown voltage of the second trench gate structure 70.

[0532] <Fourth Implementation Method>

[0533] Figure 25 Is with Figure 21 The cross-sectional perspective view of the corresponding region is a cross-sectional perspective view of the semiconductor device 171 according to the fourth embodiment of the present invention. Figure 26 From Figure 25 A cross-sectional perspective view showing the structure above semiconductor layer 2 removed. Hereinafter, the same reference numerals will be used for structures corresponding to those described in the semiconductor device 161, and descriptions will be omitted.

[0534] Hereinafter, the construction of the region at one end of the first FET structure 58 and the region at one end of the second FET structure 68 will be described as an example, and the description of the construction of the region at the other end of the first FET structure 58 and the region at the other end of the second FET structure 68 will be omitted.

[0535] In semiconductor device 161, a plurality of first FET structures 58 and a plurality of second FET structures 68 are formed in a configuration where one first FET structure 58 and one second FET structure 68 are arranged alternately. In contrast, in semiconductor device 171, a plurality of first FET structures 58 and a plurality of second FET structures 68 are formed in a configuration where groups of a plurality of first FET structures 58 (in this configuration, two) and groups of a plurality of second FET structures 68 (in this configuration, two) are arranged alternately.

[0536] Furthermore, in semiconductor device 161, a plurality of first trench contact structures 162 are connected to corresponding first trench gate structures 60 in a one-to-one correspondence. In contrast, in semiconductor device 171, the plurality of first trench contact structures 162 are respectively connected to groups of adjacent (in this configuration, two) first trench gate structures 60. The plurality of first trench contact structures 162 are formed in an arched shape when viewed from above.

[0537] Furthermore, in semiconductor device 161, a plurality of second trench contact structures 163 are connected to corresponding second trench gate structures 70 in a one-to-one correspondence. In contrast, in semiconductor device 171, the plurality of second trench contact structures 163 are each connected to a group of adjacent (in this configuration, two) second trench gate structures 70. The plurality of second trench contact structures 163 are formed in an arched shape when viewed from above. The structure of semiconductor device 171 will now be described in detail.

[0538] Reference Figure 25 as well as Figure 26In this manner, the multiple unit regions 75 are respectively divided into regions between two adjacent first FET structures 58, regions between one adjacent first FET structure 58 and one adjacent second FET structure 68, and regions between two adjacent second FET structures 68.

[0539] In this method, three total channel ratios RT are applied in multiple unit regions 75. The three total channel ratios RT include a first total channel ratio RT1, a second total channel ratio RT2, and a third total channel ratio RT3.

[0540] The first total channel ratio RT1 is applied to the region between two adjacent first FET structures 58. In the region between two adjacent first FET structures 58, no second channel region 111 is formed in its construction.

[0541] The first total channel ratio RT1 is the sum of the first channel ratios R1 of two adjacent first FET structures 58. The first total channel ratio RT1 can also be adjusted to be greater than 0% and less than 100% (preferably greater than 0% and less than 100%). In this mode, the first total channel ratio RT1 is adjusted to 50%. In the first total channel ratio RT1, the first channel ratio R1 on one side and the first channel ratio R1 on the other side are both 25%.

[0542] The second total channel ratio RT2 is applied to the region between a first FET structure 58 and a second FET structure 68 that are adjacent to each other. In the region between a first FET structure 58 and a second FET structure 68 that are adjacent to each other, a first channel region 91 and a second channel region 111 are formed on its structure.

[0543] The second total channel ratio RT2 is the sum of the first channel ratio R1 and the second channel ratio R2. The second total channel ratio RT2 can also be adjusted to be above 0% and below 100% (preferably above 0% and below 100%). In this method, the second total channel ratio RT2 is adjusted to 50%. In the second total channel ratio RT2, the first channel ratio R1 is 25%, and the second channel ratio R2 is 25%.

[0544] The third total channel ratio RT3 is applied to the region between two adjacent second FET structures 68. In the region between two adjacent second FET structures 68, the first channel region 91 is not formed in its construction.

[0545] The third total channel ratio RT3 is the sum of the second channel ratios R2 of two adjacent second FET structures 68. The third total channel ratio RT3 can also be adjusted to be greater than 0% and less than 100% (preferably greater than 0% and less than 100%). In this configuration, the third total channel ratio RT3 is adjusted to 50%. In the third total channel ratio RT3, the second channel ratio R2 on one side and the second channel ratio R2 on the other side are both 25%.

[0546] The first channel region 91 occupies 1 / 2 (50%) of all channels, and the second channel region 111 occupies 1 / 2 (50%) of all channels. In this configuration, the average channel ratio (RAV) is 50%.

[0547] In each of the first trench contact structures 162, the first contact trench 164 is connected to one end of a plurality of adjacent first gate trenches 81. The first contact insulating layer 165 is integrally formed with the first insulating layer 82 in the connecting portion between each of the first gate trenches 81 and the first contact trench 164.

[0548] Specifically, the first contact insulating layer 165 includes an outgoing insulating layer 165A extending into each of the first gate trenches 81, and is integrally formed with the first bottom insulating layer 84 and the first opening insulating layer 85 within each of the first gate trenches 81, extending across the connecting portion.

[0549] The first contact electrode 166 is integrally formed with the first bottom-side electrode 86 in the connecting portion between each of the first gate trenches 81 and the first contact trenches 164. Specifically, the first contact electrode 166 includes a lead-out electrode 166A extending into each of the first gate trenches 81 and passing through the connecting portion to be electrically connected to the first bottom-side electrode 86 in each of the first gate trenches 81. In each of the first gate trenches 81, a first intermediate insulating layer 88 is located between the first contact electrode 166 and the first opening-side electrode 87.

[0550] In each of the second trench gate configurations 70, the second contact trench 167 is connected to one end of a plurality of adjacent second gate trenches 101. The second contact insulating layer 168 is integrally formed with the second insulating layer 102 in the communication between each second gate trench 101 and the second contact trench 167.

[0551] Specifically, the second contact insulating layer 168 includes an outgoing insulating layer 168A extending into each of the second gate trenches 101, and is integrally formed with the second bottom insulating layer 104 and the second opening insulating layer 105 within each of the second gate trenches 101, extending across the connecting portion.

[0552] The second contact electrode 169 is integrally formed with the second bottom-side electrode 106 in the connecting portion between each second gate trench 101 and the second contact trench 167. Specifically, the second contact electrode 169 includes a lead-out electrode 169A extending into each second gate trench 101 and passing through the connecting portion to be electrically connected to the second bottom-side electrode 106 within each second gate trench 101. Within each second gate trench 101, a second intermediate insulating layer 108 is located between the second contact electrode 169 and the second opening-side electrode 107.

[0553] Figure 27A It is used for explanation Figure 25 A cross-sectional perspective view of the normal operation of the semiconductor device 171 shown. Figure 27B It is used for explanation Figure 25 A cross-sectional perspective view of the active clamping operation of the semiconductor device 171 shown. Figure 27A as well as Figure 27B For ease of explanation, the structure above the first main surface 3 is omitted, and the gate control wiring 17 is simplified.

[0554] Reference Figure 27A During normal operation of the power MISFET 9, a first turn-on signal Von1 is input to the first gate control wiring 17A, and a second turn-on signal Von2 is input to the second gate control wiring 17B. The first turn-on signal Von1 and the second turn-on signal Von2 are respectively input from the controller IC10.

[0555] The first turn-on signal Von1 and the second turn-on signal Von2 each have a voltage greater than or equal to the gate threshold voltage Vth. Alternatively, the first turn-on signal Von1 and the second turn-on signal Von2 may each have the same voltage.

[0556] In this case, the first opening-side electrode 87, the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 are all turned on. That is, the first opening-side electrode 87, the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 function as gate electrodes.

[0557] Therefore, both the first channel area 91 and the second channel area 111 are controlled to be in the connected state. Figure 27A In the diagram, the first channel region 91 and the second channel region 111 in the connected state are shown by dotted shadow lines.

[0558] As a result, both the first MISFET 56 and the second MISFET 57 are driven (fully on control). The channel utilization RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. Therefore, the areal resistivity Ron·A is... Figure 13The resistivity Ron·A in the graph is close to that shown by the second plotted point P2.

[0559] On the other hand, refer to Figure 27B When the power MISFET9 is in active clamping mode, a disconnect signal Voff is input to the first gate control wiring 17A, and a clamping signal VCon is input to the second gate control wiring 17B.

[0560] The disconnect signal Voff and the clamp turn-on signal VCon are input from controller IC10. The disconnect signal Voff is a voltage less than the gate threshold voltage Vth (e.g., a reference voltage). The clamp turn-on signal VCon has a voltage greater than or equal to the gate threshold voltage Vth. The clamp turn-on signal VCon may also have a voltage less than or lower than the voltage during normal operation.

[0561] In this case, the first bottom-side electrode 86 and the first opening-side electrode 87 are respectively in an off state, while the second bottom-side electrode 106 and the second opening-side electrode 107 are respectively in an on state. Therefore, the first channel region 91 is controlled to be in an off state and the second channel region 111 is controlled to be in an on state. Figure 27B In the diagram, the first channel region 91 in the disconnected state is shown by smeared shading, and the second channel region 111 in the connected state is shown by dotted shading.

[0562] As a result, the first MISFET 56 is controlled to be in the off state, while the second MISFET 57 is controlled to be in the on state (second half-on control). Thus, the channel utilization RU during active clamping operation becomes greater than zero and less than the channel utilization RU during normal operation.

[0563] The channel utilization RU during active clamping operation is 50%. Additionally, the characteristic channel ratio RC during active clamping operation is 25%. Therefore, the active clamping tolerance Eac is... Figure 13 The active clamp tolerance Eac is shown in the graph near the fourth plotted point P4.

[0564] In this control example, an example of applying a second half-on control during active clamping operation is described. However, a first half-on control can also be applied during active clamping operation.

[0565] As described above, the semiconductor device 171 can achieve the same effect as that described for the semiconductor device 161. Furthermore, in the semiconductor device 171, a plurality of first FET structures 58 and a plurality of second FET structures 68 are formed in a configuration in which groups of a plurality of (in this configuration, two) first FET structures 58 and groups of a plurality of (in this configuration, two) second FET structures 68 are alternately arranged.

[0566] In a configuration where multiple first FET structures 58 are adjacent to each other, a first channel region 91 can be formed in the region between the multiple adjacent first FET structures 58 without being connected to the second channel region 111. Therefore, the first channel region 91 can be appropriately formed, thereby allowing the first channel ratio R1 to be appropriately adjusted.

[0567] Similarly, in a configuration where multiple second FET structures 68 are adjacent to each other, a second channel region 111 can be formed in the region between the multiple adjacent second FET structures 68 without being connected to the first channel region 91. Therefore, the second channel region 111 can be appropriately formed, thereby allowing the second channel ratio R2 to be appropriately adjusted. As a result, the average channel ratio RAV and the characteristic channel ratio RC can be appropriately adjusted.

[0568] <Fifth Implementation Method>

[0569] Figure 28 Is with Figure 25 The cross-sectional perspective view of the corresponding region is a cross-sectional perspective view showing the semiconductor device 181 according to the fifth embodiment of the present invention. Hereinafter, the same reference numerals will be used to mark the structures corresponding to those described for the semiconductor device 171, and descriptions will be omitted.

[0570] In this method, a first total channel ratio RT1, a second total channel ratio RT2, and a third total channel ratio RT3 with different values ​​are applied in multiple cell regions 75.

[0571] As an example, the first total channel ratio RT1 can also be adjusted to be above 60% and below 80%. In this method, the first total channel ratio RT1 is adjusted to 75%. In the first total channel ratio RT1, the first channel ratio R1 on one side and the first channel ratio R1 on the other side are both 37.5%.

[0572] As an example, the second total channel ratio RT2 can also be adjusted to be greater than 40% and less than 60%. In this method, the second total channel ratio RT2 is adjusted to 50%. In the second total channel ratio RT2, the first channel ratio R1 is 25%, and the second channel ratio R2 is 25%.

[0573] As an example, the third total channel ratio RT3 can also be adjusted to be between 20% and 40%. In this method, the third total channel ratio RT3 is adjusted to 25%. In the third total channel ratio RT3, the second channel ratio R2 on one side and the second channel ratio R2 on the other side are both 12.5%.

[0574] The first channel region 91 occupies more than 50% (1 / 2) of all channels. In this configuration, the first channel region 91 occupies 62.5% of all channels, and the second channel region 111 occupies 37.5% of all channels. That is, the proportion of the second channel R2 is less than the proportion of the first channel R1 (R2 < R1). In this configuration, the average channel proportion RAV is 50%. The other structures in the semiconductor device 181 are the same as those in the semiconductor device 171. In this configuration, the control described below is implemented.

[0575] Figure 29A It is used for explanation Figure 28 A cross-sectional perspective view of the normal operation of the first control example of the semiconductor device 181 shown. Figure 29B It is used for explanation Figure 28 A cross-sectional perspective view of the active clamping operation of the first control example of the semiconductor device 181 shown. Figure 29A as well as Figure 29B For ease of explanation, the structure above the first main surface 3 is omitted, and the gate control wiring 17 is simplified.

[0576] Reference Figure 29A During normal operation of the power MISFET 9, a first turn-on signal Von1 is input to the first gate control wiring 17A, and a second turn-on signal Von2 is input to the second gate control wiring 17B. The first turn-on signal Von1 and the second turn-on signal Von2 are respectively input from the controller IC10.

[0577] The first turn-on signal Von1 and the second turn-on signal Von2 each have a voltage greater than or equal to the gate threshold voltage Vth. Alternatively, the first turn-on signal Von1 and the second turn-on signal Von2 may each have the same voltage.

[0578] In this case, the first opening-side electrode 87, the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 are all turned on. That is, the first opening-side electrode 87, the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 function as gate electrodes.

[0579] Therefore, both the first channel area 91 and the second channel area 111 are controlled to be in the connected state. Figure 29A In the diagram, the first channel region 91 and the second channel region 111 in the connected state are shown by dotted shadow lines.

[0580] As a result, both the first MISFET 56 and the second MISFET 57 are driven (fully on control). The channel utilization RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. Therefore, the areal resistivity Ron·A is... Figure 13 The resistivity Ron·A in the graph is close to that shown by the second plotted point P2.

[0581] On the other hand, refer to Figure 29B When the power MISFET9 is in active clamping mode, a disconnect signal Voff is input to the first gate control wiring 17A, and a clamping signal VCon is input to the second gate control wiring 17B.

[0582] The disconnect signal Voff and the clamp turn-on signal VCon are input from controller IC10. The disconnect signal Voff has a voltage less than the gate threshold voltage Vth (e.g., a reference voltage). The clamp turn-on signal VCon has a voltage greater than or equal to the gate threshold voltage Vth. The clamp turn-on signal VCon may also have a voltage less than or lower than the voltage during normal operation.

[0583] In this case, the first bottom-side electrode 86 and the first opening-side electrode 87 are respectively in an off state, while the second bottom-side electrode 106 and the second opening-side electrode 107 are respectively in an on state. Therefore, the first channel region 91 is controlled to be in an off state and the second channel region 111 is controlled to be in an on state. Figure 29B In the diagram, the first channel region 91 in the disconnected state is shown by smeared shading, and the second channel region 111 in the connected state is shown by dotted shading.

[0584] As a result, the first MISFET 56 is controlled to be in the off state, while the second MISFET 57 is controlled to be in the on state (second half-on control). Therefore, the channel utilization RU during active clamping operation becomes greater than zero and less than the channel utilization RU during normal operation. Specifically, the channel utilization RU during active clamping operation is less than half of the channel utilization RU during normal operation.

[0585] The channel utilization rate RU during active clamping operation is 37.5%. Additionally, the characteristic channel ratio RC during active clamping operation is 18.75%. Therefore, the active clamping tolerance Eac is... Figure 13 The active clamping tolerance Eac is close to or exceeds the active clamping tolerance Eac shown by the fourth plotted point P4 in the chart.

[0586] Figure 30A It is used for explanation Figure 28 A cross-sectional perspective view of the normal operation of the second control example of the semiconductor device 181 shown. Figure 30B It is used for explanation Figure 28 A cross-sectional perspective view of the active clamping operation of the second control example of the semiconductor device 181 shown. Figure 30A as well as Figure 30BFor ease of explanation, the structure above the first main surface 3 is omitted, and the gate control wiring 17 is simplified.

[0587] Reference Figure 30A During normal operation of the power MISFET 9, an on signal Von is input to the first gate control wiring 17A, and an off signal Voff is input to the second gate control wiring 17B. The on signal Von and the off signal Voff are input from the controller IC 10. The on signal Von has a voltage greater than or equal to the gate threshold voltage Vth. The on signal Von and the off signal Voff have voltages less than the gate threshold voltage Vth (e.g., a reference voltage).

[0588] In this case, the first bottom-side electrode 86 and the first opening-side electrode 87 are in the ON state, while the second bottom-side electrode 106 and the second opening-side electrode 107 are in the OFF state. That is, the first bottom-side electrode 86 and the first opening-side electrode 87 function as gate electrodes, while the second bottom-side electrode 106 and the second opening-side electrode 107 function as field electrodes.

[0589] Therefore, the first channel region 91 is controlled to be in the ON state and the second channel region 111 is controlled to be in the OFF state. Figure 30A In the diagram, the first channel region 91 in the on state is shown by dotted shadow lines, and the second channel region 111 in the on state is shown by smeared shadow lines.

[0590] As a result, the first MISFET 56 is controlled to be in the ON state, while the second MISFET 57 is controlled to be in the OFF state (first half-ON control). Consequently, the second channel region 111, which has a second channel ratio R2 (R2 < R1) that is less than the first channel ratio R1, is controlled to be in the OFF state, and therefore the characteristic channel ratio RC during normal operation is less than the average channel ratio RAV.

[0591] The channel utilization rate RU during normal operation is 62.5%. Additionally, the characteristic channel ratio RC during normal operation is 31.25%. Therefore, the areal resistivity Ron·A is... Figure 13 The resistivity Ron·A in the graph is close to that shown by the third plotted point P3.

[0592] On the other hand, refer to Figure 30B When the power MISFET9 is actively clamped, a disconnect signal Voff is input to the first gate control wiring 17A, and a clamping signal VCon is input to the second gate control wiring 17B. The disconnect signal Voff and the clamping signal VCon are input from the controller IC10.

[0593] The off signal Voff has a voltage less than the gate threshold voltage Vth (e.g., a reference voltage). The clamp on signal VCon has a voltage greater than or equal to the gate threshold voltage Vth. The clamp on signal VCon may also have a voltage less than or lower than the voltage during normal operation.

[0594] In this case, the first bottom-side electrode 86 and the first opening-side electrode 87 are in the off state, while the second bottom-side electrode 106 and the second opening-side electrode 107 are in the on state. That is, the first bottom-side electrode 86 and the first opening-side electrode 87 function as field electrodes, while the second bottom-side electrode 106 and the second opening-side electrode 107 function as gate electrodes.

[0595] Therefore, the first channel region 91 is controlled to be in the off state and the second channel region 111 is controlled to be in the on state. Figure 30B In the diagram, the first channel region 91 in the disconnected state is shown by smeared shading, and the second channel region 111 in the connected state is shown by dotted shading.

[0596] As a result, the first MISFET 56 is controlled to be in the off state, while the second MISFET 57 is controlled to be in the on state (second half-on control). The second channel region 111, which has a second channel ratio R2 (R2 < R1) that is less than the first channel ratio R1, is controlled to be in the on state. Therefore, the channel utilization RU during active clamping operation becomes greater than zero and less than the channel utilization RU during normal operation.

[0597] The channel utilization rate RU during active clamping operation is 37.5%. Additionally, the characteristic channel ratio RC during active clamping operation is 18.75%. Therefore, the active clamping tolerance Eac is... Figure 13 The active clamping tolerance Eac is close to or exceeds the active clamping tolerance Eac shown by the second plotted point P2 in the chart.

[0598] As described above, the semiconductor device 181 can achieve the same effect as that described for the semiconductor device 171. In particular, according to the semiconductor device 181, the second channel ratio R2 is different from the first channel ratio R1 (R1≠R2). Specifically, the second channel ratio R2 is smaller than the first channel ratio R1 (R1>R2).

[0599] In this configuration, the controller IC10 controls the first MISFET 56 and the second MISFET 57 such that the channel utilization RU during active clamping operation is greater than zero and less than the channel utilization RU during normal operation. This improves the active clamping tolerance (Eac).

[0600] Furthermore, according to the semiconductor device 181, as shown in the second control example, a first half-on control is applied during normal operation, and a second half-on control can be applied during active clamping operation. Additionally, according to the semiconductor device 181, it is also possible to apply the second half-on control during normal operation and the first half-on control during active clamping operation. That is, according to the semiconductor device 181, by simply changing the control method, the same average channel ratio RAV can be achieved, and various area resistivity Ron·A and active clamping tolerance Eac can be realized.

[0601] <Sixth Implementation Method>

[0602] Figure 31 Is with Figure 7 The cross-sectional perspective view of the corresponding region is a cross-sectional perspective view showing the semiconductor device 191 according to the sixth embodiment of the present invention. Hereinafter, the same reference numerals will be used to mark the structures corresponding to the structure described for the semiconductor device 1, and the description will be omitted.

[0603] In the semiconductor device 1, in the first trench gate configuration 60, the first insulating layer 82 includes a first bottom-side insulating layer 84 and a first opening-side insulating layer 85, and the first electrode 83 includes a first bottom-side electrode 86, a first opening-side electrode 87 and a first intermediate insulating layer 88.

[0604] In contrast, in semiconductor device 191, the first insulating layer 82 does not include the first bottom-side insulating layer 84, and the first electrode 83 does not include the first bottom-side electrode 86 and the first intermediate insulating layer 88. That is, in semiconductor device 191, the first insulating layer 82 includes a first gate insulating layer 192 corresponding to the first opening-side insulating layer 85, and the first electrode 83 includes a first gate electrode 193 corresponding to the first opening-side electrode 87.

[0605] Additionally, in the semiconductor device 1, in the second trench gate configuration 70, the second insulating layer 102 includes a second bottom-side insulating layer 104 and a second opening-side insulating layer 105, and the second electrode 103 includes a second bottom-side electrode 106, a second opening-side electrode 107, and a second intermediate insulating layer 108.

[0606] In contrast, in semiconductor device 191, the second insulating layer 102 does not include the second bottom insulating layer 104, and the second electrode 103 does not include the second bottom electrode 106 and the second intermediate insulating layer 108. That is, in semiconductor device 191, the second insulating layer 102 includes a second gate insulating layer 194 corresponding to the second opening-side insulating layer 105, and the second electrode 103 includes a second gate electrode 195 corresponding to the second opening-side electrode 107.

[0607] In addition, semiconductor device 1 has a trench contact structure 120. In contrast, semiconductor device 191 does not have a trench contact structure 120. The structure of semiconductor device 191 will be described in detail below.

[0608] In the first trench gate configuration 60, the first gate insulating layer 192 is formed as a film along the inner wall of the first gate trench 81. The first gate insulating layer 192 divides concave spaces within the first gate trench 81.

[0609] The thickness of the portion of the first gate insulating layer 192 that covers the bottom wall 63 of the first gate trench 81 can also be greater than the thickness of the portions of the first gate insulating layer 192 that cover the first sidewall 61 and the second sidewall 62 of the first gate trench 81. Of course, the first gate insulating layer 192 can also have the same thickness.

[0610] The first gate electrode 193 is embedded in the first gate trench 81 through the first gate insulating layer 192. Specifically, the first gate electrode 193 is embedded as a single unit in the concave space defined by the first gate insulating layer 192 in the first gate trench 81. A first gate control signal (first control signal) including an on signal Von and an off signal Voff is applied to the first gate electrode 193.

[0611] The first gate electrode 193 may also comprise at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloys, and copper alloys. In this embodiment, the first gate electrode 193 comprises conductive polysilicon. The conductive polysilicon may also contain n-type or p-type impurities. Preferably, the conductive polysilicon contains n-type impurities.

[0612] In the second trench gate configuration 70, the second gate insulating layer 194 is formed as a film along the inner wall of the second gate trench 101. The second gate insulating layer 194 divides concave spaces within the second gate trench 101.

[0613] The thickness of the portion of the second gate insulating layer 194 covering the bottom wall 73 of the second gate trench 101 can also be greater than the thickness of the portion of the second gate insulating layer 194 covering the second sidewall 72 of the second gate trench 101. Of course, the second gate insulating layer 194 can also have the same thickness.

[0614] The second gate electrode 195 is embedded in the second gate trench 101 through the second gate insulating layer 194. Specifically, the second gate electrode 195 is embedded as a single unit in the concave space defined by the second gate insulating layer 194 in the second gate trench 101. A second gate control signal (second control signal) including an on signal Von and an off signal Voff is applied to the second gate electrode 195.

[0615] The second gate electrode 195 may also comprise at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloys, and copper alloys. Preferably, the second gate electrode 195 comprises the same type of conductive material as the first gate electrode 193. In this embodiment, the second gate electrode 195 comprises conductive polysilicon. The conductive polysilicon may also contain n-type or p-type impurities. Preferably, the conductive polysilicon contains n-type impurities.

[0616] Although specific illustrations are omitted, the first gate control wiring 17A is electrically connected to the first gate electrode 193, and the second gate control wiring 17B is electrically connected to the second gate electrode 195.

[0617] Figure 32A It is used for explanation Figure 31 A cross-sectional perspective view of the normal operation of the semiconductor device 191 shown. Figure 32B It is used for explanation Figure 31 A cross-sectional perspective view of the active clamping action of the semiconductor device 191 shown.

[0618] Reference Figure 32A During normal operation of the power MISFET 9, a first turn-on signal Von1 is input to the first gate control wiring 17A, and a second turn-on signal Von2 is input to the second gate control wiring 17B. The first turn-on signal Von1 and the second turn-on signal Von2 are respectively input from the controller IC10.

[0619] The first turn-on signal Von1 and the second turn-on signal Von2 each have a voltage greater than or equal to the gate threshold voltage Vth. Alternatively, the first turn-on signal Von1 and the second turn-on signal Von2 may each have the same voltage.

[0620] In this case, the first gate electrode 193 and the second gate electrode 195 are both turned on. Therefore, both the first channel region 91 and the second channel region 111 are controlled to be turned on. Figure 32A In the diagram, the first channel region 91 and the second channel region 111 in the connected state are shown by dotted shadow lines.

[0621] As a result, both the first MISFET 56 and the second MISFET 57 are driven (fully on control). The channel utilization RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. Therefore, compared with the case where the characteristic channel ratio RC is less than 50%, the area resistivity Ron·A decreases.

[0622] On the other hand, refer to Figure 32BWhen the power MISFET9 is in active clamping mode, a disconnect signal Voff is input to the first gate control wiring 17A, and a clamping signal VCon is input to the second gate control wiring 17B.

[0623] The disconnect signal Voff and the clamp turn-on signal VCon are input from controller IC10. The disconnect signal Voff has a voltage less than the gate threshold voltage Vth (e.g., a reference voltage). The clamp turn-on signal VCon has a voltage greater than or equal to the gate threshold voltage Vth. The clamp turn-on signal VCon may also have a voltage less than or lower than the voltage during normal operation.

[0624] In this case, the first gate electrode 193 is in an off state, and the second gate electrode 195 is in an on state. Therefore, the first channel region 91 is controlled to be in an off state, and the second channel region 111 is controlled to be in an on state. Figure 32B In the middle. The first channel region 91 in the disconnected state is shown by smeared shading, and the second channel region 111 in the connected state is shown by dotted shading.

[0625] As a result, the first MISFET 56 is controlled to be in the off state, while the second MISFET 57 is controlled to be in the on state (second half-on control). Thus, the channel utilization RU during active clamping operation becomes greater than zero and less than the channel utilization RU during normal operation.

[0626] The channel utilization rate RU during active clamping operation is 50%. Additionally, the characteristic channel ratio RC during active clamping operation is 25%. Therefore, compared to cases where the characteristic channel ratio RC exceeds 25%, the active clamping tolerance Eac is improved.

[0627] In this control example, an example of applying a second half-on control during active clamping operation is described. However, a first half-on control can also be applied during active clamping operation.

[0628] As described above, the semiconductor device 191 can achieve the same effect as that described for the semiconductor device 1. In this embodiment, an example is shown where the second channel ratio R2 (second channel area S2) is equal to the first channel ratio R1 (first channel area S1). However, compared to the second embodiment (see...),... Figure 16 Similar to the case where the first channel ratio R1 is different from the second channel ratio R2 (R1≠R2), the second channel ratio R2 can also be smaller than the first channel ratio R1 (R2<R1).

[0629] <Seventh Implementation Method>

[0630] Figure 33 Is with Figure 31The cross-sectional perspective view of the corresponding region is a perspective view showing the semiconductor device 201 according to the seventh embodiment of the present invention. Hereinafter, the same reference numerals will be used to mark the structures corresponding to the structure described for the semiconductor device 191, and the description will be omitted.

[0631] In semiconductor device 191, a plurality of first FET structures 58 and a plurality of second FET structures 68 are formed in a configuration where one first FET structure 58 and one second FET structure 68 are arranged alternately. In contrast, in semiconductor device 201, a plurality of first FET structures 58 and a plurality of second FET structures 68 are formed in a configuration where groups of a plurality of first FET structures 58 (in this configuration, two) and groups of a plurality of second FET structures 68 (in this configuration, two) are arranged alternately.

[0632] Furthermore, semiconductor device 191 does not have trench contact structure 120. In contrast, semiconductor device 201 has trench contact structure 120. Specifically, semiconductor device 201 includes a plurality of trench contact structures 120, which are connected to the first trench gate structure 60 and the second trench gate structure 70 respectively in a manner that electrically insulates the first trench gate structure 60 and the second trench gate structure 70 from each other.

[0633] Furthermore, in semiconductor device 191, the second channel ratio R2 (second channel area S2) is equal to the first channel ratio R1 (first channel area S1). In contrast, in semiconductor device 201, the second channel ratio R2 is different from the first channel ratio R1 (R1 ≠ R2). Specifically, the second channel ratio R2 is smaller than the first channel ratio R1 (R2 < R1). The structure of semiconductor device 201 will be described in detail below.

[0634] Reference Figure 33 The multiple unit regions 75 are respectively divided into the region between two adjacent first FET structures 58, the region between one adjacent first FET structure 58 and one adjacent second FET structure 68, and the region between two adjacent second FET structures 68.

[0635] In this method, three total channel ratios RT with mutually different values ​​are applied to multiple cell regions 75. The three total channel ratios RT include a first total channel ratio RT1, a second total channel ratio RT2, and a third total channel ratio RT3.

[0636] The first total channel ratio RT1 is applied to the region between two adjacent first FET structures 58. In the region between two adjacent first FET structures 58, a second channel region 111 is not structurally formed.

[0637] The first total channel ratio RT1 is the sum of the first channel ratios R1 of two adjacent first FET structures 58. As an example, the first total channel ratio RT1 can also be adjusted to be above 60% and below 80%. In this case, the first total channel ratio RT1 is adjusted to 75%. In the first total channel ratio RT1, the first channel ratio R1 on one side and the first channel ratio R1 on the other side are both 37.5%.

[0638] The second total channel ratio RT2 is applied to the region between a first FET structure 58 and a second FET structure 68 that are adjacent to each other. In the region between a first FET structure 58 and a second FET structure 68 that are adjacent to each other, a first channel region 91 and a second channel region 111 are formed.

[0639] The second total channel ratio RT2 is the sum of the first channel ratio R1 and the second channel ratio R2. As an example, the second total channel ratio RT2 can also be adjusted to be greater than 40% and less than 60%. In this case, the second total channel ratio RT2 is adjusted to 50%. In the second total channel ratio RT2, the first channel ratio R1 is 25%, and the second channel ratio R2 is 25%.

[0640] The third total channel ratio RT3 is applied to the region between two adjacent second FET structures 68. In the region between two adjacent second FET structures 68, the first channel region 91 is not formed in its construction.

[0641] The third total channel ratio RT3 is the sum of the second channel ratios R2 of the two adjacent second FET structures 68. As an example, the third total channel ratio RT3 can also be adjusted to be above 20% and below 40%. In this case, the third total channel ratio RT3 is adjusted to 25%. In the third total channel ratio RT3, the second channel ratio R2 on one side and the second channel ratio R2 on the other side are both 12.5%.

[0642] The first channel region 91 occupies more than 50% (1 / 2) of all channels. In this configuration, the first channel region 91 occupies 62.5% of all channels, and the second channel region 111 occupies 37.5% of all channels. That is, the proportion of the second channel R2 is less than the proportion of the first channel R1 (R2 < R1). In this configuration, the average channel proportion RAV is 50%.

[0643] The plurality of trench contact structures 120 include a plurality of first trench contact structures 202 and a plurality of second trench contact structures 203. The plurality of first trench contact structures 202 are spaced apart from the plurality of second trench gate structures 70 and respectively connected to one end of a corresponding plurality of first trench gate structures 60. The plurality of first trench contact structures 202 are formed in an arch shape when viewed from above.

[0644] Multiple second trench contact structures 203 are spaced apart from multiple first trench gate structures 60 and connected to one end of corresponding multiple second trench gate structures 70. The multiple second trench contact structures 203 are formed in an arch shape when viewed from above.

[0645] Each first trench contact structure 202 includes a first contact trench 204, a first contact insulating layer 205, and a first contact electrode 206. In this configuration, the first contact trench 204, the first contact insulating layer 205, and the first contact electrode 206 each have a structure corresponding to the first gate trench 81, the first gate insulating layer 192, and the first gate electrode 193, respectively.

[0646] In each of the first trench contact structures 202, the first contact trench 204 is connected to one end of a plurality of adjacent first gate trenches 81. The first contact insulating layer 205 is integrally formed with the first gate insulating layer 192 in the connecting portion between each of the first gate trenches 81 and the first contact trench 204. The first contact electrode 206 is integrally formed with the first gate electrode 193 in the connecting portion between each of the first gate trenches 81 and the first contact trench 204.

[0647] Each second trench contact structure 203 includes a second contact trench 207, a second contact insulating layer 208, and a second contact electrode 209. In this configuration, the second contact trench 207, the second contact insulating layer 208, and the second contact electrode 209 each have a structure corresponding to the second gate trench 101, the second gate insulating layer 194, and the second gate electrode 195, respectively.

[0648] In each of the second trench contact structures 203, the second contact trench 207 communicates with one end of a plurality of adjacent second gate trenches 101. The second contact insulating layer 208 is integrally formed with the second gate insulating layer 194 in the communication portion between each second gate trench 101 and the second contact trench 207. The second contact electrode 209 is integrally formed with the second gate electrode 195 in the communication portion between each second gate trench 101 and the second contact trench 207.

[0649] Although specific illustrations are omitted, the first gate control wiring 17A is electrically connected to the first gate electrode 193 and the first contact electrode 206, and the second gate control wiring 17B is electrically connected to the second gate electrode 195 and the second contact electrode 209.

[0650] Figure 34A It is used for explanation Figure 33 A cross-sectional perspective view of the normal operation of the semiconductor device 201 shown. Figure 34B It is used for explanation Figure 33 A cross-sectional perspective view of the active clamping operation of the semiconductor device 201 shown. Figure 34A as well as Figure 34B For ease of explanation, the structure above the first main surface 3 is omitted, and the gate control wiring 17 is simplified.

[0651] Reference Figure 34A During normal operation of the power MISFET 9, a first turn-on signal Von1 is input to the first gate control wiring 17A, and a second turn-on signal Von2 is input to the second gate control wiring 17B. The first turn-on signal Von1 and the second turn-on signal Von2 are respectively input from the controller IC10.

[0652] The first turn-on signal Von1 and the second turn-on signal Von2 each have a voltage greater than or equal to the gate threshold voltage Vth. Alternatively, the first turn-on signal Von1 and the second turn-on signal Von2 may each have the same voltage.

[0653] In this case, the first gate electrode 193 and the second gate electrode 195 are both turned on. Therefore, both the first channel region 91 and the second channel region 111 are controlled to be turned on. Figure 34A In the diagram, the first channel region 91 and the second channel region 111 in the connected state are shown by dotted shadow lines.

[0654] As a result, both the first MISFET 56 and the second MISFET 57 are driven (fully on control). The channel utilization RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. Therefore, compared with the case where the characteristic channel ratio RC is less than 50%, the area resistivity Ron·A decreases.

[0655] On the other hand, refer to Figure 34B When the power MISFET9 is actively clamped, a disconnect signal Voff is input to the first gate control wiring 17A, and a clamping signal VCon is input to the second gate control wiring 17B. The disconnect signal Voff and the clamping signal VCon are input from the controller IC10.

[0656] The off signal Voff has a voltage less than the gate threshold voltage Vth (e.g., a reference voltage). The clamp on signal VCon has a voltage greater than or equal to the gate threshold voltage Vth. The clamp on signal VCon may also have a voltage less than or lower than the voltage during normal operation.

[0657] In this case, the first gate electrode 193 is in an off state, and the second gate electrode 195 is in an on state. Therefore, the first channel region 91 is controlled to be in an off state, and the second channel region 111 is controlled to be in an on state. Figure 34B In the diagram, the first channel region 91 in the disconnected state is shown by smeared shading, and the second channel region 111 in the connected state is shown by dotted shading.

[0658] As a result, the first MISFET 56 is controlled to be in the off state, while the second MISFET 57 is controlled to be in the on state (second half-on control). Therefore, the channel utilization RU during active clamping operation becomes greater than zero and less than the channel utilization RU during normal operation. Specifically, the channel utilization RU during active clamping operation is less than half of the channel utilization RU during normal operation.

[0659] The channel utilization rate RU during active clamping operation is 37.5%. Additionally, the characteristic channel ratio RC during active clamping operation is 18.75%. Therefore, compared to cases where the characteristic channel ratio RC exceeds 18.75%, the active clamping tolerance Eac is improved.

[0660] As described above, the semiconductor device 201 can achieve the same effect as that described for the semiconductor device 191. Furthermore, in the semiconductor device 201, a plurality of first FET structures 58 and a plurality of second FET structures 68 are formed in a configuration in which groups of a plurality of (in this configuration, two) first FET structures 58 and groups of a plurality of (in this configuration, two) second FET structures 68 are alternately arranged.

[0661] In a configuration where multiple first FET structures 58 are adjacent to each other, a first channel region 91 can be formed in the region between the multiple adjacent first FET structures 58 without being connected to the second channel region 111. Therefore, the first channel region 91 can be appropriately formed, thereby allowing the first channel ratio R1 to be appropriately adjusted.

[0662] Similarly, in a configuration where multiple second FET structures 68 are adjacent to each other, a second channel region 111 can be formed in the region between the multiple adjacent second FET structures 68 without being connected to the first channel region 91. Therefore, the second channel region 111 can be appropriately formed, thereby allowing the second channel ratio R2 to be appropriately adjusted. As a result, the average channel ratio RAV and the characteristic channel ratio RC can be appropriately adjusted.

[0663] <Eighth Implementation Method>

[0664] Figure 35 Is with Figure 7The cross-sectional perspective view of the corresponding region is a partially cut-off cross-sectional perspective view of the semiconductor device 211 according to the eighth embodiment of the present invention. Hereinafter, the same reference numerals will be used to denote structures corresponding to those described in the semiconductor device 1, and descriptions will be omitted.

[0665] Semiconductor device 1 includes a trench-gate type first FET structure 58 and a trench-gate type second FET structure 68. In contrast, semiconductor device 211 includes a planar-gate type first FET structure 58 and a planar-gate type second FET structure 68. The specific structure of semiconductor device 211 will be described below.

[0666] Reference Figure 35 Multiple main regions 55 are formed on the surface portion of the first main surface 3 of the semiconductor layer 2. These multiple main regions 55 form the basis of the power MISFET 9. The multiple main regions 55 are formed with spacing along a first direction X and extend in a stripe shape along a second direction Y. When viewed from above, the multiple main regions 55 are generally formed in a stripe shape.

[0667] Each first FET structure 58 includes a first source region 92 formed on the surface portion of each body region 55. The first source region 92 extends in a strip shape along the second direction Y. Each second FET structure 68 includes a second source region 112 formed on the surface portion of each body region 55. Specifically, the second source region 112 is formed with gaps along the first direction X and extends in a strip shape along the second direction Y.

[0668] Each first FET structure 58 and each second FET structure 68 includes a p-type layer formed on the surface portion of each body region 55. + The contact region 212 is common in both the first FET configuration 58 and the second FET configuration 68. The contact region 212 is formed in the region between the first source region 92 and the second source region 112. The contact region 212 extends in a strip shape along the second direction Y.

[0669] The first FET structure 58 includes a first planar gate structure 213 formed on the first main surface 3 of the semiconductor layer 2. The first planar gate structure 213 extends in a strip along the second direction Y and is opposite to the drift region 54, the main body region 55 and the first source region 92.

[0670] Specifically, each first planar gate structure 213 includes a first gate insulating layer 214 and a first gate electrode 215. The first gate insulating layer 214 is formed on the first main surface 3. The first gate insulating layer 214 covers the drift region 54, the main region 55, and the first source region 92 on the first main surface 3. The first gate electrode 215 is located opposite the drift region 54, the main region 55, and the first source region 92 through the first gate insulating layer 214.

[0671] In this configuration, the first channel region 91 of the first MISFET 56 is formed in the body region 55 between the drift region 54 and the first source region 92. The first channel region 91 is opposite to the first gate electrode 215 through the first gate insulating layer 214.

[0672] The second FET structure 68 includes a second planar gate structure 223 formed on the second main surface 4 of the semiconductor layer 2. The second planar gate structure 223 extends in a strip shape along the second direction Y and is opposite to the drift region 54, the main region 55 and the second source region 112.

[0673] Specifically, each second planar gate structure 223 includes a second gate insulating layer 224 and a second gate electrode 225. The second gate insulating layer 224 is formed on the second main surface 4. The second gate insulating layer 224 covers the drift region 54, the main region 55, and the second source region 112 on the second main surface 4. The second gate electrode 225 is located opposite the drift region 54, the main region 55, and the second source region 112 through the second gate insulating layer 224.

[0674] In this configuration, the second channel region 111 of the second MISFET 57 is formed in the body region 55 between the drift region 54 and the second source region 112. The second channel region 111 is opposite to the second gate electrode 225 through the second gate insulating layer 224.

[0675] An interlayer insulating layer 142 is formed on the first main surface 3. A plurality of source openings 230 are formed in the interlayer insulating layer 142. Each source opening 230 is formed in a portion of the interlayer insulating layer 142 that covers the region between adjacent first planar gate structures 213 and second planar gate structures 223. Each source opening 230 exposes the first source region 92, the second source region 112, and the contact region 212.

[0676] Although specific illustrations are omitted, the source electrode 12 is formed on the interlayer insulating layer 142 in such a way that it enters each source opening 230. The source electrode 12 is electrically connected to the first source region 92, the second source region 112, and the contact region 212 within each source opening 230. Additionally, although specific illustrations are omitted, the first gate control wiring 17A is electrically connected to the first gate electrode 193, and the second gate control wiring 17B is electrically connected to the second gate electrode 195.

[0677] Figure 36A It is used for explanation Figure 35 A cross-sectional perspective view of the normal operation of the semiconductor device 211 shown. Figure 36B It is used for explanation Figure 35 A cross-sectional perspective view of the active clamping action of the semiconductor device 211 shown.

[0678] Reference Figure 36A During normal operation of the power MISFET 9, a first turn-on signal Von1 is input to the first gate control wiring 17A, and a second turn-on signal Von2 is input to the second gate control wiring 17B. The first turn-on signal Von1 and the second turn-on signal Von2 are respectively input from the controller IC10.

[0679] The first turn-on signal Von1 and the second turn-on signal Von2 each have a voltage greater than or equal to the gate threshold voltage Vth. Alternatively, the first turn-on signal Von1 and the second turn-on signal Von2 may each have the same voltage.

[0680] In this case, the first gate electrode 193 and the second gate electrode 195 are both turned on. As a result, both the first channel region 91 and the second channel region 111 are controlled to be turned on.

[0681] As a result, both the first MISFET 56 and the second MISFET 57 are driven (fully on control). The channel utilization RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. Therefore, compared with the case where the characteristic channel ratio RC is less than 50%, the area resistivity Ron·A decreases.

[0682] On the other hand, refer to Figure 36B When the power MISFET9 is actively clamped, a disconnect signal Voff is input to the first gate control wiring 17A, and a clamping signal VCon is input to the second gate control wiring 17B. The disconnect signal Voff and the clamping signal VCon are input from the controller IC10.

[0683] The off signal Voff has a voltage less than the gate threshold voltage Vth (e.g., a reference voltage). The clamp on signal VCon has a voltage greater than or equal to the gate threshold voltage Vth. The clamp on signal VCon may also have a voltage less than or lower than the voltage during normal operation.

[0684] In this case, the first gate electrode 193 is in the off state, and the second gate electrode 195 is in the on state. As a result, the first channel region 91 is controlled to be in the off state and the second channel region 111 is controlled to be in the on state.

[0685] As a result, the first MISFET 56 is controlled to be in the off state, and the second MISFET 57 is controlled to be in the on state (second half-on control). Therefore, the channel utilization RU during active clamping operation becomes greater than zero and less than the channel utilization RU during normal operation. The channel utilization RU during active clamping operation is 50%. Furthermore, the characteristic channel ratio RC during active clamping operation is 25%. Therefore, compared to cases where the characteristic channel ratio RC exceeds 25%, the active clamping tolerance Eac is improved.

[0686] As described above, semiconductor device 211 can also achieve the same effect as semiconductor device 1.

[0687] <Ninth Implementation Method>

[0688] Figure 37 This is a perspective view of the semiconductor device 241 according to the ninth embodiment of the present invention, viewed from one direction. Hereinafter, the same reference numerals will be used to denote the structures corresponding to those described in the semiconductor device 1, and descriptions will be omitted.

[0689] In the first embodiment described above, an example of a semiconductor device 1 being a high-side switching device was presented. However, the semiconductor device 1 can also be provided as a low-side switching device. Here, an example of a semiconductor device 1 manufactured as a low-side switching device will be described as the semiconductor device 241 of the ninth embodiment.

[0690] The configuration (control example) of the power MISFET 9 assembled in the semiconductor device 241 is not limited to the configuration (control example) of the power MISFET 9 in the first embodiment. Any one of the configurations (control examples) of the power MISFET 9 shown in the second, third, fourth, fifth, sixth, seventh, and eighth embodiments can be applied. The description of the configuration (control example) of the power MISFET 9 in the first to eighth embodiments will be referenced, and the description of the configuration (control example) of the power MISFET 9 in the semiconductor device 241 will be omitted.

[0691] Reference Figure 37 Similar to the first embodiment, the semiconductor device 241 includes a semiconductor layer 2. Also similar to the first embodiment, an output region 6 and an input region 7 are divided within the semiconductor layer 2. The output region 6 includes a power MISFET 9. The input region 7 includes a controller IC 10.

[0692] Multiple (three in this case) electrodes 11, 12, and 13 are formed on semiconductor layer 2. Figure 37 In the diagram, multiple electrodes 11 to 13 are shown by shading. The number, arrangement, and planar shape of the multiple electrodes 11 to 13 are arbitrary and not limited to any particular type. Figure 37 As shown in the diagram.

[0693] The number, arrangement, and planar shape of the multiple electrodes 11-13 are adjusted according to the specifications of the power MISFET9 and the controller IC10. In this configuration, the multiple electrodes 11-13 include a drain electrode 11 (output electrode), a source electrode 12 (reference voltage electrode), and an input electrode 13.

[0694] Similar to the first embodiment, the drain electrode 11 is formed on the second main surface 4 of the semiconductor layer 2. The drain electrode 11 transmits the electrical signal generated by the power MISFET 9 to the outside.

[0695] Similar to the first embodiment, the source electrode 12 is formed on the output region 6 in the first main surface 3. The source electrode 12 provides a reference voltage (e.g., ground voltage) to the power MISFET 9 and various functional circuits of the controller IC 10.

[0696] Similar to the first embodiment, the input electrode 13 is formed on the input region 7 in the first main surface 3. The input electrode 13 transmits the input voltage for driving the controller IC 10.

[0697] Similar to the first embodiment, a gate control wiring 17, as an example of control wiring, is formed on the semiconductor layer 2. In this embodiment, the gate control wiring 17 includes a first gate control wiring 17A, a second gate control wiring 17B, and a third gate control wiring 17C. The gate control wiring 17 is selectively wound to the output region 6 and the input region 7. The gate control wiring 17 is electrically connected to the gate of the power MISFET 9 in the output region 6 and electrically connected to the controller IC 10 in the input region 7.

[0698] Figure 38 It means Figure 37 The diagram shows a block circuit illustrating the electrical structure of the semiconductor device 241. The following explanation will use the example of the semiconductor device 241 being mounted in a vehicle.

[0699] Semiconductor device 241 includes a drain electrode 11 as an output electrode, a source electrode 12 as a reference voltage electrode, an input electrode 13, a gate control wiring 17, a power MISFET 9, and a controller IC 10.

[0700] Drain electrode 11 is electrically connected to the drain of power MISFET 9. Drain electrode 11 is connected to the load. Source electrode 12 is electrically connected to the source of power MISFET 9. Source electrode 12 provides a reference voltage to power MISFET 9 and controller IC 10.

[0701] Input electrode 13 can also be connected to an MCU, DC / DC converter, LDO, etc. Input electrode 13 provides input voltage to controller IC 10. The gate of power MISFET 9 is connected to controller IC 10 (gate control circuit 25 described later) via gate control wiring 17.

[0702] In this configuration, the controller IC10 includes a current and voltage control circuit 23, a protection circuit 24, a gate control circuit 25, and an active clamping circuit 26.

[0703] The current and voltage control circuit 23 is connected to the source electrode 12, the input electrode 13, the protection circuit 24, and the gate control circuit 25. The current and voltage control circuit 23 generates various voltages based on electrical signals from the input electrode 13 and from the protection circuit 24. In this configuration, the current and voltage control circuit 23 includes a drive voltage generation circuit 30, a first constant voltage generation circuit 31, a second constant voltage generation circuit 32, and a reference voltage and reference current generation circuit 33.

[0704] The drive voltage generation circuit 30 generates a drive voltage for driving the gate control circuit 25. The drive voltage generated by the drive voltage generation circuit 30 is input to the gate control circuit 25.

[0705] The first constant voltage generation circuit 31 generates a first constant voltage for driving the protection circuit 24. The first constant voltage generation circuit 31 may also include a Zener diode and a regulator circuit. The first constant voltage is input to the protection circuit 24 (e.g., overcurrent protection circuit 34).

[0706] The second constant voltage generation circuit 32 generates a second constant voltage for driving the protection circuit 24. The second constant voltage generation circuit 32 may also include a Zener diode and a regulator circuit. The second constant voltage is input to the protection circuit 24 (e.g., overheat protection circuit 36).

[0707] The reference voltage and reference current generation circuit 33 generates reference voltages and reference currents for various circuits. These reference voltages and reference currents are then input to the various circuits. In cases where the various circuits include a comparator, the reference voltage and reference current can also be input to that comparator.

[0708] Protection circuit 24 is connected to current and voltage control circuit 23, gate control circuit 25, and the source of power MISFET 9. Protection circuit 24 includes overcurrent protection circuit 34 and overheat protection circuit 36.

[0709] Overcurrent protection circuit 34 protects power MISFET 9 from overcurrent. Overcurrent protection circuit 34 is connected to gate control circuit 25. Overcurrent protection circuit 34 may also include current monitoring circuit. The signal generated by overcurrent protection circuit 34 is input to gate control circuit 25 (specifically, drive signal output circuit 40 described later).

[0710] Overheat protection circuit 36 ​​protects power MISFET 9 from excessive temperature rise. Overheat protection circuit 36 ​​is connected to current and voltage control circuit 23. Overheat protection circuit 36 ​​monitors the temperature of semiconductor device 241. Overheat protection circuit 36 ​​may also include temperature sensing devices such as temperature-sensing diodes and thermistors. The signal generated by overheat protection circuit 36 ​​is input to current and voltage control circuit 23.

[0711] The gate control circuit 25 controls the on and off states of the power MISFET 9. The gate control circuit 25 is connected to the current and voltage control circuit 23, the protection circuit 24, and the gate of the power MISFET 9.

[0712] The gate control circuit 25 generates multiple gate control signals corresponding to the number of gate control lines 17 based on electrical signals from the current and voltage control circuit 23 and from the protection circuit 24. These multiple gate control signals are input to the gate of the power MISFET 9 via the gate control lines 17.

[0713] Specifically, the gate control circuit 25 includes an oscillation circuit 38, a charge pump circuit 39, and a drive signal output circuit 40. The oscillation circuit 38 oscillates according to the electrical signal from the current-voltage control circuit 23 and generates a predetermined electrical signal. The electrical signal generated by the oscillation circuit 38 is input to the charge pump circuit 39. The charge pump circuit 39 boosts the electrical signal from the oscillation circuit 38. The boosted electrical signal from the charge pump circuit 39 is then input to the drive signal output circuit 40.

[0714] The drive signal output circuit 40 generates various gate control signals based on electrical signals from the charge pump circuit 39 and the protection circuit 24 (specifically, the overcurrent protection circuit 34). These gate control signals are input to the gate of the power MISFET 9 via the gate control wiring 17. This drives and controls the power MISFET 9.

[0715] The active clamping circuit 26 protects the power MISFET 9 from back electromotive force. The active clamping circuit 26 is connected to the drain electrode 11 and the gate of the power MISFET 9.

[0716] Figure 39 It is used for explanation Figure 37 The circuit diagram shows the normal operation of the semiconductor device 241 and its active clamping operation. Figure 40 yes Figure 39 The circuit diagram shown is a waveform diagram of the main electrical signals used.

[0717] Here, a circuit example with an inductive load L connected to the power MISFET 9 is used to explain the normal operation and active clamping operation of the semiconductor device 241. The example uses a device with windings (coils) such as a solenoid, motor, transformer, or relay as the inductive load L. The inductive load L is also called an L-load.

[0718] Reference Figure 39 The source of the power MISFET9 is connected to ground. The drain of the power MISFET9 is electrically connected to the inductive load L. The gate and drain of the power MISFET9 are connected to the active clamping circuit 26. The gate and source of the power MISFET9 are connected to a resistor R. In this circuit example, the active clamping circuit 26 includes k Zener diodes DZ that are mutually biased.

[0719] Reference Figure 39 as well as Figure 40 If an on signal Von is input to the gate of the power MISFET9 which is in the off state, the power MISFET9 switches from the off state to the on state (normal operation). The on signal Von has a voltage greater than or equal to the gate threshold voltage Vth (Vth≤Von). The power MISFET9 remains on for a predetermined on time TON.

[0720] If the power MISFET9 switches to the ON state, the drain current ID begins to flow from the drain of the power MISFET9 towards the source. The drain current ID increases proportionally to the ON time TON of the power MISFET9. The inductive load L stores inductive energy due to the increase in drain current ID.

[0721] If an off signal Voff is input to the gate of the power MISFET9, the power MISFET9 switches from the on state to the off state. The off signal Voff has a voltage less than the gate threshold voltage Vth (Voff < Vth). The off signal Voff can also be a reference voltage (e.g., ground voltage). When the power MISFET9 switches to the off state, the induced energy of the inductive load L is applied to the power MISFET9 as a back electromotive force.

[0722] Therefore, the power MISFET9 enters an active clamping state (active clamping operation). If the power MISFET9 enters an active clamping state, the drain voltage VDS rises sharply to the clamping voltage VDSSCL.

[0723] The power MISFET9 fails when the clamping voltage VDSSCL exceeds the maximum rated drain voltage VDSS (VDSS < VDSSCL). The power MISFET9 is designed so that the clamping voltage VDSSCL is below the maximum rated drain voltage VDSS (VDSSCL ≤ VDSS).

[0724] When the clamping voltage VDSSCL is below the maximum rated drain voltage VDSS (VDSSCL ≤ VDSS), the reverse current IZ flows to the active clamping circuit 26. This creates a limiting voltage VL between the terminals of the active clamping circuit 26. In this configuration, the limiting voltage VL is the sum of the voltages VZ between the terminals of the Zener diode DZ in the active clamping circuit 26 (VL = k·VZ).

[0725] Additionally, the reverse current IZ reaches ground through resistor R. This creates an inter-terminal voltage VR between the terminals of resistor R. The inter-terminal voltage VR (=IZ×R) of resistor R is adjusted to be above the gate threshold voltage Vth (Vth≤VR). The inter-terminal voltage VR is applied as the clamping turn-on voltage VCLP between the gate and source of the power MISFET9. Therefore, the power MISFET9 remains on in an active clamped state. The clamping turn-on voltage VCLP (inter-terminal voltage VR) can also be a voltage less than the turn-on signal Von.

[0726] Therefore, the inductive energy of the inductive load L is consumed (absorbed) in the power MISFET 9. The drain current ID is reduced to zero from its peak IAV before the power MISFET 9 is turned off after the active clamping time TAV. As a result, the gate voltage VGS becomes the ground voltage, the drain voltage VDS becomes the power supply voltage VB, and the power MISFET 9 switches from the on state to the off state.

[0727] The active clamping withstand capacity Eac of the power MISFET9 is defined based on its withstand capacity during active clamping operation. Specifically, the active clamping withstand capacity Eac is defined based on the withstand capacity of the power MISFET9 relative to the back electromotive force generated by the induced energy of the inductive load L when it transitions from the on state to the off state.

[0728] More specifically, such as Figure 39 As is clear in the circuit example, the active clamp tolerance Eac is defined based on the tolerance relative to the energy generated by the clamp voltage VDSSCL.

[0729] As described above, semiconductor device 241 can also achieve the same effect as semiconductor device 1.

[0730] The embodiments of the present invention have been described, but the present invention can also be implemented in other ways.

[0731] In the above embodiments, when the first bottom-side electrode 86 and the second bottom-side electrode 106, which are electrically connected to the third gate control wiring 17C, function as field electrodes, the third gate control wiring 17C can also be electrically connected to the source electrode 12 to replace the controller IC.

[0732] In this case, the third gate control wiring 17C can also be led out from the source electrode 12. Therefore, the reference voltage (e.g., ground voltage) is transmitted from the source electrode 12 to the first bottom-side electrode 86 and the second bottom-side electrode 106 via the third gate control wiring 17C. According to this configuration, the same effect as described in the semiconductor device 1 can be achieved.

[0733] In the above embodiments, as long as the channel utilization RU during active clamping operation and the channel utilization RU during normal operation can be properly controlled, the arrangement of the plurality of first FET structures 58 and the plurality of second FET structures 68 is arbitrary.

[0734] For example, multiple second FET structures 68 may be arranged alternately with multiple first FET structures 58 in a configuration that alternates between them. Multiple second FET structures 68 may also be arranged alternately with multiple first FET structures 58 in a configuration that alternates between them in a configuration that alternates between two, three, four, five, six, seven, eight, nine, or ten first FET structures 58.

[0735] Similarly, multiple first FET structures 58 can also be arranged alternately with multiple second FET structures 68 in a configuration that alternates between them. Multiple first FET structures 58 can also be arranged alternately with multiple second FET structures 68 in a configuration that alternates between them ...

[0736] Of course, groups of multiple (two or more) first FET structures 58 and groups of multiple (two or more) second FET structures 68 can also be arranged alternately. Alternatively, multiple first FET structures 58 and multiple second FET structures 68 can be formed in a configuration where groups of multiple first FET structures 58 and one second FET structure 68 are arranged alternately. Alternatively, multiple first FET structures 58 and multiple second FET structures 68 can be formed in a configuration where groups of one first FET structure 58 and multiple second FET structures 68 are arranged alternately.

[0737] However, when multiple first FET structures 58 and / or multiple second FET structures 68 are arranged in a group, a bias can easily form in the temperature distribution of the semiconductor layer 2. Therefore, it is preferable that four or fewer first FET structures 58 and / or four or fewer second FET structures 68 are arranged in a group.

[0738] In the above embodiments, as long as the channel utilization rate RU during active clamping operation and the channel utilization rate RU during normal operation can be properly controlled, the value of the total channel ratio RT in each unit region 75 is arbitrary.

[0739] For example, in the above embodiments, an example of applying the total channel ratio RT, including the first total channel ratio RT1, the second total channel ratio RT2, and the third total channel ratio RT3, to multiple unit regions 75 has been described.

[0740] However, multiple (two or more) total channel ratios RT with mutually different values ​​can also be applied to multiple cell regions 75. For example, two, three, four, five or six, or more total channel ratios RT with mutually different values ​​can also be applied to multiple cell regions 75.

[0741] Furthermore, in the embodiments described above, an example of the power MISFET 9 including a first MISFET 56 and a second MISFET 57 has been described. However, the power MISFET 9 may also include two, three, four, five, six, or more MISFETs that can be controlled independently of each other. Multiple (two or more) MISFETs can be formed by simply changing the number of gate control wirings 17 connected to the trench gate configuration.

[0742] In this case, the controller IC10 controls multiple (two or more) MISFETs in such a way that the channel utilization RU during active clamping operation is greater than zero and less than the channel utilization RU during normal operation.

[0743] In the above embodiments, the gate control wiring 17 can be formed on a different layer than the drain electrode 11, source electrode 12, input electrode 13, reference voltage electrode 14, ENABLE electrode 15, and SENSE electrode 16, or it can be formed on the same layer. Furthermore, in the gate control wiring 17, the first gate control wiring 17A, the second gate control wiring 17B, and the third gate control wiring 17C can be formed on different layers or on the same layer.

[0744] In the above embodiments, the p-type semiconductor portion may also be an n-type semiconductor portion, and the n-type semiconductor portion may also be a p-type semiconductor portion. In this case, in the description of the above embodiments, the "n-type" portion is replaced with "p-type", and the "p-type" portion is replaced with "n-type".

[0745] like Figure 41 as well as Figure 42 As shown, the semiconductor devices 1, 151, 161, 171, 181, 191, 201, 211, and 241 of the above embodiments can also be assembled into a semiconductor package. Figure 41 This is a perspective view of the semiconductor package 301 through the encapsulating resin 307. Figure 42 yes Figure 41 Top view.

[0746] Reference Figure 41 as well as Figure 42 In this configuration, the semiconductor package 301 is a so-called SOP (Small Outline Package). The semiconductor package 301 includes a chip pad 302, a semiconductor chip 303, a conductive bonding material 304, a plurality of (eight in this configuration) lead electrodes 305A to 305H, a plurality of (eight in this configuration) wires 306A to 306H, and a sealing resin 307.

[0747] The chip pad 302 is made of a metal plate formed in a cuboid shape. The chip pad 302 may also contain iron, aluminum, or copper. The semiconductor chip 303 is made of any one of the semiconductor devices 1, 151, 161, 171, 181, 191, 201, 211, and 241 of the first to ninth embodiments. Here, the semiconductor chip 303 is made of the semiconductor device 1 of the first embodiment.

[0748] The semiconductor chip 303 is positioned on the chip pad 302 with its second main surface 4 facing the chip pad 302. The drain electrode 11 of the semiconductor chip 303 is connected to the chip pad 302 via a conductive bonding material 304. The conductive bonding material 304 may also be metal paste or solder.

[0749] The multiple lead electrodes 305A to 305H include a first lead electrode 305A, a second lead electrode 305B, a third lead electrode 305C, a fourth lead electrode 305D, a fifth lead electrode 305E, a sixth lead electrode 305F, a seventh lead electrode 305G, and an eighth lead electrode 305H. The number of lead electrodes is selected according to the function of the semiconductor chip 303 and is not limited to a certain number. Figure 41 as well as Figure 42 The number shown.

[0750] The multiple lead electrodes 305A to 305H may also contain iron, aluminum, or copper. The multiple lead electrodes 305A to 305H are arranged around the chip pad 302 with spacing from it.

[0751] Specifically, the four lead electrodes 305A to 305D are arranged with gaps along one side of the chip pad 302. The remaining four lead electrodes 305E to 305H are arranged with gaps along the side of the chip pad 302 opposite to the side where the lead electrodes 305A to 305D are arranged.

[0752] Multiple lead electrodes 305A to 305H are each formed as a strip extending in a direction orthogonal to the arrangement direction. Each lead electrode 305A to 305H has one end opposite to the chip pad 302 and another end on the opposite side. One end of each lead electrode 305A to 305H is internally connected to the semiconductor chip 303. The other end of each lead electrode 305A to 305H is externally connected to a mounting substrate or other connection object.

[0753] The multiple wires 306A to 306H include a first wire 306A, a second wire 306B, a third wire 306C, a fourth wire 306D, a fifth wire 306E, a sixth wire 306F, a seventh wire 306G, and an eighth wire 306H. The number of wires is selected according to the function of the semiconductor chip 303 (semiconductor device) and is not limited to a certain number. Figure 41 as well as Figure 42 The number shown.

[0754] The first lead 306A is electrically connected to one end of the first lead electrode 305A and the source electrode 12. In this configuration, the first lead 306A is constructed from a metal clamping element. The first lead 306A may also contain iron, gold, aluminum, or copper. The first lead 306A effectively dissipates the heat generated in the power MISFET 9 to the outside. Of course, the first lead 306A may also be constructed from a bonding lead.

[0755] The second wire 306B is electrically connected to one end of the second lead electrode 305B and the reference voltage electrode 14. The third wire 306C is electrically connected to one end of the third lead electrode 305C and the ENABLE electrode 15. The fourth wire 306D is electrically connected to one end of the fourth lead electrode 305D and the SENSE electrode 16.

[0756] The fifth lead 306E is electrically connected to one end of the fifth lead electrode 305E and the chip pad 302. The sixth lead 306F is electrically connected to one end of the sixth lead electrode 305F and the chip pad 302. The seventh lead 306G is electrically connected to one end of the seventh lead electrode 305G and the input electrode 13. The eighth lead 306H is electrically connected to one end of the eighth lead electrode 305H and the chip pad 302.

[0757] In this configuration, the second to eighth conductors 306B to 306H are composed of bonding leads. The second to eighth conductors 306B to 306H may also contain gold, aluminum, or copper, respectively. The connection method of the multiple conductors 306A to 306H relative to the semiconductor chip 303 and the multiple lead electrodes 305A to 305H is arbitrary and not limited to any particular configuration. Figure 41 as well as Figure 42 The connection method shown.

[0758] The sealing resin 307 seals the semiconductor chip 303, the chip pad 302, one end of the multiple lead electrodes 305A-305H, and the multiple wires 306A-306H in such a way that the other ends of the multiple lead electrodes 305A-305H are exposed. The sealing resin 307 is formed in a cuboid shape. The sealing resin 307 may also contain epoxy resin.

[0759] The semiconductor package 301 is not limited to SOP. As a semiconductor package 301, TO (Transistor Outline), QFN (Quad For Non-Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package), SOJ (Small Outline J-leaded Package), or various similar methods can also be used.

[0760] like Figure 43 As shown, semiconductor packages 301 (semiconductor devices 1, 151, 161, 171, 181, 191, 201, 211, 241) can also be assembled into circuit modules. Figure 43This is a top view showing a portion of the circuit module 311 in the first example.

[0761] Reference Figure 43 The circuit module 311 includes a mounting substrate 312, a plurality of wirings 313, a semiconductor package 301 (semiconductor devices 1, 151, 161, 171, 181, 191, 201, 211, 241), and a conductive bonding material 314.

[0762] Mounting substrate 312 includes a main surface 315. A plurality of wirings 313 are formed on the main surface 315 of mounting substrate 312. Semiconductor packages 301 (semiconductor devices 1, 151, 161, 171, 181, 191, 201, 211, 241) are mounted on mounting substrate 312 in a manner electrically connected to the plurality of wirings 313 via a conductive bonding material 314. The conductive bonding material 314 may also be metal paste or solder.

[0763] In the above embodiments, examples of semiconductor devices 1, 151, 161, 171, 181, 191, 201, 211, and 241 integrating a power MISFET 9 and a controller IC 10 have been described.

[0764] However, semiconductor devices 1, 151, 161, 171, 181, 191, 201, 211, and 241 that only have power MISFET9 can also be used. In addition, semiconductor devices 1, 151, 161, 171, 181, 191, 201, 211, and 241 that only have power MISFET9 can also be assembled into the semiconductor package 301 described above.

[0765] like Figure 44 As shown, semiconductor packages 301 (semiconductor devices 1, 151, 161, 171, 181, 191, 201, 211, 241) with only power MISFET9 can also be assembled into circuit modules. Figure 44 This is a top view showing a portion of the circuit module 321 in the second example.

[0766] Reference Figure 44 The circuit module 321 includes a mounting substrate 322, a plurality of wirings 323, a semiconductor package 301 (semiconductor devices 1, 151, 161, 171, 181, 191, 201, 211, 241), a first conductive bonding material 324, a controller IC device 325, and a second conductive bonding material 326.

[0767] Mounting substrate 322 includes a main surface 327. A plurality of wirings 323 are formed on the main surface 327 of mounting substrate 322. Semiconductor package 301 is mounted on mounting substrate 322. Semiconductor package 301 is electrically connected to the plurality of wirings 323 via a first conductive bonding material 324. The first conductive bonding material 324 may also be metal paste or solder.

[0768] Controller IC device 325 includes controller IC 10 (reference) Figure 2 , Figure 38 The controller IC device 325 is mounted on the mounting substrate 322. The controller IC device 325 is electrically connected to a plurality of wires 323 via a second conductive bonding material 326. The controller IC device 325 is also electrically connected to the semiconductor package 301 via a plurality of wires 323.

[0769] The electrical connection configuration of the controller IC device 325 relative to the semiconductor package 301 and Figure 2 Same. The controller IC device 325 controls the semiconductor package 301 (semiconductor devices 1, 151, 161, 171, 181, 191, 201, 211, 241) from the outside.

[0770] This configuration also achieves the effects described in the above embodiments. In this embodiment, an example of a controller IC device 325, in which a single chip including the controller IC 10 is mounted on a mounting substrate 322, is illustrated.

[0771] However, instead of the controller IC device 325, a circuit network with the same function as the controller IC 10 can be mounted on the mounting substrate 322. The circuit network with the same function as the controller IC 10 can also be constructed by mounting multiple discrete devices, IC chips with arbitrary functions, on the mounting substrate 322.

[0772] Of course, the structure of the controller IC10 and the circuit network with the same function as the controller IC10 in the above embodiments is arbitrary and does not necessarily have to include all the functional circuits (that is, sensor MISFET21, input circuit 22, current and voltage control circuit 23, protection circuit 24, gate control circuit 25, active clamping circuit 26, current detection circuit 27, power supply reverse connection protection circuit 28, and abnormal detection circuit 29). Some functional circuits can also be removed.

[0773] This specification does not limit the arbitrary combination of features shown in the first to ninth embodiments. The first to ninth embodiments can be combined in any form and in any manner. That is, a semiconductor device can also employ the features shown in the first to ninth embodiments in any form and in any manner.

[0774] In addition, various design changes can be implemented within the scope of the matters described in the technical solution.

[0775] Next, a detailed explanation will be given with specific examples of the electrical construction used for the first half-on control (or second half-on control) of the power MISFET9 during active clamping operation.

[0776] <Tenth Implementation Method>

[0777] Figure 45 This refers to the semiconductor device according to the tenth embodiment of the present invention (i.e., in the case where semiconductor device 1 is a high-side switch, for example, see reference). Figures 1-4 (The following is a block circuit diagram of the electrical structure used for the first half-on control of the power MISFET during active clamping operation.)

[0778] The semiconductor device X1 in this embodiment includes a drain electrode 11 (= power supply electrode VBB), a source electrode 12 (= output electrode OUT), a power MISFET 9, a gate control circuit 25, and an active clamping circuit 26. Components that have already appeared are labeled with the same symbols.

[0779] Furthermore, in this figure, for the sake of simplicity, only a portion of the components are shown; however, semiconductor device X1 can also be understood to essentially include semiconductor device 1 as described above (see Figure 1). Figure 2 The same constituent elements.

[0780] The power MISFET9 is a gate-segmented device whose construction has been described in detail so far by illustrating various embodiments. That is, as... Figure 48 As shown, the power MISFET9 can be equivalently represented as a first MISFET56 and a second MISFET57 connected in parallel (which are respectively equivalent to the first transistor and the second transistor).

[0781] If another method is used, it can be understood that the first MISFET56 and the second MISFET57, which are controlled independently respectively, are integrated into a single power MISFET9 as a single gate-segmented element.

[0782] The gate control circuit 25 performs gate control of the power MISFET 9 (and consequently, gate control of the first MISFET 56 and the second MISFET 57). For example, in an enabled state (equivalent to the first operating state) where the enable signal EN is high, the gate control circuit 25 turns on both the first MISFET 56 and the second MISFET 57, and in a disabled state (equivalent to the second operating state) where the enable signal EN is low, turns off both the first MISFET 56 and the second MISFET 57, thereby generating gate signals G1 and G2 for the first MISFET 56 and the second MISFET 57 respectively.

[0783] In addition, the gate control circuit 25 has the following function: it receives the input of the internal node voltage Vx from the active clamp circuit 26, and after the transition from the enabled state (EN=H) to the disabled state (EN=L) and before the active clamp circuit 26 operates (= before the output voltage VOUT becomes clamped), it short-circuits the gate-source of the second MISFET 57. That is, it completely stops the second MISFET 57 by setting G2=VOUT, thereby realizing the first half-on control function of the power MISFET 9.

[0784] An active clamping circuit 26 is connected between the drain and gate of the first MISFET 56. When the output voltage VOUT of the source electrode 12 becomes negative, the first MISFET 56 is forcibly turned on (not completely turned off), thereby limiting the drain-source voltage (=VB - VOUT) of both the first MISFET 56 and the second MISFET 57 to below a predetermined clamping voltage Vclp. The second MISFET 57 does not contribute to the active clamping operation, therefore, the active clamping circuit 26 is not connected between its drain and gate.

[0785] Figure 47 It means Figure 45 A circuit diagram of an example configuration of the gate control circuit 25 and the active clamping circuit 26.

[0786] First, the structure of the active clamping circuit 26 will be described in detail. The active clamping circuit 26 in this embodiment includes an m-stage (e.g., m=8) Zener diode array 261, an n-stage (e.g., n=3) diode array 262, and an N-channel MISFET 263 (equivalent to a third transistor).

[0787] The cathode of Zener diode array 261 and the drain of MISFET 263 are connected to the drain electrode 11 (equivalent to the power supply electrode VBB where the power supply voltage VB is applied) of both the first MISFET 56 and the second MISFET 57. The anode of Zener diode array 261 is connected to the anode of diode array 262. The cathode of diode array 262 is connected to the gate of MISFET 263. The source of MISFET 263 is connected to the gate of the first MISFET 56 (equivalent to the application terminal of gate signal G1). The back gate of MISFET 263 and the sources of both the first MISFET 56 and the second MISFET 57 are connected to the source electrode 12 (equivalent to the output electrode OUT where the output voltage VOUT is applied). As described above. Figure 45 as well as Figure 46 As shown, an inductive load L such as a coil or solenoid can be connected to the source electrode 12.

[0788] The structure of the gate control circuit 25 will be described in detail below. The gate control circuit 25 in this embodiment includes current sources 251 to 254, a controller 255, and an N-channel MISFET 256 (equivalent to a fourth transistor).

[0789] Current source 251 is connected between the application terminal of boost voltage VG (= charge pump output) and the gate of first MISFET 56, and generates source current IH1.

[0790] Current source 252 is connected between the application terminal of boost voltage VG and the gate of second MISFET 57, and generates source current IH2.

[0791] Current source 253 is connected between the gate of the first MISFET 56 and the application terminal of the output voltage VOUT (= source electrode 12), and generates sink current IL1.

[0792] Current source 254 is connected between the gate of the second MISFET 57 and the application terminal of the output voltage VOUT, and generates a sink current IL2.

[0793] When the controller 255 is in the enabled state (EN=H), it turns on current sources 251 and 252 and turns off current sources 253 and 254. Through this current control, source currents IH1 and IH2 flow into the gates of the first MISFET 56 and the second MISFET 57, respectively.

[0794] On the other hand, in the disabled state (EN=L), the controller 255 disconnects current sources 251 and 252 and connects current sources 253 and 254. Through this current control, the sink currents IL1 and IL2 are directed from the gates of the first MISFET 56 and the second MISFET 57, respectively.

[0795] MISFET 256 is connected between the gate and source of the second MISFET 57 and is turned on / off according to the internal node voltage Vx of the active clamping circuit 26. As shown in this figure, the internal node voltage Vx is preferably the gate voltage of the input MISFET 263. However, the internal node voltage Vx is not limited to this; for example, any anode voltage of the n-stage diodes forming the diode array 262 can also be used as the internal node voltage Vx.

[0796] In addition, in the semiconductor device X1, besides the aforementioned components, Zener diodes ZD1 to ZD...

Claims

1. A semiconductor device, characterized in that, have: The output electrode is configured to be connected to an inductive load; The grounding electrode is configured to be connected to the grounding terminal; The first transistor and the second transistor are configured to be connected in parallel between the output electrode and the ground electrode. An active clamping circuit, configured to be connected to the gate of the first transistor; and The gate control circuit is configured to control the gates of the first transistor and the second transistor respectively in a manner that the first transistor and the second transistor are turned on in a first operating state and turned off in a second operating state. After the gate control circuit transitions from the first operating state to the second operating state, and before the active clamping circuit operates, it short-circuits the gate-source of the second transistor. The above-mentioned active clamping circuit includes: A Zener diode, configured such that its cathode is connected to the drain of the first transistor described above; and The diode is configured such that its anode is connected to the anode of the aforementioned Zener diode, and its cathode is connected to the gate of the aforementioned first transistor. The aforementioned gate control circuit includes a third transistor connected between the gate and source of the second transistor, which is switched on / off according to the internal node voltage of the active clamping circuit. The aforementioned internal node voltage is the gate voltage of the aforementioned third transistor. The aforementioned gate control circuit also includes: The first switch is configured to be connected between the input electrode to which an external control signal is applied and the gate of the first transistor, and is turned on when the external control signal is higher than the low voltage detection threshold. The second switch is configured to be connected between the input electrode and the gate of the second transistor, and is turned on when the external control signal is higher than the low voltage detection threshold; and The third switch is connected between the internal node voltage application terminal and the gate of the third transistor, and is turned on when the external control signal is lower than the low voltage detection threshold.

2. The semiconductor device according to claim 1, characterized in that, The active clamping circuit described above limits the drain-source voltage of the first transistor and the second transistor to below a predetermined clamping voltage.

3. The semiconductor device according to claim 1, characterized in that, The first channel region of the first transistor and the second channel region of the second transistor are arranged adjacent to each other.

4. The semiconductor device according to claim 1, characterized in that, The aforementioned gate control circuit also includes: A first upper resistor, configured to be connected between the first switch and the gate of the first transistor, adjusts the rise rate of the first gate signal applied to the first transistor; and The second upper resistor is configured to be connected between the second switch and the gate of the second transistor to adjust the rise rate of the second gate signal applied to the second transistor.

5. The semiconductor device according to claim 4, characterized in that, The aforementioned gate control circuit also includes: A first PMOSFET, configured to be connected between the gate of the first transistor and the ground electrode, is turned on / off according to the external control signal; and The second PMOSFET is configured to be connected between the gate of the second transistor and the ground electrode, and is turned on / off according to the external control signal.

6. The semiconductor device according to claim 5, characterized in that, The aforementioned gate control circuit also includes: A first lower resistor, configured to be connected between the first PMOSFET and the ground electrode, adjusts the descent rate of the first gate signal; and The second lower resistor is configured to be connected between the second PMOSFET and the ground electrode to adjust the descent speed of the second gate signal.

7. The semiconductor device according to claim 1, characterized in that, In the first operating state, the gate control circuit causes current to flow into the gates of the first transistor and the second transistor respectively, and in the second operating state, it draws current out from the gates of the first transistor and the second transistor respectively.

8. The semiconductor device according to claim 1, characterized in that, The first transistor and the second transistor are formed as a single gate split element.

9. The semiconductor device according to claim 1, characterized in that, The channel region of the first transistor is formed at a first ratio, and the channel region of the second transistor is formed at a second ratio different from the first ratio.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, The channel utilization rate during active clamping operation is greater than zero and less than that during normal operation.

11. An electronic device, characterized in that, have: The semiconductor device according to any one of claims 1 to 10; and An inductive load connected to the aforementioned semiconductor device.

12. A semiconductor device, characterized in that, have: A gate-splitter transistor is configured such that its on-resistance varies by individual control of multiple gate signals; The gate control circuit is configured to individually control the plurality of gate signals in such a way that the on-resistance decreases compared to the stable value during the on-state transition of the gate segmentation transistor. as well as An active clamping circuit is configured to limit the voltage across the gate splitting transistor to below a predetermined clamping voltage. Before the active clamping circuit operates, the gate control circuit individually controls the plurality of gate signals by increasing the on-resistance compared to the stable value. The aforementioned gate-splitting transistor includes: a first gate and a second gate, and a third gate configured to be connected to the aforementioned active clamping circuit. The aforementioned gate control circuit includes: A first switch, configured to be connected between the first gate and source of the gate-splitting transistor, is disconnected when the on-resistance decreases below the stable value; and The second and third switches are configured to be connected between the first and second gates and the source of the gate-splitting transistor, respectively, and are turned on when the on-resistance increases compared to the stable value. The second and third switches are respectively turned on / off according to the internal node voltage of the active clamping circuit. The above-mentioned active clamping circuit includes: A Zener diode, configured such that its cathode is connected to the drain of the aforementioned gate-splitter transistor; A diode, configured such that its anode is connected to the anode of the aforementioned Zener diode; The transistor is configured such that its drain is connected to the drain of the gate-divided transistor, its source is connected to the third gate of the gate-divided transistor, and its gate is connected to the cathode of the diode.

13. The semiconductor device according to claim 12, characterized in that, It also has an output voltage monitoring circuit, which is configured to monitor the output voltage of the gate split transistor and generate a drive signal for the first switch.

14. The semiconductor device according to claim 13, characterized in that, The above-mentioned output voltage monitoring circuit includes: The threshold voltage generation unit is configured to generate a predetermined threshold voltage; The comparator is configured to compare the above-mentioned output voltage with the above-mentioned threshold voltage and generate a comparison signal; The delay unit applies a predetermined delay to the comparison signal and generates a delayed signal; and A level shifter is configured to level-shift the aforementioned delayed signal and generate the aforementioned drive signal.

15. The semiconductor device according to claim 12, characterized in that, It also has an overcurrent protection circuit configured to detect the output current flowing through the gate split transistor and limit it to below a predetermined upper limit value.

16. The semiconductor device according to any one of claims 12 to 15, characterized in that, It also has an overheat protection circuit, which is configured to forcibly disconnect the gate segment transistor when the temperature of the gate segment transistor reaches a predetermined upper limit value, or when the temperature difference between the gate segment transistor and other circuit blocks reaches a predetermined upper limit value.

17. An electronic device, characterized in that, have: The semiconductor device according to any one of claims 12 to 16; and The load connected to the aforementioned semiconductor device.

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