Source driver, display device, and driving method of source driver

Abstract

A source driver, a display device including the source driver, and a driving method for the source driver are provided. The display device includes: a display panel including a plurality of horizontal lines, each horizontal line including a plurality of pixels; a timing controller configured to output a polarity control signal representing the polarity corresponding to each of the plurality of horizontal lines and having a value inverted in units of n horizontal lines; and a source driver configured to generate timing pulse signals sequentially representing the data charging time of each of the plurality of horizontal lines, and to output a data voltage corresponding to the polarity of each of the plurality of horizontal lines to the display panel based on the timing pulse signals. When the value of the polarity control signal is inverted, the source driver generates a timing pulse signal including a data charging time corresponding to a count value obtained by counting the number of horizontal lines after polarity inversion.

Description

[0001] Cross-references to related applications

[0002] The entire contents of Korean Patent Application No. 10-2020-0120038, filed on September 17, 2020, with the Korean Intellectual Property Office, entitled “Source Driver, Display Device Including the Source Driver, and Method of Operating the Source Driver”, are incorporated herein by reference. Technical Field

[0003] The embodiments relate to a source driver, a display device including the source driver, and a method for driving the source driver. Background Technology

[0004] Display devices are widely used in smartphones, laptops, monitors, and other devices, and include display panels for displaying images, which provide multiple pixels. Pixels are driven by data signals provided from display driver integrated circuits (ICs), thus the image is realized by the display panel. Summary of the Invention

[0005] This embodiment pertains to a display device, which includes: a display panel comprising a plurality of horizontal lines, each horizontal line comprising a plurality of pixels; a source driver configured to generate timing pulse signals sequentially representing the data charging time of each of the plurality of horizontal lines, and configured to output a data voltage having a polarity corresponding to each of the plurality of horizontal lines to the display panel based on the timing pulse signals; and a timing controller configured to output a polarity control signal representing the polarity of the data voltage corresponding to each of the plurality of horizontal lines, the polarity control signal having a value inverted in units of n (where n is a positive integer) horizontal lines. When the value of the polarity control signal is inverted, the source driver can generate timing pulse signals representing data charging times corresponding to count values ​​obtained by counting the number of horizontal lines after the polarity of the data voltage is inverted.

[0006] The embodiment also relates to a driving method for a source driver, the driving method comprising: receiving a polarity control signal representing the polarity corresponding to each of a plurality of horizontal lines on a display panel, the polarity control signal having a value inverted in units of n (where n is a positive integer) horizontal lines; generating a first timing pulse signal comprising pulses having a pulse width having a period corresponding to one horizontal line time; generating a second timing pulse signal based on the polarity control signal by changing the rise time relative to each pulse in the first timing pulse signal; and outputting a data voltage having a polarity corresponding to each of the plurality of horizontal lines to the display panel based on the second timing pulse signal.

[0007] The embodiment also relates to a source driver, including: control logic configured to receive a polarity control signal representing the polarity corresponding to each of a plurality of horizontal lines on a display panel and having a value inverted in units of n (where n is a positive integer) horizontal lines, and configured to generate a timing pulse signal sequentially representing the data charging time of each of the plurality of horizontal lines; and a buffer configured to output a data voltage to the display panel based on the timing pulse signal. The control logic may be configured to generate a timing pulse signal including a data charging time corresponding to a count value obtained by counting the number of horizontal lines after the polarity is inverted when the value of the polarity control signal is inverted. Attached Figure Description

[0008] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, wherein:

[0009] Figure 1 This is a block diagram illustrating a display device according to an example embodiment;

[0010] Figure 2 This is a block diagram illustrating the configuration of the source driver according to an example embodiment;

[0011] Figure 3 This is a schematic diagram illustrating an example embodiment of driving a display panel based on a line inversion scheme;

[0012] Figure 4 It shows based on Figure 3 A schematic diagram of the waveforms of various signals in the line reversal scheme;

[0013] Figure 5 This is a schematic diagram illustrating an example embodiment of driving a display panel based on a line inversion scheme;

[0014] Figure 6 It shows based on Figure 5 A schematic diagram of the waveforms of various signals in the line reversal scheme;

[0015] Figure 7 This is a block diagram illustrating a detailed configuration of the source driver according to an example embodiment;

[0016] Figure 8 It is shown by Figure 7 A schematic diagram of the waveforms of various signals generated by the source driver;

[0017] Figure 9 This is a schematic diagram illustrating a delay schedule according to an example embodiment;

[0018] Figure 10 This is a schematic diagram illustrating the operation of a gate driver employing a line-inverting scheme;

[0019] Figure 11 This is a schematic diagram illustrating grouped data according to an example embodiment;

[0020] Figure 12 This is a schematic diagram illustrating the waveforms of grouped data and various signals according to an example embodiment;

[0021] Figure 13 This is a flowchart illustrating an operation method of a source driver according to an example embodiment;

[0022] Figure 14 This is a flowchart illustrating a method for generating a timing pulse signal according to an example embodiment;

[0023] Figure 15 An example of a display device according to an exemplary embodiment is shown; and

[0024] Figure 16 An example of a display device according to an example embodiment is shown. Detailed Implementation

[0025] Figure 1 This is a block diagram illustrating a display device 1000 according to an example embodiment.

[0026] refer to Figure 1The display device 1000 may include a display panel 1200 for displaying images and a display driving circuit 1100. The display device 1000 according to the example embodiment may be equipped in an electronic device with image display capabilities. For example, the electronic device may include a smartphone, a personal computer (PC), a portable multimedia player (PMP), a camera, a wearable device, a television (TV), a digital video disk (DVD) player, a refrigerator, an air conditioner, an air purifier, a set-top box, a robot, a drone, various medical devices, navigation devices, a global positioning system (GPS) receiver, vehicle equipment, furniture, or various measuring devices.

[0027] Display panel 1200 may include display units for displaying real images, and may also include display devices for receiving image signals electrically transmitted thereto to display two-dimensional (2D) images, such as organic light-emitting diode (OLED) displays, thin-film transistor-liquid crystal displays (TFT-LCDs), field emission displays, and plasma display panels (PDPs). However, embodiments are not limited thereto, and display panel 1200 may be implemented as different types of flat panel displays or flexible display panels.

[0028] The display panel 1200 may include a plurality of gate lines GL1 to GLn (where n is an integer of 2 or greater), a plurality of data lines DL1 to DLm (where m is an integer of 2 or greater) arranged along a direction intersecting the plurality of gate lines GL1 to GLn, and a plurality of pixels PX respectively disposed in a plurality of regions defined by the intersection of the gate lines GL1 to GLn and the data lines DL1 to DLm.

[0029] For example, when the display panel 1200 is a TFT-LCD, each pixel in pixel PX may include a thin-film transistor (TFT), a liquid crystal capacitor connected to the drain of the TFT, and a storage capacitor. The TFT includes a gate and a source connected to its corresponding gate line and data line, respectively. Furthermore, when a gate line is selected from multiple gate lines GL1 to GLn, the TFT of the pixel PX connected to the selected gate line can be turned on, and then the source driver 200 can apply a data voltage to multiple data lines DL1 to DLm. The data voltage can be applied to the liquid crystal capacitor and storage capacitor via the TFT of the corresponding pixel PX, and the liquid crystal capacitor and storage capacitor can be driven by the data voltage, thereby enabling image display.

[0030] The display panel 1200 may include multiple horizontal lines (or rows), and each horizontal line may be configured with pixels PX connected to a corresponding gate line. For example, pixels PX connected to the first row of the first gate line GL1 may be configured as the first horizontal line, and pixels PX connected to the second row of the second gate line GL2 may be configured as the second horizontal line.

[0031] A pixel PX of a horizontal line can be driven within one horizontal line time, and a pixel PX of another horizontal line can be driven within the next horizontal line time. For example, during the first horizontal line time, a pixel PX corresponding to the first gate line GL1 can be driven, and then during the second horizontal line time, a pixel PX corresponding to the second gate line GL2 can be driven. In this way, pixels PX of the display panel 1200 can be driven from the first to the nth horizontal line time.

[0032] The display driving circuit 1100 may include a timing controller 100, a source driver 200, a gate driver 300, and a voltage generator 400. The display driving circuit 1100 can convert image data I_DATA received from the outside into multiple analog signals (e.g., multiple data voltages) for driving the display panel 1200, and can provide the multiple analog signals to the display panel 1200.

[0033] The timing controller 100 can control all operations of the display driving circuit 1100. For example, the timing controller 100 can control the components of the display driving circuit 1100 (e.g., the source driver 200 and the gate driver 300) so that the display panel 1200 displays an image corresponding to the image data I_DATA received from the outside.

[0034] Specifically, the timing controller 100 can generate pixel data RGB_DATA (which has a format converted based on the interface specification of the source driver 200) based on the received image data I_DATA, and can output the pixel data RGB_DATA to the source driver 200. Furthermore, the timing controller 100 can generate various control signals CTRL1 and CTRL2 for timing the source driver 200 and the gate driver 300. The timing controller 100 can output a first control signal CTRL1 to the source driver 200 and a second control signal CTRL2 to the gate driver 300. The first control signal CTRL1 may include a polarity control signal, and the second control signal CTRL2 may include a gate timing signal.

[0035] The source driver 200 can convert pixel data RGB_DATA received from the timing controller 100 into multiple image signals (e.g., multiple data voltages), and can output multiple data voltages to the display panel 1200 through multiple data lines DL1 to DLm.

[0036] Specifically, the source driver 200 can receive pixel data in units of horizontal lines (i.e., in units of data corresponding to multiple pixels PX included in a horizontal line of the display panel 1200). Furthermore, the source driver 200 can convert the pixel data RGB_DATA received from the timing controller 100 into multiple data voltages based on multiple grayscale voltages VG[1:a] (also called gamma voltages) received from the voltage generator 400. Additionally, the source driver 200 can output multiple data voltages to the display panel 1200 in units of horizontal lines via multiple data lines DL1 to DLm. For example, the source driver 200 can output multiple data voltages corresponding to multiple pixels PX included in a first horizontal line of the display panel 1200, and then output multiple data voltages corresponding to multiple pixels PX included in a second horizontal line.

[0037] The gate driver 300 can be connected to multiple gate lines GL1 to GLn of the display panel 1200 and can sequentially drive the multiple gate lines GL1 to GLn of the display panel 1200. Based on the control of the timing controller 100, the gate driver 300 can sequentially provide multiple gate turn-on signals with valid levels (e.g., logic high levels) to the multiple gate lines GL1 to GLn. Therefore, multiple gate lines GL1 to GLn can be sequentially selected, and multiple data voltages can be applied to the pixels PX of the horizontal lines corresponding to the selected gate lines via multiple data lines DL1 to DLm.

[0038] The voltage generator 400 can generate various voltages for driving the display device 1000. For example, the voltage generator 400 can receive a source voltage from an external source. Furthermore, the voltage generator 400 can generate multiple grayscale voltages VG[1:a] and a common voltage VCOM, and can output these multiple grayscale voltages VG[1:a] and the common voltage VCOM to the source driver 200. Additionally, the voltage generator 400 can generate a gate on-state voltage VON and a gate off-state voltage VOFF, and can output these two voltages to the gate driver 300.

[0039] The configuration of the display driving circuit 1100 according to the example embodiment may include additional components. For example, the display driving circuit 110 may be implemented to include a memory (not shown) that stores received image data I_DATA in units of frames.

[0040] Figure 2 This is a block diagram illustrating the configuration of the source driver 200 according to an example embodiment. Specifically, Figure 2 It is shown Figure 1 A block diagram of the configuration of the source driver 200.

[0041] refer to Figure 1 and Figure 2 The source driver 200 may include control logic 240, latch unit 210, decoder 220, and buffer 230. The source driver 200 may be implemented as a semiconductor chip. Alternatively, the functionality of the source driver 200 may be implemented in a semiconductor device such as a system-on-a-chip.

[0042] The source driver 200 can be based on m data lines DL1 to DLm, comprising m channels, and can output data voltages Y1 to Ym for driving the display panel 1200 through the m channels. The data voltages Y1 to Ym can be signals provided to drive pixels PX connected to a gate line of the display panel 1200, and the data voltages Y1 to Ym can be output to the m gate lines GL1 to GLm, thereby realizing one frame in the display panel 1200.

[0043] The latch unit 210 can receive and latch multiple pixel data D1 to Dm used to drive the display panel 1200. The pixel data D1 to Dm can be from... Figure 1 The timing controller 100 provides pixel data RGB_DATA. The latch unit 210 can receive and store multiple pixel data D1 to Dm, and can output the stored pixel data D1 to Dm in parallel to the decoder 220.

[0044] Decoder 220 can decode pixel data D1 to Dm corresponding to digital signals into analog voltages. Decoder 220 may include multiple decoders (not shown) corresponding to the number of channels of source driver 200, and the corresponding pixel data and multiple grayscale voltages VG[1:a] can be provided to the multiple decoders respectively. Multiple grayscale voltages VG[1:a] can be received from voltage generator 400. Decoder 220 can decode pixel data D1 to Dm, and can select and output a grayscale voltage from the multiple grayscale voltages VG[1:a].

[0045] For example, when each pixel data in pixel data D1 to Dm consists of k bits (where k is an integer of 1 or greater) and multiple grayscale voltages VG[1:a] include 2k grayscale voltages, each decoder can decode k bits of data to select and output a grayscale voltage.

[0046] The voltage generated by voltage generator 400 can be referred to as reference grayscale voltage VG[1:a], and the voltage selected by decoder 220 based on each of the m channels can be referred to as grayscale voltage V1 to Vm.

[0047] The grayscale voltages V1 to Vm output from decoder 220 can be provided as data voltages Y1 to Ym to data lines DL1 to DLm via buffer 230. Buffer 230 can receive and buffer the grayscale voltages V1 to Vm to generate data voltages Y1 to Ym for driving data lines DL1 to DLm. Based on m channels, buffer 230 can include m output buffers.

[0048] Control logic 240 can provide timing pulses TP, representing the output timing of buffer 230, to buffer 230 based on the control of timing controller 100. Buffer 230 can output data voltages Y1 to Ym in horizontal line units based on the timing pulse signal TP.

[0049] The timing pulse signal TP may include multiple pulses representing the output timing of the data voltage corresponding to each of the multiple horizontal lines of the display panel 1200. The output timing may be the time it takes for the pulse to transition from a first level (e.g., logic high) to a second level (e.g., logic low), or it may be the time it takes for the pulse to transition from a second level to a first level. The timing pulse signal TP may be implemented as a pulse comprising one horizontal line time unit, but the embodiments are not limited thereto.

[0050] When the display panel 1200 is a liquid crystal display panel, the liquid crystal may degrade when data voltages of the same polarity are continuously applied to the display panel 1200. Therefore, a polarity inversion scheme that changes the polarity of the data voltage at a certain cycle can be applied to the display device 1000 to prevent quality degradation. The polarity inversion scheme may include changing the polarity of the data voltage based on a cycle corresponding to one or more scan units. The polarity inversion scheme may include a frame inversion scheme, a line inversion scheme, a column inversion scheme, a dot inversion scheme, and a mixed inversion scheme based on scan units.

[0051] An example embodiment in which a line reversal scheme based on changing the polarity on a unit of at least one horizontal line will now be described.

[0052] In an example embodiment, the source driver 200 can operate based on a line-reversal scheme according to the polarity control signal POL of the first control signal CTRL1 received from the timing controller 100. The polarity control signal POL can be a signal with a value (or state) that is reversed in units of n horizontal lines (or every n horizontal lines) (e.g., reversed from high to low, or from low to high). The source driver 200 can change the polarity of the data voltage based on the polarity control signal POL in units of n horizontal lines (or every n horizontal lines), and can provide a polarity-reversed data voltage to the display panel 1200.

[0053] When driving based on a polarity reversal scheme, a charge-sharing operation can be performed to temporarily share the charge of data lines DL1 to DLm whenever the polarity changes. For example, a charge-sharing operation can be performed when the data voltage of the horizontal line corresponding to the positive polarity is output and then the polarity changes to negative, or when the data voltage of the horizontal line corresponding to the negative polarity is output and then the polarity changes to positive. For example, the charge-sharing operation can be performed within the horizontal line time corresponding to the first horizontal line after the polarity change.

[0054] The charge-sharing operation may include connecting data lines DL1 to DLm and charging them with a common voltage VCOM (i.e., the charge-sharing voltage), and then disconnecting the data lines DL1 to DLm; while the charge-sharing operation is being performed, the output of each of the data voltages Y1 to Ym can be stopped. Therefore, when the source driver 200 is implemented to output data voltages on a horizontal line in units of horizontal line time, all charge-sharing operations and data output operations can be performed on the first horizontal line within the horizontal line time after the polarity change.

[0055] Therefore, in the horizontal lines where charge sharing operation is performed, data voltages Y1 to Ym can only be output to the corresponding horizontal lines for the time excluding the time for performing charge sharing operation (i.e., charge sharing time). This may reduce the output time of data voltages Y1 to Ym, and thus, the pixel PX of the corresponding horizontal line may not be fully charged. To provide sufficient charging, the source driver 200 according to the example embodiment can generate a timing pulse signal TP based on the polarity control signal POL, wherein the data charging time for each horizontal line is sufficiently guaranteed. This will be referred to below. Figures 3 to 6 Detailed description.

[0056] Figure 3 This illustrates an example embodiment of a display panel 1200 driven by a line inversion scheme, and Figure 4 It shows based on Figure 3 A schematic diagram of the waveforms of various signals in the line reversal scheme.

[0057] Figure 3 This is a schematic diagram illustrating an example embodiment, wherein the display panel 1200 is driven based on a 2-line inversion scheme that reverses the polarity of the data voltage in units of two horizontal lines. Figure 3 For ease of description, an example of a display panel 1200 including eight data lines DL1 to DL8, eight gate lines GL1 to GL8, and sixty-four pixels will now be described.

[0058] refer to Figure 3 Pixels positioned on a vertical line can be driven by alternating positive and negative data voltages between every two horizontal lines. For example, to drive pixels corresponding to odd-numbered data lines DL1, DL3, DL5, and DL7, positive data voltages can be provided to pixels connected to the first gate line GL1, the second gate line GL2, the fifth gate line GL5, and the sixth gate line GL6, while negative data voltages can be provided to pixels connected to the third gate line GL3, the fourth gate line GL4, the seventh gate line GL7, and the eighth gate line GL8. Similarly, to drive pixels corresponding to even-numbered data lines DL2, DL4, DL6, and DL8, negative data voltages can be provided to pixels connected to the first gate line GL1, the second gate line GL2, the fifth gate line GL5, and the sixth gate line GL6, while positive data voltages can be provided to pixels connected to the third gate line GL3, the fourth gate line GL4, the seventh gate line GL7, and the eighth gate line GL8.

[0059] exist Figure 3The example shows that a pixel PX positioned in a horizontal line can be driven by alternating positive and negative data voltages between every two horizontal lines. However, the embodiment is not limited to this, and a pixel PX positioned in a horizontal line can be driven with data voltages of the same polarity.

[0060] Figure 4 The waveforms of various signals associated with the example embodiment are shown, wherein the data voltage Yn of the nth channel of the source driver 200 is based on Figure 3 The line inversion scheme is provided to the display panel 1200. For ease of description, an example of applying the same pixel data to the source driver 200 will now be described below.

[0061] refer to Figure 4 The source driver 200 (specifically, control logic 240) can generate a first timing pulse signal TP1, which periodically has pulses with a certain pulse width. For example, the first timing pulse signal TP1 can have a horizontal time T. H The pulse is repeated in units, where the first level (e.g., a logic high level) can represent the charge-sharing time T. CS And the second level (e.g., logic low) can represent the data charging time T. DC During charge sharing time T CS The data cable can be charged using the common voltage VCOM. The common voltage VCOM can be used with the positive data voltage V. DD(H) and negative data voltage V DD(L) The intermediate voltage level HALF V DD However, according to the embodiments, the common voltage VCOM can have different levels.

[0062] When the display panel 1200 is driven using a line inversion scheme based on the first timing pulse signal TP1, the first horizontal line ( Figure 4 The Nth and N+2th horizontal lines, after a polarity change, can only be used during the data charging time T reduced by the charge-sharing operation. DC The internal data voltage Yn is used for charging, therefore the target voltage (e.g., V) may not be reached. DD(L) or V DD(H) Therefore, the source driver 200 can generate a second timing pulse TP2 based on the first timing pulse signal TP1 and the polarity control signal POL, where the data charging time is sufficient.

[0063] Specifically, the source driver 200 can receive a polarity control signal POL, which has a value that is inverted in units of two horizontal lines. Based on the polarity control signal POL, the source driver 200 can check the first horizontal line (e.g., the Nth horizontal line and the (N+2)th horizontal line) after the polarity change, and can delay the pulse corresponding to the second horizontal line (e.g., the (N+1)th horizontal line and the (N+3)th horizontal line by a delay time t. TP_DELAY1 This increases the data charging time of the first horizontal line in the first timing pulse signal TP1, thereby generating the second timing pulse signal TP2.

[0064] Delay time t TP_DELAY1 This can be the time added to the data charging time so that the horizontal line that has already performed charge sharing operation is fully charged by the target data voltage. In the example embodiment, the delay time t TP_DELAY1 Data can be derived from common voltage VCOM or HALF V based on the data voltage. DD Charged to positive data voltage V DD(H) (or negative data voltage V) DD(L) The time is determined by, for example, when the data voltage is from the common voltage VCOM or HALF V. DD Charged to positive data voltage V DD(H) (or negative data voltage V) DD(L) Given that the time is t1, and the data charging time of the first horizontal line after the polarity change in the current first timing pulse signal TP1 is t2, the delay time t TP_DELAY1 It can be determined as t1-t2. Regarding the delay time t... TP_DELAY1 The information can be received from the timing controller 100 or stored in the memory of the source driver 200.

[0065] The source driver 200 can generate a second timing pulse signal TP2 so as not to change the total time (i.e., 2T) allocated to the horizontal lines with the same polarity (e.g., the Nth to N+1th horizontal lines or the N+2th to N+3th horizontal lines). H Therefore, in the first timing pulse signal TP1 and the second timing pulse signal TP2, the total time allocated to the positive horizontal line and the total time allocated to the negative horizontal line can be the same.

[0066] As mentioned above, since the total time allocated to the horizontal lines with the same polarity is the same, and the pulse of the second horizontal line after the polarity change is delayed, the data charging time of the second horizontal line can be shortened to the time of the delay.

[0067] The source driver 200 can output a data voltage Yn based on a second timing pulse signal TP2. Specifically, refer to... Figure 4The source driver 200 can, based on the order of the Nth horizontal line (which is the first horizontal line after polarity change), perform a charge sharing operation at the time T corresponding to the pulse of the Nth horizontal line. CS Internal charge sharing operation (see) Figure 4 ① in the middle.

[0068] When the charge sharing operation is complete, the source driver 200 can output the data voltage Yn of the Nth horizontal line during the data charging time up to the pulse of the N+1th horizontal line (see [link]). Figure 4 (② in the middle).

[0069] The source driver 200 can be in time T corresponding to the pulse of the (N+1)th horizontal line. CS Internal high-impedance (Hi-Z) operation (see [link]) Figure 4 (③) Since the charge sharing operation has already been performed on the Nth horizontal line with the same polarity as the N+1th horizontal line, the charge sharing operation can be omitted. The high impedance operation can be an operation in which the display panel 1200 maintains the previous charge level by turning off the switch that connects the source driver 200 to the display panel 1200.

[0070] When the high-impedance operation is complete, the source driver 200 can output the data voltage Yn of the N+1 horizontal line during the data charging time up to the pulse before the N+2 horizontal line (see [reference]). Figure 4 (④ in the middle)

[0071] According to the above example embodiment, the source driver 200 can be implemented at time T corresponding to the pulse of the (N+1)th horizontal line. CS Instead of high-impedance operation, the source driver 200 performs an output operation on the data voltage Yn. Therefore, the source driver 200 can output the data voltage Yn within the horizontal time of the (N+1)th horizontal line.

[0072] Based on the order of each of the N+2 and N+3 horizontal lines after the polarity change, the operation of the source driver 200 can be substantially the same as the operation based on the order of each of the N and N+1 horizontal lines, except for the change in the polarity of the data voltage.

[0073] Figure 5 This is a schematic diagram illustrating an example embodiment of a display panel 1200 driven by a line inversion scheme, and Figure 6 It shows based on Figure 5 A schematic diagram of the waveforms of various signals in the line reversal scheme.

[0074] Figure 5This is a schematic diagram illustrating an example embodiment, wherein the display panel 1200 is driven based on a 4-line inversion scheme that reverses the polarity of the data voltage in units of four horizontal lines. Figure 5 For ease of description, an example of a display panel 1200 including eight data lines DL1 to DL8, eight gate lines GL1 to GL8, and sixty-four pixels will now be described.

[0075] refer to Figure 5 Pixels positioned along a vertical line can be driven by alternating positive and negative data voltages across every four horizontal lines. For example, to drive pixels corresponding to odd-numbered data lines DL1, DL3, DL5, and DL7, positive data voltages can be provided to pixels connected to the first gate line GL1, the second gate line GL2, the third gate line GL3, and the fourth gate line GL4, while negative data voltages can be provided to pixels connected to the fifth gate line GL5, the sixth gate line GL6, the seventh gate line GL7, and the eighth gate line GL8. Similarly, to drive pixels corresponding to even-numbered data lines DL2, DL4, DL6, and DL8, negative data voltages can be provided to pixels connected to the first gate line GL1, the second gate line GL2, the third gate line GL3, and the fourth gate line GL4, while positive data voltages can be provided to pixels connected to the fifth gate line GL5, the sixth gate line GL6, the seventh gate line GL7, and the eighth gate line GL8.

[0076] exist Figure 5 The example shows that a pixel PX positioned in a horizontal line can be driven by alternating positive and negative data voltages in every four horizontal lines. However, the embodiment is not limited to this, and a pixel PX positioned in a horizontal line can be driven with data voltages of the same polarity.

[0077] Figure 6 The waveforms of various signals associated with the embodiments are shown, wherein the data voltage Yn of the nth channel of the source driver 200 is based on Figure 5 The line reversal scheme is provided to the display panel 1200. Figure 6 In, with Figure 4 Descriptions that are identical or similar to those in the original text can be omitted.

[0078] refer to Figure 6 The source driver 200 (specifically, control logic 240) can generate a first timing pulse signal TP1, which periodically has pulses with a certain pulse width. For example, the first timing pulse signal TP1 can have a horizontal time T. H The pulses are repeated in units, and the first level (e.g., a logic high level) can represent the charge sharing time T. CSAnd the second level (e.g., logic low) can represent the data charging time T. DC During charge sharing time T CS The data cable can be charged using a common voltage VCOM, and the common voltage VCOM can be used with a positive data voltage V. DD(H) and negative data voltage V DD(L) The intermediate voltage level HALF V DD .

[0079] Furthermore, the source driver 200 can receive a polarity control signal POL, which has a value that is inverted in units of four horizontal lines. Based on the polarity control signal POL, the source driver 200 can check the first horizontal line (e.g., the Nth horizontal line) after the polarity change and delay the pulse corresponding to the second horizontal line (e.g., the N+1th horizontal line) by a first delay time t. TP_DELAY1 The pulse corresponding to the third horizontal line (e.g., the N+2th horizontal line) is delayed by a second delay time t. TP_DELAY2 And the pulse corresponding to the fourth level (e.g., the N+3rd level) will be delayed by a third delay time t. TP_DELAY3 This increases the data charging time of the first horizontal line in the first timing pulse signal TP1, thereby generating the second timing pulse signal TP2.

[0080] In example embodiments, such as Figure 6 As shown, the first delay time t TP_DELAY1 Second delay time t TP_DELAY2 and the third delay time t TP_DELAY3 It can be based on the first delay time t TP_DELAY1 Second delay time t TP_DELAY2 and the third delay time t TP_DELAY3 The order decreases. In another example embodiment, the first delay time t TP_DELAY1 Second delay time t TP_DELAY2 and the third delay time t TP_DELAY3 It can be based on the first delay time t TP_DELAY1 Second delay time t TP_DELAY2 and the third delay time t TP_DELAY3 The order increases. In another example embodiment, the first delay time t... TP_DELAY1 Second delay time t TP_DELAY2 and the third delay time t TP_DELAY3 At least some of the delay times can be the same. Regarding the first delay time t... TP_DELAY1 Second delay time t TP_DELAY2 and the third delay time t TP_DELAY3 The information can be received from the timing controller 100 or stored in the memory of the source driver 200.

[0081] The source driver 200 can generate a second timing pulse signal TP2 so as not to change the total time (i.e., 4T) allocated to the horizontal lines with the same polarity (e.g., the Nth to the N+3rd horizontal lines). H Therefore, in the first timing pulse signal TP1 and the second timing pulse signal TP2, the total time allocated to the positive horizontal line and the total time allocated to the negative horizontal line can be the same.

[0082] As described above, because the total time allocated to the horizontal lines with the same polarity is the same, and the pulses of the second to fourth horizontal lines after the polarity change are delayed, the data charging time of the second to fourth horizontal lines can be shortened to the delayed time. However, the embodiment is not limited to this, and the second timing pulse signal TP2 can be generated by delaying only the pulses of some of the second to fourth horizontal lines.

[0083] The source driver 200 can output a data voltage Yn based on a second timing pulse signal TP2. Specifically, refer to... Figure 6 The source driver 200 can, based on the sequence of the Nth horizontal line as the first horizontal line after polarity change, perform a charge sharing time T corresponding to the pulse of the Nth horizontal line. CS Internal charge sharing operation (see) Figure 6 ① in the middle.

[0084] When the charge sharing operation is complete, the source driver 200 can output the data voltage Yn of the Nth horizontal line during the data charging time up to the pulse of the N+1th horizontal line (see [link]). Figure 6 (② in the middle).

[0085] The source driver 200 can be in time T corresponding to the pulse of the (N+1)th horizontal line. CS Internal high-impedance (Hi-Z) operation (see Figure 6 (③) Since the charge sharing operation has already been performed on the Nth horizontal line with the same polarity as the N+1th horizontal line, the charge sharing operation can be omitted.

[0086] When the high-impedance operation is complete, the source driver 200 can output the data voltage Yn of the N+1 horizontal line during the data charging time up to the pulse before the N+2 horizontal line (see [reference]). Figure 6 (④ in the middle)

[0087] The source driver 200 can be in time T corresponding to the pulse of the (N+2)th horizontal line. CS Internal high-impedance (Hi-Z) operation (see Figure 6 (⑤ in the middle).

[0088] When high-impedance (Hi-Z) operation is complete, the source driver 200 can output the data voltage Yn of the N+2 level during the data charging time up to the pulse of the N+3 level (see [reference]). Figure 6 (⑥ in the text)

[0089] The source driver 200 can be in time T corresponding to the pulse of the (N+3)th horizontal line. CS Internal high-impedance (Hi-Z) operation (see Figure 6 (⑦).

[0090] When the high-impedance operation is complete, the source driver 200 can output the data voltage Yn of the N+3 level during the data charging time up to the pulse of the N+4 level (see [reference]). Figure 6 (⑧ in the middle)

[0091] According to an example embodiment, the source driver 200 can be at time T corresponding to the pulses of the (N+1)th horizontal line, the pulse of the (N+2)th horizontal line, and the pulse of the (N+3)th horizontal line. CS Instead of high-impedance operation, the source driver 200 performs an output operation on the data voltage Yn. Therefore, the source driver 200 can output the data voltage Yn at the horizontal time of each of the N+1, N+2, and N+3 horizontal lines.

[0092] As referenced above Figures 3 to 6 The example embodiment can use a timing pulse signal, wherein the output timing of some horizontal lines with the same polarity is delayed within the total time allocated to horizontal lines with the same polarity. Therefore, the source driver 200 according to the example embodiment can adequately perform the charging of the data voltage for each horizontal line without increasing the time used to display a frame of image signal on the display panel 1200.

[0093] Figure 7 This is a block diagram illustrating a detailed configuration of the source driver 200 according to an example embodiment. Figure 8 It is shown by Figure 7 A schematic diagram of the waveforms of various signals generated by the source driver 200. Figure 9 This is a schematic diagram illustrating the Delay Time Schedule (DTT) according to an example embodiment. Specifically, Figure 9 It is shown Figure 7 A schematic diagram of an example of a Delay Time Schedule (DTT).

[0094] In this example embodiment, for ease of description, an example of a source driver 200 based on a 2-wire inversion scheme will now be described.

[0095] refer to Figure 7The control logic 240 may include polarity comparison logic 241, line counter 243, and line start control logic 240.

[0096] Polarity comparison logic 241 can receive a polarity control signal POL from timing controller 100 and can generate a polarity comparison signal C_POL based on the polarity control signal POL. Furthermore, polarity comparison logic 241 can provide the generated polarity comparison signal C_POL to line counter 243. The polarity comparison signal C_POL can represent a comparison result obtained by comparing the polarity of the current horizontal line (e.g., the Nth horizontal line) with the polarity of a previous horizontal line (e.g., the (N-1)th horizontal line). For example, when the polarity of the current horizontal line is different from the polarity of the previous horizontal line, the polarity comparison signal C_POL can have a first level (e.g., logic high), and when the polarity of the current horizontal line is the same as the polarity of the previous horizontal line, the polarity comparison signal C_POL can have a second level (e.g., logic low). Therefore, when the polarity comparison signal C_POL transitions from the second level to the first level, this can indicate a change in polarity in the corresponding horizontal line.

[0097] The polarity comparison logic 241 can generate a reset signal RST based on the polarity comparison signal C_POL, and can provide the generated reset signal RST to the line counter 243. For example, the rising edge of the polarity comparison signal C_POL can be sensed, so the polarity comparison logic 241 can generate a reset signal RST with an active level. Therefore, the reset signal RST can have an active level associated with the horizontal line of polarity change. For example, the reset signal RST can have an active level at each time corresponding to two horizontal lines in a 2-line inversion scheme, and can have an active level at each time corresponding to four horizontal lines in a 4-line inversion scheme.

[0098] The line counter 243 can count the number of horizontal lines to generate... Figure 8 The line counter 243 can increment the count value of the count signal CNT when a rising or falling edge of the polarity comparison signal C_POL is sensed. The line counter 243 can provide the count signal CNT to the line start control logic 240.

[0099] The line counter 243 can reset the counting signal CNT based on the reset signal RST received from the polarity comparison logic 241. For example, the line counter 243 can reset the counting signal CNT when the reset signal RST has an active level. The reset signal RST can have an active level associated with a polarity-changing horizontal line, so the counting signal CNT can be reset at each polarity-changing horizontal line.

[0100] The line start control logic 240 can generate the first timing pulse signal TP1. Figure 8 The first timing pulse signal TP1 can be synchronized with Figure 4 The first timing pulse signal TP1 is the same, therefore, its repeated description is omitted.

[0101] The line start control logic 240 can generate a second timing pulse signal TP2 based on the first timing pulse signal TP1 and the counting signal CNT. For example, when the counting signal CNT has a reset value ( Figure 8 When the horizontal line starts (0), the line start control logic 240 can determine that the corresponding horizontal line is the first horizontal line after the polarity change, and can delay the horizontal line immediately following the corresponding horizontal line (i.e., the second horizontal line) in the first timing pulse signal TP1. Figure 8 The delay time t in TP_DELAY1 The line start control logic 240 can provide the second timing pulse signal TP2 to the buffer 230 to generate the second timing pulse signal TP2.

[0102] The buffer 230 can output data voltages Y1 to Ym to the display panel 1200 based on the second timing pulse signal TP2.

[0103] Refer again Figure 7 In the example embodiment, the line start control logic 240 may receive information DI about the delay time from the timing controller 100. The information DI about the delay time may include an index corresponding to a specific delay time.

[0104] In the example embodiment, a Delay Time Schedule (DTT) including matching information about multiple indices and multiple delay times is used (see...). Figure 9 Then the line start control logic 240 can check the delay time corresponding to the index included in the information DI about the delay time. Figure 8 t TP_DELAY1 Furthermore, the pulse delay can be adjusted by the checked delay time to generate a second timing pulse signal TP2.

[0105] In another example embodiment, the line start control logic 240 may not receive information about the delay time from the timing controller 100, but may instead generate a second timing pulse signal TP2 from the delay time value stored in the line start control logic 240 or an external memory.

[0106] refer to Figure 9The Delay Time Schedule (DTT) can include matching information about an index and a delay time. The index can consist of 3 bits, and the corresponding delay time value can vary based on whether the level of each bit constituting the index is logic high (H) or logic low (L). Based on the index value, the Delay Time Schedule (DTT) can include a delay time of approximately 0.0 μs to approximately 2.8 μs, but this is merely an example, and embodiments are not limited thereto.

[0107] In an example embodiment, the timing controller 100 may determine a specific index based on at least one of the following: scanning units according to the line reversal scheme (e.g., two horizontal lines or four horizontal lines), information about image data I_DATA, and various information about the display device 1000. Furthermore, the timing controller 100 may add the determined index to information DI about the delay time, and may provide the indexed information DI to the line start control logic 240.

[0108] Although relative to Figure 9 The index is described as consisting of 3 bits, but the embodiments are not limited to this. For example, the index may consist of more or fewer than 3 bits.

[0109] Furthermore, although relative to Figure 9 The source driver 200 is described as including a latency timetable DTT, but the embodiments are not limited thereto. For example, the source driver 200 may be implemented to include a separate latency timetable DTT determined by the frame rate of the display device 1000.

[0110] Figure 10 This is a schematic diagram illustrating the operation of a gate driver 300 employing a line-inverting scheme. Specifically, Figure 10 Multiple gate-on signals VON1 to VONn are shown, each corresponding to a gate line GL1 to GLn of the display panel 1200.

[0111] In this example embodiment, for ease of description, an example of a gate driver 300 based on a 2-wire inversion scheme will be described.

[0112] refer to Figure 10 The gate driver 300 can provide each of the gate turn-on signals VON1 to VONn to the corresponding gate line among the gate lines GL1 to GLn based on the second control signal CTRL2 received from the timing controller 100. Each gate line among GL1 to GLn can be turned on at the time when the corresponding gate turn-on signal among the gate turn-on signals VON1 to VONn transitions to an active level. Typically, the gate driver 300 can drive the gate lines GL1 to GLn sequentially, so that the gate turn-on signals VON1 to VONn can sequentially have active levels.

[0113] According to an example embodiment, the gate driver 300 can drive gate lines GL1 to GLn based on the data voltage output time of the source driver 200. Specifically, the source driver 200 can output a data voltage based on a timing pulse signal, wherein the output timing of some horizontal lines with the same polarity is delayed within the time allocated to the horizontal lines with the same polarity. Therefore, the gate driver 300 can generate gate turn-on signals VON1 to VONn based on the timing pulse signal.

[0114] Therefore, when the source driver 200 outputs a data voltage at a period corresponding to the horizontal line time (i.e., when using the first timing pulse signal TP1), the gate driver 300 can generate gate turn-on signals VON1 to VONn, wherein the gate turn-on signals VON1 to VONn have an effective level sequentially at a specific time interval. However, when the source driver 200 delays the output timing of each horizontal line other than the first horizontal line among the horizontal lines with the same polarity (i.e., when using the second timing pulse signal TP2), the gate driver 300 can delay the time when the effective level of the gate turn-on signal of the gate line corresponding to the other horizontal lines appears.

[0115] For example, such as Figure 10 As shown, when applying the 2-wire inversion scheme, the effective level of the gate turn-on signal VON2 of the second gate line GL2 (among the first gate line GL1 and the second gate line GL2 having the same polarity (e.g., positive polarity)) can be delayed. Furthermore, the effective level of the gate turn-on signal VON4 of the fourth gate line GL4 (among the third gate line GL3 and the fourth gate line GL4 having the same polarity (e.g., negative polarity)) can be delayed.

[0116] As another example (not shown), when the 4-line inversion scheme is applied, the effective level of each of the gate turn-on signals VON2 to VON4 of the second gate line GL2 to the fourth gate line GL4 (among the first gate line GL1 to the fourth gate line GL4 with the same polarity) can be delayed.

[0117] Figure 11 This is a schematic diagram illustrating grouped data according to an example embodiment. Figure 12 This is a schematic diagram illustrating the waveforms of grouped data and various signals according to an example embodiment.

[0118] refer to Figure 11Multiple data packets PD1 and PD2 can represent data provided to the source driver 200 by the timing controller 100. The multiple data packets PD1 and PD2 can include a horizontal blank period (HBP) and a horizontal active period (HAP), and can be distributed per horizontal time (T). H The units repeatedly include time periods HBP and HAP.

[0119] The horizontal blank period HBP can be a period during which the timing controller 100 does not apply pixel data RGB_DATA to the source driver 200, and can be, for example, a period allocated to ensure that the source driver 200 is used for driving the display panel 1200 based on the pixel data RGB_DATA. The horizontal active period HAP can be a period that includes the first control signal CTRL1 and the pixel data RGB_DATA. However, embodiments are not limited to this, and multiple packets of data PD1 and PD2 can include additional periods (e.g., row start times representing the start of a row).

[0120] The source driver 200 can drive the display panel 1200 during the horizontal active period (HAP), so the end of the data charging time for each horizontal line (or the rising edge of the pulse for the next horizontal line) can be included in the horizontal blank period (HBP). According to the example embodiment, the source driver 200 can use a timing pulse signal in which the output timing of some horizontal lines (except for the first horizontal line after the polarity change) of the same polarity is delayed. Therefore, the end of the data charging time for a certain horizontal line (or the rising edge of the pulse for the next horizontal line) may not occur in the horizontal blank period (HBP). Therefore, when the horizontal blank period (HBP) is relatively short (e.g., ...), ... Figure 11 The data in the grouped data (PD1) may not be included in the horizontal blank period HBP at the end of the data charging time of each horizontal line (or the rising edge of the pulse of the next horizontal line).

[0121] refer to Figure 12 As can be seen, the end of the data charging time for the Nth horizontal line (or the rising edge of the pulse for the N+1th horizontal line) is included in the horizontal active period HAP of the grouped data PD1. Therefore, the driving of the display panel 1200 may not be actively executed by the source driver 200.

[0122] Therefore, from Figure 11 As can be seen from the grouped data PD2, the ratio of HBP during the horizontal blank period can be adjusted to increase the horizontal time T. H Specifically, grouped data PD2 can reduce the horizontal effective period (HAP) and increase the horizontal blank period (HBP) without changing the total horizontal time T. HIn this scenario, because data transmission must be completed within the horizontally active period (HAP), the operating frequency of the interface between the timing controller 100 and the source driver 200 may increase. (Reference) Figure 12 As can be seen, the end of the data charging time for the Nth horizontal line (or the rising edge of the pulse for the N+1th horizontal line) is included in the horizontal blank period HBP of the grouped data PD2. Therefore, the driving of the display panel 1200 can be actively executed by the source driver 200.

[0123] Figure 13 This is a flowchart illustrating the operation method of the source driver 200 according to an example embodiment. Figure 13 The operation method can be provided by Figure 1 , 2 And the source driver 200 of 7 is used to execute.

[0124] refer to Figure 13 In operation S100, the source driver 200 can receive a polarity control signal. Specifically, the source driver 200 can operate based on a line reversal scheme that changes polarity in units of at least one horizontal line, and can receive a polarity control signal from the timing controller 100. The polarity control signal can be a signal with a value that reverses in units of n horizontal lines.

[0125] When the value of the polarity control signal is inverted, in operation S200, the source driver 200 can generate a timing pulse signal that includes a data charging time, which corresponds to a count value obtained by counting the number of horizontal lines after the inversion is performed. Specifically, the source driver 200 can increment the count value each time a horizontal line time has elapsed after the value of the polarity control signal is inverted. The source driver 200 can generate a timing pulse signal that includes a data charging time, which corresponds to the count value of each of the n horizontal lines.

[0126] In an example embodiment, the source driver 200 can check the data charging time corresponding to the count value of the current horizontal line among multiple data charging times, and can determine the checked data charging time as the data charging time of the current horizontal line. In this case, the data charging time corresponding to the minimum count value among the multiple data charging times can be the longest. For example, after the value of the polarity control signal is reversed, the count value of the first horizontal line can be 0, and the count value of the second horizontal line can be 1. In this case, the data charging time corresponding to the first horizontal line can be longer than the data charging time corresponding to the second horizontal line. Furthermore, the longest data charging time can be from the data voltage at the intermediate level (at the positive data voltage V). DD(H) and negative data voltage V DD(L) (Between) charging to positive data voltage VDD(H) Level or negative data voltage V DD(L) The time of the level.

[0127] In operation S300, the source driver 200 can output a data voltage based on a generated timing pulse signal. Specifically, the source driver 200 can alternately provide k (where k is an integer of 1 or greater) positive data voltages and k negative data voltages to the display panel 1200 based on the timing pulse signal. In an example embodiment, the source driver 200 can output a data voltage in response to the falling edge of each pulse included in the timing pulse, and can stop the output of the data voltage in response to the rising edge of each pulse in the timing pulse.

[0128] Figure 14 This is a flowchart illustrating a method for generating a timing pulse signal according to an example embodiment. Specifically, Figure 14 It is shown Figure 13 A flowchart detailing the operation of S200.

[0129] refer to Figure 14 In operation S210, the source driver 200 can generate a polarity comparison signal based on the polarity control signal. Specifically, the source driver 200 can compare the polarity of the current horizontal line with the polarity of the previous horizontal line to generate the polarity comparison signal. In an example embodiment, when the polarity of the previous horizontal line is different from the polarity of the current horizontal line, the polarity comparison signal can be generated to have a first level (e.g., a logic high level), and when the polarity of the previous horizontal line is the same as the polarity of the current horizontal line, the polarity comparison signal can be generated to have a second level (e.g., a logic low level). The source driver 200 can generate a reset signal based on the polarity comparison signal. The reset signal can have an effective level associated with the horizontal line whose polarity has changed.

[0130] In operation S220, the source driver 200 can count the number of horizontal lines based on the polarity comparison signal. Specifically, when the rising and falling edges of the polarity comparison signal are sensed, the source driver 200 can increment the count value of the counting signal. When the reset signal has an active level, the count value of the counting signal can be reset.

[0131] In operation S230, the source driver 200 can generate a first timing pulse signal, which includes pulses with a certain pulse width in units of horizontal line time.

[0132] In operation S240, the source driver 200 can check the first horizontal line among the horizontal lines corresponding to the same polarity based on the count value. Specifically, the source driver 200 can check the time period in the first timing pulse signal corresponding to n consecutive horizontal lines, wherein the n consecutive horizontal lines have data voltages with the same polarity.

[0133] In operation S250, the source driver 200 can delay the pulses of at least one horizontal line corresponding to the same polarity in the first timing pulse signal based on a count value to generate a second timing pulse signal, and the source driver 200 can output a data voltage from the second timing pulse signal. Specifically, the source driver 200 can delay the rise time of the pulse of at least one of the n horizontal lines during the check period to generate the second timing pulse signal. In an example embodiment, the source driver 200 can delay the rise time of the pulse of each of the n horizontal lines other than the first horizontal line to generate the second timing pulse signal. One period of the second timing pulse signal (i.e., the pulse with an effective level) can correspond to a charge-sharing operation or a high-impedance operation, and another period of the second timing pulse signal (i.e., different from the effective level) can correspond to the data voltage output operation (i.e., the data charging time). Therefore, the data charging time of the first horizontal line can be increased.

[0134] The time used to delay the horizontal line pulse (i.e., the delay time) can be determined based on the time it takes for the data voltage to charge from the charge-sharing voltage to the positive data voltage (or negative data voltage). When applying a line reversal scheme based on units corresponding to three or more horizontal lines, the delay time for each of the other horizontal lines can be set individually. Information about the delay time can be received from the timing controller 100 or stored in the source driver 200 or external memory.

[0135] Figure 15 An example of a display device 2000 according to an example embodiment is shown. Figure 15 The display device 2000 may include a device containing a medium or large display panel 2200, and may be applied, for example, to a television (TV), a monitor, etc.

[0136] refer to Figure 15 The display device 2000 may include a source driver 2110, a timing controller 2120, a gate driver 2130, and a display panel 2200.

[0137] The timing controller 2120 may be configured with one or more source driver integrated circuits (SDICs) or modules. The timing controller 2120 may communicate with multiple source driver ICs (SDICs) and multiple gate driver ICs (GDICs).

[0138] The timing controller 2120 may be an integrated circuit (TCON IC) that can generate control signals for controlling the drive timing of each of the multiple source driver ICs SDIC and multiple gate driver ICs GDIC, and can provide control signals to the multiple source driver ICs SDIC and multiple gate driver ICs GDIC.

[0139] Source driver 2110 may include multiple source driver ICs SDIC. These multiple source driver ICs SDIC can be mounted on a circuit film (such as a tape carrier package (TCP), chip on film (COF), or flexible printed circuit (FPC)) and can be attached to the display panel 2200 using tape automatic bonding (TAB) or mounted in a non-display area of ​​the display panel 2200 using chip on glass (COG).

[0140] Gate driver 2130 may include multiple gate driver ICs (GDICs). These GDICs can be mounted on a circuit film and attached to the display panel 2200 using a TAB type, or mounted in a non-display area of ​​the display panel 2200 using a COG type. Alternatively, gate driver 2130 can be directly formed on the lower substrate of the display panel 2200 using a gate-driver-in-panel (GIP) type. Gate driver 2130 can be formed in a non-display area outside the pixel array forming pixels in the display panel 2200 and can be formed using the same thin-film transistor (TFT) process as the pixels.

[0141] As shown above (for reference) Figures 1 to 14The source driver 2110 can generate a timing pulse signal based on the polarity control signal, wherein the data charging time of each horizontal line of the display panel 2200 is sufficiently guaranteed, and a data voltage can be output to the display panel 2200. Therefore, the display panel 2200 can prevent the appearance of fine horizontal lines caused by different data voltage charging ratios of the horizontal lines, thereby improving image quality.

[0142] Figure 16 An example of a display device 3000 according to an example embodiment is shown. Figure 16 The display device 3000 may include a device containing a small-sized display panel 3200, and may be applied, for example, to mobile devices such as smartphones and tablet PCs.

[0143] refer to Figure 16 The display device 3000 may include a display driving circuit 3100 and a display panel 3200. The display driving circuit 3100 may be configured with one or more ICs and may be mounted on a circuit film (such as TCP, COF, or FPC). Furthermore, the display driving circuit 3100 may be attached to the display panel 3200 using a TAB type, or mounted on a non-display area (e.g., an area where no image is displayed) using a COG type.

[0144] The display driving circuit 3100 may include a source driver 3110 and a timing controller 3120, and may also include a gate driver (not shown). In an example embodiment, the gate driver may be mounted on the display panel 3200.

[0145] As referenced above Figures 1 to 14 The source driver 3110 can generate a timing pulse signal based on the polarity control signal, wherein the data charging time of each horizontal line of the display panel 3200 is sufficiently guaranteed, and a data voltage can be output to the display panel 3200. Therefore, the display panel 3200 can prevent the appearance of fine horizontal lines caused by different data voltage charging rates of the horizontal lines, thereby improving image quality.

[0146] By summarizing and reviewing, to prevent pixel degradation, a technique can be implemented to drive data lines using a polarity inversion scheme. Polarity inversion schemes can include frame inversion (inverting polarity on a frame-by-frame basis), line inversion (inverting polarity on a line-by-line basis), and pixel inversion (inverting polarity on a pixel-by-pixel basis).

[0147] As described above, the embodiments may provide a source driver, a display device including the source driver, and a method of operating the source driver, wherein the source driver determines the output timing of a data voltage corresponding to each of a plurality of horizontal lines on a display panel based on a polarity control signal.

[0148] The embodiment may provide a source driver, a display device including the source driver, and a method of operating the source driver, wherein the source driver generates a timing pulse signal based on a polarity control signal, representing the data charging time corresponding to each of a plurality of horizontal lines on the display panel.

[0149] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A display device, comprising: The display panel includes multiple horizontal lines, each of which contains multiple pixels; A source driver is configured to generate timing pulse signals that sequentially represent the data charging time of each of the plurality of horizontal lines, and is configured to output a data voltage having a polarity corresponding to each of the plurality of horizontal lines to the display panel based on the timing pulse signals. and A timing controller is configured to output a polarity control signal representing the polarity of a data voltage corresponding to each of the plurality of horizontal lines, the polarity control signal having a value that is inverted in units of n horizontal lines, where n is a positive integer. Based on the polarity control signal, a polarity comparison signal is generated. This polarity comparison signal represents a first level when the polarity of the previous horizontal line is different from the polarity of the current horizontal line, and represents a second level when the polarity of the previous horizontal line is the same as the polarity of the current horizontal line. For each horizontal time, the level of the polarity comparison signal is detected to generate a count signal representing the count value of the corresponding horizontal line, the count signal corresponding to the number of second levels detected for each horizontal time. as well as When the value of the polarity control signal is reversed, the source driver generates a reset signal with an effective level associated with the horizontal line of the polarity change based on the polarity comparison signal, resets the count value generated before the polarity control signal is reversed based on the reset signal, and generates a timing pulse signal representing the data charging time, which corresponds to the count value obtained by counting the number of horizontal lines after the polarity of the data voltage is reversed.

2. The display device according to claim 1, wherein: The data charging time includes multiple data charging times, and The longest data charging time among the multiple data charging times corresponds to the minimum count value.

3. The display device according to claim 2, wherein The longest data charging time includes the time it takes for the data voltage to charge from an intermediate voltage level to either a positive or negative data voltage level, where the intermediate voltage level is between the positive and negative data voltage levels.

4. The display device according to claim 1, wherein The timing pulse signal includes the data charging time of the n horizontal lines corresponding to the same polarity within a time period.

5. The display device according to claim 1, wherein The source driver is configured as follows: A reference timing pulse signal, which repeatedly includes a certain data charging time, is generated with a period corresponding to the time of a horizontal line. The timing pulse signal is generated by changing the charging time of n data in the reference timing pulse signal in units of n horizontal lines corresponding to the same polarity identified by the polarity control signal.

6. The display device of claim 5, wherein, The source driver is configured to generate the timing pulse signal by delaying the start point of the data charging time of at least one of the n horizontal lines in the reference timing pulse signal based on a delay time corresponding to the count value.

7. The display device of claim 6, wherein, The source driver is configured to generate the timing pulse signal by delaying the start point of the data charging time of each of the n horizontal lines, excluding the first horizontal line, in the reference timing pulse signal.

8. A method for driving a source driver, the method comprising: Receive a polarity control signal that represents the polarity corresponding to each of the multiple horizontal lines on the display panel, the polarity control signal having a value that is reversed in units of n horizontal lines, where n is a positive integer; Generate a first timing pulse signal, the first timing pulse signal comprising pulses having a certain pulse width with a period corresponding to the time of a horizontal line; Based on the polarity control signal, a second timing pulse signal is generated by changing the rise time of each pulse in the first timing pulse signal relative to the pulse in the first timing pulse signal; as well as Based on the second timing pulse signal, a data voltage with a polarity corresponding to each of the plurality of horizontal lines is output to the display panel. The generation of the second timing pulse signal includes: Based on the polarity control signal, a polarity comparison signal is generated. This polarity comparison signal represents a first level when the polarity of the previous horizontal line is different from the polarity of the current horizontal line, and represents a second level when the polarity of the previous horizontal line is the same as the polarity of the current horizontal line; and A count signal representing the count value of the corresponding horizontal line is generated by detecting the level of the polarity comparison signal at each horizontal line time, wherein the count signal corresponds to the number of second levels detected at each horizontal line time. When the value of the polarity control signal is inverted, a reset signal with an effective level associated with the horizontal line of the polarity change is generated based on the polarity comparison signal; and The reset signal resets the count value generated before the polarity control signal is reversed, and generates a second timing pulse signal representing the data charging time, which corresponds to the count value obtained by counting the number of horizontal lines after the polarity of the data voltage is reversed.

9. The driving method according to claim 8, wherein The generation of the second timing pulse signal also includes: Examine the time periods in the first timing pulse signal corresponding to n consecutive horizontal lines of data voltage with the same polarity; and The second timing pulse signal is generated by delaying the rise time of the pulse of at least one of the n horizontal lines in the inspected time period.

10. The driving method of claim 9, wherein, Generating the second timing pulse signal by delaying the rise time of the pulse of at least one of the n horizontal lines in the inspected time period includes generating the second timing pulse signal by delaying the rise time of the pulse of each of the n horizontal lines other than the first horizontal line.

11. The driving method according to claim 9, wherein, Generating the second timing pulse signal by delaying the rise time of the pulse of at least one of the n horizontal lines in the inspected time period includes delaying the rise time of the pulse by a delay time corresponding to a count value obtained by counting the number of horizontal lines in the inspected time period.

12. The driving method according to claim 11, wherein The delay time corresponding to the count value increases as the count value increases.

13. The driving method of claim 8, wherein, The output data voltage includes: In response to the falling edge of each pulse included in the second timing pulse signal, the data voltage is output; and The output of the data voltage is stopped in response to the rising edge of each pulse in the pulses included in the second timing pulse signal.

14. A source driver, comprising: The control logic is configured to receive a polarity control signal, which represents the polarity corresponding to each of the multiple horizontal lines on the display panel and has a value that is reversed in units of n horizontal lines, where n is a positive integer, and is configured to generate a timing pulse signal that sequentially represents the data charging time of each of the multiple horizontal lines. and A buffer is configured to output a data voltage to the display panel based on the timing pulse signal, wherein: The control logic is configured as follows: Based on the polarity control signal, a polarity comparison signal is generated. This polarity comparison signal represents a first level when the polarity of the previous horizontal line is different from the polarity of the current horizontal line, and represents a second level when the polarity of the previous horizontal line is the same as the polarity of the current horizontal line. For each horizontal time, the level of the polarity comparison signal is detected to generate a count signal representing the count value of the corresponding horizontal line, the count signal corresponding to the number of second levels detected for each horizontal time. as well as When the value of the polarity control signal is reversed, a reset signal with an effective level associated with the horizontal line of polarity change is generated based on the polarity comparison signal. The count value generated before the polarity control signal is reversed is reset based on the reset signal, and the timing pulse signal representing the data charging time is generated, which corresponds to the count value obtained by counting the number of horizontal lines after the polarity of the data voltage is reversed.

15. The source driver of claim 14, wherein, The control logic is configured to generate the timing pulse signal such that the data charging time of the first horizontal line among the n horizontal lines after the polarity is reversed is the longest data charging time.

16. The source driver of claim 15, wherein, The data charging time of the first horizontal line includes the time it takes for the data voltage to charge from an intermediate voltage level to a positive or negative data voltage, wherein the intermediate voltage level is between the positive and negative data voltages.

17. The source driver according to claim 14, wherein: The control logic is configured to generate a reference timing pulse signal that repeatedly includes a data charging time at a period corresponding to the time of a horizontal line. The control logic is configured to generate the timing pulse signal by delaying the start point of the data charging time of at least one of the n horizontal lines in the reference timing pulse signal based on the delay time corresponding to the count value.

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