Circuit Board

Abstract

The present application relates to a circuit board, which includes: at least one first circuit layer and at least one second circuit layer, wherein the first circuit layer and the second circuit layer are spaced apart in the vertical direction, and a gradient signal line is arranged on the first circuit layer; the second circuit layer includes a hollow area, and the position of the hollow area corresponds to the position of the gradient signal line on the adjacent first circuit layer. Since the hollow area is hollowed out according to the routing method of the gradient signal line on the first circuit layer, by increasing the thickness of the medium, a thicker line width can be designed on the first circuit layer to achieve the purpose of reducing signal loss. Accordingly, the impedance change in the area where the gradient line signal is located can be minimized by optimizing the hollow area to solve the problem of impedance discontinuity in the gradient line area, thereby improving the quality of signal transmission on the circuit.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a circuit board. Background Art

[0002] With the continuous development of electronic technology, especially the continuous development of high-speed signal technology, such as 32G two-level signal modulation technology (Non-Return-to-Zero, NRZ) and 56G four-level signal modulation technology (Pulse Amplitude Modulation, PAM4), the requirements for signal quality are getting higher and higher.

[0003] At present, for the routing of high-speed signal links, there is usually a problem that the routing length and routing path cannot be further optimized, which leads to large signal loss. In order to reduce signal loss, wider routing can be designed in local areas on the circuit board to reduce signal loss. However, the connector area or chip fan-out area on the circuit board is generally densely populated with vias, and the routing line width cannot be increased. These areas can only use thin lines to ensure routing fan-out, while wide lines can be used outside the connector or chip fan-out area (i.e., the Open Field area) to control the loss. In this process, a gradient line design will appear, and the gradient line appears as an impedance discontinuity point. When a signal with a fast rising edge encounters an impedance discontinuity, signal reflection, jitter and other phenomena that affect the signal quality will occur.

[0004] Based on this, how to increase the line width of the signal line while reducing the impedance discontinuity problem in the gradient line area has become a technical problem that needs to be solved urgently when laying out signal lines on current circuit boards. Summary of the invention

[0005] Based on this, it is necessary to provide a circuit board to address the above technical problems, and the routing and ground hole designs of each circuit layer of the circuit board are optimized to reduce the impedance discontinuity problem in the gradient line area on the circuit board.

[0006] In a first aspect, a circuit board comprises: at least one first circuit layer and at least one second circuit layer, the first circuit layer and the second circuit layer are arranged at intervals in a vertical direction, and a gradient signal line is arranged on the first circuit layer;

[0007] The second circuit layer includes a hollow area, and the position of the hollow area corresponds to the position of the gradient signal line on the adjacent first circuit layer.

[0008] In this embodiment, since the hollow area is hollowed out according to the routing method of the gradient signal line on the first circuit layer, by increasing the dielectric thickness, a thicker line width can be designed on the first circuit layer to achieve the purpose of reducing signal loss. Accordingly, the impedance change in the area where the gradient line signal is located can be minimized by optimizing the hollow area to solve the problem of discontinuous impedance in the gradient line area, thereby improving the quality of signal transmission on the circuit board.

[0009] In one of the embodiments, the circuit board further comprises a plurality of ground holes arranged around the gradient signal line, and the horizontal distance between each of the ground holes and the gradient signal line decreases as the width of the gradient signal line decreases.

[0010] In this embodiment, the influence of the ground hole on the impedance change in the area where the gradient signal line is located is taken into consideration, and the horizontal distance between the ground hole and the gradient signal line is designed to change with the width of the gradient signal line, so that the impedance discontinuity in the area where the gradient signal line is located can be reduced.

[0011] In one of the embodiments, the shortest distance between the center point of the ground hole and the edge line of the hollow area is less than a preset threshold.

[0012] In this embodiment, by arranging the ground hole at a position very close to the edge line of the hollow area, the influence of the ground hole on the impedance of the area where the gradient signal line is located can be reduced.

[0013] In one of the embodiments, the ground holes include first ground holes arranged in the two side areas where the width of the gradient signal line remains unchanged, and second ground holes arranged in the two side areas where the width of the gradient signal line changes; the distance between two adjacent first ground holes is greater than the distance between two adjacent second ground holes.

[0014] In this embodiment, the placement design of the ground holes is optimized so that the ground holes are arranged in an arc shape on the circuit board around the gradient signal line, which not only plays an isolation role and reduces the signal crosstalk between different gradient signal lines, but also can reduce the impedance change in the area where the gradient signal line is located, so as to solve the problem of discontinuous impedance in the area where the gradient signal line is located.

[0015] In one of the embodiments, the first circuit layer further includes at least one first plane board, and the first plane board is arranged between two adjacent gradient signal lines in the horizontal direction.

[0016] In this embodiment, by arranging the first plane plate between different gradient signal lines in the horizontal direction, signal crosstalk between different gradient signal lines in the horizontal direction can be reduced, thereby improving the quality of signal transmission on the circuit board.

[0017] In one embodiment, the position of the first plane plate on each of the first circuit layers corresponds to the position of the gradient signal line on the adjacent first circuit layer.

[0018] This embodiment realizes a circuit board structure in which gradient signal lines of different layers are staggered with the first plane board, so that gradient signal lines of the same layer are far apart in the horizontal direction, and gradient signal lines that are close in the vertical direction are located in different layers, so as to reduce crosstalk between gradient signal lines.

[0019] In one embodiment, the circuit board further includes a second plane board, and the second plane board is arranged between two adjacent second circuit layers.

[0020] In this embodiment, by arranging the second plane board between different second circuit layers in the vertical direction, signal crosstalk between different gradient signal lines in the vertical direction can be reduced, thereby improving the quality of signal transmission on the circuit board.

[0021] In one of the embodiments, the first circuit layer further includes at least one third plane board, and the third plane board is arranged between two adjacent gradient signal lines in the horizontal direction.

[0022] This embodiment can reduce signal crosstalk between different gradient signal lines in the horizontal direction and the vertical direction respectively by setting a third plane board between different gradient signal lines in the horizontal direction and setting a third plane board between different second circuit layers in the vertical direction, thereby improving the quality of signal transmission on the circuit board.

[0023] In one embodiment, the hollow area is U-shaped.

[0024] In this embodiment, the design of the hollow area can facilitate the routing of the relatively wide lines in the gradient signal line, thereby reducing the signal loss on the circuit board.

[0025] In one of the embodiments, the bottom of the U-shape is a three-fold line structure, and the shape of the three-fold line structure is compatible with the shape of the gradient signal line.

[0026] The hollowed-out area designed in this embodiment minimizes the impedance change in the area where the gradient signal line is located, thereby reducing impedance discontinuity. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic diagram of a circuit board in one embodiment;

[0028] Figure 2 is a schematic diagram of a gradually changing signal line in one embodiment;

[0029] Figure 3is a schematic diagram of a hollowed-out area in one embodiment;

[0030] Figure 4 is a schematic diagram of a hollowed-out area in one embodiment;

[0031] Figure 5 is a schematic diagram of a second circuit layer in one embodiment;

[0032] Figure 6 is a top plan view of a second circuit layer in one embodiment;

[0033] Figure 7 is a top plan view of a first circuit layer in one embodiment;

[0034] Figure 8 A top plan view of a first circuit layer and a second circuit layer superimposed in one embodiment;

[0035] Fig. 9 is a top view of the first plane in one embodiment;

[0036] Fig.10 is a schematic diagram of a circuit board in one embodiment;

[0037] Fig.11 is a schematic diagram of a circuit board in one embodiment;

[0038] Fig.12 A top-view plane in which the first plane, the first circuit layer, and the second circuit layer overlap in one embodiment;

[0039] Fig.13 is a schematic diagram of a circuit board in one embodiment;

[0040] Fig.14 is a schematic diagram of a circuit board in one embodiment;

[0041] Fig.15 is a schematic diagram of a circuit board in one embodiment;

[0042] Fig.16 is a schematic diagram of a circuit board in one embodiment;

[0043] Reference numerals:

[0044] Ground via 0, first circuit layer 1, second circuit layer 2;

[0045] A first ground hole 01, a second ground hole 02, and a gradient signal line 11;

[0046] A first plane plate 12, a second plane plate 13, and a third plane plate 14;

[0047] A hollow area 21, an area 211 where the bottom of the U-shape is located;

[0048] The upper part of the U-shape is located in an area 212, and the left edge line 213 of the hollow area;

[0049] The right edge line 213 of the hollow area. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0051] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0052] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0053] At present, when wiring on an existing circuit board, such as a printed circuit board (PCB), the routing length and routing path on the PCB can be optimized to reduce the loss. However, if the overall link loss on the PCB is close to the limit, the routing length and routing path cannot be further optimized, and a wider routing can be designed in a local area to reduce the loss. However, the connector area or the chip Fan-out area on the PCB has dense vias, and the routing line width cannot be increased. These areas select thin lines to ensure the routing fan-out, while thick lines can be selected outside the connector or chip fan-out area (Open Field area) to control the loss. Therefore, there is a design of a gradient signal line on the circuit board, and there will be a point of impedance discontinuity in the area where the gradient signal line is located. Then, in actual applications, when a signal with a fast rising edge encounters a point of impedance discontinuity, signal reflection, jitter, and signal quality problems will occur. For the existing gradient signal line area, little attention is paid to its impedance change. Even if attention is paid to its impedance change, there is no effective method to solve or reduce the discontinuity of impedance change, and the influence of the ground hole on the impedance of the gradient area is not considered. In the actual application of circuit boards, especially when the signal rate is high, the impedance discontinuity problem in the gradient area will greatly affect the signal quality, so how to optimize the impedance of the gradient area where the gradient signal line is located to reduce the impedance discontinuity is crucial. Based on the above problems, the present application designs a circuit board that can effectively solve the impedance discontinuity problem in the gradient area where the gradient signal line is located, and has extremely high signal transmission quality. The following embodiments will specifically illustrate the circuit board provided by the present application.

[0054] Figure 1 A schematic diagram of a circuit board provided in an embodiment, such as Figure 1 As shown, the circuit board includes: at least one first circuit layer 1 and at least one second circuit layer 2, the first circuit layer 1 and the second circuit layer 2 are arranged at intervals in the vertical direction, and the first circuit layer 1 is provided with a gradient signal line 11; the second circuit layer 2 includes a hollow area 21, and the position of the hollow area 21 corresponds to the position of the gradient signal line 11 on the adjacent first circuit layer 1.

[0055] Among them, the gradual change signal line 11 is a signal line whose width changes from wide to narrow (see Figure 2 The gradient signal line a) shown in FIG. 1 may also be a signal line whose width changes from narrow to wide (see FIG. Figure 2 The gradient signal line b shown in FIG. 1 ); the gradient signal line 11 can be a high-speed signal line or a low-speed signal line; the gradient signal line 11 can be a single signal line or a differential line pair (see FIG. 1 ). Figure 2 The gradient signal line c) is shown.

[0056] The first circuit layer 1 is provided with a plurality of connector areas, chip fan-out Fan-out areas and Open Field areas, and the connection area between the connector area or the chip fan-out Fan-out area and the Open Field area usually corresponds to the area where the gradient signal line is located, that is, the signal line with a relatively narrow width in the gradient signal line is in the connector area or the chip fan-out Fan-out area, and the signal line with a relatively wide width in the gradient signal line is in the Open Field area, for example, Figure 2 The narrower line segment in the gradient signal line 11 of a is in the connector area or the chip fan-out area. Figure 2 The width variation area and the line segment with a wider width in the gradient signal line 11 of a are in the Open Field area.

[0057] The shape of the hollow area 21 can be any shape, and the position of the hollow area 21 corresponds to the position of the gradient signal line 11 on the adjacent first circuit layer, for example, see Figure 1 The position of the gradient signal line 11 corresponds to the position of the hollow areas 21 of the two upper and lower adjacent second circuit layers 2, and the hollow areas 21 of the two upper and lower adjacent second circuit layers 2 are also the same in shape, size and position in the respective second circuit layers 2. The design of the hollow area can facilitate the routing of the relatively wide lines in the gradient signal line, thereby reducing the signal loss on the circuit board.

[0058] Optionally, the shape of the hollow area 21 may be U-shaped (such as Figure 3 The area 211 where the bottom of the U-shape is located corresponds to the width change area and a part of the narrow width area of ​​the gradient signal line 11, and the area 212 where the upper part of the U-shape is located corresponds to a part of the wide width area of ​​the gradient signal line 11. Optionally, the bottom of the U-shape is a three-fold line structure, and the shape of the three-fold line structure is adapted to the shape of the gradient signal line 11, that is, Figure 4 The shape of the hollow area 21 in the middle, the two sides of the gradient signal line 11 with a wider width correspond to the upper area of ​​the U-shape, and the gradient signal line 11 starts to fold inward at the turning point A where the gradient signal line 11 changes from wide to narrow, and finally goes straight at the point B where the gradient signal line is about to become narrow, forming a three-fold line structure. The hollow area designed in this way minimizes the impedance change in the area where the gradient signal line is located, thereby reducing impedance discontinuity. It should be noted that the shape of the three-fold line structure is compatible with the shape of the gradient signal line 11, and can represent the fold line in the three-fold line structure (for example Figure 4 The inclination (slope) of the line segment AB in the gradient signal line and the inclination ( Figure 4Such a design can minimize the impedance change in the area where the gradient signal line is located, greatly reducing impedance discontinuity.

[0059] In this embodiment, when routing on the circuit board, the position of the gradient signal line can be first determined on each first circuit layer on the circuit board, and when routing the gradient signal line at the position, the medium at the corresponding position on the adjacent second circuit layer in the vertical direction of the gradient signal line is correspondingly hollowed out. For example, the gradient signal line is defined from top to bottom in the vertical direction. Figure 1 The layers where the circuit layers of the circuit board are located, #1 layer, #2 layer, #3 layer, #4 layer, #5 layer, #6 layer, #7 layer, #8 layer, #9 layer, see Figure 1 At the position where the first gradient signal line 11 is located on the right side of the middle #3 layer, the corresponding medium of the second circuit layer 2 of the upper and lower adjacent #2 layer and the corresponding medium of the second circuit layer 2 of the #4 layer are hollowed out to form two hollow areas 21 on the upper and lower #2 layers and #4 layers, and a structure in which the first circuit layer 1 and the second circuit layer 2 are spaced apart is formed.

[0060] It should be noted that the above Figure 3 and Figure 4 The shape of the hollow area 21 is adapted to the gradient signal line 11, and the gradient signal line whose width changes from wide to narrow is used as an example for explanation. For other types of gradient signal lines, the adaptation method of the corresponding hollow area is similar, and it is not repeated here. In addition, a plurality of gradient signal lines are set on the first circuit board, and a plurality of hollow areas are set on the second circuit board. In the above embodiments, one gradient signal line and one hollow area are used for explanation. The characteristics of other gradient signal lines and hollow areas are the same, and they are not repeated here. Moreover, Figure 1 The structure of each circuit board containing two gradient signal lines or hollow areas is only given in the figure. The right side of the structure can be further derived to make each first circuit layer contain multiple gradient signal lines and each second circuit layer contain multiple hollow areas. Figure 1 , Fig.10 , Fig.11 , Fig.13 , Fig.14 , Fig.15 and Fig.16 )'s structure of each circuit layer can be extended in this way, and will not be repeated later.

[0061] The above-mentioned circuit board includes: at least one first circuit layer and at least one second circuit layer, wherein the first circuit layer and the second circuit layer are arranged at intervals in the vertical direction, and a gradient signal line is arranged on the first circuit layer; the second circuit layer includes a hollow area, and the position of the hollow area corresponds to the position of the gradient signal line on the adjacent first circuit layer. Since the hollow area is hollowed out according to the routing method of the gradient signal line on the first circuit layer, by increasing the thickness of the medium, a thicker line width can be designed on the first circuit layer to achieve the purpose of reducing signal loss. Accordingly, the impedance change in the area where the gradient line signal is located can be minimized by optimizing the hollow area to solve the problem of impedance discontinuity in the gradient line area, thereby improving the quality of signal transmission on the circuit class.

[0062] exist Figure 1 The circuit board shown in the embodiment optimizes the routing of the gradient signal line. The present application also provides an optimization design method for the ground hole on the circuit board, that is, Figure 1 The circuit board shown in the embodiment further includes a plurality of ground holes 0 arranged around the gradient signal line 11. The horizontal distance between each ground hole 0 and the gradient signal line 11 decreases as the width of the gradient signal line 11 becomes narrower (see Figure 5 As shown in the plan schematic diagram of the second circuit layer 2 superimposed on the first circuit layer 1, and the shortest distance between the center point of each ground hole 0 and the edge line of the hollow area 21 (the left edge line 213 of the hollow area or the right edge line 214 of the hollow area) is less than the preset threshold, the ground hole 0 includes a first ground hole 01 arranged in the two side areas where the width of the gradient signal line 11 remains unchanged, and a second ground hole 02 arranged in the two side areas where the width of the gradient signal line 11 changes; the distance between two adjacent first ground holes 01 is greater than the distance between two adjacent second ground holes 02.

[0063] The ground vias 0 in this embodiment are arranged on the first circuit layer 1 on both sides of the gradient signal line 11, and the distance between each two adjacent ground vias 0 can be set to any distance, usually set to 30mil or 40mil. The ground vias 0 are placed around the gradient signal line 11, which can reduce the crosstalk of the gradient signal line 11 to a certain extent. However, in the area where the gradient signal line is located, since the routing is no longer uniform, the ground vias 0 need to be placed in a certain way, such as Figure 5As shown, the placement of the ground holes 0 is optimized. Specifically, the ground holes 0 are placed in the two side areas of the gradient signal line 11. For example, three first ground holes 01 are placed in the two side areas where the width of the gradient signal line 11 remains unchanged, and are placed symmetrically, and two second ground holes 02 are placed in the two side areas where the width of the gradient signal line 11 changes, and are placed symmetrically. As the width of the gradient signal line 11 changes, the distance between adjacent ground holes 0 also changes with the width of the gradient signal line 11. Specifically, as the width of the gradient signal line 11 becomes narrower, the distance between two adjacent first ground holes 01 is the same, and the distance between two adjacent second ground holes 02 is the same, as shown in FIG. Figure 5 The distance between two adjacent first ground holes 01 is greater than the distance between two adjacent second ground holes 02. For example, the distance between each first ground hole 01 is 30 mil, and the distance between each second ground hole 02 is 20 mil. The above-mentioned optimization design of the placement of the ground holes takes into account the influence of the ground holes on the impedance change in the area where the gradient signal line is located, and by designing the horizontal distance between the ground hole and the gradient signal line to change with the width of the gradient signal line, the impedance discontinuity in the area where the gradient signal line is located can be reduced.

[0064] In actual applications, the ground hole 0 is usually arranged near the edge line of the hollow area 21. For example, the distance between the first ground hole 01 on the left and the left edge line 213 of the hollow area 21 is less than the preset threshold, and the distance between the first ground hole 01 on the right and the right edge line 214 of the hollow area 21 is less than the preset threshold; the distance between the second ground hole 02 on the left and the left edge line 213 of the hollow area 21 is less than the preset threshold, and the distance between the second ground hole 02 on the right and the right edge line 214 of the hollow area 21 is less than the preset threshold. Among them, the preset threshold can be determined in advance according to the need for optimizing the ground hole. Generally, the preset threshold is very small, so that the first ground hole 01 on the left side of the first circuit layer 1 is very close to the left edge line 213 of the hollow area 21, and the first ground hole 01 on the right side is very close to the right edge line 214 of the hollow area 21; the second ground hole 02 on the left side of the first circuit layer 1 is very close to the left edge line 213 of the hollow area 21, and the second ground hole 02 on the right side is very close to the right edge line 214 of the hollow area 21, so as to isolate different gradient signal lines 11. In addition, by setting the ground hole at a position very close to the edge line of the hollow area, the impedance effect of the ground hole on the area where the gradient signal line is located can be reduced. Refer to the design effect diagram of the ground hole placed near the hollow area on the second circuit layer of the actual design circuit board, as shown in Figure 6 As shown, for example, the diagram can represent Figure 1The top plan view of the ground via on the second circuit layer of layer #2 on the circuit board in the figure is placed near the hollow area, and can also represent the top plan view of the ground via placed near the hollow area on any other layer, which is not limited here. In addition, you can also refer to the top plan view of the first circuit layer of the actual designed circuit board, such as Figure 7 As shown, the ground holes are placed on the first circuit board 1 around the gradient signal line. This figure can be expressed as Figure 1 A top view of the first circuit layer 1 of any of the layers #1, #5, and #9 on the circuit board. Furthermore, a top view of the second circuit layer of the actual designed circuit board superimposed on the first circuit layer can also be referred to, such as Figure 8 As shown, for example, the diagram can represent Figure 1 The top plan view of the second circuit layer 2 of layer #2 on the middle circuit board superimposed on the first circuit layer 1 of layer #1 may also represent a top plan view of the superposition of the other two circuit layers.

[0065] It should be noted that the above Figure 5 , Figure 6 , Figure 7 or Figure 8 The placement of the ground holes 0 (including 01 and 02) is adapted to the gradient signal line 11, and the gradient signal line of the differential routing type whose width changes from wide to narrow is used as an example for explanation. For other types of gradient signal lines, the placement method of the corresponding ground holes 0 is similar, and the description is not repeated here.

[0066] In the above embodiment, the placement design of the ground holes is optimized so that the ground holes are arranged in an arc shape on the circuit board around the gradient signal line, which not only plays an isolation role and reduces the signal crosstalk between different gradient signal lines, but also can reduce the impedance change in the area where the gradient signal line is located, so as to solve the problem of discontinuous impedance in the area where the gradient signal line is located.

[0067] The first circuit layer 1 in any of the above embodiments further includes at least one first plane plate 12 , and the first plane plate 12 is arranged between two adjacent gradient signal lines 11 in the horizontal direction.

[0068] The first plane plate 12 can be used as a reference plane for the gradient signal line 11. A ground hole 0 is provided on the first plane plate 12. Since the ground hole is opened in the stacking direction (vertical direction) of the circuit board, the placement design of the ground hole on the first plane plate 12 is the same as the placement design of the ground hole on the first circuit layer and the placement design of the ground hole on the second circuit board. Fig. 9 A top plan view of the first planar panel is shown.

[0069] The circuit board structure described in this embodiment is exemplified, for example, Fig.10The schematic diagram of the circuit board shown in the figure defines the layers where each circuit layer in the circuit board is located from top to bottom in the vertical direction, #1 layer, #2 layer, #3 layer, #4 layer, #5 layer, #6 layer, #7 layer, #8 layer, #9 layer, and the circuit layers in the middle of the circuit board are used for exemplary description. The first plane board 12 of the first circuit layer 1 on the #1 layer is arranged between two adjacent gradient signal lines 11 on the #1 layer, and the first plane board 12 of the first circuit layer 1 on the #5 layer is arranged between two adjacent gradient signal lines 11 on the #5 layer. Then, the gradient signal lines 11 corresponding to the two first plane boards 12 are on the first circuit layer 11 of the #3 layer. Therefore, the first plane board 12 of the first circuit layer 1 on the #3 layer is arranged between two adjacent gradient signal lines 11 on the #5 layer. The gradient signal line 11 on the circuit layer 11 uses the first plane board 12 of the #1 layer or the first plane board 12 of the #5 layer as a reference plane; accordingly, the first plane board 12 of the first circuit layer 1 on the #9 layer is arranged between two adjacent gradient signal lines 11 on the #9 layer, and the first plane board 12 of the first circuit layer 1 on the #5 layer is arranged between two adjacent gradient signal lines 11 on the #5 layer, and the gradient signal line 11 corresponding to these two first plane boards 12 is on the first circuit layer 11 of the #7 layer, therefore, the gradient signal line 11 on the first circuit layer 11 of the #7 layer uses the first plane board 12 of the #5 layer or the first plane board 12 of the #9 layer as a reference plane. In this embodiment, by arranging the first plane board between different gradient signal lines in the horizontal direction, the signal crosstalk between different gradient signal lines in the horizontal direction can be reduced, thereby improving the quality of signal transmission on the circuit board.

[0070] Optionally, based on the first plane board provided in the above embodiment, the structure of the circuit board can also be as follows: Fig.11 As shown, the first plane plate 12 is arranged between two adjacent gradient signal lines 11 in the horizontal direction, and the signal crosstalk between different gradient signal lines 11 can also be reduced in the horizontal direction. The middle gradient signal line on the #3 layer can also use the first plane plate 12 of the #1 layer or the first plane plate 12 of the #5 layer as a reference plane; the middle gradient signal line on the #7 layer can also use the first plane plate 12 of the #5 layer or the first plane plate 12 of the #9 layer as a reference plane.

[0071] Optionally, the position of the first plane plate 12 on each first circuit layer 1 on the circuit board provided in the present application corresponds to the position 11 of the gradient signal line on the adjacent first circuit layer 1. Fig.10In the circuit board shown, for example, the position of the first plane board 12 on the #1 layer corresponds to the position of the gradient signal line 11 on the first circuit layer 1 of the adjacent #3 layer; the position of the first plane board 12 on the #5 layer corresponds to the position of the gradient signal line 11 on the first circuit layer 1 of the adjacent #3 layer, and corresponds to the position of the gradient signal line 11 on the first circuit layer 1 of the adjacent #7 layer; the position of the first plane board 12 on the #9 layer corresponds to the position of the gradient signal line 11 on the first circuit layer 1 of the adjacent #7 layer. Such a design constitutes a circuit board structure in which gradient signal lines and first plane boards of different layers are staggered, and realizes a design scheme of interlayer reference, so that gradient signal lines of the same layer are far apart in the horizontal direction, and gradient signal lines with close distance in the vertical direction are located in different layers, so as to reduce crosstalk between gradient signal lines.

[0072] In addition, when there is a first plane board, a top view of the first plane board superimposed with the second circuit layer and the first circuit layer can be referred to, such as Fig.12 As shown, the first plane board 12 is superimposed on the second circuit layer and the first circuit layer from top to bottom, for example, Fig.10 The first plane board 12 of layer #1 is superimposed on the second circuit layer 2 of layer #2 and the first circuit layer 1 of layer #3. The superposition method of other first plane boards is the same and will not be repeated here.

[0073] In one embodiment, a circuit board is designed, and the circuit board further includes a second plane board 13 . The second plane board 13 is disposed between two adjacent second circuit layers 2 .

[0074] The second plane plate 13 can be used as a reference plane for the gradient signal line 11. A ground hole 0 is provided on the second plane plate 13. Since the ground hole is opened in the stacking direction (vertical direction) of the circuit board, the placement design of the ground hole on the second plane plate 13 is the same as the placement design of the ground hole on the first circuit layer and the placement design of the ground hole on the second circuit board. Fig. 9 Schematic diagram of the first plane plate shown (the second plane plate 13 has the same structure as the first plane plate 12).

[0075] The circuit board structure described in this embodiment is exemplified, for example, Fig.13The schematic diagram of the circuit board shown in the figure defines the layers where each circuit layer in the circuit board is located from top to bottom in the vertical direction, namely, layer #1, layer #2, layer #3, layer #4, layer #5, layer #6, layer #7, layer #8, layer #9, layer #10, layer #11, layer #12, and layer #13. Each second plane board 13 of the first circuit layer 1 on layer #1 is arranged on the second circuit layer 2 of the adjacent layer #2; each second plane board 13 of the first circuit layer 1 on layer #5 is arranged between the second circuit layer 2 of the adjacent layer #4 and the second circuit layer 2 of the adjacent layer #6; each second plane board 13 of the first circuit layer 1 on layer #9 is arranged between the second circuit layer 2 of the adjacent layer #8 and the second circuit layer 2 of the adjacent layer #10; each second plane board 13 of the first circuit layer 1 on layer #13 is arranged under the second circuit layer 2 of the adjacent layer #12. Moreover, in this design structure, each gradient signal line can use the second plane board adjacent in the vertical direction as a reference plane, such as Fig.13 As shown, the gradient signal line 11 on the #3 layer uses the second plane board 13 of the #1 layer or the second plane board 13 of the #5 layer as a reference plane; the gradient signal line 11 on the #7 layer uses the second plane board 13 of the #5 layer or the second plane board 13 of the #9 layer as a reference plane; the gradient signal line 11 on the #11 layer uses the second plane board 13 of the #9 layer or the second plane board 13 of the #13 layer as a reference plane. In this embodiment, by arranging the second plane board between different second circuit layers in the vertical direction, the signal crosstalk between different gradient signal lines in the vertical direction can be reduced, thereby improving the quality of signal transmission on the circuit board.

[0076] In one embodiment, Fig.13 Based on the circuit board described in the embodiment, a circuit board is also designed, and the first circuit layer 1 in the circuit board also includes at least one third plane board 14, and the third plane board 14 is arranged between two adjacent gradient signal lines 11 in the horizontal direction.

[0077] Among them, the third plane plate 14 is provided with a ground hole, and because the ground hole is opened in the stacking direction (vertical direction) of the circuit board, the placement design of the ground hole on the third plane plate 14 is the same as the placement design of the ground hole on the first circuit layer and the placement design of the ground hole on the second circuit board, see Fig. 9 Schematic diagram of the first plane plate shown (the third plane plate 14 has the same structure as the first plane plate 12).

[0078] The circuit board structure described in this embodiment is exemplified, for example, Fig.14The schematic diagram of the circuit board shown in the figure defines the layers where the circuit layers in the circuit board are located from top to bottom in the vertical direction, layer #1, layer #2, layer #3, layer #4, layer #5, layer #6, layer #7, layer #8, layer #9, layer #10, layer #11, layer #12, and layer #13. In the horizontal direction, the third plane board 14 of the first circuit layer 1 on layer #3 is arranged between two adjacent gradient signal lines 11 on the same layer; the third plane board 14 of the first circuit layer 1 on layer #7 is arranged between two adjacent gradient signal lines 11 on the same layer; the third plane board 14 of the first circuit layer 1 on layer #11 is arranged between two adjacent gradient signal lines 11 on the same layer; The third plane board 14 of a circuit layer 1 is arranged between two adjacent gradient signal lines 11 on the same layer; accordingly, in the vertical direction, the second plane board 13 is arranged on the first circuit layer 1 on the #1, #5, #9 and #13 layers respectively; in this embodiment, by arranging the third plane board between different gradient signal lines in the horizontal direction and arranging the second plane board between different second circuit layers in the vertical direction, the signal crosstalk between different gradient signal lines in the horizontal direction and the vertical direction can be reduced respectively, thereby improving the quality of signal transmission on the circuit board.

[0079] Optional, in Fig.14 Based on the circuit board described in the embodiment, a circuit board is also designed, such as Fig.15 As shown, the position of the third plane board 14 on each first circuit layer 1 in the circuit board corresponds to the position of the gradient signal line 11 on the adjacent first circuit layer 1 .

[0080] like Fig.15 In the circuit board shown, for example, the position of the third plane board 14 on the #3 layer corresponds to the position of the gradient signal line 11 on the first circuit layer 1 of the adjacent #7 layer; the position of a third plane board 14 on the #7 layer corresponds to the position of the gradient signal line 11 on the first circuit layer 1 of the adjacent #11 layer, and the position of another third plane board 14 on the #7 layer corresponds to the position of the gradient signal line 11 on the first circuit layer 1 of the adjacent #11 layer. Such a design constitutes a circuit board structure in which gradient signal lines and third plane boards of different layers are staggered, and realizes a design scheme of interlayer reference, so that gradient signal lines of the same layer are far apart in the horizontal direction, and gradient signal lines with close distance in the vertical direction are located in different layers, so as to reduce crosstalk between gradient signal lines.

[0081] In one embodiment, Fig.13 Based on the circuit board described in the embodiment, a circuit board is also designed, such as Fig.16 As shown, the second circuit layer 2 in the circuit board further includes at least one third plane plate 14, and the third plane plate 14 is arranged between two adjacent hollow areas 21 on the second circuit layer 2 in the horizontal direction.

[0082] The third plane plate 14 can be used as a reference plane for the gradient signal line 11 adjacent to it in the vertical direction. A ground hole is provided on the third plane plate 14. Since the ground hole is opened in the stacking direction (vertical direction) of the circuit board, the placement design of the ground hole on the third plane plate 14 is the same as the placement design of the ground hole on the first circuit layer and the placement design of the ground hole on the second circuit board. Fig. 9 Schematic diagram of the first plane plate shown (the third plane plate 14 has the same structure as the first plane plate 12).

[0083] The circuit board structure described in this embodiment is exemplified, for example, Fig.16 The schematic diagram of the circuit board shown in the figure defines the layers where each circuit layer in the circuit board is located from top to bottom in the vertical direction, #1 layer, #2 layer, #3 layer, #4 layer, #5 layer, #6 layer, #7 layer, #8 layer, #9 layer, #10 layer, #11 layer, #12 layer, #13 layer. In the horizontal direction, the third plane plate 14 of the second circuit layer 2 on the #2 layer is arranged between two adjacent hollow areas 21 on the same layer; the third plane plate 14 of the second circuit layer 2 on the #6 layer is arranged between two adjacent hollow areas 21 on the same layer; the third plane plate 14 of the second circuit layer 2 on the #10 layer is arranged between two adjacent hollow areas 21 on the same layer; The third plane board 14 of the second circuit layer 2 is arranged between two adjacent hollow areas 21 on the same layer; correspondingly, in the vertical direction, the second plane board 13 is arranged on the first circuit layer 1 on the #1, #5, #9 and #13 layers respectively; in this embodiment, by arranging the third plane board between different hollow areas in the horizontal direction and arranging the second plane board between different second circuit layers in the vertical direction, the signal crosstalk between different gradient signal lines in the horizontal direction and the vertical direction can be reduced respectively, thereby improving the quality of signal transmission on the circuit board.

[0084] Those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by this application. In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0085] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

[0086] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A circuit board, characterized in that: The circuit board comprises: at least one first circuit layer and at least one second circuit layer, the first circuit layer and the second circuit layer are arranged at intervals in the vertical direction, and a gradient signal line is arranged on the first circuit layer; the gradient signal line comprises a differential line pair; the first circuit layer further comprises at least one first plane board, the first plane board is arranged between two adjacent gradient signal lines in the horizontal direction; the circuit board further comprises a second plane board, the second plane board is arranged between two adjacent second circuit layers; the first circuit layer further comprises at least one third plane board, the third plane board is arranged between two adjacent gradient signal lines in the horizontal direction; the second circuit layer further comprises at least one third plane board, the third plane board is arranged between two adjacent hollow areas on the second circuit layer in the horizontal direction; The second circuit layer includes a hollow area, and the position of the hollow area corresponds to the position of the gradient signal line on the adjacent first circuit layer; The circuit board also includes a plurality of ground holes arranged around the gradient signal line, and the horizontal distance between each of the ground holes and the gradient signal line decreases as the width of the gradient signal line becomes narrower; the shortest distance between the center point of each of the ground holes and the edge line of the hollow area is less than a preset threshold, and the shape formed by each of the ground holes is the same as the shape of the edge line of the hollow area.

2. The circuit board according to claim 1, characterized in that: The ground holes include first ground holes arranged in the two side areas where the width of the gradient signal line remains unchanged, and second ground holes arranged in the two side areas where the width of the gradient signal line changes; the distance between two adjacent first ground holes is greater than the distance between two adjacent second ground holes.

3. The circuit board according to claim 2, characterized in that: The distance between two adjacent first ground holes is the same, and the distance between two adjacent second ground holes is the same.

4. The circuit board according to any one of claims 1 to 3, characterized in that: The ground holes are arranged in an arc shape on the circuit board around the gradient signal line.

5. The circuit board according to any one of claims 1 to 3, characterized in that: The gradient signal line on the first circuit layer uses a first plane plate which is two layers away from the first circuit layer as a reference plane.

6. The circuit board according to any one of claims 1 to 3, characterized in that: The position of the first plane plate on each of the first circuit layers corresponds to the position of the gradient signal line on the adjacent first circuit layer.

7. The circuit board according to any one of claims 1 to 3, characterized in that: The second plane plate is a reference plane for the gradient signal line.

8. The circuit board according to any one of claims 1 to 3, characterized in that: The position of the third plane board on each of the first circuit layers corresponds to the position of the gradient signal line on the adjacent first circuit layer.

9. The circuit board according to claim 1, characterized in that: The shape of the hollow area is U-shaped.

10. The circuit board according to claim 9, characterized in that: The bottom of the U-shape is a three-fold line structure, and the shape of the three-fold line structure is compatible with the shape of the gradient signal line.

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