Non-volatile memory with virtual ground circuitry

Abstract

A memory includes virtual ground circuitry configured to generate a virtual ground voltage (greater than zero volts) at a virtual ground node; a memory array of resistive memory cells, each resistive memory cell in the memory array including a select transistor and a resistive storage element and coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a first set of column lines for a memory read operation from a selected set of the resistive memory cells. The memory includes read circuitry; and a first column line multiplexer configured to couple each selected first column line of the first set of column lines to the read circuitry during the memory read operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory read operation.

Description

Technical Field

[0001] This invention relates to non-volatile memory, and more particularly, to non-volatile memory having a virtual grounding circuit system. Background Technology

[0002] This application relates to U.S. Patent Application Serial No. 17 / 032537 (Attorney No. 82250770US01), filed on the same date and assigned to the assignee of this invention, entitled “Non-Volatile Memory Having Virtual GroundCircuitry”.

[0003] Non-volatile memory is used to store data in electronic systems, including storing data in the electronic system when the system is powered off. One type of non-volatile memory is resistive memory, in which each bit cell of the resistive memory includes a resistive storage element that is in a high-resistance state (HRS) or a low-resistance state (LRS) depending on the logic state of the bit cell. In some embodiments, for a write operation of a bit cell of the resistive memory, a write current is provided in a first direction through the resistive storage element to place it in the HRS, and a write current is provided in a second opposite direction through the resistive storage element to place it in the LRS. Summary of the Invention

[0004] In one embodiment, a memory includes a virtual grounding circuit system coupled to a first power supply terminal and a second power supply terminal and configured to generate a virtual grounding voltage at a virtual grounding node, wherein the first power supply terminal is configured to provide a first power supply voltage and the second power supply terminal is configured to provide a second power supply voltage less than the first power supply voltage, wherein the virtual grounding voltage is greater than zero volts and lies between the first power supply voltage and the second power supply voltage; and a memory array of resistive memory cells, each resistive memory cell in the memory array including a selection transistor and a resistive storage element for storing a value, wherein each resistive memory cell is coupled to a plurality of first... The memory array comprises: a first column line; a first decoder configured to select a first column line set from a plurality of first column lines for a memory read operation from a selected set of resistive memory cells coupled to the selected first column line set; a read circuitry configured to provide a read value stored in the selected set of resistive memory cells during a memory read operation; and a first column line multiplexer (MUX) configured to couple each selected first column line from the first column line set to the read circuitry during a memory read operation, and configured to couple each unselected first column line from the plurality of first column lines to a virtual ground node during a memory read operation. In one aspect, each resistive memory cell of the memory array is coupled to a second column line from a plurality of second column lines, and the memory further includes a second column line multiplexer (MUX) configured to couple each second column line from the plurality of second column lines to a virtual ground node during a memory read operation. In another aspect, the plurality of first column lines are characterized as one of source lines or bit lines, and the plurality of second column lines are characterized as another of source lines or bit lines. In another aspect of the above embodiments, the virtual grounding circuit system includes a flip-flop voltage follower circuit having a current source coupled in series with a source follower transistor and a sink transistor between a first power supply terminal and a second power supply terminal, wherein a first current electrode of the source follower transistor is coupled to the current source, and a second current electrode of the source follower transistor is coupled to the virtual grounding node. In another aspect, the first current electrode of the sink transistor is coupled to the virtual grounding node, the second current electrode of the sink transistor is coupled to the second power supply terminal, and the control electrode of the sink transistor is coupled to the first current electrode of the source follower transistor. In yet another aspect, the virtual grounding circuit system further includes an operational amplifier having an output configured to provide a replicated virtual grounding voltage; a transistor having a first current electrode, a control electrode, and a second current electrode, wherein the second current electrode of the transistor is coupled to the output of the operational amplifier, and the first current electrode of the transistor is coupled to the gate electrode of the transistor and to the gate electrode of the source follower transistor; and a second current source coupled between the first power supply terminal and the first current electrode of the transistor.In another aspect, the virtual grounding circuit system includes a current compensator coupled to a virtual ground node via a first enable switch, wherein the first enable switch is configured to conduct to couple the current compensator to the virtual ground node during a memory read operation. In yet another aspect, the current compensator includes a compensator current source coupled between the first enable switch and a second power supply terminal. In yet another aspect, the virtual grounding circuit system includes a source follower amplifier, wherein the transistors of the source follower amplifier have a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output of the amplifier of the source follower amplifier, and a second current electrode coupled to the virtual ground node. In yet another aspect of the above embodiments, the read circuit system includes a set of sense amplifiers, each sense amplifier having a first input coupled to a corresponding first column line in a selected first column line set and a second input coupled to a corresponding reference current path, and an output providing a bit value for a read value for a memory read operation. In another embodiment, the read circuitry further includes a first current source corresponding to a first input of each sense amplifier and a second current source corresponding to a second input of each sense amplifier, wherein during a memory read operation, the read circuitry is configured to provide read current from each first current source to a corresponding column line in a selected first column line set and to provide read current from each second current source to a corresponding reference current path. In yet another embodiment, during a memory read operation, the virtual ground circuitry is further configured to stabilize a virtual ground voltage at a virtual ground node within a series of reads. In yet another embodiment, each reference current path is coupled between a virtual ground node and a second input of the corresponding sense amplifier. In yet another embodiment, each of the first and second current sources is coupled between a first power supply terminal and the corresponding sense amplifier.

[0005] In another embodiment, in a memory having a first power supply terminal configured to provide a first power supply voltage, a second power supply terminal configured to provide a second power supply voltage less than the first power supply voltage, and a memory array in which each resistive memory cell is coupled to resistive cells of a plurality of first column lines, a method includes selecting a first set of first column lines from the plurality of first column lines for a memory read operation from the selected set of resistive memory cells coupled to the selected first column line set; and generating a virtual ground voltage at a virtual ground node, wherein the virtual ground voltage is greater than the second power supply voltage. The method further includes, during the read operation, coupling an unselected first column line from the plurality of first column lines to the virtual ground node; coupling each first column line from the selected first column line set to a first input of a corresponding sense amplifier among a plurality of sense amplifiers; coupling a corresponding reference current path to a second input of each sense amplifier among the plurality of sense amplifiers, wherein each corresponding reference current path is coupled between the virtual ground node and the corresponding sense amplifier among the plurality of sense amplifiers; and providing a read current to each first column line from the selected first column line set and to each corresponding reference current path. In one aspect, generating a dummy ground voltage is performed by a flip-flop voltage follower circuit, which includes a current source having a first terminal coupled to a first power supply; a source follower transistor having a first current electrode coupled to a second terminal of the current source and a second current electrode coupled to a dummy ground node; and a sink having a first current electrode coupled to a dummy ground node, a second current electrode coupled to a second power supply, and a control electrode coupled to the first current electrode of the source follower transistor. In another aspect, generating a dummy ground voltage is performed by a source follower amplifier coupled between a first power supply and a dummy ground node. In another aspect, during a read operation, the method further includes coupling a current source between the dummy ground node and a second power supply to remove charge from the dummy ground node. In another aspect, each resistive memory cell of the memory array is coupled to a second column of a plurality of second column lines, and the method further includes coupling each of the plurality of second column lines to a dummy ground node during a memory read operation. In another aspect, the plurality of first column lines are characterized as one of source lines or bit lines, and the plurality of second column lines are characterized as another of source lines or bit lines. Attached Figure Description

[0006] The invention is illustrated by way of example and is not limited to the drawings, in which similar reference numerals indicate similar elements. Elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0007] Figure 1 This is a circuit diagram of a non-volatile memory circuit according to an embodiment of the present invention.

[0008] Figure 2 This is according to an embodiment of the present invention. Figure 1 The circuit diagram of the source-line multiplexer for a non-volatile memory circuit.

[0009] Figure 3 This is according to an embodiment of the present invention. Figure 1 The circuit diagram of a bit-line multiplexer for a non-volatile memory circuit.

[0010] Figure 4 and 5 It is used according to an embodiment of the present invention. Figure 1 The circuit diagram of the virtual grounding (VG) circuit system.

[0011] Figure 6 This illustrates a reading operation according to an embodiment of the present invention. Figure 1 A circuit diagram of a portion of a non-volatile memory circuit.

[0012] Figure 7 This is a block diagram of the write circuit of a non-volatile memory circuit according to an embodiment of the present invention.

[0013] Figure 8 This is according to an embodiment of the present invention. Figure 7 The circuit diagram of the write drive circuit of the write circuit.

[0014] Figure 9 This is a circuit diagram illustrating the voltage applied to a node during a write operation to a memory cell according to an embodiment of the present invention.

[0015] Figure 10 This is a circuit diagram illustrating the voltage applied to a node during a write operation to a memory cell according to an embodiment of the present invention.

[0016] Figure 11 This is a circuit diagram illustrating a voltage applied to a node coupled to an unselected memory cell during memory operation according to an embodiment of the present invention.

[0017] Unless otherwise specified, the same reference symbols are used in different drawings to indicate the exact same object. The drawings are not necessarily drawn to scale. Detailed Implementation

[0018] The following is a detailed description of the modes used to carry out the invention. The description is intended to illustrate the invention and should not be considered limiting.

[0019] As disclosed herein, the memory includes a resistive memory cell array and a virtual ground generator that provides a virtual ground voltage applied as a source bias voltage to the column lines (e.g., source lines or bit lines) during read operations. By using a virtual ground instead of a true ground (where the virtual ground is greater than the true ground, i.e., greater than 0V), leakage current through unselected cells can be reduced. In one embodiment, the parasitic capacitance of the memory array attributable to unselected memory cells can provide stability to the virtual ground. In one embodiment, current compensation techniques are used in conjunction with the virtual ground to compensate for any charge transferred to the virtual ground. This allows the virtual ground to maintain its target level even after multiple consecutive reads.

[0020] As also disclosed herein, a virtual ground can be used during write operations to reduce time-dependent gate oxide breakdown (TDDB) stress within NVM circuitry, such as resistive memory circuitry. In one embodiment, during write operations, an attempt is made to reduce TDDB stress by applying a virtual ground level bias to all unselected source lines and all unselected bit lines instead of a true ground, potentially extending the endurance of the NVM circuitry.

[0021] Figure 1A circuit diagram of a non-volatile memory circuit 10 according to an embodiment of the present invention is shown. The memory circuit 10 includes an array 12 of non-volatile memory cells (e.g., 23-30), a controller 20, a row decoder 14, a column decoder 16, a read circuitry system 18, a virtual ground (VG) circuitry system 78, and a write circuitry system 150. In one embodiment, the memory cells of the array 12 are characterized as resistive memory cells having a select transistor (e.g., 32) and a resistive storage element (e.g., 34). Types of resistive memory cells include, for example, MRAM, ReRAM, carbon nanotube, and phase-change memory cells. In some embodiments, these resistive memory cells may be implemented using a magnetic tunneling junction (MTJ), thus each bit cell may be described as including a select transistor (e.g., 32) and an MTJ (e.g., 34). It should be noted that in the illustrated embodiment, the select gate transistor is an N-type metal-oxide-semiconductor (NMOS) transistor. However, other types of resistive memory cells may have other configurations and / or may be implemented using other types of resistive memory structures. In some embodiments, the memory circuitry 10 may be coupled to a processor circuitry (not shown) of an electronic system, which provides data to be written into the memory and receives data to be read from the memory. The memory 10 is also coupled to a power supply voltage terminal, which is coupled to receive a corresponding power supply voltage, such as VDD and VSS, where VDD is greater than VSS. In one embodiment, VSS is true ground or 0V. It should be noted that, as used herein, VDD and VSS may also refer to a voltage supply terminal receiving the corresponding power supply voltage.

[0022] The memory cells of array 12 are arranged in rows and columns. Each cell in a row is coupled to a corresponding word line WL0-WLM, for a select transistor (e.g., 32) controlling the access transistor (e.g., 34) to the resistive storage element (e.g., 34) of the cell during memory operation. The word lines are controlled by a row decoder 14, which asserts a selected word line based on a first portion of the address received by the controller 20 of memory circuitry 10 for memory operation. Array 12 comprises M+1 rows, in Figure 1 The diagram shows two rows. However, in other embodiments, the array may include a different number of rows. For example, an 8Mb memory array may have 2048 rows plus several (e.g., 2 or 4) redundant rows.

[0023] In the illustrated embodiment, each column of array 12 is coupled to a corresponding source line SL00-SLNK and a corresponding bit line BL00-BLNK. Array 12 includes (N+1)*(K+1) source lines and (N+1)*(K+1) bit lines, wherein... Figure 1Four source lines (e.g., SL00, SLN0, SLOK, and SLNK) and four bit lines (e.g., BL00, BLNO, BL0K, and BLNK) are shown. However, in other embodiments, array 12 may have a different number of columns (e.g., 64*(N+1)). In other embodiments, each column of the array may include a source line paired with two bit lines, a single bit line, or different combinations of bit lines and source lines. As described herein, "column line" or "column" may refer to a source line or a bit line. Array 12 may also include one or more columns of reference cells. In the illustrated embodiment, the selection transistor for the reference cell is shown in the readout circuitry system discussed separately below. Each cell may include a reference resistor, or each column may share a reference resistor.

[0024] In the illustrated embodiment, memory circuitry 10 includes a column decoder 16 for selecting subsets of bit lines and source lines (SL00-SLNK, BL00-BLNK) to provide bit data lines (BDL0-BDLK) and source data lines (SDL0-SDLK). In the illustrated embodiment, both bit data lines and source data lines are provided to write circuitry 150, and the source data lines are provided to read circuitry 18. However, in alternative embodiments, bit data lines, instead of source data lines, may be provided to read circuitry 18. Column decoder 16 includes a bit line multiplexer 44 for selecting a subset of bit lines (BL00-BLNK) during memory operations and a source line multiplexer 46 for selecting a subset of source lines (SL00-SLNK). Control inputs for bit line multiplexer 44 (including a bit line select bus BLSel and a complementary bit line select bus *BLSel, each having N+1 bits) are provided by bit line decoder 48. The control input for the source line multiplexer 46 (including a source line select bus SLSel and a complementary source line select bus *SLSel, each having N+1 bits) is provided by the source line decoder 50. The control signals from decoders 48 and 50 are based on a second portion of the address received by controller 20, and one or more of a write enable signal (WR_EN) and a read enable signal (RD_EN), the second portion of which provides a second address portion for decoders 48 and 50. Controller 20 may use WR_EN and RD_EN generated from the read / write signals (R / W) received by controller 20 as part of the control signals for memory access requests.

[0025] The column decoder 16 selects a number of selected bit lines and selected source lines from a total of (K+1)*(N+1) bit lines and source lines of array 12 based on a second portion of the address received by controller 20 for memory operations. In some embodiments, K+1 represents the size of a data unit being written to or read from memory array 12 during memory operations (e.g., 8 bits, 16 bits, 32 bits, 64 bits). In other embodiments, K+1 may include multiple data units in a row (e.g., 128 bits, 256 bits). N+1 represents the decoding rate of column decoder 16 (e.g., 4:1, 8:1, 16:1). That is, referring to array 12, bit lines BL00-BLNK each include K+1 groups of N+1 bit lines, such that a first number of indices refer to one bit line within a specific group of N+1 bit lines in the K+1 groups, and a second number of indices refer to one group in the K+1 groups. For example, BL30 refers to bit line 3 in group 0, and BLNK refers to bit line N in group K. The same arrangement and naming apply to source lines SL00-SLNK.

[0026] During a write operation, the selected source line and the selected bit line are coupled to a write circuit system 150, which also receives write data via data lines (D0-DK) and complementary data lines (*D0-*DK). (See reference...) Figure 7 and 8 The write circuitry 150, as described, includes source line driver circuitry and bit line driver circuitry that receive write data for storage in selected rows of array 12. In one embodiment, during a write operation to a bit cell of a column, the column-corresponding bit line driver couples the column's bit line (e.g., BL00) to a write voltage of VDD or VSS, and the column-corresponding source line driver couples the column's source line (e.g., SL00) to another write voltage of VDD or VSS, depending on the data value being written, as determined by the data lines (D0-DK) and complementary data lines (*D0-*DK). During the write operation, a voltage differential is provided by a resistive storage element (e.g., 34) that conducts a selection transistor (e.g., 32) across its polarity to determine whether a 1 or a 0 is written to the cell, based on an assertion of the appropriate word line.

[0027] In the illustrated embodiment, during a read operation, the selected source line is provided to the read circuitry system 18 via the mux transistor in the SLMUX 46 and via the source data lines (SDL0-SDLK). The read circuitry system 18 includes K+1 sense amplifiers SA0-SAK (e.g., 66 and 68), where each sense amplifier provides the corresponding read bit value from the cell to the output data lines (DO0-DOK).

[0028] Each sense amplifier (e.g., 66) of the readout circuitry 18 has an inverting input (-) from the column decoder 16 coupled to the corresponding column data line (e.g., SDL0) and coupled via an enable switch (e.g., 52) to the corresponding current load device (e.g., 51), and a non-inverting input (+) coupled to the corresponding reference path (e.g., 53 and 54) and coupled via an enable switch (e.g., 58) to the corresponding load device. For example, SAK has an inverting input coupled to SDLK and coupled via an enable switch 58 to the corresponding current load device 59, and a non-inverting input (+) coupled to the corresponding reference path (e.g., 62 and 61) and coupled via an enable switch (e.g., 64) to the corresponding load device (e.g., 65). All enable switches are controlled by RD_EN such that the enable switches are closed (conductive) when RD_EN is asserted for a read operation and open (non-conductive) when RD_EN is denied (when no read operation occurs).

[0029] In one embodiment, each current-loaded device (i.e., current source) may be implemented as a p-type metal-oxide-semiconductor (PMOS) transistor having a first current electrode coupled to a first voltage supply terminal, such as VDD, a control electrode coupled to receive a bias voltage, and a second current electrode coupled to an inverting or non-inverting input corresponding to an SA. In one embodiment, each SA is implemented as a comparator. In the illustrated embodiment, the selected column data line coupled to the sense amplifier from the column decoder 16 refers to the selected source data line (e.g., SDL0) from the SLMUX 46. However, in an alternative embodiment, the selected column data line may refer to the selected bit data line (e.g., BDL0) from the BLMUX 44. Moreover, in an alternative embodiment, the inverting and non-inverting inputs may be interchanged.

[0030] Each reference path in the read circuitry system 18 includes a corresponding reference resistor (e.g., RR053) and a corresponding selection transistor (e.g., 54). As stated above, in one embodiment, array 12 includes one or more columns of reference memory cells, where each reference memory cell includes a corresponding selection transistor for enabling the reference memory cell for a read operation. In one embodiment, each group of N+1 source lines has a corresponding column of reference memory cells. Alternatively, one column of reference memory cells can be used for all arrays 12. When asserting a word line for a read operation, the word line also enables the corresponding selection transistor in the reference column (e.g., 54) that connects the corresponding reference resistor (e.g., RR053) to the non-inverting input of the corresponding sense amplifier. Therefore, in Figure 1In the read operation, the reference selection transistor (e.g., 54) corresponds to the selected reference selection transistor of the reference memory cell in the array 12, and WLi corresponds to the selected word line, such that the gate electrode of the reference selection transistor (e.g., 54) receives the same voltage as the selected word line of the array 12.

[0031] In the illustrated embodiment, each column of the reference memory cell has a corresponding reference resistor (one of RR0 53-RRK 61) that can be located outside of array 12. For example, for any row selected within a specific group in K+1 groups (e.g., K=0), the same reference resistor (e.g., RR053) is used for the reference path regardless of which source line is selected within the group. For example, for a selected cell in a group where K=3, RR3 is used for the reference path regardless of which source line within group K=3 is selected. In an alternative embodiment, each reference memory cell in array 12 may include a reference resistor in addition to a reference selection transistor. It should be noted that in one embodiment, the reference resistor (also referred to as a reference resistance element that may include one or more resistors) each has a resistance set to a resistance value approximately midway between the resistance value of HRS and the resistance value of LRS. In one embodiment, the reference resistor is adjustable.

[0032] During the read operation, RD_EN is asserted, causing enable switches (e.g., switches 52 and 58) to close, thereby providing a forced read current I to the input nodes of the sense amplifier (e.g., at node 55 at the inverting input of SA0 and node 56 at the non-inverting input of SA0). The current on the source data line (e.g., SDL0) determines the voltage at the inverting input (e.g., the voltage at node 55), and the current in the reference path determines the voltage at the non-inverting input (e.g., the voltage at node 56). The sense amplifier compares the resulting voltages at its inputs and provides an output data bit (e.g., DO0) as "1" if the voltage at the non-inverting input is greater than the voltage at the inverting input, otherwise it provides "0".

[0033] It should be noted that, similar to the description of SA0, each sense amplifier is coupled to a corresponding source data line and a reference path. For example, SAK has an inverting input coupled to SDLK and via enable switch 58 to a corresponding current load device 59, and a non-inverting input (+) coupled to a corresponding reference path (e.g., 62 and 61) and via enable switch (e.g., 64) to a corresponding load device (e.g., 65).

[0034] Each reference path in the readout circuitry 18 is coupled between the input of the sense amplifier (a non-inverting input in the illustrated embodiment) and the virtual ground (VG) node. The VG voltage is supplied to the VG node via VG circuitry 78. See below for further details. Figure 4 and 5 An embodiment of a VG circuit system 78 is provided. A reference voltage is selected such that the resulting VG voltage is greater than true ground (e.g., 0V) and lies between VSS and VDD. In one embodiment, the VG voltage is at least 100mV greater than VSS. Alternatively, the VG voltage is at least 150mV greater than VSS. In this embodiment, the reference voltage is approximately 150mV.

[0035] Figure 2 This is a circuit diagram showing portions of the receive control signals SL0Sel-SLNSel and corresponding complementary signals *SL0Sel-*SLNSel for source-line multiplexer 46. For each memory read or write operation (e.g., when asserting RD_EN or WR_EN), one bit line from the N+1 bit lines in each of the K+1 groups is selected. Thus, for each memory operation, one of SL0Sel-SLNSel is asserted (asserted as logic high) by SL decoder 50 based on a portion of the received access address from controller 20. Multiplexer 46 includes K+1 number of source-line multiplexer circuits (100, 110) for coupling one source line from a set of N source lines (e.g., SL00-SLN0 or SL0K-SLNK) to a corresponding source data line (e.g., SDL0 or SDLK) during a memory operation. In the illustrated embodiment, each multiplexer circuit (e.g., 100) includes 2*(N+1) mux transistors. Each multiplexer circuit (e.g., 100) includes a mux transistor comprising a coupling transistor (e.g., 102, 104) for each source line (e.g., for SL00, SLN0, respectively) to couple the selected source line to the source data line (SDL0) during memory operation. Each multiplexer circuit (e.g., 100) also includes a deselection transistor (e.g., 103, 105) for each source line (e.g., for SL00, SLN0, respectively) to couple an unselected source line to the VG node to receive the VG voltage during memory operation. Multiplexer circuit 110 includes coupling transistors 112 and 114 and deselection transistors 113 and 115.

[0036] The gates (control electrodes of the FETs) of the coupling transistors (102, 104, 112, and 114) are controlled by control signals (SL0Sel-SLNSel). One of the control signals (SL0Sel-SLNSel) is asserted as a logic high to couple a set of selected K+1 source lines to the corresponding K+1 source data lines (SDL0-SDLK) during memory operations, and one source line for each multiplexer circuit (100, 110) is coupled to the corresponding source data line (SDL0, SDLK) (where RD_EN or WR_EN is asserted to indicate a read or write operation, respectively). The gates of the deselect transistors (103, 105, 113, and 115) are controlled by complementary control signals (*SL0Sel-*SLNSel). Each complementary control signal corresponding to the unselected source line (*SL0Sel-*SLNSel) is asserted as a logic high to couple the unselected source line to VG during memory operation. During memory operation, for each multiplexer circuit (100, 110), N bit lines will be unselected and coupled to VG.

[0037] Figure 3 This is a circuit diagram showing portions of the receive control signals BL0Sel-BLNSel and corresponding complementary signals *BL0Sel-*BLNSel of bit-line multiplexer 44. For each write operation (when asserting WR_EN to indicate a write operation), one bit line from the N+1 bit lines in each of the K+1 groups is selected. Therefore, for each write operation, the BL decoder 48 asserts one of BL0Sel-BLNSel as logic high based on a portion of the access address received from controller 20. Multiplexer 44 includes K+1 number of bit-line multiplexer circuits (80, 81) for coupling one bit line from the set of N+1 bit lines (e.g., BL00-BLN0) to the corresponding bit data line (e.g., BDL0) during a memory write operation. In the illustrated embodiment, each multiplexer circuit (e.g., 80) includes 2*(N+1) mux transistors. Each multiplexer circuit (e.g., 80) includes a mux transistor comprising a coupling transistor (e.g., 82, 84) for each bit line (BL00, BLN0, respectively) to couple the selected bit line to a bit data line (BDL0) during a memory write operation. Each multiplexer circuit (e.g., 80) also includes a deselection transistor (e.g., 83, 85) for each bit line (BL00, BLN0, respectively) to couple unselected bit lines to the VG node to receive the VG voltage during a memory write operation. Multiplexer circuit 81 includes coupling transistors 92 and 94 and deselection transistors 93 and 95.

[0038] The gates (control electrodes of the FETs) of the coupling transistors (82, 84, 92, and 94) are controlled by control signals (BL0Sel-BLNSel). One of the control signals (BL0Sel-BLNSel) is asserted as a logic high to couple the selected set of K+1 bit lines to the corresponding K+1 bit data lines (BDL0-BDLK) during a memory write operation, and one bit line for each multiplexer circuit (80, 81) is coupled to the corresponding data line (BDL0, BDLK) (where WR_EN is asserted). The gates of the deselection transistors (83, 85, 93, and 95) are controlled by complementary control signals (*BL0Sel-*BLNSel). Each complementary control signal (*BL0Sel-*BLNSel) corresponding to an unselected bit line is asserted as a logic high to couple the unselected bit line to VG during a memory write operation. During a memory write operation, for each multiplexer circuit (80, 81), N bit lines will be unselected and coupled to VG.

[0039] However, at any time except when a write operation occurs (e.g., when WR_EN is negated regardless of the value of RD_EN), there is no selection of any bit lines by the multiplexer circuits (80, 81). Alternatively, all control signals (BL0Sel-BLNSel) are negated to logic low and all complementary control signals (*BL0Sel-*BLNSel) are asserted to logic high to couple all bit lines to VG. Therefore, during a read operation where RD_EN is asserted, instead of providing control signals and complementary control signals based on the address portion from controller 20, the BL decoder 48 alternatively provides these control signals to conduct all deselect transistors (e.g., 83, 85, 93, and 95) so that all bit lines are coupled to VG. During a memory read operation, for each multiplexer circuit (80, 81), N+1 bit lines (instead of N bit lines as in a write operation) will be coupled to VG.

[0040] Figure 4 Show Figure 1 One embodiment of the VG circuit system 78. The VG circuit system 78 includes a VG replica generator circuit 128 coupled to a flip-flop voltage follower circuit 130. The VG replica generator circuit 128 includes an operational amplifier 120 having an output coupled to a circuit node 122, where the circuit node 122 provides a replica of the desired VG voltage, referred to as VG_REPLICA. Thus, in one embodiment, VG_REPLICA is approximately 150mV (in one embodiment, as referenced above). Figure 1As discussed, this corresponds to the desired voltage level of VG. Opamp 120 has a first (e.g., non-inverting) input coupled to receive a reference voltage REF, and a second (e.g., inverting) input coupled to node 122, and regulates the voltage on node 122 to match REF. VG replica generator circuit 128 includes a current source 126 having a first terminal coupled to VDD and a second terminal coupled to a first current electrode of transistor 124. The second current electrode of transistor 124 is coupled to circuit node 122, and the control electrode of transistor 124 is coupled to the first current electrode of transistor 124. The first current electrode of transistor 124 provides voltage VG_GATE to the control electrode of transistor 124 and to the control electrode of transistor 132 within the flip voltage follower circuit 130. Voltage VG_GATE controls the current flowing through transistors 124 and 132.

[0041] The flip-flop voltage follower circuit 130 includes a current source 136 and transistors 132 and 134. In the illustrated embodiment, each of transistors 134, 132, and 134 is an N-type transistor. Transistor 132 may be referred to as a source follower device or a source follower transistor, and transistor 134 is referred to as a sink device or a sink transistor. A first terminal of current source 136 is coupled to VDD, and a second terminal is coupled to circuit node 138 at a first current electrode of transistor 132. A second current electrode of transistor 132 is coupled to the first current electrode of transistor 134 and also provides the VG voltage to the VG node. A second current electrode of transistor 134 is coupled to VSS (e.g., ground), and a control electrode of transistor 134 is coupled to node 138 to receive the voltage SINK_GATE.

[0042] In operation, opamp 120 generates VG_REPLICA. Assuming transistors 124 and 132 are of the same size, VG_REPLICA causes the flip-flop voltage follower 130 to generate a nearly identical value at VG. VG replication circuit 128 provides VG_GATE from the first current electrode of transistor 124 to transistor 132. Transistor 132 operates as a source follower generating the VG voltage at its second current electrode. Absorption device 134 is used to absorb excess current introduced from node 138 during read operations. For example, during a read operation, a forced read current I is provided to both the selected source line coupled to the selected bit cell and the reference current path, such that the VG node receives a current that is twice (2I) of I for each of the K+1 columns. Therefore, the absorption device 134 coupled to node 138 operates as a voltage detector, which, based on the voltage SINK_GATE, keeps VG stable at the VG voltage by reducing the additional current during reading as needed by pulling down VG.

[0043] In one embodiment, the VG replicator circuit 128 is placed in a globally shared location within system 10. The flip-flop voltage follower 130, which actually drives the VG, can be placed in one or more locations within system 10. That is, one or more of these circuits can be distributed for each sense amplifier, all of which receive VG_GATE from the global VG generator circuit.

[0044] Figure 5 It is shown that Figure 1 An alternative embodiment of the VG circuit system 78 is a VG circuit system 78'. The VG circuit system 78' includes a VG generator 70 and a current compensator 74 coupled to the VG generator 70 via a switch 73. The VG generator 70 is implemented as a source follower amplifier to set the VG voltage. The VG generator includes an amplifier 71 having a first input (e.g., a non-inverting input) coupled to receive a reference voltage, a second input (e.g., an inverting input) coupled to the VG node, and an output coupled to a control electrode of an NMOS transistor 72. The transistor 72 has a first current electrode coupled to VDD and a second current electrode coupled to the second input of the amplifier 71 and the VG node. The second current electrode of the transistor 72 generates a VG voltage at the VG node to match the reference voltage.

[0045] The memory circuit 10 also includes a current compensator circuit 74 coupled to the VG node via a switch 73 controlled by RD_EN. The current compensator 74 includes a current source 76 that generates a current "2I(K+1)" (i.e., twice the amount of the forced read current (I) generated by each current-loaded device (e.g., 51, 57) for K+1 columns in the read circuitry system 18). Therefore, during a read operation (when RD_EN is asserted), the current compensator 74 removes the additional charge introduced by the current-loaded devices (e.g., 51 and 57) from the VG node during each read operation. In this way, VG is stabilized and maintained at the same voltage level even after multiple read operations.

[0046] Figure 6A portion of memory circuitry 10 is shown during a read operation. Assuming bit cell 32 is selected at the intersection of access addresses WL0 and SL00, this portion of memory circuitry 10 provides DO0. It should be noted that during such read operations, each bit cell at the intersection of WL0 and the selected source lines (e.g., SL01, SL02, SL03, ..., SL0K) is also read to provide DO0-DOK. During the read operation, RD_EN is asserted, and thus switches 58, 52, and 73 (in the case of using VG circuitry 78') are all closed (conducting) to provide a forced read current I through each of the selected source lines (e.g., SL00) and the corresponding reference path.

[0047] For example, a forced read current I is provided to SDL0 via a closed enable switch 52, which in turn is coupled to transistor 102 in SLMUX 46 (in Figure 4 (Shown as a closed switch) coupled to SL00. Current flows through the select transistor 32 and the MTJ 34 of the selected bit cell 23 to the corresponding bit line BL00, which is connected to the deselect transistor 83 of the BL MUX 44 (in Figure 4 The closed switch (shown in the diagram) is coupled to the VG node. A forced current is also provided via the closed enable switch 58 through a corresponding reference path including a reference select transistor 54, the gate of which also receives the word line voltage applied to the selected word line (WL0) and a reference resistor (RR053). The reference resistor RR053 is coupled between the reference select transistor 54 and the VG node. The resulting voltages at nodes 56 and 55 are compared by a sense amplifier SA066 to output the stored bit value as DO0. For example, if the voltage at node 56 is greater than the voltage at node 55, then DO0 has a bit value "1"; otherwise, DO0 has a bit value "0".

[0048] Implemented in VG circuit system Figure 4 In the case of the VG circuit system 78, the absorption device 134 maintains stability by absorbing the additional current introduced during reading. Stability is maintained even across a series of read operations. In the VG circuit system implemented as... Figure 5In the case of the VG circuit system 78', the VG node is coupled to a current source 76 of the current compensator 74 via a closed switch 73, which is coupled to the VSS (e.g., ground). Since a forced read current I is provided to both the selected source line coupled to the selected bit cell and the reference current path, the VG node receives twice I (2I) for each of the K+1 columns. Without the current compensator 74, the charge on the node VG would increase with each subsequent read operation. However, with the current compensator 74 present, the current source 76 balances the additional charge on the VG node generated by the total forced read current 2I (K+1) provided to the VG node. This allows the VG node to stably maintain the voltage level provided to it by the dummy ground generator 70. Furthermore, it should be noted that, regardless of how the VG circuit system is implemented, it is configured to stabilize the VG voltage at the VG node, and the remaining unselected portion of array 12 provides column line stability capacitance, which further contributes to VG voltage stabilization.

[0049] As discussed above, alternative embodiments may use bit lines instead of source lines to perform read operations. In this embodiment, reference... Figure 6 For example, instead of providing the forced read current I through the closed enable switch 52 to SDL0 and SL00, through the select transistor 32, through MTJ 34 to BL00, and then to VG, alternatively, the forced read current is provided through the closed enable switch to BDL0 and BL00, through MTJ 34, through the select transistor 32 to SL00, and then to VG. That is, in this embodiment, in SLMUX 46, all source lines will be coupled to VG, and in BLMUX, any unselected bit lines will be coupled to VG. In this embodiment, BDL0-BDLK will be provided to the corresponding sense amplifiers SA0-SAK of the read circuit system 18 instead of to SDL0-SDLK.

[0050] As referenced above Figure 2 and 3 As described, using VG for unselected source lines and all bit lines (or alternatively, for unselected bit lines and all source lines) during read operations helps reduce memory bit leakage during read operations. Furthermore, since the VG voltage is close to true ground (in one embodiment, only 150mV greater than true ground), it has minimal or no impact on write performance for write operations that can utilize true ground (e.g., in bit line and source line drivers of a write circuitry system). No inherent access time loss is attributable to the presence of the VG voltage in this sensing scheme.

[0051] Figure 7A more detailed view of a write circuitry system 150 according to an embodiment of the present invention is shown. Each bit data line (BDL0-BDLK) is coupled to a corresponding bit line driver (e.g., 152, 156), and each source data line (SDL0-SDLK) is coupled to a corresponding source line driver (e.g., 154, 158). Each bit line driver and each source line driver receives a corresponding data value D0-DK and a complementary data value *D0-*DK. For example, bit line driver 0152 is coupled to BDL0 and receives D0 and *D0, and bit line driver K156 is coupled to BDLK and receives DK and *DK. Similarly, source line driver 0154 is coupled to SDL0 and receives D0 and *D0, and source line driver K158 is coupled to SDLK and receives DK and *DK.

[0052] Figure 8 This is a circuit diagram of bit line driver circuit 152 and source line driver circuit 154. Other bit line driver circuits (156) and source line driver circuits (158) are configured accordingly. Driver circuit 152 includes a ground switch 182 for coupling the bit data line (BDL0) to ground during data writing to a selected memory cell of the bit line, and a switch 184 for coupling the bit data line (BDL0) to the write voltage VDD, depending on the values ​​of the data signal D0 and the complementary data signal *D0, which respectively control the conductivity of the switches. When D0 is high and *D0 is low, switch 182 is closed and switch 184 is open to ground the bit data line BDL0. When D0 is low and *D0 is high, switch 182 is open and switch 184 is closed to pull the bit data line BDL0 to a high write voltage VDD.

[0053] The source line drive circuit 154 includes a ground switch 186 for coupling the source data line (SDL0) to ground during data writing to a selected memory cell and a switch 188 for coupling the source data line (SDL0) to the write voltage VDD, depending on the values ​​of complementary data signals *D0 and D0, which respectively control the conductivity of the switches. When *D0 is high and D0 is low, switch 186 is closed and switch 188 is open to ground the source data line SDL0. When *D0 is low and D0 is high, switch 186 is open and switch 188 is closed to pull the source data line SDL0 to a high write voltage VDD.

[0054] Therefore, when the data signal D0 is high and the complementary data signal *D0 is low, the bit data line (BDL0) is grounded and the source data line (SDL0) is pulled to VDD to write a "1" value to the selected memory cell coupled between the source data line and the bit data line during a write operation. When the data signal D0 is low and the complementary data signal *D0 is high, the bit data line (BDL0) is pulled to VDD and the source data line (SDL0) is grounded to write a "0" value to the selected memory cell coupled between the source data line and the bit data line during a memory write operation. In some embodiments, the switch is implemented with an NMOSFET, but in other embodiments it may be implemented with other types of switches (e.g., through a gate).

[0055] Figure 9-11 This is a circuit diagram illustrating the voltage levels of different signals performing memory operations relative to memory cell 23. Memory operations on other cells of array 12 can be performed in a similar manner. Memory cell 23 includes a selection transistor 32 whose gate is controlled by word line WL0 and includes a resistive storage element (34) of an MJT, which is an MRAM cell in the illustrated embodiment. Memory cell 23 is coupled to source line SL00 and bit line BL00. When SL0Sel is asserted as a logic high, source line SL00 can be coupled to source data line SDL0 via coupling transistor 102 of source multiplexer 46, such that VDD is applied to the gate of coupling transistor 102. When signal *SL0Sel is a logic high, source line SL00 is coupled to VG via conductivity deselect transistor 103 of source multiplexer 46. When BL0Sel is asserted high, bit line BL00 is coupled to bit data line BDL0 via coupling transistor 82 of bit line multiplexer 44, such that VDD is applied to the gate of coupling transistor 82. When signal *BL0Sel is at logic high, bit line BL00 is coupled to VG via conductivity deselect transistor 83 of bit line multiplexer 44. The transistor does not conduct when either the coupling or deselect transistor receives logic low (corresponding to VSS) at its corresponding gate electrode. During memory writes, SLSel0 and *SLSel0 are provided via SL decoder 50, and BL0Sel and *BL0Sel are provided via BL decoder 48.

[0056] In one embodiment of a resistive memory array in which each memory cell includes an MTJ as a resistive memory element, when current flows through the resistive memory element of the memory cell in a first direction, the memory cell is written into a low-resistance state (LRS) where the magnetic moments of the AC magnetic layers of the MTJ are aligned in the same direction, and when current flows through the resistive memory element in a second direction opposite to the first direction, the memory cell is written into a high-resistance state (HRS) where the magnetic moments of the AC magnetic layers of the MTJ are not aligned in the same direction. In one embodiment, HRS corresponds to logic level "1" and LRS corresponds to logic level "0". However, in an alternative embodiment, LRS may correspond to logic level "1" and HRS may correspond to logic level "0". In one embodiment, the resistance of HRS is 2-3 times the resistance of LRS, wherein the resistance of LRS may be in the range of 2k-8k ohms.

[0057] Figure 9 The diagram illustrates the voltage applied when a logic level "0" is written to memory cell 23. In the illustrated embodiment, the write is indicated by a resistive element 34 being in the LRS. In some cases, the resistive element 34 is in the HRS, indicating that a logic level "1" is being stored, before being written to "0". To write a "0" value from a "1" value to cell 23, the resistive storage element 34 is moved from the HRS to the LRS. In the illustrated embodiment, to change the resistance state of the MTJ to LRS, it is along the "upward" direction (relative to) through the MTJ. Figure 9 The view provides a write current (e.g., 60 microamps (µA)), where node 200 is at a higher voltage than node 202 to align the magnetic moment of the MTJ of the resistive memory element 34. Because the data signal *D0 is high (indicating that a "0" will be written), the write voltage VDD is applied to the bit data line BDL0 via the closed switch 184 of the bit line drive circuit 152, and the source data line SDL0 is grounded (at VSS) via the closed switch 186 of the source write drive circuit 154 (see...). Figure 8 The control signal SL0Sel is asserted high (at VDD), which conducts transistor 102 and, through the asserted word line WL0 (at VDD), conducts select transistor 32 to pull node 202 to ground. The signal BL0Sel is also high (at VDD), which conducts transistor 82 to bind BL00 to BDL0 and pull the voltage of node 200 to VDD. This causes current to flow through MTJ 34 to align the magnetic moment of the MTJ of storage element 34 from HSR to LSR.

[0058] Figure 10 This shows the voltage applied when a logic level "1" is written to memory cell 23. Compared to... Figure 9The condition is along the downward direction through the storage element 34 (relative to) Figure 10 A current is applied (see view). In some cases, the resistive element 34 is in the LRS indicating that a "0" is being stored before being written with a "1". To write a "1" value from a "0" value to cell 23, the resistive storage element 34 is moved from the LRS to the HRS. In the illustrated embodiment, to change the resistance state of the MTJ to the HRS, a current is applied along the "downward" direction through the MTJ (relative to the HRS). Figure 10 The view provides a high current of 80 microamps (µA), where node 202 is at a higher voltage than node 200 to change the torque of the MTJ to antiparallel. Because the data signal D0 is high (to indicate that a "1" will be written), the write voltage VDD is applied to the source data line SDL0 via the closed switch 188 of the source line drive circuit 154, and the bit data line BDL0 is grounded at VSS via the closed switch 182 of the bit line write drive circuit 152 (see...). Figure 8 The control signal BL0Sel is high (at VDD), which conducts transistor 82 to pull node 200 towards VSS. The select transistor 32 is conducted via the assertion word line WL0 (at VDD). The signal SL0Sel is high (at VDD), which conducts transistor 102 to pull node 202 towards VDD, thereby generating a current sufficient to change the torque of the MJT of memory element 34 into an misaligned current.

[0059] During the writing of a "0" or "1" to memory cell 23, *SL0Sel and *BL0Sel are negated to apply VSS to the gates of deselect transistors 103 and 83 because SL0Sel and BL0Sel are asserted to select memory cell 23. This makes these deselect transistors non-conductive to prevent SL00 or BL00 from being connected to VG. However, it should be noted that in the MUX circuit 100 of the SLMUX 46 (see...) Figure 2 This causes the remaining deselection transistors (e.g., deselection transistor 105) corresponding to SL10-SLN0 to conduct so that each of SL10-SLN0 (the unselected source lines) is coupled to VG during writing. Similarly, in the MUX circuit 80 of the BLMUX 44 (see... Figure 3 This causes the remaining deselect transistors (e.g., deselect transistor 85) corresponding to BL10-BLN0 to conduct so that each of BL10-BLN0 (the unselected bit lines) is also coupled to VG during the write operation.

[0060] For example, Figure 11The voltage is shown when memory cell 23 is in an unselected row during a memory operation (during a read or write operation). In the illustrated embodiment, cell 23 is in a selected row because word line WL0 is at the asserted voltage value VDD. However, the voltages of the other signals will be the same if cell 23 is in an unselected row. As discussed above, signal *SL0Sel is high (at VDD) to connect source line SL00 to VG through transistor 103. Signal *BL0Sel is also high (at VDD) to connect bit line BL00 to VG through transistor 83. Both signals SL0Sel and BL0Sel are at a low voltage state (at VSS) to isolate source line SL00 from source data line SDL0 and bit line BL00 from bit data line BDL0. It should be noted that the voltage conditions of control signals SL0Sel, *SL0Sel, BL0Sel, and *BL0Sel can be the same when a memory operation is not being performed.

[0061] The write endurance of NVM circuit 10 depends on the amount of voltage that can be applied to the gate oxide and the duration of stress on both the selected gate of the bit cell and the gate of the device in the MUX circuit. During write operations, time-dependent gate oxide breakdown (TDDB) caused by transistor aging is reduced by biasing the source at VG rather than grounding the unselected source line and the unselected bit line, thus extending the lifetime (i.e., endurance) of NVM circuit 10. Figure 9-11 As illustrated in the example, each transistor within the NVM circuit 10 receives a voltage at its gate electrode, thereby generating TDDB stress on these transistors. For example, the select transistors (e.g., transistor 32) for unselected source lines and unselected bit lines, as well as the deselect transistors (e.g., 103 and 83), receive VDD at their gates, thus generating TDDB stress. However, this stress can be reduced by connecting the unselected source lines and bit lines to VG instead of true ground, because VG > true ground, thus reducing the voltage difference between the gate and source. Furthermore, it should be noted that by applying a source bias to the deselect transistors for the unselected source lines and unselected bit lines, the stress on all the unselected deselect transistors (e.g., 103 and 83) in the MUX circuit, which in turn exceed the number of selected coupled transistors (e.g., 102 and 82) in the MUX circuit, is reduced. For example, in a MUX circuit of SLMUX46 or BLMUX44, for a write operation, the gate of one of the selected coupled transistors in each of the N+1 coupled transistors in each of the K+1 groups receives VDD, while the gates of the N unselected deselected transistors in each of the N+1 deselected transistors in each of the K+1 groups receive VDD.

[0062] In an alternative embodiment, using VG to bias the source to the unselected source line and unselected bit line during a write operation can reduce TDDB stress in other types of NVM memory (e.g., other types of resistive RAM).

[0063] It is understood how the VG voltage can be used to reduce leakage current in resistive memory arrays during read operations. In one embodiment, during a read operation, all unselected source lines and all bit lines are biased to a virtual ground level rather than a true ground. Alternatively, depending on the memory array design, all unselected bit lines and all source lines are biased to a virtual ground level rather than a true ground. This bias reduces leakage current. During a read operation, all voltage levels are increased relative to a virtual ground, resulting in almost no time (performance) penalty compared to using a true ground. It is also understood how the VG voltage can be used to reduce TDDB stress in NVM circuitry, such as in resistive memory circuitry, during write operations. In one embodiment, during a write operation, all unselected source lines and all unselected bit lines are biased to a virtual ground level rather than a true ground. In one embodiment, the VG voltage can be properly maintained and stabilized by using a VG replication voltage and a toggle follower voltage circuit to generate the VG voltage, wherein the toggle follower voltage circuit includes a sink to remove additional current generated during reads. Alternatively, an adjustable source follower amplifier can be used to provide the VG voltage, and a current compensator can be used during read operations to compensate for any extra charge on the VG node, thus maintaining the VG node charge neutral.

[0064] While specific embodiments of the invention have been shown and described, those skilled in the art will recognize that further changes and modifications can be made based on the teachings herein without departing from the invention and its broader aspects, and therefore the appended claims are intended to cover all such changes and modifications within the true spirit and scope of the invention.

Claims

1. A memory, characterized in that, include: A virtual grounding circuit system coupled to a first power supply terminal and a second power supply terminal and configured to generate a virtual grounding voltage at a virtual grounding node, wherein the first power supply terminal is configured to provide a first power supply voltage and the second power supply terminal is configured to provide a second power supply voltage less than the first power supply voltage, wherein the virtual grounding voltage is greater than zero volts and is between the first power supply voltage and the second power supply voltage. A memory array of resistive memory cells, each resistive memory cell in the memory array including a selection transistor and a resistive storage element for storing a value, wherein each resistive memory cell is coupled to a first column line of a plurality of first column lines; A first decoder is configured to select a first set of first column lines from the plurality of first column lines for a memory read operation from a selected set of resistive memory cells coupled to the selected first set of first column lines. A read circuit system configured to provide read values ​​from the selected set of resistive memory cells during the memory read operation; as well as A first column line multiplexer (MUX) is configured to couple each selected first column line from the first column line set to the read circuit system during the memory read operation, and is also configured to couple each unselected first column line from the plurality of first column lines to the virtual ground node during the memory read operation. The virtual grounding circuit system mentioned above includes: A flip-flop voltage follower circuit having a current source coupled in series with a source follower transistor and a sink transistor between a first power supply terminal and a second power supply terminal, wherein a first current electrode of the source follower transistor is coupled to the current source, and a second current electrode of the source follower transistor is coupled to the virtual ground node.

2. The memory according to claim 1, characterized in that, Each resistive memory cell of the memory array is coupled to a second column line of a plurality of second column lines, the memory further comprising: A second column line multiplexer (MUX) is configured to couple each of the plurality of second column lines to the virtual ground node during the memory read operation.

3. The memory according to claim 2, characterized in that, The plurality of first column lines represent one of the source lines or bit lines, and the plurality of second column lines represent the other of the source lines or bit lines.

4. The memory according to claim 1, characterized in that, The virtual grounding circuit system includes: A current compensator coupled to the virtual ground node via a first enable switch, wherein the first enable switch is configured to conduct to couple the current compensator to the virtual ground node during the memory read operation.

5. The memory according to claim 1, characterized in that, The readout circuitry includes a set of sense amplifiers, each sense amplifier having a first input coupled to a corresponding first column line in the selected first column line set and a second input coupled to a corresponding reference current path, and an output providing a bit value of the readout value for the memory readout operation.

6. The memory according to claim 5, characterized in that, The readout circuitry further includes a first current source corresponding to the first input of each sense amplifier and a second current source corresponding to the second input of each sense amplifier, wherein during the memory readout operation, the readout circuitry is configured to provide a readout current from each first current source to the corresponding column line of the selected first column line set and to provide a readout current from each second current source to the corresponding reference current path.

7. A method in a memory having a first power supply terminal configured to provide a first power supply voltage, a second power supply terminal configured to provide a second power supply voltage less than the first power supply voltage, and a memory array of resistive cells, wherein each resistive memory cell in the memory array is coupled to a first column line of a plurality of first column lines, characterized in that, The method includes: A first column line set is selected from the plurality of first column lines for a memory read operation from a selected set of resistive memory cells coupled to the selected first column line set; A virtual grounding voltage is generated at the virtual grounding node, wherein the virtual grounding voltage is greater than the second power supply voltage; During the read operation: Couple all unselected first column lines of the plurality of first column lines to the virtual ground node; Each first column line in the selected first column line set is coupled to the first input of the corresponding sense amplifier in a plurality of sense amplifiers; Couple a corresponding reference current path to the second input of each of the plurality of sense amplifiers, wherein each corresponding reference current path is coupled between the virtual ground node and the corresponding sense amplifier among the plurality of sense amplifiers; and The read current is provided to each of the first column lines in the selected first column line set and to each corresponding reference current path; The generation of the virtual ground voltage is performed by a flip-flop voltage follower circuit, wherein the flip-flop voltage follower circuit includes: A current source having a first end coupled to the first power supply terminal; A source follower transistor having a first current electrode coupled to a second terminal of the current source and a second current electrode coupled to the virtual ground node; and An absorption device having a first current electrode coupled to the virtual ground node, a second current electrode coupled to the second power supply terminal, and a control electrode coupled to the first current electrode of the source follower transistor.

8. The method according to claim 7, characterized in that, Each resistive memory cell of the memory array is coupled to a second column line of a plurality of second column lines, the method further comprising: During the memory read operation, each of the plurality of second column lines is coupled to the virtual ground node.

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