Display panel and display device including the same

Abstract

An embodiment of the present application discloses a display panel and a display device, wherein the display panel includes a first display area and a second display area, the second display area includes a transmittance area, and the sum of the resistivities of a first reset signal line, a first initialization signal line, and a first bias adjustment signal line located in the first display area is not greater than the sum of the resistivities of a second reset signal line, a second initialization signal line, and a second bias adjustment signal line located in the second display area, so that at least one of the first reset signal line, the first initialization signal line, and the first bias adjustment signal line, which have relatively high resistivity requirements, is arranged on a film layer with a smaller signal line resistivity, thereby improving the display performance of the first display area, and at least one of the second reset signal line, the second initialization signal line, and the second bias adjustment signal line, which have relatively low resistivity requirements, is arranged on a film layer with a larger signal line resistivity, thereby taking into account both the display performance and the transmittance performance of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device including the display panel. Background Art

[0002] With the rapid development of display technology, in addition to traditional functions such as information display, the requirements for the appearance of displays are also gradually increasing. A larger screen-to-body ratio is the trend of the future market, so display devices with under-screen camera structures are very popular among consumers.

[0003] Currently, display devices with under-display camera structures typically have a transmissive area within the display panel's display area, allowing light to pass through the display area and reach the camera located below the display panel, allowing the camera to capture the image. For display devices with under-display camera structures, balancing the display performance and light transmission performance of the display panel within the device has become a hot topic for researchers in this field. Summary of the Invention

[0004] To solve the above technical problems, embodiments of the present application provide a display panel and a display device to balance the display performance and light transmittance of the display panel.

[0005] To solve the above problems, the embodiments of the present application provide the following technical solutions:

[0006] A display panel, comprising:

[0007] A pixel circuit and a light-emitting element, wherein the pixel circuit includes a driving transistor, and the driving transistor is used to provide a driving current for the light-emitting element;

[0008] a reset signal line, an initialization signal line, and a bias adjustment signal line, wherein the reset signal line is used to provide a reset signal to the gate of the driving transistor, the initialization signal line is used to provide an initialization signal to the light-emitting element, and the bias adjustment signal line is used to provide a bias adjustment signal to the driving transistor;

[0009] The display panel includes a first display area and a second display area, the second display area includes a transmission area, the first display area includes a first reset signal line, a first initialization signal line and a first bias adjustment signal line, and the second display area includes a second reset signal line, a second initialization signal line and a second bias adjustment signal line; wherein,

[0010] The resistivity of the first reset signal line is ρ11, the resistivity of the first initialization signal line is ρ12, and the resistivity of the first bias adjustment signal line is ρ13; the resistivity of the second reset signal line is ρ21, the resistivity of the second initialization signal line is ρ22, and the resistivity of the first bias adjustment signal line is ρ23; wherein,

[0011] ρ11+ρ12+ρ13≤ρ21+ρ22+ρ23.

[0012] A display device comprises the above-mentioned display panel, wherein the transmission area is provided with a functional device corresponding to the transmission area, and the functional device can receive or reflect light through the transmission area.

[0013] Compared with the existing technology, the above technical solution has the following advantages:

[0014] In the display panel and display device provided in the embodiments of the present application, the sum of the resistivities of the first reset signal line, the first initialization signal line, and the first bias adjustment signal line located in the first display area is not greater than the sum of the resistivities of the second reset signal line, the second initialization signal line, and the second bias adjustment signal line located in the second display area, so that at least one of the signal lines with relatively high resistivity requirements among the first reset signal line, the first initialization signal line, and the first bias adjustment signal line located in the first display area is set on a film layer with a smaller signal line resistivity, thereby improving the display performance of the first display area, and at least one of the signal lines with relatively low resistivity requirements among the second reset signal line, the second initialization signal line, and the second bias adjustment signal line located in the second display area is set on a film layer with a larger signal line resistivity, thereby reducing the number of signal lines on the film layer with a smaller signal line resistivity, increasing the area of ​​the transmission area of ​​the second display area, and ensuring the light transmittance performance of the second display area, thereby taking into account both the display performance and light transmittance performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 A schematic structural diagram of a pixel circuit in a display panel provided in one embodiment of the present application;

[0017] Figure 2 A top view of a display panel provided in one embodiment of the present application;

[0018] Figure 3A top view of a display panel provided in another embodiment of the present application;

[0019] Figure 4 A schematic structural diagram of a pixel circuit in a display panel provided in yet another embodiment of the present application;

[0020] Figure 5 A schematic structural diagram of a pixel circuit in a display panel provided in yet another embodiment of the present application;

[0021] Figure 6 A schematic structural diagram of a pixel circuit in a display panel provided in yet another embodiment of the present application;

[0022] Figure 7 Schematic diagram of the drift of the Id-Vg curve of the driver transistor during long-term operation;

[0023] Figure 8 A schematic structural diagram of a pixel circuit in a display panel provided in yet another embodiment of the present application;

[0024] Figure 9 A schematic structural diagram of a pixel circuit in a display panel provided in yet another embodiment of the present application;

[0025] Figure 10 A schematic structural diagram of a pixel circuit in a display panel provided in yet another embodiment of the present application;

[0026] Figure 11 A schematic structural diagram of a pixel circuit in a display panel provided in yet another embodiment of the present application;

[0027] Figure 12 A schematic structural diagram of a pixel circuit in a display panel provided in yet another embodiment of the present application;

[0028] Figure 13 A schematic structural diagram of a pixel circuit in a display panel provided in yet another embodiment of the present application;

[0029] Figure 14 A top view of a display panel provided in yet another embodiment of the present application;

[0030] Figure 15 A schematic diagram of the relative positions of a second reset signal line and a second initialization signal line in a display panel provided by one embodiment of the present application;

[0031] Figure 16 A schematic diagram of the relative positions of a second reset signal line and a second bias adjustment signal line in a display panel provided by one embodiment of the present application;

[0032] Figure 17A schematic diagram of the relative positions of a second initialization signal line and a second bias adjustment signal line in a display panel provided by one embodiment of the present application;

[0033] Figure 18 A schematic diagram of the relative positions of a first reset signal line, a first initialization signal line, and a first bias adjustment signal line in a display panel provided by one embodiment of the present application;

[0034] Figure 19 A schematic diagram of the relative positions of a first initialization signal line and a second initialization signal line in a display panel provided by one embodiment of the present application;

[0035] Figure 20 A top view of a display panel provided in yet another embodiment of the present application;

[0036] Figure 21 A top view of a display panel provided in yet another embodiment of the present application;

[0037] Figure 22 A partial top view of a display panel provided in yet another embodiment of the present application;

[0038] Figure 23 A schematic structural diagram of a display device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0040] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0041] As described in the background technology section, for a display device with an under-screen camera structure, how to balance the display performance and light transmittance performance of the display panel in the display device has gradually become a research hotspot for those skilled in the art.

[0042] In view of this, an embodiment of the present application provides a display panel, such as Figure 1 As shown, the display panel includes:

[0043] A pixel circuit 10 and a light-emitting element 20, wherein the pixel circuit 10 includes a driving transistor T1, and the driving transistor T1 is used to provide a driving current to the light-emitting element 20, so as to control the light-emitting state of the light-emitting element 20 through the driving current;

[0044] A reset signal line, an initialization signal line and a bias adjustment signal line, wherein the reset signal line is used to provide a reset signal Vref for the gate of the driving transistor T1, the initialization signal line is used to provide an initialization signal Vini for the light-emitting element 20, and the bias adjustment signal line is used to provide a bias adjustment signal V0 for the driving transistor T1.

[0045] like Figure 2 As shown, the display panel provided in the embodiment of the present application includes: a first display area 100 and a second display area 200, and the second display area 200 includes a transparent area 201. It should be noted that, in actual applications, the first display area 100 and the second display area 200 both include multiple sub-pixels, and each sub-pixel includes a pixel circuit and a light-emitting element to realize the display of the sub-pixel.

[0046] like Figure 3 As shown, in the embodiment of the present application, the first display area 100 includes a first reset signal line 31, a first initialization signal line 32 and a first bias adjustment signal line 33, and the second display area 200 includes a second reset signal line 41, a second initialization signal line 42 and a second bias adjustment signal line 43; wherein, the first reset signal line 31 is used to provide a reset signal Vref to the pixel circuit 10 located in the first display area 100, the first initialization signal line 32 is used to provide an initialization signal Vini to the pixel circuit 10 located in the first display area 100, and the first bias adjustment signal line 33 is used to provide a bias adjustment signal V0 to the pixel circuit 10 located in the first display area 100; the second reset signal line 41 is used to provide a reset signal Vref to the pixel circuit 10 located in the second display area 200, the second initialization signal line 42 is used to provide an initialization signal Vini to the pixel circuit 10 located in the second display area 200, and the second bias adjustment signal line 43 is used to provide a bias adjustment signal V0 to the pixel circuit 10 located in the second display area 200. Optionally, the first reset signal line, the first initialization signal line, the first bias adjustment signal line, the second reset signal line, the second initialization signal line, and the second bias adjustment signal line extend in the same direction.

[0047] Specifically, in an embodiment of the present application, the resistivity of the first reset signal line is ρ11, the resistivity of the first initialization signal line is ρ12, and the resistivity of the first bias adjustment signal line is ρ13; the resistivity of the second reset signal line is ρ21, the resistivity of the second initialization signal line is ρ22, and the resistivity of the first bias adjustment signal line is ρ23.

[0048] The inventors have discovered that, in actual applications, the resistivity of the three signal lines, namely the reset signal line, the initialization signal line, and the bias adjustment signal line, which are electrically connected to the pixel circuit, has a certain influence on the performance of the transistors electrically connected thereto. The smaller the resistivity of the signal line, the faster the transistors electrically connected thereto switch from one state to another. On the contrary, the greater the resistivity of the signal line, the slower the transistors electrically connected thereto switch from one state to another. That is, the resistivity of the three signal lines, namely the reset signal line, the initialization signal line, and the bias adjustment signal line, which are electrically connected to the pixel circuit, directly affects the state conversion switching performance of the transistors electrically connected thereto, thereby responding to the display performance of the sub-pixel where the pixel circuit is located.

[0049] It should be noted that the first display area is a normal display area and does not have too many requirements for light transmittance. Therefore, the setting of the first reset signal line, the first initialization signal line and the first bias adjustment signal line does not need to consider the space occupancy too much, and is mainly set based on their resistance requirements; the second display area includes a transmission area, and the transmission area has certain requirements for light transmittance. Therefore, the setting of the second reset signal line, the second initialization signal line and the second bias adjustment signal line needs to fully consider the space they occupy. The smaller the space occupied by the second reset signal line, the second initialization signal line and the second bias adjustment signal line, the larger the available area of ​​the transmission area in the second display area. Conversely, the larger the space occupied by the second reset signal line, the second initialization signal line and the second bias adjustment signal line, the smaller the available area of ​​the transmission area in the second display area. Therefore, the setting of the second reset signal line, the second initialization signal line and the second bias adjustment signal line not only needs to consider their resistance requirements, but also fully consider the space they occupy.

[0050] Therefore, in the embodiment of the present application, ρ11+ρ12+ρ13≤ρ21+ρ22+ρ23, that is, the sum of the resistivities of the first reset signal line, the first initialization signal line, and the first bias adjustment signal line located in the first display area is not greater than the sum of the resistivities of the second reset signal line, the second initialization signal line, and the second bias adjustment signal line located in the second display area, so that at least one of the first reset signal line, the first initialization signal line, and the first bias adjustment signal line can be set on a film layer with a smaller resistivity, that is, there are more lines on the film layer with a smaller resistivity to reduce the resistivity of the signal line. , improve the state switching speed of the transistor electrically connected to the signal line, thereby improving the display performance of the sub-pixel, and further improving the display performance of the first display area, and set at least one of the second reset signal line, the second initialization signal line and the second bias adjustment signal on a film layer with a larger resistivity to avoid setting the second reset signal line, the second initialization signal line and the second bias adjustment signal line on the film layer where the first reset signal line, the first initialization signal line and the first bias adjustment signal line are located, resulting in an excessive number of signal lines on the film layer where the first reset signal line, the first initialization signal line and the first bias adjustment signal line are located.

[0051] It should be noted that, assuming that the second reset signal line, the second initialization signal line, and the second bias adjustment signal line are also set in the film layer where the first reset signal line, the first initialization signal line, and the first bias adjustment signal line are located, the following problems may exist: there are too many signal lines on the film layer where the first reset signal line, the first initialization signal line, and the first bias adjustment signal line are located. In order to ensure that there is sufficient insulation safety distance between adjacent signal lines on the film layer where the first reset signal line, the first initialization signal line, and the first bias adjustment signal line are located, it is necessary to increase the distance between adjacent signal lines on the film layer where the first reset signal line, the first initialization signal line, and the first bias adjustment signal line are located. As a result, the space occupied by the signal lines on the film layer where the first reset signal line, the first initialization signal line, and the first bias adjustment signal line are located is too large, affecting the area of ​​the transmission area and the light transmittance performance of the second display area. In order to ensure the area of ​​the transmission area of ​​the second display area, it is necessary to reduce the distance between adjacent signal lines on the film layer where the first reset signal line, the first initialization signal line, and the first bias adjustment signal line are located, which makes it easy for adjacent signal lines on the film layer where the first reset signal line, the first initialization signal line, and the first bias adjustment signal line to short-circuit.

[0052] In the display panel provided in the embodiment of the present application, the second display area is provided with a transmissive area, which needs to realize the light-transmitting function. Compared with the first display area, the display performance of the second display area needs to take into account the transmittance. Therefore, the display panel provided in the embodiment of the present application sets at least one of the second reset signal line, the second initialization signal line and the second bias adjustment signal line on the wiring film layer with a larger resistivity to reduce the number of signal lines on the film layer where the first reset signal line, the first initialization signal line and the first bias adjustment signal line are located, thereby ensuring that the signal lines on the film layer where the first reset signal line, the first initialization signal line and the first bias adjustment signal line are located have good electrical performance. , so that there is a larger distance between adjacent signal lines on the film layer where the first reset signal line, the first initialization signal line and the first bias adjustment signal line are located, so as to ensure that the adjacent signal lines on the film layer where the first reset signal line, the first initialization signal line and the first bias adjustment signal line are located are insulated from each other, reducing the probability of short circuit between adjacent signal lines on the film layer where the first reset signal line, the first initialization signal line and the first bias adjustment signal line are located, thereby improving the display performance of the first display area, and moreover, the film layer where the first reset signal line, the first initialization signal line and the first bias adjustment signal line are located can have a larger area to correspond to the transmittance area of ​​the second display area, thereby improving the light transmittance performance of the second display area.

[0053] It should be noted that in the display panel provided in the embodiment of the present application, the signal lines located in the same film layer are made of the same material and have the same resistivity, and the signal lines located in different film layers are made of different materials and have different resistivities, but the present application is not limited to this. In other embodiments of the present application, the signal lines located in different film layers may also have some film layers made of the same material and have the same resistivity, and some film layers made of different materials and have different resistivities, depending on the specific circumstances.

[0054] The display panel provided in the embodiment of the present application is described below by taking as an example that the signal lines located in the same film layer are made of the same material and have the same resistivity.

[0055] It should be noted that the embodiment of the present application does not require the specific resistivity of the first reset signal line, the first initialization signal line, the first bias adjustment signal line, the second reset signal line, the second initialization signal line and the second bias adjustment signal line, as long as the resistivity of the film layer where at least one of the first reset signal line, the first initialization signal line and the first bias adjustment signal line is located is smaller than the resistivity of at least one of the second reset signal line, the second initialization signal line and the second bias adjustment signal line, so that ρ11+ρ12+ρ13≤ρ21+ρ22+ρ23.

[0056] It should also be noted that, in the embodiment of the present application, the first reset signal line, the first initialization signal line and the first bias adjustment signal line can be in the same film layer or in different film layers. Similarly, the second reset signal line, the second initialization signal line and the second bias adjustment signal line can also be in the same film layer or in different film layers, as long as at least one of the first reset signal line, the first initialization signal line and the first bias adjustment signal line is arranged on a film layer with a smaller signal line resistivity, and at least one of the second reset signal line, the second initialization signal line and the second bias adjustment signal line is arranged on a film layer with a larger signal line resistivity.

[0057] In summary, in the display panel provided in the embodiment of the present application, ρ11+ρ12+ρ13≤ρ21+ρ22+ρ23, so that at least one of the first reset signal line, the first initialization signal line and the first bias adjustment signal line located in the first display area, which have relatively high resistivity requirements, is set on a film layer with a smaller signal line resistivity, thereby improving the display performance of the first display area, and at least one of the second reset signal line, the second initialization signal line and the second bias adjustment signal line located in the second display area, which have relatively low resistivity requirements, is set on a film layer with a larger signal line resistivity, thereby reducing the number of signal lines on the film layer with a smaller signal line resistivity, increasing the area of ​​the transmittance zone of the second display area, and ensuring the light transmittance of the second display area, thereby taking into account both the display performance and the light transmittance of the display panel.

[0058] Based on the above embodiment, in one embodiment of the present application, Figure 1 As shown, the pixel circuit 10 includes a reset transistor T2, an initialization transistor T3, and a bias adjustment transistor T4. The reset transistor T2 is connected between the reset signal line and the gate of the driving transistor T1; the initialization transistor T3 is connected between the initialization signal line and the light-emitting element 20; and the bias adjustment transistor T4 is connected between the bias adjustment signal line and the first electrode S or the second electrode D of the driving transistor T1. The reset transistor T2 is used to reset the gate of the driving transistor T1 (i.e., the first node N1); the initialization transistor T3 is used to reset the anode of the light-emitting element 20; and the bias adjustment transistor T4 is used to adjust the potential difference between the first electrode S or the second electrode D and the gate of the driving transistor T1.

[0059] Specifically, such as Figure 1 、 Figure 4-Figure 6 As shown, Figure 1 A schematic structural diagram of a pixel circuit of a display panel provided in an embodiment of the present application is shown in FIG. Figure 4 This is a schematic structural diagram of a pixel circuit of another display panel provided in an embodiment of the present application. Figure 5is a structural diagram of a pixel circuit of another display panel provided in an embodiment of the present application. Figure 6 1 is a schematic diagram of the structure of a pixel circuit of another display panel provided by an embodiment of the present application. In this embodiment, the pixel circuit 10 includes, in addition to a driving transistor T1, a reset transistor T2, an initialization transistor T3, and a bias adjustment transistor T4, a data writing transistor T5, a compensation transistor T6, a first light-emitting control transistor T7, and a second light-emitting control transistor T8. The data writing transistor T5 is connected between a data signal line and a first electrode S of the driving transistor T1 to provide a data signal Vdata to the driving transistor T1. The compensation transistor T6 is connected between a second electrode D of the driving transistor T1 and a gate of the driving transistor T1 to write the data signal Vdata into the gate of the driving transistor T1 to compensate for the threshold voltage of the driving transistor T1. The first light-emitting control transistor T7 is connected between a power signal line and the first electrode S or the second electrode D of the driving transistor T1. The second light-emitting control transistor T8 is connected between the second electrode D or the first electrode S of the driving transistor T1 and the light-emitting element 20 to provide a driving current to the light-emitting element 20 when the driving transistor T1 is turned on.

[0060] The display panel provided by the embodiment of the present application is described below in conjunction with a specific circuit. It should be noted that the operation process of the pixel circuit includes a pre-stage and a light-emitting stage, wherein the pre-stage includes a reset stage, an initialization stage, a bias adjustment stage, and a threshold compensation stage.

[0061] Continue as Figures 1-4 As shown, in the embodiment of the present application, in the threshold compensation stage, after the driving transistor T1 is turned on, it is used to write the data signal Vdata into the compensation transistor, and in the light emitting stage, after the driving transistor T1 is turned on, it is used to provide a driving current for the light emitting element 20;

[0062] One end of the reset transistor T2 is connected to the reset signal line for receiving the reset signal Vref, and the other end of the reset transistor T2 is connected to the gate of the driving transistor T1. In the reset phase, the reset transistor T2 is turned on to provide the reset signal Vref to the gate of the driving transistor T1. In this embodiment, the reset transistor T2 directly provides the reset signal Vref to the gate of the driving transistor T1. Specifically, the gate of the reset transistor T2 receives the scan signal S3. The scan signal S3 received by the pixel circuit 10 is a pulse signal. The valid pulse of the scan signal S3 controls the transmission path of the first and second electrodes of the reset transistor T2 to be turned on, so that the reset signal Vref is written to the gate of the driving transistor T1; the invalid pulse of the scan signal S3 controls the transmission path of the first and second electrodes of the reset transistor T2 to be turned off, that is, under the control of the scan signal S3, the reset transistor T2 selectively writes the reset signal Vref to the gate of the driving transistor T1. It should be noted that in the reset phase, the scan signal S3 is a valid pulse.

[0063] One end of the initialization transistor T3 is connected to the initialization signal line for receiving the initialization signal Vini, and the other end of the initialization transistor T3 is connected to the anode of the light-emitting element 20. In the initialization stage, the initialization transistor T3 is turned on to provide the initialization signal Vini to the anode of the light-emitting element 20. Specifically, the gate of the initialization transistor T3 receives the scan signal S4. The scan signal S4 received by the pixel circuit 10 is a pulse signal. The valid pulse of the scan signal S4 controls the transmission path of the first and second poles of the initialization transistor T3 to be turned on, so that the initialization signal Vini is written to the anode of the light-emitting element 20 to initialize the anode of the light-emitting element 20; the invalid pulse of the scan signal S4 controls the transmission path of the first and second poles of the initialization transistor T3 to be turned off. That is, under the control of the scan signal S4, the initialization transistor T3 selectively initializes the anode of the light-emitting element 20. It should be noted that in the initialization stage, the scan signal S4 is a valid pulse.

[0064] The bias adjustment transistor T4 is connected between the first electrode S or the second electrode D of the driving transistor T1 and a bias adjustment signal line. The bias adjustment signal line provides a bias adjustment signal V0. During the bias adjustment phase, the bias adjustment transistor T4 is turned on and provides the bias adjustment signal V0 to the first electrode S or the second electrode D of the driving transistor T1. Specifically, the gate of the bias adjustment transistor T4 receives a scanning signal SV. The scanning signal SV received by the pixel circuit 10 is a pulse signal. An active pulse of the scanning signal SV controls the transmission path between the first electrode and the second electrode of the bias adjustment transistor T4 to conduct, thereby providing the bias adjustment signal V0 to the first electrode S or the second electrode D of the driving transistor T1. An inactive pulse of the scanning signal SV controls the transmission path between the first electrode and the second electrode of the bias adjustment transistor T4 to shut off. That is, under the control of the scanning signal SV, the bias adjustment transistor T4 selectively provides the bias adjustment signal V0 to the first electrode S or the second electrode D of the driving transistor T1. It should be noted that during the bias adjustment phase, the bias adjustment signal V0 is an active pulse.

[0065] One end of the data write transistor T5 is connected to the data write signal line, and the other end is connected to the first electrode S of the driving transistor T1. During the compensation phase, the data write transistor T5 is turned on to write the data signal Vdata into the first electrode S of the driving transistor T1. Specifically, the gate of the data write transistor T5 receives the scan signal S1. The scan signal S1 received by the pixel circuit 10 is a pulse signal. The valid pulse of the scan signal S1 controls the transmission path between the first electrode and the second electrode of the data write transistor T5 to be conductive, thereby providing the data signal Vdata to the first electrode S of the driving transistor T1. The invalid pulse of the scan signal S1 controls the transmission path between the first electrode and the second electrode of the data write transistor T5 to be disconnected. That is, under the control of the scan signal S1, the data write transistor T5 selectively provides the data signal Vdata to the first electrode of the driving transistor T1. It should be noted that during the threshold compensation phase, the scan signal S1 is a valid pulse.

[0066] One end of the compensation transistor T6 is connected to the gate of the driving transistor T1 (i.e., the first node N1), and the other end is connected to the second electrode D of the driving transistor T1 (i.e., the third node N3). During the compensation phase, the compensation transistor T6 is turned on and writes the data signal Vdata transmitted to the second electrode S of the driving transistor T1 into the gate of the driving transistor T1. Specifically, the gate of the compensation transistor T6 receives the scan signal S2. The scan signal S2 received by the pixel circuit 10 is a pulse signal. The valid pulse of the scan signal S2 controls the transmission path between the first electrode and the second electrode of the compensation transistor T6 to be conductive, and writes the data signal Vdata into the gate of the driving transistor T1 to adjust the voltage between the gate of the driving transistor T1 and the second electrode D thereof, thereby compensating the threshold voltage of the driving transistor T1. The inactive pulse of the scan signal S2 controls the transmission path between the first electrode and the second electrode of the compensation transistor T6 to be disconnected. That is, under the control of the scan signal S2, the compensation transistor T6 selectively compensates for the threshold voltage of the driving transistor T1. It should be noted that during the threshold compensation phase, the scan signal S2 is a valid pulse.

[0067] One end of the first light-emitting control transistor T7 is connected to a power signal line, and the other end is connected to one end of the driving transistor T1. One end of the second light-emitting control transistor T8 is connected to the other end of the driving transistor, and the other end is connected to the anode of the light-emitting element. During the light-emitting phase, the first light-emitting control transistor T7 transmits the power signal PVDD to the light-emitting element 20, providing a driving current for the light-emitting element 20. Specifically, the gate of the first light-emitting control transistor T7 receives the light-emitting control signal EM. The light-emitting control signal EM received by the pixel circuit is a pulse signal. The active pulse of the light-emitting control signal EM controls the transmission path between the first electrode and the second electrode of the first light-emitting control transistor T7 and the transmission path between the first electrode and the second electrode of the second light-emitting control transistor T8 to conduct, so as to transmit the power signal PVDD to the light-emitting element 20 when the driving transistor T1 is turned on. The inactive pulse of the light-emitting control signal EM controls the transmission path between the first electrode and the second electrode of the first light-emitting control transistor T7 and the transmission path between the first electrode and the second electrode of the second light-emitting control transistor T8 to shut off. That is, under the control of the light-emitting control signal EM, the first light-emitting control transistor T7 and the second light-emitting control transistor T8 selectively provide a driving current to the light-emitting element 20. It should be noted that, in the light emitting stage, the light emitting control signal EM is a valid pulse.

[0068] It should be noted that, in the above embodiment, the driving transistor T1 may be a PMOS transistor or an NMOS transistor. Figure 1 and Figure 4 The pixel circuit shown is a PMOS type transistor in which the driving transistor T1 is a PMOS type transistor. Figure 5 and Figure 6 The pixel circuit shown is a pixel circuit in which the driving transistor T1 is an NMOS transistor; Figure 1 and Figure 5 In the embodiment, the bias adjustment transistor T4 is connected between the second electrode D of the driving transistor T1 and the bias adjustment signal line, and the bias adjustment signal V0 is a high level signal V0H. Figure 4 and Figure 6 In the embodiment of the present invention, the bias adjustment transistor T4 is connected between the first electrode S of the driving transistor T1 and the bias adjustment signal line, and the bias adjustment signal V0 is a low-level signal V0L. When the driving transistor T1 is turned on during the bias adjustment phase, the bias adjustment signal V0 can be transmitted between the first electrode S and the second electrode D of the driving transistor T1.

[0069] Similarly, other transistors in the pixel circuit (such as a reset transistor, an initialization transistor, a bias adjustment transistor, a compensation transistor, a data writing transistor, a first light emission control transistor and / or a second light emission control transistor, etc.) can also be PMOS transistors or NMOS transistors, for example Figure 1 As shown, the initialization transistor T3, the bias adjustment transistor T4, the data writing transistor T5, the first light emission control transistor T7 and the second light emission control transistor T8 are all PMOS, and the reset transistor T2 and the compensation transistor T6 are all NMOS, or, for example Figure 5 As shown, the initialization transistor T3, the data writing transistor T5, the first light-emitting control transistor T7, and the second light-emitting control transistor T8 are all PMOS transistors, and the reset transistor T2, the bias adjustment transistor T4, and the compensation transistor T6 are all NMOS transistors. This application does not limit this, and the specific configuration depends on the specific situation. It should be noted that for a PMOS transistor, the valid pulse received by its gate is a low-level signal, and the invalid pulse received by its gate is a high-level signal. For an NMOS transistor, the valid pulse received by its gate is a high-level signal, and the invalid pulse received by its gate is a low-level signal.

[0070] It should be noted that if Figure 1 As shown, for a PMOS type driving transistor T1, when the pixel circuit 10 is in a non-bias adjustment stage such as a light emitting stage, if the driving transistor T1 is in an on state, that is, in a state where its gate potential is less than the first electrode potential, the driving transistor T1 operates in a non-saturated state, and its second electrode voltage is often less than the gate voltage, resulting in the phenomenon that the PMOS transistor is turned on, but its second electrode voltage is less than the gate voltage. Moreover, the voltage difference between the second electrode voltage of the driving transistor and its gate voltage is often large, and the potential difference is large. Figure 5As shown, for an NMOS-type driving transistor T1, when the pixel circuit 10 is in a non-bias adjustment phase, such as a light-emitting phase, if the driving transistor T1 is in an on state, that is, its gate potential is greater than the first electrode potential, and its second electrode voltage is the PVDD signal, the NMOS transistor is turned on, but the second electrode voltage is greater than the gate voltage. Moreover, the voltage difference between the second electrode voltage of the driving transistor and its gate voltage is often large, resulting in a large potential difference. Such a setting over a long period of time will lead to ion polarization within the driving transistor, thereby forming a built-in electric field within the driving transistor, causing the threshold voltage of the driving transistor to continue to increase.

[0071] like Figure 7 As shown, Figure 7 A schematic diagram shows the drift of the Id-Vg curve of a driver transistor during long-term operation. This shift in the Id-Vg curve of driver transistor T1 affects the drive current flowing into the light-emitting element during the light-emitting phase, thereby affecting the display uniformity. For example, when a black screen switches to a white screen, the display brightness slowly increases, requiring 4-5 frames of data refresh before the brightness stabilizes. Due to this long recovery time, the human eye may notice flickering on the screen.

[0072] In this embodiment, the working process of the pixel circuit 10 includes a bias adjustment stage, Figure 1 Taking the pixel circuit shown as an example, in the bias adjustment phase, the scanning signal SV is a valid pulse, the bias adjustment transistor T4 is turned on, and the bias adjustment signal V0 provided by the bias adjustment signal line is written into the second electrode D of the driving transistor T1 through the turned-on bias adjustment transistor T4, thereby adjusting the potential difference between the second electrode and the gate of the driving transistor T1. It should be noted that when the bias adjustment transistor T4 writes the bias adjustment signal V0 into the first electrode S of the driving transistor T1, if the driving transistor T0 is turned on during the bias adjustment phase, the bias adjustment signal V0 will also be transmitted from the first electrode S of the driving transistor to the second electrode D of the driving transistor, thereby achieving the purpose of adjusting the potential difference between the second electrode and the gate of the driving transistor, resulting in a decrease in the threshold voltage of the driving transistor T1 during the bias adjustment phase, thereby balancing the increase in the threshold voltage of the driving transistor T1 during the non-bias adjustment phase, reducing the offset of the Id-Vg curve, and improving the display uniformity of the display panel.

[0073] It should be noted that, based on the above embodiments, in one embodiment of the present application, when the driving transistor is a PMOS transistor, the bias adjustment signal V0 can be a constant high-level signal, that is, the voltage of the bias adjustment signal V0 is fixed; in other embodiments of the present application, the size of the bias adjustment signal in different bias adjustment stages may also be different. For example, the bias adjustment signal V0 may also be gradual, gradually increasing or decreasing within a certain range of a data refresh cycle; or the bias adjustment signal V0 is a high-level signal with a certain floating range. The present application does not limit this, and it depends on the specific circumstances; optionally, in the present embodiment, the voltage of the bias adjustment signal V0 is higher than the data signal Vdata received by the pixel circuit, so as to achieve the effect of adjusting the threshold voltage offset of the driving transistor faster.

[0074] Similarly, when the driving transistor is an NMOS transistor, the bias adjustment signal V0 can be a constant low-level signal, that is, the voltage of the bias adjustment signal V0 is fixed; or the bias adjustment signal can be of different sizes in different bias adjustment stages. For example, the bias adjustment signal V0 can be gradual, gradually increasing or decreasing within a certain range of a data refresh cycle; or the bias adjustment signal V0 can be a low-level signal with a certain floating range. This application does not limit this, and it depends on the specific situation. Optionally, in this embodiment, the voltage of the bias adjustment signal V0 is lower than the data signal Vdata received by the pixel circuit, so as to achieve the effect of adjusting the threshold voltage offset faster.

[0075] Below is Figure 1 The structure shown is used as an example to describe the relevant working process of adjusting the threshold voltage of the driving transistor in the bias adjustment stage.

[0076] like Figure 1 As shown, the driving transistor T1 is a PMOS transistor, and the bias adjustment signal V0 is a high-level signal V0H. During the bias adjustment phase, the compensation transistor T6 is turned off, and the second electrode D of the driving transistor T1 receives the high-level signal V0H. At this time, compared to the non-bias adjustment phase, during the bias adjustment phase, the potential of the second electrode of the driving transistor T1 is increased to a certain extent, thereby adjusting the potentials of the gate, first electrode S, and second electrode D of the driving transistor T1 during the bias adjustment phase. Optionally, the potential of the second electrode of the driving transistor T1 is higher than the potential of its gate, that is, the potential of the third node N3 is higher than the potential of the first node N1, so that the driving transistor T1 is reverse-biased, thereby reducing the degree of ion polarization within the driving transistor T1 and lowering the threshold voltage of the driving transistor T1. By biasing the driving transistor T1, the threshold voltage of the driving transistor T1 is adjusted, and the potential difference between the gate potential and the second electrode potential of the driving transistor T1 is improved.

[0077] Optionally, based on the above embodiments, in one embodiment of the present application, the reset signal line can be multiplexed as an initialization signal line, specifically: the first reset signal line is multiplexed as the first initialization signal line, and the second reset signal line is multiplexed as the second initialization signal line, so as to reduce the number of signal lines in the display panel, but the present application is not limited to this. In other embodiments of the present application, the first reset signal line and the first initialization signal line can also be two independent signal lines. Similarly, the second reset signal line and the second initialization signal line are two independent signal lines, depending on the specific circumstances.

[0078] It should be noted that, in the pixel circuits of the above-mentioned embodiments, the reset transistor and the bias adjustment transistor are two independent transistors, but the present application does not limit this. In other embodiments of the present application, the reset transistor can also be reused as a bias adjustment transistor to reduce the number of transistors in the pixel circuit and simplify the structure of the pixel circuit, depending on the specific circumstances.

[0079] The following describes the case where the reset transistor is multiplexed as a bias adjustment transistor in conjunction with a specific circuit structure.

[0080] like Figures 8-13 As shown, in the embodiment of the present application, the pixel circuit includes a reset transistor T2, an initialization transistor T3, and a compensation transistor T6; wherein the reset transistor T2 is connected between the reset signal line and the first electrode S or the second electrode D of the driving transistor T1, the compensation transistor T6 is connected between the gate and the second electrode D of the driving transistor T1, and the initialization transistor T3 is connected between the initialization signal line and the light-emitting element 20. It should be noted that, in the embodiment of the present application, the operation process of the pixel circuit includes a bias adjustment stage. During the bias adjustment stage, the reset transistor T2 is multiplexed as the bias adjustment transistor T4, and the reset signal line is multiplexed as the bias adjustment signal line. Specifically, the reset transistor of the first display area is multiplexed as the bias adjustment transistor of the first display area, and the first reset signal line is multiplexed as the first bias adjustment signal line; the reset transistor of the second display area is multiplexed as the bias adjustment transistor of the second display area, and the second reset signal line is multiplexed as the second bias adjustment signal line.

[0081] It should be noted that when the first reset signal line is multiplexed as the first bias adjustment signal line, the resistivity of the first reset signal line is the same as the resistivity of the first bias adjustment signal line, that is, ρ11=ρ13; similarly, when the second reset signal line is multiplexed as the second bias adjustment signal line, the resistivity of the second reset signal line is the same as the resistivity of the second bias adjustment signal line, that is, ρ21=ρ23.

[0082] In addition, in the display panel provided in the embodiment of the present application, the pixel circuit further includes: a data writing transistor T5, a first light-emitting control transistor T7, and a second light-emitting control transistor T8; wherein the data writing transistor T5 is connected between the data signal line and the first electrode S of the driving transistor T1, the first light-emitting control transistor T7 is connected between the power signal line and the first electrode S or the second electrode D of the driving transistor T1, and the second light-emitting control transistor T8 is connected between the second electrode D or the first electrode S of the driving transistor T1 and the light-emitting element 20.

[0083] As can be seen from the above, the working process of the pixel circuit includes a pre-stage and a light-emitting stage, wherein the pre-stage includes a reset stage, an initialization stage, a bias adjustment stage and a threshold compensation stage. Figure 1 、 Figure 4-Figure 6 The pixel circuit shown is similar, and this application will not go into details. The following describes the relevant processes of the pixel circuit working in the reset stage and the bias adjustment stage when the reset transistor is multiplexed as a bias adjustment transistor.

[0084] Specifically, such as Figure 8 As shown, in the reset phase, the scanning signal S3 is a valid pulse signal, and the scanning signal S2 is a valid pulse signal, the reset transistor T2 is in the on state, the transmission path between the first electrode and the second electrode of the reset transistor T2 is conductive, and the compensation transistor T6 is in the on state, the transmission path between the first electrode and the second electrode of the compensation transistor T6 is conductive, the reset signal Vref passes through the reset transistor T2 and the compensation transistor T6 in sequence to reach the gate of the driving transistor T1, and resets the gate of the driving transistor T1. After the gate of the driving transistor T1 is reset, the compensation transistor T6 is turned off.

[0085] In the bias adjustment stage, the scanning signal S3 is a valid pulse signal, and the scanning signal S2 is an invalid pulse signal. The reset transistor T2 is in the on state, and the transmission path between the first electrode and the second electrode of the reset transistor T2 is conductive. The compensation transistor T6 is in the off state, and the transmission path between the first electrode and the second electrode of the compensation transistor T6 is disconnected. The reset signal Vref passes through the reset transistor T2 and reaches the first electrode S or the second electrode D of the driving transistor T1, providing the bias adjustment signal Vref to the first electrode S or the second electrode D of the driving transistor T1, thereby achieving the purpose of adjusting the potential difference between the second electrode and the gate of the driving transistor T1, so that the threshold voltage of the driving transistor T1 is reduced in the bias adjustment stage, thereby balancing the increment of the threshold voltage of the driving transistor T1 in the non-bias adjustment stage, reducing the offset degree of the Id-Vg curve, and improving the display uniformity of the display panel.

[0086] It can be seen that in this embodiment, the reset transistor can be reused as a bias adjustment transistor, and the reset signal line can be reused as the bias adjustment signal line, thereby reducing the number of transistors and signal lines in the display panel while improving the display uniformity of the display panel, and reducing the difficulty of layout of transistors and signal lines in the display panel.

[0087] It should be noted that, in the above embodiment, the driving transistor T1 may be a PMOS transistor or an NMOS transistor. Figure 8 and Figure 9 The pixel circuit shown is a PMOS type transistor in which the driving transistor T1 is a PMOS type transistor. Figure 10 and Figure 11 The pixel circuit shown is a pixel circuit in which the driving transistor T1 is an NMOS transistor; Figure 8 and Figure 10 In the embodiment, the reset transistor T2 is connected between the second electrode D of the driving transistor T1 and the reset signal line. In the reset phase, the reset signal Vref is a low-level signal. In the bias adjustment phase, the reset signal Vref is a high-level signal V0H. Figure 9 and Figure 11 In the embodiment, the reset transistor T2 is connected between the first electrode S of the driving transistor T1 and the reset signal line. In the reset phase, the reset signal Vref is a low level signal. In the bias adjustment phase, the reset signal Vref is also a low level signal.

[0088] It should also be noted that the reset transistor T2 may also be a PMOS transistor or an NMOS transistor. Figure 8 、 Figure 9 、 Figure 12 and Figure 13 The pixel circuit shown is a PMOS type transistor in which the reset transistor T2 is a PMOS type transistor. Figure 10 and Figure 11 The pixel circuit shown is one in which the reset transistor T2 is an NMOS transistor.

[0089] Similarly, other transistors in the pixel circuit (such as data writing transistors, compensation transistors, initialization transistors, first light-emitting control transistors, second light-emitting control transistors, etc.) can also be PMOS transistors or NMOS transistors. This application does not limit this, and it depends on the specific situation.

[0090] Optionally, based on the above embodiment, in one embodiment of the present application, the reset signal line can be multiplexed as an initialization signal line. Specifically, the first reset signal line can be multiplexed as the first initialization signal line. During the initialization phase, the reset signal Vref input to the first reset signal line is a low-level signal. The second reset signal line can also be multiplexed as the second initialization signal line. During the initialization phase, the reset signal input to the second reset signal line is a low-level signal, so as to further reduce the number of signal lines in the display panel. However, the present application does not limit this. In other embodiments of the present application, the first reset signal line and the first initialization signal line can also be two independent signal lines. Similarly, the second reset signal line and the second initialization signal line are two independent signal lines, depending on the specific circumstances.

[0091] The display panel provided in the embodiment of the present application is described below by taking the reset signal line and the initialization signal line as two independent signal lines as an example.

[0092] As can be seen from the above, during the operation of the display panel, the display of each frame of the display screen includes a pre-stage and a light-emitting element. In the pre-stage, the operation process of the pixel circuit includes a reset stage, an initialization stage, a bias adjustment stage, and a threshold compensation stage. In the reset stage, the reset signal line resets the gate voltage of the driving transistor. In the threshold compensation stage, the gate voltage of the driving transistor is threshold compensated to write the data signal Vdata to the gate of the driving transistor. In the initialization stage, the initialization signal line resets the anode of the light-emitting element so that after entering the light-emitting stage, the driving current received by the light-emitting element is sufficiently accurate to achieve precise light emission and alleviate the flickering phenomenon of the display screen. In the threshold compensation stage, it occurs after the reset stage.

[0093] It can be seen from this that the reset of the anode of the light-emitting element by the initialization signal line directly affects the luminous performance of the light-emitting element. During the display process of each frame of the display image, before entering the light-emitting stage, it is necessary to fully reset the anode of the light-emitting element using the initialization signal line through the initialization transistor to ensure that the driving current received by the light-emitting element is accurate enough when each frame of the display image is displayed, so that the light-emitting element emits light accurately and reduces the probability of flickering on the display image. After the reset signal line resets the gate of the driving transistor, the gate of the driving transistor will also receive the data write signal in the threshold compensation stage, that is, the reset voltage of the gate of the driving transistor by the reset signal line does not directly affect the display of the display image of the data holding frame. That is, compared with the gate reset process of the driving transistor, the anode reset process of the light-emitting element has a greater impact on the driving current of the light-emitting element and a greater impact on the display quality of the display image. That is, compared with the driving transistor, the state switching performance of the initialization transistor has a greater impact on the display quality of the display image. Accordingly, compared with the reset signal line, the initialization signal line has higher requirements on resistivity.

[0094] In this embodiment, based on ρ11+ρ12+ρ13≤ρ21+ρ22+ρ23, optionally, ρ11<ρ21, and / or, ρ12<ρ22, and / or, ρ13<ρ23, that is, the first reset signal line and the second reset signal line are located in different film layers, and / or, the first initialization signal line and the second initialization signal line are located in different film layers, and / or, the first bias adjustment signal line and the second bias adjustment signal line are located in different film layers.

[0095] Based on this, in an optional embodiment of the present application, ρ11>ρ12, so that the first initialization signal line with higher resistivity requirement is set in the film layer with lower signal resistivity, and the first reset signal line with relatively lower resistivity requirement is set in the film layer with larger resistivity, thereby further reducing the number of signal lines in the film layer where the first initialization signal line is located on the basis of giving priority to ensuring the working performance of the initialization transistor that has a greater impact on the display quality of the display screen in the pixel circuit, so as to facilitate the layout of the first initialization signal line and the setting of the transparent area of ​​the second display area.

[0096] Similarly, in an optional embodiment of the present application, ρ21>ρ22, so that the second initialization signal line with higher resistivity requirements is set in a film layer with lower signal resistivity, and the second reset signal line with relatively lower resistivity requirements is set in a film layer with larger resistivity, thereby further reducing the number of signal lines in the film layer where the second initialization signal line is located on the basis of giving priority to ensuring the working performance of the initialization transistor that has a greater impact on the display quality of the display screen in the pixel circuit, so as to facilitate the layout of the second initialization signal line and the setting of the transparent area of ​​the second display area.

[0097] It should be noted that during the operation of the pixel circuit, the bias adjustment phase occurs before the threshold compensation phase and is used to adjust the potential difference between the second electrode and the gate of the driving transistor T1, thereby reducing the threshold voltage of the driving transistor T1. This balances the threshold voltage increment of the driving transistor T1 during the non-bias adjustment phase and reduces the offset of the Id-Vg curve of the driving transistor. The Id-Vg curve of the driving transistor directly affects the display uniformity of the display panel.

[0098] As can be seen from this, during the bias adjustment phase, the bias adjustment transistor adjusts the electric field within the drive transistor, thereby adjusting the Id-Vg curve of the drive transistor and, in turn, adjusting the display uniformity of the display panel. Therefore, compared to the gate reset process of the drive transistor, the bias adjustment process of the drive transistor has a greater impact on the display quality of the display image. In other words, compared to the drive transistor, the state switching performance of the bias adjustment transistor has a greater impact on the display quality of the display image. Accordingly, compared to the reset signal line, the bias adjustment signal line has a higher resistivity requirement.

[0099] Based on this, in an optional embodiment of the present application, ρ11>ρ13, so that the first bias adjustment signal line with higher resistivity requirement is set in the film layer with lower signal resistivity, and the first reset signal line with relatively lower resistivity requirement is set in the film layer with larger resistivity, thereby further reducing the number of signal lines in the film layer where the first bias adjustment signal line is located on the basis of giving priority to ensuring the working performance of the bias adjustment transistor that has a greater impact on the display quality of the display screen in the pixel circuit, so as to facilitate the layout of the first bias adjustment signal line and the setting of the transparent area of ​​the second display area.

[0100] Similarly, in an optional embodiment of the present application, ρ21>ρ23, so that the second bias adjustment signal line with higher resistivity requirements is set in a film layer with lower signal resistivity, and the second reset signal line with relatively lower resistivity requirements is set in a film layer with larger resistivity, thereby further reducing the number of signal lines in the film layer where the second bias adjustment signal line is located on the basis of giving priority to ensuring the working performance of the bias adjustment transistor that has a greater impact on the display quality of the display screen in the pixel circuit, so as to facilitate the layout of the second bias adjustment signal line and the setting of the transparent area of ​​the second display area.

[0101] It should be noted that, as can be seen from the foregoing, while the state switching performance of the bias adjustment transistor and the initialization transistor both directly affect the uniformity of the display image, the initialization transistor is directly connected to the anode of the light-emitting element and has a greater impact on the drive current of the light-emitting element. Therefore, compared with the bias adjustment transistor, the state switching performance of the initialization transistor has a greater impact on the display quality. Accordingly, compared with the bias adjustment signal line, the initialization signal line has a higher resistivity requirement.

[0102] Based on this, in an optional embodiment of the present application, ρ13>ρ12, so that the first initialization signal line with higher resistivity requirement is set in the film layer with lower signal resistivity, and the first bias adjustment signal line with relatively lower resistivity requirement is set in the film layer with larger resistivity, thereby further reducing the number of signal lines in the film layer where the first initialization signal line is located on the basis of giving priority to ensuring the working performance of the initialization transistor that has a greater impact on the display quality of the display screen in the pixel circuit, so as to facilitate the layout of the first initialization signal line and the setting of the transparent area of ​​the second display area.

[0103] Similarly, in an optional embodiment of the present application, ρ23>ρ22, so that the second initialization signal line with higher resistivity requirements is set in a film layer with lower signal resistivity, and the second bias adjustment signal line with relatively lower resistivity requirements is set in a film layer with higher resistivity, thereby further reducing the number of signal lines in the film layer where the second initialization signal line is located on the basis of giving priority to ensuring the working performance of the initialization transistor that has a greater impact on the display quality of the display screen in the pixel circuit, so as to facilitate the layout of the second initialization signal line and the setting of the transparent area of ​​the second display area.

[0104] As can be seen from the above, among the reset signal line, the initialization signal line and the bias adjustment signal line, the initialization signal line has the highest requirement on resistivity, the bias adjustment signal line has the second highest requirement on resistivity, and the reset signal line has an even lower requirement on resistivity. Therefore, in an optional embodiment of the present application, ρ11>ρ12 and ρ11>ρ13, and / or, ρ21>ρ22 and ρ21>ρ23, so that the initialization signal line and the bias adjustment signal line with higher resistivity requirements are set in the film layer with lower signal resistivity, and the reset signal line with relatively lower resistivity requirements is set in the film layer with higher resistivity, so as to give priority to ensuring the working performance of the initialization transistor and the bias adjustment transistor in the pixel circuit that have a greater impact on the display quality of the display screen, and further reduce the number of signal lines in the film layer where the initialization signal line is located, so as to facilitate the layout of the initialization signal line and the setting of the transparent area of ​​the second display area.

[0105] In another optional embodiment of the present application, ρ11>ρ13>ρ12 and / or ρ21>ρ23>ρ22, so that signal lines with different resistivity requirements are set on different film layers, such as the initialization signal line with the highest resistivity requirement is set on the film layer with the smallest signal resistivity, the bias adjustment signal line with the second highest resistivity requirement is set on the film layer with the second smallest signal resistivity, and the reset signal line with the lowest resistivity requirement is set on the film layer with the largest resistivity. The present application does not impose any restrictions on this, and it depends on the specific situation.

[0106] Since the first display area has a low transmittance requirement and is primarily used for display, the second display area is provided with a transmissive area and, in addition to being used for display, also requires light transmittance. Therefore, in the embodiments of the present application, the display panel has higher resistivity requirements for the signal lines that provide signals to the pixel circuits in the first display area than for the signal lines that provide signals to the pixel circuits in the second display area. Furthermore, as can be seen from the foregoing, the bias adjustment signal line has an intermediate resistivity requirement among the reset signal line, the initialization signal line, and the bias adjustment signal line.

[0107] Therefore, in an optional embodiment of the present application, (ρ23-ρ13)>(ρ22-ρ12) and / or (ρ23-ρ13)>(ρ21-ρ11), further, (ρ23-ρ13)>(ρ22-ρ12)≥(ρ21-ρ11), so that the first bias adjustment signal line of the first display area is set on a film layer with a smaller signal line resistivity, and the second bias signal line of the second display area is set on a film layer with a larger signal line resistivity. Specifically, the first initialization signal line and the second initialization signal line are set in the same film layer, the first reset signal line and the second reset signal line are set in the same film layer, and the first bias adjustment signal line and the second bias adjustment signal line are set in different film layers, so as to take into account the number of signal lines on the film layer with a smaller signal line resistivity and the overall quality of the display screen of the display panel.

[0108] It should be noted that when the first initialization signal line and the second initialization signal line are arranged in the same film layer, and the first reset signal line and the second reset signal line are arranged in the same film layer, the first initialization signal line and the second initialization signal line are arranged in a film layer with a smaller resistivity, and the first reset signal line and the second reset signal line are arranged in a film layer with a larger resistivity, but the present application does not limit this. In other embodiments of the present application, the first initialization signal line, the second initialization signal line, the first reset signal line and the second reset signal line can also be arranged in other ways, depending on the specific circumstances.

[0109] In addition, in other embodiments, the following may exist: (ρ22-ρ12)>(ρ21-ρ11), and / or (ρ22-ρ12)>(ρ23-ρ13); further, (ρ22-ρ12)>(ρ23-ρ13)≥(ρ21-ρ11), in which case the first initialization signal line and the second initialization signal line are located in different film layers; the following may also exist: (ρ21-ρ11)>(ρ22-ρ12), and / or (ρ21-ρ11)>(ρ23-ρ13), further, (ρ21-ρ11)>(ρ23-ρ13)≥(ρ22-ρ12), in which case the first reset signal line and the second reset signal line are located in different film layers.

[0110] Based on any of the above embodiments, in one embodiment of the present application, Figure 14 As shown, when projected onto a plane parallel to the surface of the display panel, the spacing between the first reset signal line and the first initialization signal line is D11, the spacing between the first initialization signal line and the first bias adjustment signal line is D12, and the spacing between the first reset signal line and the first bias adjustment signal line is D13; when projected onto a plane parallel to the surface of the display panel, the spacing between the second reset signal line and the second initialization signal line is D21, the spacing between the second initialization signal line and the second bias adjustment signal line is D22, and the spacing between the second reset signal line and the second bias adjustment signal line is D23.

[0111] As can be seen from the above, the first display area mainly needs to realize the display function and does not have high requirements for transmittance. Therefore, the layout of the signal lines in the first display area mainly considers the signal transmission signal, such as trying to set them on a film layer with a small resistivity of the signal line and the insulation effect between adjacent signal lines. The second display area not only needs to realize the display function, but also has a transmission area and needs to realize the light transmission function. Therefore, the layout of the signal lines in the second display area also needs to consider the area of ​​the transmission area.

[0112] Therefore, in one embodiment of the present application, when projected onto a plane parallel to the surface of the display panel, the distance between the first reset signal line and the first initialization signal line is greater than the distance between the second reset signal line and the second initialization signal line, that is, D11>D21, so that there is a larger distance between the first reset signal line and the first initialization signal line in the first display area, reducing the probability of short circuit between the first reset signal line and the first initialization signal line and reducing parasitic capacitance, ensuring that the first reset signal line and the first initialization signal line are insulated from each other, and having a smaller distance between the second reset signal line and the second initialization signal line in the second display area, reducing the space occupied by the second reset signal line and the second initialization signal line, so that there is more space in the second display area to set the transmission area, thereby increasing the area of ​​the transmission area.

[0113] On the basis of any of the above embodiments, in one embodiment of the present application, when projected onto a plane parallel to the surface of the display panel, the spacing between the first initialization signal line and the first bias adjustment signal line is greater than the spacing between the second initialization signal line and the second bias adjustment signal line, that is, D12>D22, so that the first initialization signal line and the first bias adjustment signal line in the first display area have a larger spacing, reducing the probability of short circuit between the first initialization signal line and the first bias adjustment signal line and reducing parasitic capacitance, ensuring that the first initialization signal line and the first bias adjustment signal line are insulated from each other, and having a smaller spacing between the second initialization signal line and the second bias adjustment signal line in the second display area, reducing the space occupied by the second initialization signal line and the second bias adjustment signal line, so that the second display area can have more space to set the transmission area, thereby increasing the area of ​​the transmission area.

[0114] On the basis of any of the above embodiments, in one embodiment of the present application, when projected onto a plane parallel to the surface of the display panel, the spacing between the first reset signal line and the first bias adjustment signal line is greater than the spacing between the second reset signal line and the second bias adjustment signal line, that is, D13>D23, so that there is a larger spacing between the first reset signal line and the first bias adjustment signal line in the first display area, reducing the probability of short circuit between the first reset signal line and the first bias adjustment signal line and reducing parasitic capacitance, ensuring that the first reset signal line and the first bias adjustment signal line are insulated from each other, and having a smaller spacing between the second reset signal line and the second bias adjustment signal line in the second display area, reducing the space occupied by the second reset signal line and the second bias adjustment signal line, so that there is more space in the second display area to set the transmission area, thereby increasing the area of ​​the transmission area.

[0115] Based on any of the above embodiments, in one embodiment of the present application, Figure 15As shown, in the direction X perpendicular to the surface of the display panel, the second reset signal line 41 and the second initialization signal line 42 at least partially overlap, so as to ensure the mutual insulation of the second reset signal line 41 and the second initialization signal line 42 by arranging the second reset signal line 41 and the second initialization signal line 42 on different film layers, and in the direction X perpendicular to the surface of the display panel, the second reset signal line 41 and the second initialization signal line 42 at least partially overlap, so as to further reduce the space occupied by the second reset signal line 41 and the second initialization signal line 42 when projected onto a plane parallel to the surface of the display panel, so that there is more space in the second display area to set the transmission area, thereby increasing the area of ​​the transmission area.

[0116] Optionally, the signal lines of the film layer where the second reset signal line and the second initialization signal line are located have different resistivities, that is, the second reset signal line and the second initialization signal line are located on film layers with different resistivities, but this application does not limit this and it depends on the specific situation.

[0117] Based on any of the above embodiments, in one embodiment of the present application, Figure 16 As shown, in the direction X perpendicular to the surface of the display panel, the second reset signal line 41 and the second bias adjustment signal line 43 at least partially overlap, so as to ensure the mutual insulation of the second reset signal line 41 and the second bias adjustment signal line 43 by arranging the second reset signal line 41 and the second bias adjustment signal line 43 on different film layers, and in the direction X perpendicular to the surface of the display panel, the second reset signal line 41 and the second bias adjustment signal line 43 at least partially overlap, so as to further reduce the space occupied by the second reset signal line 41 and the second bias adjustment signal line 43 when projected onto a plane parallel to the surface of the display panel, so that the second display area can have more space to set the transmission area, thereby increasing the area of ​​the transmission area.

[0118] Optionally, the signal lines of the film layer where the second reset signal line and the second bias adjustment signal line are located have different resistivities, that is, the second reset signal line and the second bias adjustment signal line are located on film layers with different resistivities, but this application does not limit this and it depends on the specific situation.

[0119] Based on any of the above embodiments, in one embodiment of the present application, Figure 17As shown, in the direction X perpendicular to the surface of the display panel, the second initialization signal line 42 and the second bias adjustment signal line 43 at least partially overlap, so as to ensure the mutual insulation of the second initialization signal line 42 and the second bias adjustment signal line 43 by arranging the second initialization signal line 42 and the second bias adjustment signal line 43 on different film layers, and in the direction X perpendicular to the surface of the display panel, the second initialization signal line 42 and the second bias adjustment signal line 43 at least partially overlap, so as to further reduce the space occupied by the second initialization signal line 42 and the second bias adjustment signal line 43 when projected onto a plane parallel to the surface of the display panel, so that the second display area can have more space to set the transmission area, thereby increasing the area of ​​the transmission area.

[0120] Optionally, the signal lines of the film layer where the second initialization signal line and the second bias adjustment signal line are located have different resistivities, that is, the second initialization signal line and the second bias adjustment signal line are located on film layers with different resistivities, but this application does not limit this and it depends on the specific situation.

[0121] Based on any of the above embodiments, in one embodiment of the present application, the first reset signal line and the second reset signal line are located in different film layers to reduce the number of signal lines in the film layer where the first reset signal line is located, facilitate the layout of the first reset signal line, and reduce the probability of the first reset signal line short-circuiting. Similarly, the first initialization signal line and the second initialization signal line are located in different film layers to reduce the number of signal lines in the film layer where the first initialization signal line is located, facilitate the layout of the first initialization signal line, and reduce the probability of the first initialization signal line short-circuiting. The first bias adjustment signal line and the second bias adjustment signal line are located in different film layers to reduce the number of signal lines in the film layer where the first bias adjustment signal line is located, facilitate the layout of the first bias adjustment signal line, and reduce the probability of the first bias adjustment signal line short-circuiting.

[0122] Optionally, in one embodiment of the present application, at least one of the three signal lines, namely the reset signal line, the initialization signal line and the bias adjustment signal line, has a portion located in the first display area and a portion located in the second display area located in different layers, such as the first reset signal line and the second reset signal line are located in different film layers, and / or the first initialization signal line and the second initialization signal line are located in different film layers, and / or the first bias adjustment signal line and the second bias adjustment signal line are located in different film layers.

[0123] In another embodiment of the present application, at least two of the three signal lines, namely the reset signal line, the initialization signal line and the bias adjustment signal line, are located in different layers in the portion located in the first display area and in the portion located in the second display area, such as the first reset signal line and the second reset signal line are located in different film layers and the first initialization signal line and the second initialization signal line are located in different film layers, and / or, the first reset signal line and the second reset signal line are located in different film layers and the first bias adjustment signal line and the second bias adjustment signal line are located in different film layers, and / or, the first initialization signal line and the second initialization signal line are located in different film layers and the first bias adjustment signal line and the second bias adjustment signal line are located in different film layers.

[0124] In another embodiment of the present application, the parts of the three signal lines, namely the reset signal line, the initialization signal line and the bias adjustment signal line, located in the first display area and the parts thereof located in the second display area are all located in different layers, that is, the first reset signal line and the second reset signal line are located in different film layers, and the first initialization signal line and the second initialization signal line are located in different film layers, and the first bias adjustment signal line and the second bias adjustment signal line are located in different film layers.

[0125] Based on any of the above embodiments, in one embodiment of the present application, at least two of the first reset signal line, the first initialization signal line and the first bias adjustment signal line are located in the same layer, so that at least two of the first reset signal line, the first initialization signal line and the first bias adjustment signal line are located on a film layer with a smaller signal line resistivity to ensure the display characteristics of the first display area.

[0126] Based on any of the above embodiments, in one embodiment of the present application, the second reset signal line, the second initialization signal line, and the second bias adjustment signal line are all located on different film layers to reduce the number of signal lines on the film layer where the signal lines of the second display area are located, thereby reducing the space occupied by the signal lines of the second display area on the film layer where they are located, so that the second display area has more areas for setting the transmission area to ensure the area of ​​the transmission area.

[0127] Optionally, in one embodiment of the present application, two of the first reset signal line, the first initialization signal line and the first bias adjustment signal line are located in the first film layer, and the other is located in the second film layer, wherein the resistivity of the first film layer is less than the resistivity of the second film layer, thereby making the resistivity of at least two of the first reset signal line, the first initialization signal line and the first bias adjustment signal line smaller, so as to ensure the display characteristics of the first display area.

[0128] As can be seen from the above, among the reset signal line, the initialization signal line and the bias adjustment signal line, the initialization signal line has the highest requirement for resistivity, and the bias adjustment signal line has the second highest requirement for resistivity. Figure 18 As shown, the first initialization signal line 32 and the first bias adjustment signal line 33 are located in the first film layer 51, and the first reset signal line 31 is located in the second film layer 52, so as to maximize the display characteristics of the first display area on the basis of placing only two signal lines among the first initialization signal line 32, the first bias adjustment signal line 33 and the first reset signal line 31 on the first film layer 51, but the present application is not limited to this. In other embodiments of the present application, the first reset signal line and the first initialization signal line may be located in the first film layer, and the first bias adjustment signal line may be located in the second film layer; or the first reset signal line and the first bias adjustment signal line may be located in the first film layer, and the first initialization signal line may be located in the second film layer, depending on the specific circumstances.

[0129] On the basis of any of the above embodiments, in one embodiment of the present application, the second reset signal line is located in the third film layer, the second initialization signal line is located in the fourth film layer, and the second bias adjustment signal line is located in the fifth film layer. As can be seen from the foregoing, among the reset signal line, the initialization signal line and the bias adjustment signal line, the initialization signal line has the highest requirement on resistivity, and the bias adjustment signal line has the second highest requirement on resistivity. Therefore, in an optional embodiment of the present application, the resistivity of the fourth film layer is less than that of the fifth film layer, and / or the resistivity of the fifth film layer is less than that of the third film layer, so that the display characteristics of the second display area are ensured by placing the second reset signal line, the second initialization signal line and the second bias adjustment signal line on the basis of film layers with different resistivities and rationally arranging the resistivities of the film layers where the second reset signal line, the second initialization signal line and the second bias adjustment signal line are located. However, the present application does not limit this and it depends on the specific circumstances.

[0130] As can be seen from the foregoing, among the reset signal line, the initialization signal line and the bias adjustment signal line, the initialization signal line has the highest requirement for resistivity. Therefore, based on the above embodiment, in one embodiment of the present application, the fourth film layer and the first film layer are the same film layer, so that the first initialization signal line and the second initialization signal line 2 are both set on the same film layer with a lower resistivity, such as Figure 19 As shown, the first initialization signal line 32 and the second initialization signal line 42 are both arranged on the first film layer 51, thereby improving the state switching performance of the initialization transistor, thereby improving the display characteristics of the first display area and the second display area.

[0131] Since the bias adjustment signal line has the lowest resistivity requirement among the reset signal line, the initialization signal line, and the bias adjustment signal line, based on any of the above embodiments, in one embodiment of the present application, the third film layer and the second film layer are the same film layer, so that the first bias adjustment signal line and the second bias adjustment signal line are disposed on a film layer with an intermediate resistivity, that is, the first bias adjustment signal line and the second bias adjustment signal line are disposed on the second film layer. This reduces the number of signal lines on the film layer with a lower resistivity, thereby ensuring that the resistivity of the first bias adjustment signal line and the second bias adjustment signal point is not too high, thereby ensuring the display characteristics of the first display area and the second display area. However, this application does not impose any limitation on this, and the specific circumstances will determine it.

[0132] It should be noted that the key parameter on the signal line that determines its signal transmission rate is the resistance of the signal line, and the factors affecting the resistance of the signal line include not only the resistivity of the signal line but also the line width of the signal line. Among them, under the premise that other parameters except the resistivity are fixed, the smaller the resistivity of the signal line, the smaller the resistance of the signal line; under the premise that other parameters except the line width are fixed, the larger the line width of the signal line, the smaller the resistance of the signal line.

[0133] Based on any of the above embodiments, in one embodiment of the present application, Figure 20 As shown, the line width of the first reset signal line 31 is W11, the line width of the first initialization signal line 32 is W12, and the spacing between the first bias adjustment signal lines 33 is W13; the line width of the second reset signal line 41 is W21, the line width of the second initialization signal line 42 is W22, and the line width of the second bias adjustment signal line 43 is W23; wherein W11+W12+W13>W21+W22+W23, so as to increase the width of at least one of the first reset signal line 31, the first initialization signal line 32 and the first bias adjustment signal line 33. By reducing the line width of the first reset signal line 31, the first initialization signal line 32, and the first bias adjustment signal line 33 in the first display area 100, the display characteristics of the first display area 100 are ensured. By reducing the line width of at least one of the second reset signal line 41, the second initialization signal line 42, and the second bias adjustment signal line 43, the space occupied by the second reset signal line 41, the second initialization signal line 42, and the second bias adjustment signal line 43 in the second display area 200 is reduced, so as to facilitate the setting of the transmission area of ​​the second display area and ensure the light transmittance of the second display area 200. However, this is not limited to this in the present application and it depends on the specific situation.

[0134] Since the display characteristic requirements of the first display area are higher than those of the second display area, optionally, on the basis of the above embodiment, in one embodiment of the present application, the line width of at least one of the first reset signal line, the first initialization signal line and the first bias adjustment signal line is greater than the signal line of the same type in the corresponding second display area, such as the line width of the first reset signal line is greater than the line width of the second reset signal line, and / or the line width of the first initialization signal line is greater than the line width of the second initialization signal line, and / or the line width of the first bias adjustment signal line is greater than the line width of the second bias adjustment signal line, that is, W11>W21 and / or W12>W22 and / or W13>W23, so as to improve the display characteristics of the first display area by increasing the line width of at least one of the first reset signal line, the first initialization signal line and the first bias adjustment signal line, and reduce the total space occupied by the second reset signal line, the second initialization signal line and the second bias adjustment signal line in the second display area by reducing the line width of at least one of the second reset signal line, the second initialization signal line and the second bias adjustment signal line, so that the second display area can have more space to set the transmission area, thereby ensuring the light transmittance of the second display area.

[0135] Since the first display area is not provided with a transmissive area and is only used for display functions, the second display area is provided with a transmissive area. Besides being used for display functions, light transmission performance must also be considered. Therefore, in the embodiments of the present application, the display panel has higher resistivity requirements for the signal lines that provide signals to the pixel circuits in the first display area than for the signal lines that provide signals to the pixel circuits in the second display area. Furthermore, as can be seen from the foregoing, the resistivity requirement for the bias adjustment signal line is intermediate among the reset signal line, the initialization signal line, and the bias adjustment signal line.

[0136] Therefore, in an optional embodiment of the present application, (W11-W21)>

[0137] (W13-W23)≥(W12-W22), so as to reduce the line width of the second reset signal line to a first extent, reduce the line width of the second initialization signal line to a second extent, and reduce the line width of the second bias adjustment signal line to a third extent, wherein the first extent is greater than the third extent, and the third extent is not less than the second extent, thereby reducing the line width of each signal line in the second display area, ensuring the transmittance of the second display area, and taking into account the display characteristics of the second display area, but this application does not limit this, and it depends on the specific situation.

[0138] Based on any of the above embodiments, in one embodiment of the present application, Figure 21As shown, the second display area 200 includes pixel islands 60 located between the transmissive areas 201 and connecting bridges 70 connecting the pixel islands 60. The pixel islands 60 located on both sides of the transmissive area 201 are connected via the connecting bridges 70, so that the pixel islands 60 located on both sides of the transmissive area 201 can be controlled by the same signal line. Optionally, in this embodiment, the pixel islands 60 include N sub-pixels 80, where N ≥ 1, and the pixel islands include pixel circuits.

[0139] Specifically, based on the above embodiment, in one embodiment of the present application, continue as follows Figure 21 As shown, the second reset signal line 41 extends along the connecting bridge 70 and is connected to the pixel island 60 to provide a reset signal for the pixel circuit 10 of each sub-pixel 80 included in the pixel island 60; similarly, the second initialization signal line 42 extends along the connecting bridge 70 and is connected to the pixel island 60 to provide an initialization signal for the pixel circuit 10 of each sub-pixel 80 included in the pixel island 60; the second bias adjustment signal line 43 extends along the connecting bridge 70 and is connected to the pixel island 60 to provide a bias adjustment signal for the pixel circuit 10 of each sub-pixel 80 included in the pixel island 60.

[0140] refer to Figure 22 , Figure 22This is a partial top view of a display panel provided in yet another embodiment of the present application, in which the second display area 200 includes a transition region 202, which includes a pixel circuit 10. The pixel circuit 10 is used to provide signals to the sub-pixels 80 in the second display area 200. A second reset signal line 41, a second initialization signal line 42, and a second bias adjustment signal line 43 are connected to the pixel circuit 10. In this embodiment, to prevent the pixel circuit 10 from affecting the transmittance of the transmissive area, the transition region 202 is provided, and the pixel circuit 10 is located within the transition region 202. In this case, the second reset signal line 41, the second initialization signal line 42, and the second bias adjustment signal line 43 pass through the transition region 202 and connect to the pixel circuit 10. In this embodiment, optionally, the line width of the first reset signal line 31 is W11, the line width of the first initialization signal line 32 is W12, and the spacing between the first bias adjustment signal lines 33 is W13; the line width of the second reset signal line 41 is W21, the line width of the second initialization signal line 42 is W22, and the line width of the second bias adjustment signal line 43 is W23; wherein, W11+W12+W13<W21+W22+W23. Therefore, the second reset signal line 41, the second initialization signal line 42, and the second bias adjustment signal line 43 need to pass through the transition region 202 to be connected to the pixel circuit 10. In some cases, winding may be required, which may cause the wiring length to be extended and the wiring resistance to increase. In order to ensure uniform display effects in the first display area and the second display area and balance the wiring resistance, it is necessary to appropriately widen the width of at least one of the second reset signal line 41, the second initialization signal line 42, and the second bias adjustment signal line 43, so that W11+W12+W13<W21+W22+W23.

[0141] In this embodiment, optionally, W11 < W21, and / or W12 < W22, and / or W13 < W23. By appropriately widening the line widths of the second reset signal line 41, the second initialization signal line 42, and the second bias adjustment signal line 43, the resistance of the wiring in the first display area and the second display area is balanced, ensuring uniform display effects in the first display area and the second display area.

[0142] In addition, in this embodiment, optionally, W22-W12>W21-W11, and / or, W23-W13>W21-W11. As shown above, among the second reset signal line 41, the second initialization signal line 42, and the second bias adjustment signal line 43, the resistivity requirement for the second initialization signal line 42 is the most stringent, followed by the second bias adjustment signal line 43, and then the second reset signal line 41. Therefore, in this application, the degree of widening of the second initialization signal line 42 compared to the first initialization signal line 32 can be greater than the degree of widening of the second reset signal line 41 compared to the first reset signal line 31, and the degree of widening of the second bias adjustment signal line 43 compared to the first bias adjustment signal line 33 can be greater than the degree of widening of the second reset signal line 41 compared to the first reset signal line 31. Further, W22-W12>

[0143] W23-W13, that is, the degree to which the second initialization signal line 42 is widened compared to the first initialization signal line 32 can be greater than the degree to which the second bias adjustment signal line 43 is widened compared to the first bias adjustment signal line 33. This allows the characteristics of each signal line to be adjusted in the first display area and the second display area, while avoiding additional wiring area and ensuring the best display effect.

[0144] In addition, an embodiment of the present application further provides a display device, which includes the display panel provided by any of the above embodiments. Specifically, in an embodiment of the present application, Figure 23 As shown, a functional device 400 is correspondingly provided in the transmission area 201 of the display panel 300 , and the functional device 400 can receive or reflect light through the transmission area 201 .

[0145] Optionally, in one embodiment of the present application, the functional device is a camera, but the present application is not limited to this. In other embodiments of the present application, the functional device may also be a fingerprint recognition device or other device, depending on the specific circumstances.

[0146] In summary, in the display panel and display device provided by the embodiments of the present application, the sum of the resistivities of the first reset signal line, the first initialization signal line and the first bias adjustment signal line located in the first display area is not greater than the sum of the resistivities of the second reset signal line, the second initialization signal line and the second bias adjustment signal line located in the second display area, so that at least one of the first reset signal line, the first initialization signal line and the first bias adjustment signal line located in the first display area, which have relatively high resistivity requirements, is set on a film layer with a smaller signal line resistivity, thereby improving the display performance of the first display area, and at least one of the second reset signal line, the second initialization signal line and the second bias adjustment signal line located in the second display area, which have relatively low resistivity requirements, is set on a film layer with a larger signal line resistivity, thereby reducing the number of signal lines on the film layer with a smaller signal line resistivity, increasing the area of ​​the transmittance area of ​​the second display area, and ensuring the light transmittance performance of the second display area, thereby taking into account both the display performance and light transmittance performance of the display panel.

[0147] The various parts in this manual are described in a combination of parallel and progressive manners. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referenced to each other.

[0148] With respect to the above description of the disclosed embodiments, the features described in the various embodiments in this specification may be interchanged or combined with one another to enable those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: A pixel circuit and a light-emitting element, wherein the pixel circuit includes a driving transistor, and the driving transistor is used to provide a driving current for the light-emitting element; a reset signal line, an initialization signal line, and a bias adjustment signal line, wherein the reset signal line is used to provide a reset signal to the gate of the driving transistor, the initialization signal line is used to provide an initialization signal to the light-emitting element, and the bias adjustment signal line is used to provide a bias adjustment signal to the driving transistor; The display panel includes a first display area and a second display area, the second display area includes a transmission area, the first display area includes a first reset signal line, a first initialization signal line and a first bias adjustment signal line, and the second display area includes a second reset signal line, a second initialization signal line and a second bias adjustment signal line; wherein, The resistivity of the first reset signal line is ρ11, the resistivity of the first initialization signal line is ρ12, and the resistivity of the first bias adjustment signal line is ρ13; the resistivity of the second reset signal line is ρ21, the resistivity of the second initialization signal line is ρ22, and the resistivity of the first bias adjustment signal line is ρ23; wherein, ρ11+ρ12+ρ13≤ρ21+ρ22+ρ23.

2. The display panel according to claim 1, wherein: ρ11>ρ12, and / or, ρ11>ρ13; ρ21>ρ22, and / or, ρ21>ρ23.

3. The display panel according to claim 1, wherein: (ρ23-ρ13)>(ρ22-ρ12), and / or, (ρ23-ρ13)>(ρ21-ρ11).

4. The display panel according to claim 1, wherein: The pixel circuit includes a reset transistor, an initialization transistor and a bias adjustment transistor; The reset transistor is connected between the reset signal line and the gate of the driving transistor; The initialization transistor is connected between the initialization signal line and the light emitting element; The bias adjustment transistor is connected between the bias adjustment signal line and the first electrode or the second electrode of the driving transistor.

5. The display panel according to claim 1, wherein: The pixel circuit includes a reset transistor, an initialization transistor and a compensation transistor; The reset transistor is connected between the reset signal line and the first electrode or the second electrode of the driving transistor, and the compensation transistor is connected between the gate and the second electrode of the driving transistor; The initialization transistor is connected between the initialization signal line and the light emitting element; wherein, The working process of the pixel circuit includes a bias adjustment stage. In the bias adjustment stage, the reset transistor is multiplexed as a bias adjustment transistor, and the reset signal line is multiplexed as the bias adjustment signal line.

6. The display panel according to claim 5, wherein: ρ11=ρ13, and ρ21=ρ23.

7. The display panel according to claim 1, wherein: When projected onto a plane parallel to the surface of the display panel, a distance between the first reset signal line and the first initialization signal line is D11, a distance between the first initialization signal line and the first bias adjustment signal line is D12, and a distance between the first reset signal line and the first bias adjustment signal line is D13; When projected onto a plane parallel to the surface of the display panel, the distance between the second reset signal line and the second initialization signal line is D21, the distance between the second initialization signal line and the second bias adjustment signal line is D22, and the distance between the second reset signal line and the second bias adjustment signal line is D23; wherein, D11>D21, and / or, D12>D22, and / or, D13>D23.

8. The display panel according to claim 1, wherein: In a direction perpendicular to the surface of the display panel, the second reset signal line at least partially overlaps with the second initialization signal line; and / or the second reset signal line at least partially overlaps with the second bias adjustment signal line; And / or, the second initialization signal line at least partially overlaps with the second bias adjustment signal line.

9. The display panel according to claim 1, wherein: The first reset signal line and the second reset signal line are located in different film layers; and / or, The first initialization signal line and the second initialization signal line are located in different film layers; and / or, The first bias adjustment signal line and the second bias adjustment signal line are located in different film layers.

10. The display panel according to claim 1, wherein At least two of the first reset signal line, the first initialization signal line, and the first bias adjustment signal line are located in the same film layer; The second reset signal line, the second initialization signal line and the second bias adjustment signal line are located in different film layers.

11. The display panel according to claim 10, wherein: Two of the first reset signal line, the first initialization signal line, and the first bias adjustment signal line are located in a first film layer, and the other one is located in a second film layer. The resistivity of the first film layer is smaller than that of the second film layer.

12. The display panel according to claim 11, wherein: The first initialization signal line and the first bias adjustment signal line are located in the first film layer, and the first reset signal line is located in the second film layer.

13. The display panel according to claim 11, wherein: The second reset signal line is located in the third film layer, the second initialization signal line is located in the fourth film layer, and the second bias adjustment signal line is located in the fifth film layer; wherein, The resistivity of the fourth film layer is smaller than that of the fifth film layer, and / or the resistivity of the fifth film layer is smaller than that of the third film layer.

14. The display panel according to claim 13, wherein: The fourth film layer is the same as the first film layer, and the third film layer is the same as the second film layer.

15. The display panel according to claim 1, wherein The line width of the first reset signal line is W11, the line width of the first initialization signal line is W12, and the spacing between the first bias adjustment signal lines is W13; The line width of the second reset signal line is W21, the line width of the second initialization signal line is W22, and the line width of the second bias adjustment signal line is W23; wherein, W11+W12+W13>W21+W22+W23.

16. The display panel according to claim 15, wherein: W11>W21, and / or, W12>W22, and / or, W13>W23.

17. The display panel according to claim 15, wherein: (W11-W21)>(W13-W23)≥(W12-W22).

18. The display panel according to claim 1, wherein The second display area includes pixel islands located between the transmission areas and connecting bridges connecting the pixel islands, the pixel islands include N sub-pixels, N≥1, and the pixel islands include pixel circuits; wherein, The second reset signal line, the second initialization signal line, and the second bias adjustment signal line extend along the connection bridge and are connected to the pixel island.

19. The display panel according to claim 1, wherein The second display area includes a transition area, the transition area includes a pixel circuit, and the pixel circuit is used to provide signals for sub-pixels in the second display area; The second reset signal line, the second initialization signal line, and the second bias adjustment signal line are connected to the pixel circuits in the transition region.

20. The display panel according to claim 19, wherein The line width of the first reset signal line is W11, the line width of the first initialization signal line is W12, and the spacing between the first bias adjustment signal lines is W13; The line width of the second reset signal line is W21, the line width of the second initialization signal line is W22, and the line width of the second bias adjustment signal line is W23; wherein, W11+W12+W13<W21+W22+W23.

21. The display panel according to claim 20, wherein: W11<W21, and / or, W12<W22, and / or, W13<W23.

22. The display panel according to claim 20, wherein: W22-W12>W21-W11, and / or, W23-W13>W21-W11.

23. A display device comprising the display panel according to any one of claims 1 to 22, characterized in that: The transmission area is correspondingly provided with a functional device, and the functional device can receive or reflect light through the transmission area.

24. The display device according to claim 23, wherein: The functional device is a camera.

Images