mos transistor
By introducing first and second protection diodes in parallel into the MOS transistor, the problem of damage to the gate by plasma current during etching is solved, achieving effective protection of the gate and stress testing, and improving the reliability and stability of the transistor.
Patent Information
- Application Number
- CN202111626376.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-28
- Publication Date
- 2025-11-28
- Estimated Expiration
- 2041-12-28
AI Technical Summary
During the etching process of existing MOS transistors, the gate may be damaged due to plasma current. The protection effect of existing protection diodes is limited and cannot effectively protect the gate from the influence of plasma current.
Introducing first and second protection diodes in parallel into the MOS transistor, with different polarity configurations, allows current to be conducted through one of the protection diodes regardless of whether the plasma current is positive or negative, thereby protecting the gate from damage. After the top metal layer is completed, stress testing is performed by disconnecting the second protection diode.
It effectively protects the gate from damage by plasma current during the etching process and can complete stress testing, thus improving the reliability and stability of MOS transistors.
Smart Images
Figure CN114334954B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor technology, and in particular to a MOS transistor. BACKGROUND
[0002] In the process of making a MOS transistor, various device structures are formed by etching the substrate, and the gate, source and drain need to be formed, and the source, drain, bulk and various well and drain regions need to be formed in the substrate. Therefore, etching is required, and after the first metal layer is formed, other metal layers are formed, which all involve etching. Etching requires plasma, and the plasma generates current. If the current passes through the gate and other devices, it can cause damage to the devices.
[0003] The prior art MOS transistor, taking NMOS as an example, usually has a diode connected to the gate and bulk for protection. The diode connected to the gate (G) is N-pole, and the diode connected to the bulk is P-pole. When the plasma current is negative, the protection diode is forward biased, and the device can be protected. When the plasma current is positive, the protection diode is reverse biased, and the device cannot be protected. Therefore, for the structure of the prior art, the protection diode has limitations in protecting the device. SUMMARY
[0004] The purpose of the present application is to provide a MOS transistor that can protect the gate from damage caused by plasma current.
[0005] In order to achieve the above purpose, the present application provides a MOS transistor, comprising:
[0006] a substrate;
[0007] a P-type well region and an N-type well region located in the substrate and arranged adjacent to each other;
[0008] a floating gate located on the P-type well region, a bulk located in the P-type well region, and a first protection diode, the floating gate being in communication with the N-pole of the first protection diode, and the P-pole of the first protection diode being in communication with the bulk; and
[0009] a second protection diode located in the N-type well region, the second protection diode being in parallel with the first protection diode, and the N-pole of the first protection diode being in communication with the P-pole of the second protection diode, and the P-pole of the first protection diode being in communication with the N-pole of the second protection diode.
[0010] Optionally, in the MOS transistor, the floating gate and the N-pole of the first protection diode are in communication through a first metal layer, and the P-pole of the first protection diode and the bulk are in communication through a first metal layer.
[0011] Optionally, in the MOS transistor, the N pole and the P pole of the second protection diode are communicated through a top metal layer.
[0012] Optionally, in the MOS transistor, a metal layer is further included between the first metal layer and the top metal layer, and the metal layer is communicated with the first metal layer through a via.
[0013] Optionally, in the MOS transistor, the number of the metal layers is at least two, and the at least two metal layers are sequentially stacked on the first metal layer, and the at least two metal layers are communicated through a via.
[0014] The application further provides a MOS transistor, comprising:
[0015] a substrate;
[0016] an N-type well region and a P-type well region which are adjacently arranged in the substrate;
[0017] a floating gate on the N-type well region, a bulk terminal in the N-type well region, and a first protection diode, the floating gate being communicated with the P pole of the first protection diode, and the N pole of the first protection diode being communicated with the bulk terminal; and
[0018] a second protection diode in the P-type well region, the second protection diode being parallel to the first protection diode, the P pole of the first protection diode being communicated with the N pole of the second protection diode, and the N pole of the first protection diode being communicated with the P pole of the second protection diode.
[0019] Optionally, in the MOS transistor, the floating gate and the N pole of the first protection diode are communicated through a first metal layer, and the P pole of the first protection diode and the bulk terminal are communicated through the first metal layer.
[0020] Optionally, in the MOS transistor, the N pole and the P pole of the second protection diode are communicated through a top metal layer.
[0021] Optionally, in the MOS transistor, a metal layer is further included between the first metal layer and the top metal layer, and the metal layer is communicated with the first metal layer through a via.
[0022] Optionally, in the MOS transistor, the number of the metal layers is at least two, and the at least two metal layers are sequentially stacked on the first metal layer, and the at least two metal layers are communicated through a via.
[0023] In the MOS transistor provided by the present application, no matter whether the current generated by the plasma on the gate is positive or negative, the first protection diode will be forward biased or the second protection diode will be forward biased, so that the current is led away through the first protection diode or the second protection diode to protect the gate from being damaged by the current generated by the plasma.
[0024] Further, when a voltage is applied to the gate to perform a stress test after the top metal layer is completed, the P pole and the N pole of the second protection diode are connected through the top metal layer, the second protection diode is disconnected, the first protection diode is reverse biased, at this time, the current can pass through the gate again, so that the stress test is completed. BRIEF DESCRIPTION OF DRAWINGS
[0025] Figure 1 is a structural schematic diagram of an NMOS transistor of the first embodiment of the present application;
[0026] Figure 2 is a structural schematic diagram of a PMOS transistor of the first embodiment of the present application;
[0027] In the drawings: 110-P type well region, 120-N type well region, 111-N type well region, 112-P type well region, 121-N type well region, 122-P type well region, 130-gate, 140-bulk end, 150-first protection diode, 151-N pole, 152-P pole, 160-second protection diode, 161-N pole, 162-P pole, 170-first metal layer, 180-top metal layer, 210-N type well region, 211-P type well region, 212-N type well region, 221-P type well region, 222-N type well region, 220-P type well region, 230-gate, 240-bulk end, 250-first protection diode, 251-P pole, 252-N pole, 260-second protection diode, 261-P pole, 262-N pole, 270-first metal layer, 280-top metal layer. DETAILED DESCRIPTION
[0028] The specific embodiments of the present application will be described in more detail below with reference to the accompanying drawings. The advantages and features of the present application will be more apparent from the following description. It should be noted that the drawings are very simplified and use non-precise proportions, only to facilitate, clarify the purpose of assisting the description of the embodiments of the present application.
[0029] In the following detailed description, the terms "first", "second", etc. are used to distinguish between like elements having a same, or similar, function in the context in which the elements are used and are not necessarily used to describe a particular sequential or chronological order. It is to be understood that, where appropriate, so used terms can be interchanged. Also, if a method comprising a series of steps is described herein, the order of the steps presented herein is not necessarily the only order in which the steps can be performed, and some of the described steps can be omitted and / or other steps not described herein can be added to the method.
[0030] Embodiment one
[0031] Reference is made to Figure 1 , Figure 1 As a cross-sectional view of a MOS transistor, the present application provides a MOS transistor, and embodiment one is an NMOS transistor, which comprises:
[0032] a substrate, which can be a wafer;
[0033] a P-type well region 110 and an N-type well region 120 located on the substrate and arranged adjacently;
[0034] a floating gate 130 arranged on the P-type well region 110, a bulk terminal 140 located in the P-type well region 110, and a first protection diode 150, the bulk terminal 140 and the first protection diode 150 having a certain distance, the floating gate 130 being in communication with an N pole 151 of the first protection diode 150, and a P pole 152 of the first protection diode 150 being in communication with the bulk terminal 140; and
[0035] a second protection diode 160 located in the N-type well region 120, the second protection diode 160 being in parallel with the first protection diode 150, and the N pole 151 of the first protection diode 150 being in communication (electrically connected) with a P pole 162 of the second protection diode 160, and the P pole 152 of the first protection diode 150 being in communication with an N pole 161 of the second protection diode 160. In the P-type well region 110, a plurality of P-type well regions or N-type well regions can be further nested, for example, the N pole 151 of the first protection diode 150 is made in an N-type well region 111, the P pole 152 of the first protection diode 150 is made in a P-type well region 112, and the N-type well region 111 and the P-type well region 112 are located in the P-type well region 110. Similarly, in the N-type well region 120, a plurality of P-type well regions or N-type well regions can be further nested, for example, the N pole 161 of the second protection diode 160 is made in an N-type well region 121, the P pole 162 of the second protection diode 160 is made in a P-type well region 122, and the N-type well region 121 and the P-type well region 122 are located in the N-type well region 120. In other embodiments of the present application, a drain terminal and a source terminal, or an AA region, can also be arranged in the P-type well region 110, and the forming methods of these devices are all prior art, which will not be described here.
[0036] Preferably, the floating gate 130 is connected to the N pole 151 of the first protection diode 150 through the first metal layer (Ml) 170, and the P pole 152 of the first protection diode 150 is connected to the bulk terminal 140 through the first metal layer 170. During etching, the plasma generated current can act on the gate 130. If the acting current is positive, the first protection diode 150 is reverse biased, the second protection diode 160 is forward biased, and the second protection diode 160 is turned on, so that the current is conducted away through the second protection diode 160, thereby protecting the gate 130 from being damaged by the plasma current. If the acting current is negative, the first protection diode 150 is forward biased, the second protection diode 160 is reverse biased, and the first protection diode 150 is turned on, so that the current is conducted away through the first protection diode 150, thereby protecting the gate 130 from being damaged by the plasma current. Therefore, no matter whether the plasma generated current is positive or negative during etching, the gate 130 can be protected.
[0037] Preferably, the N pole 161 and the P pole 162 of the second protection diode 160 are connected through the top metal layer 180. After the entire device is completed, that is, after the top metal layer 180 is completed, the entire device is subjected to a stress test. The stress test applies current to multiple locations of the entire device, and the stress of the device can be measured when the current passes through the device. For example, to test the stress of the gate 130, current needs to be applied to the gate 130 and needs to flow through the gate 130, thereby testing the stress of the gate 130. Therefore, when the top metal layer 180 is completed, the P pole 162 and the N pole 161 of the second protection diode 160 need to be connected using the top metal layer 180, so that when current is applied to the gate 130, the second protection diode 160 is open, the first protection diode 150 is reverse biased, and the current does not pass through the first protection diode 150 and the second protection diode 160, thereby allowing the gate 130 to complete the stress test.
[0038] Preferably, the NMOS transistor of the first embodiment further comprises a metal layer between the first metal layer 170 and the top metal layer 180, and the metal layer is in communication with the first metal layer 170 through a via. For example, a second metal layer between the first metal layer 270 and the top metal layer 280, when etched, some plasma charges generated will also pass through the via, the first metal layer to the first protection diode 150 or the second protection diode 160, thereby eliminating the plasma generated current, protecting the gate 130 from being affected. The number of metal layers between the first metal layer 170 and the top metal layer 180 can also be at least two, if it is at least two, then the at least two metal layers are sequentially stacked on the first metal layer, and the at least two metal layers are in communication with each other through a via, and are in communication with the first metal layer 170. Similarly, the metal layer M X between the first metal layer 170 and the top metal layer 180 will also generate plasma current, at this time, the plasma current can also be conducted away through the first protection diode 150 or the second protection diode 160, thereby protecting the gate 130 from the influence of the plasma current.
[0039] The second embodiment
[0040] Please refer to Figure 2 , the second embodiment provides a MOS transistor, which is a PMOS transistor, comprising:
[0041] a substrate, which can be a wafer;
[0042] an N-type well region 210 and a P-type well region 220 are arranged adjacent to each other on the substrate;
[0043] a floating gate 230 on the N-type well region 210, a bulk terminal 240 in the N-type well region 210, and a first protection diode 250, the bulk terminal 240 and the first protection diode 250 have a certain distance, the floating gate 230 is in communication with the P pole 251 of the first protection diode 250, and the N pole 252 of the first protection diode 250 is in communication with the bulk terminal 240; and
[0044] The second protection diode 260 is located in the P-type well region 220, and is connected in parallel with the first protection diode 250. The P pole 251 of the first protection diode 250 is connected with the N pole 262 of the second protection diode 260, and the N pole 252 of the first protection diode 250 is connected with the P pole 261 of the second protection diode 260. The N-type well region 210 can be nested with multiple P-type well regions or N-type well regions, for example, the P pole 251 of the first protection diode 250 is made in the P-type well region 211, the N pole 252 of the first protection diode 250 is made in the N-type well region 212, and the P-type well region 211 and the N-type well region 212 are located in the N-type well region 210. Similarly, the P-type well region 220 can be nested with multiple P-type well regions or N-type well regions, for example, the P pole 261 of the second protection diode 260 is made in the P-type well region 221, the N pole 262 of the second protection diode 260 is made in the N-type well region 222, and the P-type well region 221 and the N-type well region 222 are located in the P-type well region 220. In other embodiments of the present application, the N-type well region 210 can also be provided with a drain end and a source end, or an AA region, and the forming method of these devices is prior art, which will not be described here.
[0045] Preferably, the floating gate 230 is connected with the N pole 251 of the first protection diode 250 through the first metal layer 270 (M1), and the P pole 252 of the first protection diode 250 is connected with the bulk end 240 through the first metal layer 270. In the etching process, the current generated by the plasma can act on the gate 230. If the acting current is positive, the first protection diode 250 is forward biased, the second protection diode 260 is reverse biased, the first protection diode 250 is turned on, and the current is conducted away through the first protection diode 250, thereby protecting the gate 230 from being damaged by the plasma current. If the acting current is negative, the first protection diode 250 is reverse biased, the second protection diode 260 is forward biased, and the second protection diode 260 is turned on, and the current is conducted away through the second protection diode 260, thereby protecting the gate 230 from being damaged by the plasma current. Therefore, no matter whether the current generated by the plasma in the etching process is positive or negative, the gate 230 can be protected.
[0046] Preferably, the N pole 262 and the P pole 261 of the second protection diode 260 are connected through the top metal layer 280. After the whole device is finished, that is, after the top metal layer 280 is finished, the stress test is performed on the whole device. The stress test applies current to multiple locations of the whole device. When the current passes through the device, the stress of the device can be measured. For example, the stress of the gate 230 is tested. The current needs to be applied to the gate 230, and the current needs to flow through the gate 230, so as to test the stress of the gate 230. Therefore, when the top metal layer 280 is finished, the P pole 261 and the N pole 262 of the second protection diode 260 need to be connected through the top metal layer 280, so that when the current is applied to the gate 230, the second protection diode 260 is turned off, the first protection diode 250 is reversed biased, and the current does not pass through the first protection diode 250 and the second protection diode 260, so as to complete the stress test of the gate 130.
[0047] Preferably, the PMOS transistor of the second embodiment further comprises a metal layer between the first metal layer 270 and the top metal layer 280, and the metal layer is connected with the first metal layer 270 through a via. For example, the second metal layer is between the first metal layer 270 and the top metal layer 280. When the second metal layer is etched, some plasma charges generated during the etching also pass through the via, the first metal layer, and reach the first protection diode 250 or the second protection diode 260, so as to remove the current generated by the plasma and protect the gate 230. The metal layer between the first metal layer 270 and the top metal layer 280 can also be at least two layers. If it is at least two layers, the at least two metal layers are sequentially stacked on the first metal layer, and the at least two metal layers are connected through a via and connected with the first metal layer 270. Similarly, the metal layer M X In the metal layer between the first metal layer 270 and the top metal layer 280, the current generated by the plasma also appears. At this time, the plasma current can also be conducted away through the first protection diode 250 or the second protection diode 260, so as to protect the gate 230 from being damaged by the current generated by the plasma.
[0048] In summary, in the MOS transistor provided by the embodiment of the present application, no matter whether the current generated by the plasma on the gate is positive or negative, the first protection diode is forward biased or the second protection diode is forward biased, so as to conduct the current away through the first protection diode or the second protection diode, so as to protect the gate from being damaged by the current generated by the plasma.
[0049] Further, when the voltage is applied to the gate for stress test after the top metal layer is finished, the P pole and the N pole of the second protection diode are connected through the top metal layer, the second protection diode is turned off, the first protection diode is reversed biased, and at this time, the current can pass through the gate, so as to complete the stress test.
[0050] The above merely describes the preferred embodiments of the present application and does not limit the present application in any way. Any person skilled in the art can make any form of equivalent replacement, modification or change to the technical solutions and technical contents disclosed by the present application without departing from the scope of the technical solutions of the present application, and such still belongs to the protection scope of the present application.
Claims
1. A MOS transistor, characterized in that, include: Substrate; P-type well regions and N-type well regions are located within the substrate and are arranged adjacent to each other; The floating gate is located on the P-type well region, the bulk terminal is located in the P-type well region, and the first protection diode is connected to the N-terminus of the first protection diode, and the P-terminus of the first protection diode is connected to the bulk terminal. as well as A second protection diode is located within the N-type well region. The second protection diode is connected in parallel with the first protection diode, and the N-terminal of the first protection diode is connected to the P-terminal of the second protection diode, and the P-terminal of the first protection diode is connected to the N-terminal of the second protection diode.
2. The MOS transistor as described in claim 1, characterized in that, The floating gate is connected to the N-terminal of the first protection diode through a first metal layer, and the P-terminal of the first protection diode is connected to the bulk terminal through a first metal layer.
3. The MOS transistor as described in claim 2, characterized in that, The N-terminal and P-terminal of the second protection diode are connected through the top metal layer.
4. The MOS transistor as described in claim 3, characterized in that, It also includes a metal layer located between the first metal layer and the top metal layer, the metal layer being connected to the first metal layer through a via.
5. The MOS transistor as described in claim 4, characterized in that, The number of metal layers is at least two, and the at least two metal layers are stacked sequentially on the first metal layer, and the at least two metal layers are connected to each other through through holes and are also connected to the first metal layer.
6. A MOS transistor, characterized in that, include: Substrate; An N-type well region and a P-type well region are located within the substrate and are disposed adjacent to each other; The floating gate is located on the N-type well region, the bulk terminal is located in the N-type well region, and the first protection diode is connected to the P-terminal of the first protection diode, and the N-terminal of the first protection diode is connected to the bulk terminal. as well as The second protection diode is located within the P-type well region. The second protection diode is connected in parallel with the first protection diode, and the P-terminal of the first protection diode is connected to the N-terminal of the second protection diode, and the N-terminal of the first protection diode is connected to the P-terminal of the second protection diode.
7. The MOS transistor as claimed in claim 6, characterized in that, The floating gate is connected to the N-terminal of the first protection diode through a first metal layer, and the P-terminal of the first protection diode is connected to the bulk terminal through a first metal layer.
8. The MOS transistor as claimed in claim 7, characterized in that, The N-terminal and P-terminal of the second protection diode are connected through the top metal layer.
9. The MOS transistor as claimed in claim 8, characterized in that, It also includes a metal layer located between the first metal layer and the top metal layer, the metal layer being connected to the first metal layer through a via.
10. The MOS transistor as claimed in claim 9, characterized in that, The number of metal layers is at least two, and the at least two metal layers are stacked sequentially on the first metal layer, and the at least two metal layers are connected to each other through through holes and are also connected to the first metal layer.
Citation Information
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