Display substrate and display device

Abstract

The application discloses a display substrate and a display device, and belongs to the technical field of display. The display substrate has a substrate (01) with a display area (A1), a bending area (A2) and a pad area (A3), and the length of the display area (A1) in the first direction (X1) is greater than the length of the display area (A1) in the second direction (Y1). Since the pad area (A3), the bending area (A2) and the display area (A1) are arranged along the second direction (Y1), the pad area (A3) is located on the side of the longer boundary line of the display area (A1), and then the length of each signal line introduced from the pad area (A3) to the display area (A1) in the display area (A1) is shorter. Correspondingly, the pressure difference at both ends of each signal line introduced from the pad area (A3) to the display area (A1) is smaller, and the display effect of the display device using the display substrate is better.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] The display substrate is an essential part of the display device.

[0003] In related art, the base substrate of a display substrate has a display area and a pad (PAD) area. The display area can be provided with a plurality of pixels arranged in an array. The signal lines used to drive the pixels to emit light are generally introduced into the display area through the PAD area, thereby connecting to the plurality of pixels. The PAD area is generally located on the short side of the display area.

[0004] However, because the PAD area is located on the short side of the display area in the related art, the length of each signal line introduced from the PAD area to the display area is relatively long, which in turn results in a large voltage difference across each signal line, resulting in a poor display effect of the display device. Summary of the Invention

[0005] The present disclosure provides a display substrate and a display device that can solve the problem of poor display effects of display devices in related technologies. The technical solution is as follows:

[0006] In one aspect, a display substrate is provided, comprising:

[0007] a base substrate, the base substrate comprising a display area, a bending area, and a pad area, wherein a length of the display area in a first direction is greater than a length of the display area in a second direction, the first direction is perpendicular to the second direction, and the pad area, the bending area, and the display area are arranged along the second direction;

[0008] A plurality of pixels arranged in an array are located in the display area;

[0009] Multiple first power line groups and multiple first signal lines, each first power line group includes at least two first power lines for providing first DC power signals, each first power line and each first signal line extends from the pad area to the display area and is connected to at least one pixel, and the extension direction of the partial line segments of each first power line and each first signal line connected to the pixel is parallel to the second direction.

[0010] Optionally, in the bending area, the spacing between each two adjacent first power lines in each first power line group is less than or equal to a first spacing threshold, the spacing between each two adjacent first power line groups is greater than or equal to a second spacing threshold, and the first spacing threshold is less than the second spacing threshold.

[0011] The display substrate further includes: a first cross-connection portion and a second cross-connection portion, wherein the first cross-connection portion is located in the pad area, and the second cross-connection portion is located in the display area; each of the first power lines includes a first sub-line segment, a second sub-line segment, and a third sub-line segment;

[0012] The first sub-segment is located in the pad area, one end of the first sub-segment is connected to the power supply end, and the other end of the first sub-segment is connected to the first jumper;

[0013] One end of the second sub-segment is connected to the first bridge portion, and the other end of the second sub-segment is connected to the second bridge portion;

[0014] One end of the third sub-line segment is connected to the second bridge portion, and the other end of the third sub-line segment is connected to at least one of the pixels;

[0015] The first sub-segment, the second sub-segment, the third sub-segment, the first bridging portion, and the second bridging portion are all arranged in the same layer as the source / drain metal layer in the display substrate.

[0016] Optionally, each first power line group includes the same number of first power lines.

[0017] Optionally, the line width of each of the first power lines is less than or equal to a first line width threshold.

[0018] Optionally, the plurality of first signal lines include: a data signal line for providing a data signal, and / or a second power line for providing a second DC power signal.

[0019] Optionally, the plurality of first signal lines include: a plurality of data signal lines;

[0020] Each of the data signal lines comprises: a data line lead and a data line connected to each other;

[0021] The data line lead is located in the pad area and the bending area, the data line is located in the display area, and the data line is connected to at least one pixel.

[0022] Optionally, the data signal line is provided in the same layer as the first gate metal layer in the display substrate; or, the data signal line is provided in the same layer as the second gate metal layer in the display substrate.

[0023] Optionally, the line width of each of the second power lines is less than or equal to a second line width threshold.

[0024] Optionally, the base substrate further has a first lead area and a second lead area, and the first lead area, the display area and the second lead area are arranged along the first direction; the display substrate further includes: a plurality of second signal lines;

[0025] Among the multiple second signal lines, a part of the second signal lines extends from the pad area to the first lead area and is connected to at least one pixel; another part of the second signal lines extends from the pad area to the second lead area and is connected to at least one pixel.

[0026] Optionally, the line width of each of the second signal lines is less than or equal to a third line width threshold.

[0027] Optionally, the second signal line is used to provide a gate drive signal; each of the second signal lines includes: a gate line lead and a gate line connected to each other;

[0028] Wherein, the gate line lead is located in the pad area and the first lead area, or the gate line lead is located in the pad area and the second lead area;

[0029] The gate line is located in the display area, and the gate line is connected to at least one of the pixels.

[0030] Optionally, each of the second signal lines includes: a first metal layer and a second metal layer; the first metal layer is provided on the same layer as the first gate metal layer in the display substrate, and the second metal layer is provided on the same layer as the second gate metal layer in the display substrate;

[0031] Alternatively, each of the second signal lines includes: a first metal layer, a second metal layer and a third metal layer; the first metal layer is arranged on the same layer as the first gate metal layer in the display substrate, the second metal layer is arranged on the same layer as the second gate metal layer in the display substrate, and the third metal layer is arranged on the same layer as the source and drain metal layer in the display substrate.

[0032] Optionally, each type of signal line includes at least one target signal line, and the target signal line is closer to the edge of the pad area relative to other signal lines except the target signal line;

[0033] The portion of the target signal line located in the pad area includes a first target sub-segment and a second target sub-segment connected in sequence, the first target sub-segment is close to the display area relative to the second target sub-segment, and the angle between the first target sub-segment and the boundary line of the display area extending along the first direction is less than or equal to 90 degrees.

[0034] Optionally, the display substrate further comprises: a plurality of second signal lines; the first signal lines comprise: a data signal line and a second power line;

[0035] The pad area includes a first partition and a second partition that are symmetrical;

[0036] Among each type of signal lines, a portion of the signal lines is located in the first partition, and another portion of the signal lines is located in the second partition.

[0037] Optionally, among each type of signal lines, the number of signal lines located in the first partition is the same as the number of signal lines located in the second partition.

[0038] Optionally, in each of the partitions, the target line group, the second power line and the second signal line are arranged in sequence in a direction away from another partition, wherein the target line group includes the data signal line and the first power line.

[0039] Optionally, the base substrate further has a component placement area, and the component placement area and the pad area are located on the same side of the display area;

[0040] The display substrate further includes a camera component located in the component setting area;

[0041] The pad area has a first portion and a second portion connected to each other on one side thereof close to the component placement area, and an extension direction of the first portion intersects with an extension direction of the second portion.

[0042] On the other hand, a display device is provided, comprising: a driving circuit located in the pad area, and the display substrate according to the above aspect;

[0043] The driving circuit is connected to various types of signal lines included in the display substrate, and the driving circuit is used to provide signals to the connected signal lines.

[0044] The beneficial effects of the technical solution provided by the present disclosure may include at least:

[0045] In summary, embodiments of the present disclosure provide a display substrate and a display device. In this display substrate, the base substrate comprises a display area, a bending area, and a pad area, wherein the length of the display area in the first direction is greater than the length of the display area in the second direction. Because the pad area, bending area, and display area are arranged along the second direction, the pad area is located on the side of the longer boundary line of the display area. Consequently, the length of each signal line introduced from the pad area to the display area is shorter within the display area. Accordingly, the voltage difference across each signal line introduced from the pad area to the display area is smaller, resulting in a better display quality for a display device using this display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Figure 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0048] Figure 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0049] Figure 3 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0050] Figure 4 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0051] Figure 5 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0052] Figure 6 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0053] Figure 7 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0054] Figure 8 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0055] Figure 9 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0056] Figure 10 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0057] Figure 11 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0058] Figure 12 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0059] Figure 13 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0060] Figure 14 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0061] Figure 15 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0062] Figure 16 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0063] Figure 17 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0064] Figure 18 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0066] Figure 1 Schematic diagram of the structure of a display substrate provided by an embodiment of the present disclosure. Figure 1 As shown, the display substrate may include:

[0067] The base substrate 01 may include a display area A1, a bending area A2, and a pad area A3. The length of the display area A1 in a first direction X1 may be greater than the length of the display area A1 in a second direction Y1, and the first direction X1 may be perpendicular to the second direction Y1. That is, the length of the boundary line of the base substrate 01 extending along the first direction X1 is greater than the length of the boundary line of the base substrate 01 extending along the second direction Y1.

[0068] For example, reference Figure 1 Assuming that the base substrate 01 is shaped like a rectangle with rounded corners, the boundary line of the display area A1 of the base substrate 01 extending along the first direction X1 can be called the long side, and the boundary line of the display area A1 of the base substrate 01 extending along the second direction Y1 can be called the short side. In other words, the display area A1 of the base substrate 01 can be surrounded by two long sides and two short sides. Of course, the base substrate 01 can also have other shapes (such as an ellipse or a polygon). Regardless of the shape, the length of the base substrate 01 in the first direction X1 is greater than the length of the display area A1 in the second direction Y1.

[0069] In the embodiment of the present disclosure, the pad area A3, the bending area A2 and the display area A1 can be arranged along the second direction Y1. Figure 1, the bending area A2 and the pad area A3 can be located on the side of the long side of the display area A1. Since the extension direction of the signal line introduced from the pad area A3 to the display area A1 via the bending area A2 is generally parallel to the arrangement direction of the display area A1, the bending area A2 and the pad area A3 are set on the side of the long side of the display area A1, the length of the signal line introduced from the pad area A3 to the display area A1 via the bending area A2 in the display area A1 can be shorter, generally equivalent to the length of the short side of the display area A1. In addition, due to the influence of loading, the voltage difference between the beginning and end of the signal line is positively correlated with the length of the signal line, that is, the longer the length of the signal line, the greater the voltage difference between the beginning and end of the signal line; the shorter the length of the signal line, the smaller the voltage difference between the beginning and end of the signal line. Therefore, the voltage difference between the beginning and end of each signal line introduced from the pad area A3 to the display area A1 can also be made smaller.

[0070] Figure 2 Schematic diagram of another display substrate provided by an embodiment of the present disclosure. Figure 1 and Figure 2 As can be seen, the display substrate may further include: a plurality of pixels 02 arranged in an array, located within the display area A1; a plurality of first power line groups 03; and a plurality of first signal lines 04. Each first power line group 03 may include at least two first power lines VDD for providing a first DC power signal. Each first power line VDD and each first signal line 04 may extend from the pad area A3 through the bending area A2 to the display area A1 and be connected to at least one pixel 02. Furthermore, the extension direction of the portion of each first power line VDD and each first signal line 04 connecting to the pixel may be parallel to the second direction Y1.

[0071] Recombination Figure 1 By placing pad area A3 on the long side of display area A1, as opposed to the related art where pad area A3 is placed on the short side of display area A1, the length of each signal line introduced from pad area A3 into display area A1 is reduced, thereby reducing the voltage difference between the beginning and end of each signal line. Since the smaller the voltage difference between the beginning and end of each signal line, the better the display uniformity of the pixels connected to each signal line, this also improves the display uniformity of the display substrate.

[0072] It should be noted that the substrate 01 provided in the embodiment of the present disclosure may be a substrate 01 having a special size. The special size may mean that the length of the display area A1 of the substrate 01 in the first direction X1 is much greater than the length of the display area A1 in the second direction Y1. For example, the ratio of the length of the display area A1 of the substrate 01 in the first direction X1 to the length of the display area A1 in the second direction Y1 satisfies a ratio threshold. Optionally, the ratio threshold is approximately 3%. For example, Figure 1 Taking the display substrate shown as an example, in this display substrate, the ratio of the long side to the short side of the display area A1 of the base substrate 01 can meet the following requirements: 27.5:9.

[0073] In summary, embodiments of the present disclosure provide a display substrate. In this display substrate, a base substrate comprises a display area, a bending area, and a pad area, wherein the length of the display area in the first direction is greater than the length of the display area in the second direction. Because the pad area, bending area, and display area are arranged along the second direction, the pad area is located on the side of the longer boundary line of the display area. Consequently, the length of each signal line introduced from the pad area to the display area is shorter within the display area. Accordingly, the voltage differential across each signal line introduced from the pad area to the display area is smaller, resulting in a better display quality for a display device using this display substrate.

[0074] Optional, combined Figure 2 It can be seen that in the display substrate provided by the embodiments of the present disclosure, within the bend region A2, the spacing between each adjacent pair of first power line VDD in each first power line group 03 can be equal to a first spacing threshold, the spacing between each adjacent pair of first power line groups 03 can be greater than or equal to a second spacing threshold, and the first spacing threshold can be less than the second spacing threshold. For example, the first spacing threshold is typically approximately 0.001 micrometers (μm), and the second spacing threshold is typically approximately 5000 μm. In other words, multiple first power lines VDD can be grouped (i.e., block-wise) within the bend region A2.

[0075] By using block routing, on the one hand, the cross-sectional area of ​​each first power line group 03 is increased relative to that of a first power line VDD, thereby reducing the resistance of each first power line VDD in each first power line group 03. On the other hand, it is easier to route signal lines within the bending area A2, which has limited space (e.g., height and width), thus facilitating routing.

[0076] Optional, Figure 3 This is a structural diagram of another display substrate provided by an embodiment of the present disclosure. Figure 3 As shown, the display substrate may further include: a first cross-connection portion B1 and a second cross-connection portion B2, wherein the first cross-connection portion B1 may be located in the pad area A3, and the second cross-connection portion B2 may be located in the display area A1.

[0077] Each first power line VDD may include a first sub-line segment L1 ( Figure 3 Only a large metal block is used to schematically illustrate the multiple first power lines located in the pad area A3, the first sub-segment L1 being a sub-segment belonging to the metal block), the second sub-segment L2, and the third sub-segment L3. The first sub-segment L1 can be located in the pad area A3, and one end of the first sub-segment L1 can be connected to the power terminal, and the other end of the first sub-segment L1 can be connected to the first jumper B1. One end of the second sub-segment L2 can be connected to the first jumper B1, and the other end of the second sub-segment L2 can be connected to the second jumper B2. One end of the third sub-segment L3 can be connected to the second jumper B2, and the other end of the third sub-segment L3 can be located in the display area A1 and connected to at least one pixel O2 (not shown in the figure).

[0078] Combine Figure 2 The first power line VDD is led from the pad area A3 through the bend area A2 to the display area A1 as follows: The multiple first power lines VDD included in the multiple first power line groups 03 are led from the pad area A3 to the display area A1 and are first connected together at the first jumper B1. That is, the first jumper B1 is a layer of metal formed by connecting the first power lines VDD. Then, the connected multiple first power lines VDD are split and further led to the display area A1. The split multiple first power lines VDD are reconnected at the second jumper B2. That is, the second jumper B2 is another layer of metal formed by connecting the first power lines VDD. Furthermore, between the first jumper B1 and the second jumper B2, the multiple first power line groups 03 satisfy the following conditions: the spacing between each adjacent first power line VDD in each first power line group 03 is less than or equal to a first spacing threshold, and the spacing between each adjacent first power line group 03 is greater than or equal to a second spacing threshold. Finally, the multiple first power lines VDD that were connected together are further separated, and each first power line VDD is connected to at least one pixel O2. For example, each first power line VDD can be connected to a column of pixels. Accordingly, the number of first power lines VDD included in the display substrate can be the same as the number of pixel columns included.

[0079] It should be noted that, in this wiring method, combined with Figure 3The multiple first power line groups 03, both in the pad area A3 near the bend area A2 and in the display area A1 near the bend area A2, meet the following requirements: the spacing between each adjacent first power line VDD in each first power line group 03 is less than or equal to a first spacing threshold, and the spacing between each adjacent first power line group 03 is greater than or equal to a second spacing threshold. Furthermore, a driving circuit is provided within the pad area A3. The power supply connected to one end of the first sub-segment L1 can be provided by this driving circuit. In other words, one end of the first sub-segment L1 can be connected to the driving circuit.

[0080] Optionally, the first sub-segment L1, the second sub-segment L2, the third sub-segment L3, the first crossover B1, and the second crossover B2 can all be provided on the same layer as a source and drain metal (SD) layer in the display substrate. The SD layer is an essential component for forming pixels. This simplifies the manufacturing process and reduces manufacturing costs.

[0081] Optionally, each first power line group 03 may include the same number of first power lines VDD. That is, the first power lines VDD may be arranged in evenly spaced blocks. This not only further facilitates wiring but also ensures relatively consistent resistance across each first power line VDD. Consequently, the potential differences in the first power signals provided to the multiple pixels by the multiple first power lines VDD are minimal, further ensuring uniform display of the display device.

[0082] For example, combined with Figure 4 Assuming that a total of 4000 first power lines VDD are required, the 4000 first power lines VDD can be divided into ten first power line groups 03, and each first power line group 03 is set to include 400 first power lines VDD. Figure 4 The specific number of bars is not shown, and Figure 4 Only the first power line groups 03 extending from the bending area A2 to the display area A1 are shown.

[0083] Figure 5 FIG. 1 is a structural diagram of another display substrate provided by an embodiment of the present disclosure. Figure 5 As shown, the plurality of first signal lines 04 may include: a data signal line D1 for providing a data signal, and / or a second power line VSS for providing a second DC power signal. That is, the plurality of first signal lines 04 may include: a plurality of data signal lines D1, or include: a plurality of second power lines VSS, or include: a plurality of data signal lines D1 and a plurality of second power lines VSS.

[0084] Among them, continue to refer to Figure 5Each data signal line D1 may include: a data line lead D11 and a data line D12 connected to each other. The data line lead D11 may be located in the bending area A2 and the pad area A3, and the data line D12 may be located in the display area A1. The data line D12 may be connected to at least one pixel O2 located in the display area A1 (not shown in the figure). In other words, the portion of the data signal line D1 located in the bending area A2 and the pad area A3 may be referred to as the data line lead D11, and the portion of the data signal line D1 located in the display area A1 may be referred to as the data line D12.

[0085] Optional, Figure 6 This is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure. Figure 7 FIG. 1 is a structural diagram of another display substrate provided by an embodiment of the present disclosure. Figure 6 and Figure 7 It can be seen that the data signal line D1 can be provided in the same layer as the first gate metal layer G1 in the display substrate. Alternatively, the data signal line D1 can be provided in the same layer as the second gate metal layer G2 in the display substrate. For example, referring to Figure 6 and Figure 7 It can be seen that, for every two adjacent data signal lines D1, one data signal line D1 can be provided on the same layer as the first gate metal layer G1, while the other data signal line D1 can be provided on the same layer as the second gate metal layer G2. Since the gate metal layer is also an essential component of forming the pixel O2, this can further simplify the manufacturing process and reduce manufacturing costs.

[0086] Since an insulating layer is typically provided between the gate metal layers (e.g., G1 and G2) and the SD layer, and since the first power line VDD is provided on the same layer as the SD layer, in order to arrange all required data signal lines D1 and the first power line VDD within the limited size of the bending area A2 and the pad area A3, the data signal line D1 can be provided below the first power line VDD. In other words, the orthographic projection of the first power line VDD on the base substrate 01 is provided so as to partially overlap the orthographic projection of the data signal line D1 on the base substrate 01.

[0087] Figure 8 FIG. 1 is a structural diagram of another display substrate provided by an embodiment of the present disclosure. Figure 8 As shown, the base substrate 01 may further include a first lead area A4 and a second lead area A5, and the first lead area A4, the display area A1 and the second lead area A5 may be arranged along the first direction X1.

[0088] In the disclosed embodiment, the display substrate further includes: a plurality of second signal lines 05. Among the plurality of second signal lines 05, a portion of the second signal lines 05 may extend from the pad area A3 to the first lead area A4 and be connected to at least one pixel. Another portion of the second signal lines 05 may extend from the pad area A3 to the second lead area A5 and be connected to at least one pixel 02.

[0089] Optionally, the second signal line 05 can be used to provide a gate drive signal. Figure 8 As shown, each second signal line 05 may include a gate line lead 051 and a gate line 052 connected to each other.

[0090] Wherein, gate line lead 051 can be located at pad area A3 and first lead area A4, perhaps, gate line lead 051 can be located at pad area A3 and second lead area A5. Gate line 052 can be located at display area A1, and be connected with at least one pixel (not shown in the figure). Optionally, gate line lead 051 can first provide gate drive signal to gate line 052, and then gate line 052 provides the received gate drive signal to connected pixel 02. Therefore, gate line lead 051 can also be called (gate drive on array, GOA) signal line, and GOA refers to: adopt array substrate row drive technology to integrate gate drive circuit on substrate.

[0091] Optionally, due to the size limitations of the bend area A2 and the pad area A3, to ensure that all required signal lines can be arranged, the line width of each first power line VDD is less than or equal to a first line width threshold. The line width of each second power line VSS can be less than or equal to a second line width threshold. The line width of each second signal line O5 can be less than or equal to a third line width threshold. For example, the first line width threshold can be approximately 600 μm, the second line width threshold can be approximately 500 μm, and the third line width threshold can be approximately 88 μm.

[0092] Optionally, each second signal line 05 may include: a first metal layer and a second metal layer. The first metal layer may be provided on the same layer as the first gate metal layer in the display substrate, and the second metal layer may be provided on the same layer as the second gate metal layer in the display substrate. That is, the second signal line 05 may be composed of the first gate metal layer G1 and the second gate metal layer G2 connected in parallel. Alternatively, as Figure 9 and Figure 10As shown, each second signal line 05 may include: a first metal layer M1, a second metal layer M2, and a third metal layer M3. The first metal layer M1 may be provided on the same layer as the first gate metal layer G1 in the display substrate, the second metal layer M2 may be provided on the same layer as the second gate metal layer G2 in the display substrate, and the third metal layer M3 may be provided on the same layer as the source / drain metal layer SD in the display substrate. That is, the second signal line 05 may be composed of the first gate metal layer G1, the second gate metal layer G2, and the source / drain metal layer SD in parallel. In addition, referring to Figure 10 It can be seen that an insulating layer F1 is provided between each two adjacent metal layers. Furthermore, to ensure reliable connection between the first metal layer M1, the second metal layer M2, and the third metal layer M3, each insulating layer F1 can be provided with a via k that penetrates the insulating layer. The first metal layer M1 and the third metal layer M3 can be electrically connected through the via k, and the second metal layer M2 and the third metal layer M3 can be electrically connected through the via k. By using different metal layers in parallel to form the second signal line 05, each second signal line 05 can be composed of multiple metal traces of shorter length. Since the shorter the signal line, the lower the resistance on the signal line, the resistance on each second signal line 05 is reduced, ensuring a better display effect.

[0093] It should be noted that both the data line lead D11 and the gate line lead 051 can be referred to as fanout wiring because they are located in the non-display area. Figure 1 、 Figure 5 and Figure 8 Since pad area A3 is located on the long side of display area A1, to facilitate the connection between data line D12 and gate line O52 and pixels in display area A1, the position of pixel O2 can be rotated accordingly, compared to the related art. After the rotation, the direction in which gate line O52 connected to pixel O2 extends parallel to the first direction X1, and the direction in which data line D12 connected to pixel O2 extends parallel to the second direction Y1. That is, multiple pixels arranged along the first direction X1 are called a row of pixels, and multiple pixels arranged along the second direction Y1 are called a column of pixels.

[0094] Optionally, if the display substrate is an organic light-emitting diode (OLED) substrate, each pixel 02 may include a pixel circuit and a light-emitting element. The pixel circuit may be connected to a first power line VDD, a gate line 052, a data line D12, and one end (e.g., an anode) of the light-emitting element, respectively. The other end (e.g., a cathode) of the light-emitting element may also be connected to a second power line VSS. The pixel circuit may output a drive signal to the light-emitting element in response to a gate drive signal provided by the gate line 052, a data signal provided by the data line D12, and a first power signal provided by the first power line VDD. The light-emitting element may emit light under the action of a voltage difference between the received drive signal and a second power signal provided by the second power line VSS. That is, the potential of the first power signal may be an effective potential relative to the potential of the second power signal.

[0095] Optional, Figure 11 FIG. 1 is a structural diagram of another display substrate provided by an embodiment of the present disclosure. Figure 1 and Figure 11 Because pad area A3 is located on the long side of display area A1, to ensure reliable driving of pixels on both sides of display area A1 along the first direction X1, pad area A3 can include symmetrical first and second subareas A31 and A32. The bending area A2 and pad area A3 have the same layout and routing.

[0096] The first power line VDD, the first signal line 04 (including the data signal line D1 and the second power line VSS) introduced from the pad area A3 to the display area A1 through the bending area A2, and the second signal line 05 introduced from the pad area A3 to the lead area, of each type of signal line, part of the signal line can be located in the first partition A31, and the other part of the signal line can be located in the second partition A32. And, referring to Figure 11 and Figure 12 In the display substrate shown therein, the number of first power line groups included in each partition of the pad area A3 introduced into the display area A1 through the bending area A2 is 5, which are respectively marked as 03a, 03b, 03c, 03d and 03e. Figure 11 A driving circuit 10 disposed in the pad area A3 is also shown, and various signal lines are connected to the driving circuit 10 and receive signals provided by the driving circuit 10. That is, the signals provided to the pixels by various signal lines can all come from the driving circuit 10.

[0097] Take the second partition A32 as an example, Figure 12 FIG. 4 shows a schematic diagram of the overall structure of the second partition A32. Figure 13 FIG2 shows a schematic diagram of other structures in the second partition A32 except the driving circuit 10. Figure 12 and Figure 13It can be further seen that the data signal line D1 can be located below the first power line VDD. Furthermore, before connecting to pixel O2, the multiple first power lines VDD extending from pad area A3 can first be connected to the first jumper B1, then split into the bend area A2, and then connected to the second jumper B2 just after entering the display area A1. Finally, they split again and continue to enter the display area and connect to pixel O2. Figure 14 It is a schematic diagram showing the internal structure of the driving circuit 10. Figure 14 The line width of multiple signal lines (such as fan-out lines) led out from the driving circuit 10 in the idle area of ​​the pad area A3 (that is, the area where no structure is set) can be greater than the line width threshold, that is, the signal lines located in the idle area can be thickened, thereby achieving the effect of reducing the resistance of the signal lines. Figure 15 FIG1 shows a schematic diagram of a first power supply line VDD, a data line D12 included in the data signal line D1, and a gate line 052 included in the second signal line 05 in the display area A1. Figure 15 It can be further seen that after entering the display area A1 , the plurality of first power lines VDD are first connected together, ie, connected into one piece, and then split and connected to pixels.

[0098] Optionally, to facilitate routing and ensure uniform display effects of pixels 02 at various locations within the display area A1, the number of signal lines of each type located in the first partition A31 may be the same as the number of signal lines located in the second partition A32.

[0099] That is, combined Figure 11 The display substrate shown includes a total of 10 first power line groups 03, and each first power line group 03 can include 400 first power lines VDD. The display substrate also includes: 2 second power lines VSS, multiple data signal lines D1, and multiple second signal lines 05. Among the 10 first power line groups 03, 5 first power line groups 03 can be introduced into the display area A1 from the first partition A31, and 5 first power line groups 03 can be introduced into the display area A1 from the second partition A32. Of the 2 second power lines VSS, one second power line VSS can be introduced into the display area A1 from the first partition A31, and the other second power line VSS can be introduced into the display area A1 from the second partition A32. Of the multiple data signal lines D1, half of the data signal lines D1 can be introduced into the display area A1 from the first partition A31, and the other half can be introduced into the display area A1 from the second partition A32. Among the plurality of second signal lines 05 , half of the second signal lines 05 may be introduced into the display area A1 from the first partition A31 , and the other half of the second signal lines 05 may be introduced into the display area A1 from the second partition A32 .

[0100] RecombinationFigure 11 As can be seen, in each partition, the target line group, the second power line VSS and the second signal line 05 can be arranged in sequence in a direction away from another partition, wherein the target line group can include the data signal line D1 and the first power line VDD. That is, from the outermost side of the pad area A3 to the most central position of the pad area A3, the second signal line 05, the second power line VSS and the target line group can be arranged in sequence.

[0101] Optionally, in combination with Figure 11 and Figure 16 As can be seen, limited by the size of the pad area A3, in order to ensure that all types of signal lines required can be arranged in the pad area A3, in each partition, at least one target signal line is included in each type of signal line, and the target signal line is close to the edge of the pad area A3 relative to other signal lines except the target signal line. Figure 16 The bending area A2 part is not shown.

[0102] The part of the target signal line in the pad area A3 includes the first target sub-line segment L11 and the second target sub-line segment L22 connected in sequence, the first target sub-line segment L11 is close to the display area A1 relative to the second target sub-line segment L12, and the included angle a between the first target sub-line segment L11 and the boundary line J1 of the display area A1 extending in the first direction X1 can be less than or equal to 90 degrees. Generally, the included angle between the first target sub-line segment L11 and the boundary line J1 of the display area A1 extending in the first direction X1 can be set to about ten degrees.

[0103] Figure 17 is still another structure schematic diagram of a display substrate provided by the embodiment of the present disclosure. As Figure 17 indicated, the substrate substrate can further include a component arrangement area A6. And the component arrangement area A6 and the pad area A3 can be located on the same side of the display area A1. The display substrate further includes a camera component C1 located in the component arrangement area A6.

[0104] Correspondingly, in order to avoid the camera component C1, with reference to Figure 17 , the side of the pad area A3 close to the component arrangement area A6 has a first part l1 and a second part l2 connected to each other, and the extension direction of the first part l1 intersects with the extension direction of the second part l2, that is, not parallel. In this way, some space can be saved for the component arrangement area A6, facilitating the arrangement of hardware structures such as the camera component C1. For example, with reference to Figure 17 , the side of the pad area A3 close to the component arrangement area A6 has a first part l1 and a second part l2, and an included angle β can be formed between the first part l1 and the second part l2, which can also be referred to as the tangent angle of the boundary line of the pad area A3.

[0105] In summary, embodiments of the present disclosure provide a display substrate. In this display substrate, a base substrate comprises a display area, a bending area, and a pad area, wherein the length of the display area in the first direction is greater than the length of the display area in the second direction. Because the pad area, bending area, and display area are arranged along the second direction, the pad area is located on the side of the longer boundary line of the display area. Consequently, the length of each signal line introduced from the pad area to the display area is shorter within the display area. Accordingly, the voltage differential across each signal line introduced from the pad area to the display area is smaller, resulting in a better display quality for a display device using this display substrate.

[0106] Figure 18 Schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 18 As shown, the display device may include: a driving circuit 10 located in the pad area A3, and Figures 1 to 17 Any of the display substrates 20 shown. The driving circuit 10 can be connected to various types of signal lines included in the display substrate 20 and is used to provide signals to the connected signal lines.

[0107] For example, the driving circuit 10 can provide a data signal for the data signal line D1, provide a gate driving signal for the second signal line O5, provide a first power signal for the first power line VDD, and provide a second power signal for the second power line VSS.

[0108] Optionally, the display device may be any product or component with a display function, such as an OLED display device, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, or a navigator.

[0109] It should be understood that the term "plurality" used herein refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone.

[0110] It should also be understood that "C is approximately m" herein means that the difference between C and m is within the tolerance range allowed by the process parameters. For example, assuming the tolerance range allowed by the process parameters is n, then C is approximately m and can mean that C is greater than or equal to mn and less than or equal to m+n.

[0111] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the display substrate and the display device described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0112] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display substrate, characterized in that: The display substrate comprises: a base substrate, the base substrate comprising a display area, a bending area, and a pad area, wherein a length of the display area in a first direction is greater than a length of the display area in a second direction, the first direction is perpendicular to the second direction, and the pad area, the bending area, and the display area are arranged along the second direction; A plurality of pixels arranged in an array are located in the display area; a plurality of first power line groups and a plurality of first signal lines, each of the first power line groups including at least two first power lines for providing a first DC power signal, each of the first power line and each of the first signal lines extending from the pad area to the display area and connected to at least one of the pixels, and an extension direction of a portion of each of the first power line and each of the first signal lines connected to the pixel is parallel to the second direction; The base substrate further comprises a first lead area and a second lead area, and the first lead area, the display area, and the second lead area are arranged along the first direction; the display substrate further comprises: a plurality of second signal lines; among the plurality of second signal lines, a portion of the second signal lines extends from the pad area to the first lead area and is connected to at least one of the pixels; another portion of the second signal lines extends from the pad area to the second lead area and is connected to at least one of the pixels; The second signal line includes: a first metal layer, a second metal layer, and a third metal layer; the first metal layer is provided on the same layer as the first gate metal layer in the display substrate, the second metal layer is provided on the same layer as the second gate metal layer in the display substrate, and the third metal layer is provided on the same layer as the source and drain metal layer in the display substrate; Among them, the second signal line is composed of the first gate metal layer, the second gate metal layer and the source-drain metal layer in parallel; in the first gate metal layer, the second gate metal layer and the source-drain metal layer, an insulating layer is set between two adjacent metal layers, and a via is set on the insulating layer that penetrates the insulating layer. The first metal layer and the third metal layer can be electrically connected through the via, and the second metal layer and the third metal layer are electrically connected through the via.

2. The display substrate according to claim 1, wherein: In the bending area, the spacing between each two adjacent first power lines in each first power line group is less than or equal to a first spacing threshold, the spacing between each two adjacent first power line groups is greater than or equal to a second spacing threshold, and the first spacing threshold is less than the second spacing threshold.

3. The display substrate according to claim 1, wherein The display substrate further includes: a first cross-connection portion and a second cross-connection portion, wherein the first cross-connection portion is located in the pad area, and the second cross-connection portion is located in the display area; each of the first power lines includes a first sub-line segment, a second sub-line segment, and a third sub-line segment; The first sub-segment is located in the pad area, one end of the first sub-segment is connected to the power supply end, and the other end of the first sub-segment is connected to the first jumper; One end of the second sub-segment is connected to the first bridge portion, and the other end of the second sub-segment is connected to the second bridge portion; One end of the third sub-line segment is connected to the second bridge portion, and the other end of the third sub-line segment is connected to at least one of the pixels; The first sub-segment, the second sub-segment, the third sub-segment, the first bridging portion, and the second bridging portion are all arranged in the same layer as the source / drain metal layer in the display substrate.

4. The display substrate according to claim 1, wherein Each of the first power line groups includes the same number of first power lines.

5. The display substrate according to claim 1, wherein The line width of each of the first power lines is less than or equal to a first line width threshold.

6. The display substrate according to any one of claims 1 to 5, characterized in that: The plurality of first signal lines include: a data signal line for providing a data signal, and / or a second power line for providing a second DC power signal.

7. The display substrate according to claim 6, wherein: The plurality of first signal lines include: a plurality of data signal lines; Each of the data signal lines comprises: a data line lead and a data line connected to each other; The data line lead is located in the pad area and the bending area, the data line is located in the display area, and the data line is connected to at least one pixel.

8. The display substrate according to claim 6, wherein: The data signal line is provided in the same layer as the first gate metal layer in the display substrate; or the data signal line is provided in the same layer as the second gate metal layer in the display substrate.

9. The display substrate according to claim 6, wherein: The line width of each of the second power lines is less than or equal to a second line width threshold.

10. The display substrate according to any one of claims 1 to 5, characterized in that: The line width of each of the second signal lines is less than or equal to a third line width threshold.

11. The display substrate according to claim 10, wherein: The second signal line is used to provide a gate drive signal; each of the second signal lines includes: a gate line lead and a gate line connected to each other; Wherein, the gate line lead is located in the pad area and the first lead area, or the gate line lead is located in the pad area and the second lead area; The gate line is located in the display area, and the gate line is connected to at least one of the pixels.

12. The display substrate according to any one of claims 1 to 5, characterized in that: Each type of signal line includes at least one target signal line, and the target signal line is closer to the edge of the pad area than other signal lines except the target signal line; The portion of the target signal line located in the pad area includes a first target sub-segment and a second target sub-segment connected in sequence, the first target sub-segment is close to the display area relative to the second target sub-segment, and the angle between the first target sub-segment and the boundary line of the display area extending along the first direction is less than or equal to 90 degrees.

13. The display substrate according to any one of claims 1 to 5, characterized in that: The display substrate further comprises: a plurality of second signal lines; the first signal lines comprise: a data signal line and a second power line; The pad area includes a first partition and a second partition that are symmetrical; Among each type of signal lines, a portion of the signal lines is located in the first partition, and another portion of the signal lines is located in the second partition.

14. The display substrate according to claim 13, wherein: For each type of signal lines, the number of signal lines located in the first partition is the same as the number of signal lines located in the second partition.

15. The display substrate according to claim 13, wherein In each of the partitions, a target line group, the second power line, and the second signal line are sequentially arranged in a direction away from another partition, wherein the target line group includes the data signal line and the first power line.

16. The display substrate according to any one of claims 1 to 5, characterized in that: The base substrate further comprises a component setting area, wherein the component setting area and the pad area are located on the same side of the display area; The display substrate further includes a camera assembly located in the assembly setting area; The pad area has a first portion and a second portion connected to each other on one side thereof close to the component placement area, and an extension direction of the first portion intersects with an extension direction of the second portion.

17. The display substrate according to claim 1, wherein The plurality of first signal lines include: a data signal line for providing a data signal, and / or a second power line for providing a second DC power signal; each of the data signal lines includes: a data line lead and a data line connected to each other; wherein the data line lead is located in the pad area and the bending area, the data line is located in the display area, and the data line is connected to at least one of the pixels; the data signal line is provided in the same layer as the first gate metal layer in the display substrate; or the data signal line is provided in the same layer as the second gate metal layer in the display substrate; The line width of each second power line is less than or equal to a second line width threshold; the line width of each second signal line is less than or equal to a third line width threshold; Each type of signal line includes at least one target signal line, the target signal line being closer to an edge of the pad area relative to other signal lines except the target signal line; the portion of the target signal line located in the pad area includes a first target sub-segment and a second target sub-segment connected in sequence, the first target sub-segment being closer to the display area relative to the second target sub-segment, and an angle between the first target sub-segment and a boundary line of the display area extending along the first direction is less than or equal to 90 degrees; The pad area includes a symmetrical first partition and a second partition; for each type of signal line, a portion of the signal lines is located in the first partition, and another portion of the signal lines is located in the second partition, and for each type of signal line, the number of signal lines located in the first partition is the same as the number of signal lines located in the second partition; in each partition, a target line group, the second power line, and the second signal line are arranged in sequence in a direction away from the other partition, wherein the target line group includes the data signal line and the first power line; The base substrate also has a component setting area, and the component setting area and the pad area are located on the same side of the display area; the display substrate also includes a camera component located in the component setting area; the pad area has a first part and a second part that are connected to each other on the side close to the component setting area, and the extension direction of the first part intersects with the extension direction of the second part.

18. A display device, characterized in that: The display device comprises: a driving circuit located in the pad area, and a display substrate according to any one of claims 1 to 17; The driving circuit is connected to various types of signal lines included in the display substrate, and the driving circuit is used to provide signals to the connected signal lines.

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