Random computing circuit and method

Abstract

The present disclosure provides a random calculation circuit and method. The random calculation circuit includes: a mapping circuit for mapping two numbers to be calculated into a first control word respectively to obtain two first control words; a calculation circuit for generating two sequences based on the two first control words, performing a logical operation on the two sequences, counting the result sequences output by the logical operation, and obtaining a calculation result; a control circuit for controlling the calculation circuit to output the calculation result when the two first control words meet a condition; controlling the mapping circuit to re-map the two numbers to be calculated into two second control words when the two first control words do not meet the condition; and controlling the calculation circuit to output the calculation result obtained based on the two second control words when the two second control words meet the condition.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technology, and in particular to a random computing circuit and method. Background Art

[0002] In stochastic computing (SC), numbers can be represented by bit sequences. For example, the probability of a bit being 1 in a bit sequence is used to represent a number, such as using the bit sequence 1, 0, 0, 0 to represent 1 / 4.

[0003] By representing numbers as bit sequences, calculations can be handled by very simple circuits. For example, a random calculation circuit used to implement multiplication can consist of a sequence generation circuit, an AND gate, and a counting circuit. The sequence generation circuit uses a sequence to represent the number to be calculated. For example, the sequence S1: 01101010 represents 4 / 8, and the sequence S2: 10111011 represents 6 / 8. Sequences S1 and S2 are then input into an AND gate, which outputs the sequence S3: 00101010. The counting circuit counts the number of 1s and 0s in sequence S3 to obtain a probability of 3 / 8 for a bit in sequence S3 that is 1, which is the product of 4 / 8 and 6 / 8.

[0004] Because numbers are represented as bit sequences with only a fixed probability of occurrence of a 1 bit, the same number can be represented as multiple bit sequences of the same length. However, not every bit sequence guarantees accurate calculations. For example, in the previous example, if the sequence S1 is replaced with 01011100 and the sequence S2 is replaced with 11101011, the resulting sequence S3 calculated through the AND gate is 01001000, corresponding to a value of 2 / 8. This replacement of the bit sequence results in an error in the calculation.

[0005] Therefore, how to ensure the accuracy of random calculations becomes a difficulty in random calculations. Summary of the Invention

[0006] Embodiments of the present disclosure provide a random computing circuit and method.

[0007] At least one embodiment of the present disclosure provides a random calculation circuit, the random calculation circuit comprising:

[0008] A mapping circuit, configured to map two numbers to be calculated into a first control word respectively, to obtain two first control words;

[0009] a calculation circuit, configured to generate two sequences based on the two first control words, perform a logic operation on the two sequences, and count result sequences output by the logic operation to obtain a calculation result;

[0010] a control circuit, configured to control the calculation circuit to output the calculation result when the two first control words satisfy a condition; control the mapping circuit to remap the two numbers to be calculated into two second control words when the two first control words do not satisfy the condition, the second control words being different from the first control word; and control the calculation circuit to output the calculation result obtained based on the two second control words when the two second control words satisfy a condition;

[0011] When the two first control words meet a condition, the two sequences are unrelated; when the two first control words do not meet the condition, the two sequences are related.

[0012] Optionally, the control circuit includes:

[0013] a control word conversion subcircuit, configured to convert the two first control words into two integer values ​​respectively;

[0014] The coprime determination subcircuit is configured to determine whether the two integer values ​​are coprime; if the two integer values ​​are coprime, it indicates that the two first control words meet a condition; if the two integer values ​​are not coprime, it indicates that the two first control words do not meet the condition.

[0015] Optionally, the first control word includes an integer part and a decimal part;

[0016] The control word conversion subcircuit is used to move the virtual decimal point between the integer part and the decimal part to the end of the decimal part, and remove the number of bits with the end being 0 to obtain the integer value.

[0017] Optionally, the coprime determination subcircuit is configured to determine whether the two integer values ​​are coprime using a binary Euclidean algorithm.

[0018] Optionally, a mapping table of numbers and control words is stored in the mapping circuit, one number in the mapping table corresponds to multiple control words, and the duty cycles of the sequences corresponding to the multiple control words are the same.

[0019] Optionally, the computing circuit includes:

[0020] a sequence generating sub-circuit, connected to the mapping circuit, and outputting two pulse signals in response to the two first control words, wherein the pulse signals are used to represent the sequence, and the pulse signals include a first frequency signal and a second frequency signal, wherein the probability of the first frequency signal and the second frequency signal appearing in the pulse signals is controlled by the corresponding first control words;

[0021] a logic operator, connected to the sequence generating sub-circuit, for performing a logic operation on the two sequences represented by the two pulse signals and outputting a pulse representing the result sequence;

[0022] The counting subcircuit is connected to the logic operator and is used to count the high and low levels of the pulses representing the result sequence to obtain the calculation result.

[0023] Optionally, the sequence generation subcircuit includes:

[0024] Two pulse sub-circuits, each of the pulse sub-circuits generates a pulse signal according to one of the first control words.

[0025] Optionally, the pulse subcircuit includes: a signal generator and a frequency synthesizer, wherein the frequency synthesizer is connected to the signal generator, the mapping circuit and the logic operator respectively;

[0026] The signal generator generates a reference pulse signal with uniform phase intervals in response to the initial pulse signal;

[0027] The frequency synthesizer generates the pulse signal in response to the reference pulse signal and the first control word;

[0028] Wherein, the first control word includes a first coefficient and a second coefficient;

[0029] The pulse signal includes the first frequency signal generated based on the reference pulse signal and the first coefficient and the second frequency signal generated based on the reference pulse signal and the first coefficient. The proportion of the first frequency signal and the second frequency signal in the pulse signal is controlled by the second coefficient.

[0030] Optionally, the frequency synthesizer includes: a first processing unit, a second processing unit and an output unit;

[0031] a first processing unit, connected to the mapping circuit, and generating a first control signal and a second control signal based on the first control word;

[0032] a second processing unit connected to the first processing unit, selecting a first pulse signal from a reference pulse signal with uniform phase intervals based on the first control signal, selecting a second pulse signal from the reference pulse signal based on the second control signal, and selecting one of the first pulse signal and the second pulse signal as an output signal;

[0033] The output unit is connected to the second processing unit and generates the pulse signal based on the output signal of the second processing unit.

[0034] Optionally, the logic operation corresponding to the logic operator includes one of an AND gate, an OR gate, and a data selector.

[0035] Optionally, the control circuit is further configured to control the calculation circuit to stop calculation based on the two first control words when controlling the mapping circuit to map the two numbers to be calculated into the two second control words.

[0036] At least one embodiment of the present disclosure provides a random calculation method, the random calculation method comprising:

[0037] Mapping two numbers to be calculated into a first control word respectively to obtain two first control words;

[0038] generating two sequences based on the two first control words, performing a logic operation on the two sequences, and counting result sequences output by the logic operation to obtain a calculation result;

[0039] When the two first control words meet a condition, output the calculation result; when the two first control words do not meet the condition, map the two numbers to be calculated into two second control words, where the second control words are different from the first control word; when the two second control words meet the condition, output the calculation result obtained based on the two second control words;

[0040] When the two first control words meet a condition, the two sequences are unrelated; when the two first control words do not meet the condition, the two sequences are related.

[0041] Optionally, the random calculation method further includes:

[0042] Converting the two first control words into two integer values ​​respectively;

[0043] Determine whether the two integer values ​​are mutually prime; if the two integer values ​​are mutually prime, it indicates that the two first control words meet a condition; if the two integer values ​​are not mutually prime, it indicates that the two first control words do not meet the condition.

[0044] Optionally, the first control word includes an integer part and a decimal part;

[0045] The converting the two first control words into two integer values ​​respectively includes:

[0046] The virtual decimal point between the integer part and the decimal part is moved to the end of the decimal part, and the digits with the end being 0 are removed to obtain the integer value.

[0047] Optionally, mapping the two numbers to be calculated into a first control word respectively to obtain two first control words includes:

[0048] A mapping table of numbers and control words is obtained, and the two numbers to be calculated are mapped to the two first control words according to the mapping table, wherein one number in the mapping table corresponds to multiple control words, and the duty cycles of the sequences corresponding to the multiple control words are the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a structural diagram of a random calculation circuit provided by an embodiment of the present disclosure;

[0050] Figure 2 is a structural diagram of a random calculation circuit provided by an embodiment of the present disclosure;

[0051] Figure 3 is a schematic structural diagram of a computing circuit provided by an embodiment of the present disclosure;

[0052] Figure 4 is a schematic structural diagram of a pulse sub-circuit provided by an embodiment of the present disclosure;

[0053] Figure 5 is a schematic structural diagram of a ring oscillator provided by an embodiment of the present disclosure;

[0054] Figure 6 To adopt Figure 5 Waveform diagram of K-channel reference pulse signals with uniform phase intervals generated by the signal generator in FIG.

[0055] Figure 7 This is a schematic diagram of the principle of using a frequency synthesizer to synthesize a pulse signal;

[0056] Figure 8 is a structural diagram of a frequency synthesizer provided by an embodiment of the present disclosure;

[0057] Figure 9 is a flow chart of a random calculation method provided by an embodiment of the present disclosure;

[0058] Figure 10 is a flow chart of a random calculation method provided by an embodiment of the present disclosure;

[0059] Figure 11 This is a timing diagram provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] To make the principles and advantages of the present disclosure more clear, the embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings.

[0061] Figure 1 Schematic diagram of a random calculation circuit provided by an embodiment of the present disclosure. Figure 1The random calculation circuit includes: a mapping circuit 10, a calculation circuit 11 and a control circuit 12. The mapping circuit 10 is electrically connected to the calculation circuit 11 and the control circuit 12 respectively, and the calculation circuit 11 is also electrically connected to the control circuit 12.

[0062] The mapping circuit 10 is used to map two numbers to be calculated into a first control word respectively, so as to obtain two first control words.

[0063] The calculation circuit 11 is configured to generate two sequences based on the two first control words, perform a logic operation on the two sequences, and count result sequences output by the logic operation to obtain a calculation result.

[0064] The control circuit 12 is used to control the calculation circuit to output the calculation result when the two first control words meet the conditions; control the calculation circuit not to output the calculation result when the two first control words do not meet the conditions, and control the mapping circuit to re-map the two numbers to be calculated into two second control words, which are different from the first control words; and control the calculation circuit to output the calculation result obtained based on the two second control words when the two second control words meet the conditions.

[0065] When the two first control words meet a condition, the two sequences are unrelated; when the two first control words do not meet the condition, the two sequences are related.

[0066] In the disclosed embodiment, the number to be calculated is first mapped to two control words. The control word can be used to generate a sequence used in random calculation on the one hand; on the other hand, the control word can also be used to judge whether the sequence used in random calculation has correlation. When the two first control words meet the conditions, it means that the two sequences are not correlated. At this time, the calculation result obtained by the calculation circuit using the two sequences for logical operation is accurate, and the control calculation circuit outputs the calculation result. When the two first control words do not meet the conditions, it means that the two sequences are correlated. At this time, the calculation result obtained by the calculation circuit using the two sequences for logical operation is inaccurate, and the control calculation circuit does not output the calculation result, and remaps the control word, and repeats the calculation and judgment process until the accurate calculation result can be output. This method can first ensure the accuracy of random calculation. When the calculation result is inaccurate, the control word is remapped and recalculated, which wastes less time and has high computational efficiency. The random calculation circuit can be integrated into various chips as a digital intellectual property core (Intellectual Property core, IPcore), with low cost and good portability.

[0067] In the above scheme, after the calculation circuit 11 obtains the second control word, it also generates two sequences based on the two second control words, performs logical operations on the two sequences, counts the result sequences output by the logical operations, and obtains the calculation results. The calculation method is the same as the process based on the two first control words.

[0068] Optionally, the control circuit 12 is further configured to control the calculation circuit 12 to stop calculation based on the two first control words when the mapping circuit 11 is controlled to map the two numbers to be calculated into two second control words.

[0069] Here, controlling the calculation circuit 12 to stop calculation can be achieved by the control circuit 12 sending an instruction signal to the control circuit.

[0070] In the disclosed embodiments, the control word is typically a number that controls the calculation circuit to generate a sequence that can represent the number to be calculated. For example, when the number to be calculated is 1 / 2, under the control of the control word, the calculation circuit generates a sequence that can represent 1 / 2, such as the sequence 10101010.

[0071] Optionally, the mapping circuit 10 is further configured to record a mapping record of a number to be calculated in a current calculation task, so that repeated mapping to the same control word can be avoided during subsequent remapping.

[0072] Exemplarily, when remapping the control words, only one of the control words may be remapped, or two of the control words may be remapped simultaneously.

[0073] Figure 2 Schematic diagram of a random calculation circuit provided by an embodiment of the present disclosure. Figure 1 structure, Figure 2 The detailed structure of the control circuit 12 is shown in FIG. Figure 2 The control circuit 12 includes: a control word conversion subcircuit 121 and a mutual prime judgment subcircuit 122, and the control word conversion subcircuit 121 is electrically connected to the mapping circuit 10 and the mutual prime judgment subcircuit 122 respectively.

[0074] The control word conversion sub-circuit (or referred to as a control word converter, Control Word Transformer) 121 is used to convert the two first control words into two integer values ​​respectively;

[0075] The relatively prime determination subcircuit (or relatively prime estimator) 122 is used to determine whether the two integer values ​​are relatively prime; if the two integer values ​​are relatively prime, it indicates that the two first control words meet the condition; if the two integer values ​​are not relatively prime, it indicates that the two first control words do not meet the condition.

[0076] In the embodiment of the present disclosure, when the integer values ​​converted from two control words are relatively prime, it indicates that the corresponding two sequences are unrelated.

[0077] Exemplarily, the first control word includes an integer part and a fractional part;

[0078] The control word conversion sub-circuit 121 is configured to move the virtual decimal point between the integer part and the decimal part to the end of the decimal part, and remove the digits with the end being 0 to obtain the integer value.

[0079] For example, the first control word F has a total length of n bits, of which the decimal occupies m bits. That is, a virtual decimal point is set at the mth position, and the position before the decimal point is the integer, and the position after the decimal point is the decimal. Assuming that the integer part of the first control word F is 1 and the decimal part is r, then:

[0080]

[0081]

[0082] The integer value to be converted is Iqp = I × 2 m +p=F×2 m , which means shifting the virtual decimal point by m places. Where p represents the decimal part and r represents the numerator when it is a fraction. For example, when r is 0.5, m is 1 and p is 1.

[0083] For example, if F=00010.100, and the integer is 5 digits and the decimal is 3 digits, F converted to decimal is 2+1 / 2, that is, m=1, that is, the virtual decimal point is moved one place to the right to obtain Iqp=00000101 (that is, the last 0 is removed after moving to the last digit), which is 5 when converted to decimal.

[0084] Illustratively, the coprime determination subcircuit 122 is configured to determine whether the two integer values ​​are coprime by using a binary Euclidean algorithm.

[0085] The method of using the binary Euclidean algorithm to determine whether the two integer values ​​are mutually prime is as follows:

[0086] Rule 1. If a and b are both even, gcd(a,b) = 2*gcd(a / 2,b / 2);

[0087] Rule 2. If a is even and b is odd, gcd(a,b) = gcd(a / 2,b);

[0088] Rule 3. If a is odd and b is even, gcd(a,b) = gcd(a,b / 2);

[0089] Rule 4. If both a and b are odd numbers, when a > b, gcd(a, b) = gcd(a - b, b); when a < b, gcd(a, b) = gcd(a, b - 1).

[0090] Among them, a and b are the above-mentioned 2 integer values, that is, the above-mentioned Iqp. gcd(a, b) represents the greatest common divisor of a and b. If the greatest common divisor of two integers only includes 1, it means that these two integers are relatively prime. If the greatest common divisor of two integers includes other values in addition to 1, it means that these two integers are not relatively prime.

[0091] For example, if a = 35 and b = 20, then:

[0092] Step 1: Based on Rule 3, gcd(35, 20) = gcd(35, 20 / 2) = gcd(35, 10);

[0093] Step 2: Based on Rule 3, gcd(35, 10) = gcd(35, 10 / 2) = gcd(35, 5);

[0094] Step 3: Based on Rule 4, gcd(35, 5) = gcd(35 - 5, 5) = gcd(30, 5);

[0095] Step 4: Based on Rule 2, gcd(30, 5) = gcd(30 / 2, 5) = gcd(15, 5);

[0096] Step 5: Based on Rule 4, gcd(15, 5) = gcd(15 - 5, 5) = gcd(10, 5);

[0097] Step 6: Based on Rule 2, gcd(10, 5) = gcd(10 / 2, 5 = gcd(5, 5);

[0098] Based on Step 6, it can be seen that the greatest common divisor of a and b includes 5 in addition to 1. Therefore, a and b are not relatively prime.

[0099] Exemplarily, the mapping circuit 10 stores a mapping table of numbers and control words. One number in the mapping table corresponds to multiple control words, and the duty cycles of the sequences corresponding to the multiple control words are the same.

[0100] For example, in this mapping table, the decimal parts of the multiple control words corresponding to each number are non-zero decimals, thereby increasing the probability of relatively prime of the integer values converted from the two first control words and improving the calculation efficiency.

[0101] In this mapping table, the number of bits of the control words corresponding to different numbers is the same. For example, they are all 8 bits, and usually the number of bits of the integer part of different control words is the same, and the number of bits of the decimal part of different control words is the same.

[0102] Figure 3 Schematic diagram of a computing circuit provided by an embodiment of the present disclosure. Figure 3 The calculation circuit 11 includes: a sequence generating sub-circuit 111, a logic operator 112 and a counting sub-circuit 113. The logic operator 112 is electrically connected to the sequence generating sub-circuit 111 and the counting sub-circuit 113 respectively. The sequence generating sub-circuit 111 is also connected to the mapping circuit 10.

[0103] The sequence generation subcircuit 111 is configured to output two pulse signals in response to the two first control words, wherein the pulse signals are used to represent the sequence, and the pulse signals include a first frequency signal and a second frequency signal, wherein the probability of the first frequency signal and the second frequency signal appearing in the pulse signals is controlled by the corresponding first control words;

[0104] The logic operator 112 is used to perform a logic operation on the two sequences represented by the two pulse signals and output a pulse representing the result sequence;

[0105] The counting subcircuit 113 is used to count the high and low levels of the pulses representing the result sequence to obtain the calculation result.

[0106] Exemplarily, the pulse signal is a periodic signal, and the sequence in the embodiment of the present disclosure may be a period of the pulse signal, or a partial representation of less than one period or more than one period.

[0107] Exemplarily, the sequence generation subcircuit 111 includes:

[0108] Two pulse sub-circuits 110 , each of the pulse sub-circuit 110 generates a pulse signal according to one of the first control words.

[0109] Exemplarily, the pulse subcircuits each include a frequency mixing (FM) subcircuit, and the frequency mixing subcircuit may be implemented using a direct frequency averaging (DFA) technique.

[0110] For example, the random calculation circuit can be used to implement a multiplication operation. When implementing a multiplication operation, the logic operator 112 is an AND gate, that is, multiplication is implemented through an AND operation. The random calculation circuit can also be used to implement other operations, such as addition, subtraction, division, square root, square, etc. For example, when implementing an addition operation, the logic operator 112 is an OR gate or a multiplexer (MUX).

[0111] Exemplarily, the counting subcircuit 113 includes a D-flip Flop (DFF) 131. The input of the D-flip Flop 131 is connected to the logic operator 112, the control terminal of the D-flip Flop 131 is connected to the clock subcircuit 132, and the output of the D-flip Flop 131 outputs the counting result, i.e., the final calculation result.

[0112] Of course, the counting subcircuit 113 may also be implemented in other ways. For example, the counting subcircuit 113 includes a register and the register is used to implement counting.

[0113] The counting subcircuit 113 can count the 1s (high level) and 0s (low level) in the output sequence respectively to obtain a calculation result C1 / C10, where C1 is the count value of 1s and C2 is the total value of 1s and 0s. Of course, in other implementations, C1 can also be a count value of 0.

[0114] Figure 4 FIG1 shows a schematic diagram of the structure of a pulse subcircuit provided by an embodiment of the present disclosure. Figure 4 The pulse sub-circuit 110 includes a signal generator 101 and a frequency synthesizer 102. The frequency synthesizer 102 is electrically connected to the signal generator 101, the mapping circuit 10 and the logic operator 112 respectively.

[0115] The signal generator 101 generates a reference pulse signal with uniform phase intervals in response to the initial pulse signal, and the frequency synthesizer 102 generates the pulse signal in response to the reference pulse signal with uniform phase intervals and the first control word.

[0116] In which, the first control word includes a first coefficient and a second coefficient; the pulse signal includes generating the first frequency signal based on a reference pulse signal with uniform phase intervals and a second coefficient and generating the second frequency signal based on a reference pulse signal with uniform phase intervals and a second coefficient, and the proportion of the first frequency signal and the second frequency signal in the pulse signal is controlled by the first coefficient.

[0117] In this implementation, the pulse subcircuit consists of two parts, wherein the signal generator is responsible for generating a reference pulse signal with uniform phase intervals, and the frequency synthesizer is responsible for generating a pulse signal according to the reference pulse signal with uniform phase intervals and the first control word.

[0118] Exemplarily, the initial pulse signal can be generated by a voltage-controlled oscillator 100, for example, an inductor-capacitor voltage-controlled oscillator (LC Voltage Controlled Oscillator, LCVCO) is used as an oscillation source to generate the above-mentioned initial pulse signal. That is, the pulse subcircuit can also include a voltage-controlled oscillator, and the output end of the voltage-controlled oscillator is electrically connected to the input end of the signal generator. Different pulse subcircuits use different LCVCOs to generate initial pulse signals, and then pass through different signal generators, so that the initial phase and noise characteristics of the evenly spaced reference pulse signal in each pulse subcircuit are different, thereby increasing the unpredictability of the final output.

[0119] Exemplarily, the signal generator 101 may be a ring oscillator (RO). Figure 5 shows a schematic diagram of the structure of the ring oscillator, see Figure 5 The ring oscillator includes multiple NAND gates, which are connected to form a loop. The ring oscillator has multiple pins P0-P15, one of which can be used as an input end to input an initial pulse signal. The initial pulse signal is delayed by the NAND gate, and other pins are used as output ends to output multiple reference pulse signals, and the multiple reference pulse signals are reference pulse signals with uniform phase intervals.

[0120] The reference pulse signal with uniform phase intervals means that the phase changes of the multiple pulse signals generated by the signal generator 101 are the same, and the initial phase intervals of the multiple pulse signals are equal.

[0121] Figure 6 To adopt Figure 5 The waveform diagram of the K-way reference pulse signal with uniform phase intervals generated by the signal generator in FIG. Figure 6 , the waveforms of any two signals are the same (i.e., the period and amplitude are the same), and the waveforms of the K signals are evenly arranged, i.e., the intervals are the same. The phase difference between any two adjacent signals is the basic time unit Δ, and the frequency of the K signals is f i , K is an integer greater than 2.

[0122] In one implementation of the embodiment of the present disclosure, the frequency synthesizer 200 is configured to generate a pulse signal according to the following formula:

[0123] T TAF =(1-r)*T A +r*T B , T A =I*Δ,T B =(I+1)*Δ;

[0124] That is, T TAF=(1-r)*I*Δ+r*(I+1)*Δ=(I+r)*Δ, the first control word F=I+r.

[0125] Among them, T TAF is the period of the pulse signal, T A is the first frequency signal (or called the first periodic signal), T B is the second frequency signal (or the second periodic signal); I is the aforementioned second coefficient, which is used to select from the K-way reference pulse signal to synthesize the frequency signal; r is the aforementioned first coefficient, which is used to control the probability of the first frequency signal and the second frequency signal appearing, where r controls T B The probability of occurrence, 1-r controls T A Probability of occurrence.

[0126] For example, if the first control word I is 3 and r is 0.5... (subsequent decimal places are not shown), then in the first cycle, two reference pulse signals with a phase difference of 3Δ are selected from the K reference pulse signals, and then synthesized and output T A =3Δ, in the second cycle, two reference pulse signals with a phase difference of 4Δ are selected, and then synthesized and output T B =4Δ, where Δ is the phase difference between any two adjacent signals in the K-channel reference pulse signals with uniform phase intervals.

[0127] In the disclosed embodiments, the first control word can be an integer or a decimal. Each first control word can be split into an integer portion and a decimal portion. The integer portion can be used as the aforementioned second coefficient, and the decimal portion can be used as the aforementioned first coefficient to achieve frequency signal synthesis. For example, if the first control word is 5.4..., then the integer portion is 5 and the decimal portion is 0.4... For another example, if the first control word is 6, then the integer portion is 6 and the decimal portion is 0.

[0128] The following explains why when the two integer values ​​converted from the two first control words are mutually prime, the two output sequences are unrelated:

[0129] Assume that the first control words corresponding to the two numbers to be calculated are Fx and Fy, and the converted integer values ​​are Iqp x and Iqp y , the corresponding sequences are X and Y respectively. The premise for X and Y to complete random calculation is that X and Y are uncorrelated. The period of X and Y can be expressed as T in the following way X and T Y :

[0130] T X =Iqp x ·Δ,T Y =Iqp y Δ;

[0131] It can be seen that sequences X and Y both contain multiple periods T TAF , when sampled with a resolution of Δ, the X sequence can be expressed as Ω X :

[0132] Ω X ={X0,X1,X2,…,X Iqpx-1},X i ={0,1}, where i represents the sequence number of the element;

[0133] When X is sampled using Y, the resulting sequence can be expressed as Ω X|Y :

[0134] Ω X|Y ={Iqp y ·i mod Iqp x ∶i∈N}; N is a set of natural numbers;

[0135] When Iqp x and Iqp y When they are mutually prime, Ω X and Ω X|Y Equal, that is

[0136]

[0137] but

[0138]

[0139] Because P(X)P(Y)=P(X∩Y), X and Y are independent when Iqpx and Iqpy are prime numbers to each other, X and Y are independent, which means that X and Y are unrelated.

[0140] In the embodiment of the present disclosure, the sequence adopts a period T X =Iqp x ·Δ,T Y =Iqp y ·Δ represents, where each Δ time can be defined as 0 or 1, realizing the coding characteristics in units of Δ, that is, the random calculation circuit provided by the embodiment of the present disclosure has digital calculation characteristics. At the same time, the duty cycle within the period (that is, the proportion of 1 in the sequence represented) participates in the calculation to represent the number to be calculated, that is, the random calculation circuit provided by the embodiment of the present disclosure has analog calculation characteristics. By combining the frequency period and the duty cycle to jointly represent a number, it embodies the dual characteristics of the combination of digital and analog, making the random calculation more accurate and efficient.

[0141] Figure 7 This is a schematic diagram of the principle of using a frequency synthesizer to synthesize a pulse signal. Figure 7 , the frequency synthesizer uses the concept of time-averaged frequency to synthesize the output pulse signal. The following takes the synthesis of the first frequency signal as an example: the frequency synthesizer receives the first control word and K-way phase-uniformly spaced reference pulse signals. The first control word F = I + r, where I is the integer part and r is the decimal part; the phase difference between any two adjacent signals in the K-way phase-uniformly spaced reference pulse signals is the basic time unit Δ. The frequency synthesizer first constructs two different clock periods T based on the basic time unit Δ and the integer part I in the first control word F. A and T B , T A =I·Δ,T B =(I+1)·Δ, T B Compared to T A The cycle is larger, Figure 7 T B The length of the high level (or low level) is longer than T A After that, the frequency synthesizer controls T based on the fractional part r in the first control word F. A and T B The probability of occurrence, that is, the ratio of the first frequency signal to the second frequency signal mentioned above, thereby generating a pulse signal.

[0142] The fractional part of the first control word affects T A and T B The probability of occurrence, when the decimal part is 0.5, T A and T B The probability of occurrence is equal, see Figure 7 The pulse signal shown, where T A and T B When the decimal part is less than 0.5, T A The probability of occurrence is greater than T B , the special case is when the decimal part is 0, the pulse signal only has T A One component; when the decimal part is greater than 0.5, T B The probability of occurrence is greater than T A .

[0143] Figure 8 This is a schematic diagram of the structure of a frequency synthesizer provided by the present disclosure. Figure 8 The frequency synthesizer may include a first processing unit 21 , a second processing unit 22 and an output unit 23 .

[0144] a first processing unit 21 connected to the mapping circuit 10, generating a first control signal and a second control signal based on the first control word; a second processing unit 22 connected to the first processing unit 21, selecting a first pulse signal from a reference pulse signal with uniform phase intervals based on the first control signal, and selecting a second pulse signal from the reference pulse signal based on the second control signal, and selecting one of the first pulse signal and the second pulse signal as an output signal;

[0145] The output unit 23 is connected to the second processing unit 22 , and generates the pulse signal based on the output signal of the second processing unit 22 .

[0146] The following combination Figure 8 The detailed working process of the first processing unit 21, the second processing unit 22 and the output unit 23 is described as follows:

[0147] The first processing unit 21 includes a first logic controller 211 and a second logic controller 212 .

[0148] refer to Figure 8 The first logic controller 211 includes a first adder 2111, a first register 2112, and a second register 2113. The first register 2112 is connected to the first adder 2111 and the second register 2113. The first logic controller 211 is used to generate a first control signal.

[0149] The first adder 2111 adds the first control word F and the most significant bits (e.g., 5 bits) stored in the first register 2112, and then saves the addition result to the first register 2112 at the rising edge of the second clock frequency CLK2. Alternatively, the first adder 2111 may add the first control word F and all bits stored in the first register 2112, and then save the addition result to the first register 2112 at the rising edge of the second clock frequency CLK2. At the next rising edge of the second clock frequency CLK2, the most significant bits stored in the first register 2112 are stored in the second register 2113, serving as the selection signal for the first K→1 multiplexer 221, i.e., the aforementioned first control signal, for selecting one signal from the K reference pulse signals with even phase intervals as the first pulse signal.

[0150] When adding the first control word F and the most significant bit stored in the first register 2112, assuming that the value in the first register 2112 is less than 1, if the decimal part of the addition result is carried, the most significant bit stored in the second register 2113 is I+1. If the first control word does not carry during the addition, the most significant bit stored in the second register 2113 is 1. When the second register 2113 contains I+1, the corresponding output of the frequency synthesizer is T B =(I+1)·Δ, when the value in the second register 2113 is I, the frequency synthesizer outputs T A =I·Δ, it can be seen that the output T A Still T B It is related to the size of the decimal part of the first control word. The smaller the decimal part of the first control word, the less likely it is to carry. The output T A The greater the probability, the lower the output value. B The probability is high.

[0151] Here, the first register 2112 may include a first portion for storing integers and a second portion for storing decimals. During addition, the integer portion of the first control word F is added to the contents of the first portion, while the decimal portion of the first control word F is added to the contents of the second portion. This addition is binary and is implemented by an adder.

[0152] The second logic controller 212 includes a second adder 2121, a third register 2122, and a fourth register 2123. The third register 2122 is connected to the second adder 2121 and the fourth register 2123. The second logic controller 212 is used to generate a second control signal.

[0153] The second adder 2121 adds the high-level proportion control word D and the most significant bit stored in the first register 2112, and then saves the addition result to the third register 2122 at the rising edge of the second clock frequency CLK2. After the addition result is saved in the third register 2122, at the rising edge of the first clock frequency CLK1, the information stored in the third register 2122 will be stored in the fourth register 2123 and used as the selection signal of the second K→1 multiplexer 222, that is, the aforementioned second control signal, for selecting one signal from the K multi-phase input signals as the second pulse signal. The second clock frequency CLK2 is the signal of the first clock frequency CLK1 after passing through the NOT gate. The high-level proportion control word D is used to indicate T A The proportion of medium and high levels and T B For example, D includes two values, one of which is used to control T A The proportion of medium and high levels, and another value is used to control T BThe proportion of the medium and high levels, the two values ​​are periodically and alternately input into the second adder 2121.

[0154] refer to Figure 8 The second processing unit 22 includes a first K→1 multiplexer 221, a second K→1 multiplexer 222, and a 2→1 multiplexer 223. The first K→1 multiplexer 221 and the second K→1 multiplexer 222 each include a plurality of input terminals, a control input terminal, and an output terminal. The 2→1 multiplexer 223 includes a control input terminal, an output terminal, a first input terminal, and a second input terminal. The output end of the first K→1 multiplexer 221 is connected to the first input end of the 2→1 multiplexer 223, and the output end of the second K→1 multiplexer 222 is connected to the second input end of the 2→1 multiplexer 223; multiple input ends of the first K→1 multiplexer 221 and multiple input ends of the second K→1 multiplexer 222 are all connected to a signal generator; the control input end of the first K→1 multiplexer 221 is connected to the second register 2113, and the control input end of the second K→1 multiplexer 222 is connected to the fourth register 2123.

[0155] Under the control of the first control signal generated by the first logic controller 211, the control input end of the first K→1 multiplexer 221 selects one signal from the K-channel phase-uniformly spaced reference pulse signals as the output signal, namely, the first pulse signal; under the control of the second control signal generated by the second logic controller 212, the control input end of the second K→1 multiplexer 222 selects one signal from the K-channel phase-uniformly spaced reference pulse signals as the output signal, namely, the second pulse signal.

[0156] Taking the first K→1 multiplexer as an example, when selecting the output signal, it can be selected based on the value stored in the second register 2113, that is, the numerical value of the first control signal. For example, if the first control signal is 3, the third of the K phase-uniformly spaced reference pulse signals is selected as the output.

[0157] The 2→1 multiplexer 223 can select one of the first pulse signal output from the first K→1 multiplexer 221 and the second pulse signal output from the second K→1 multiplexer 222 at the rising edge of the first clock frequency CLK1 as the output signal of the 2→1 multiplexer 223. For example, the first pulse signal may be selected starting at the first rising edge and continuing until the second rising edge, the second pulse signal may be selected starting at the second rising edge and continuing until the third rising edge, and so on.

[0158] Since the 2→1 multiplexer selects from the outputs of the two K→1 multiplexers, the outputs of the two K→1 multiplexers are combined to form a new cycle. Since the first pulse signal and the second pulse signal of the output of the two K→1 multiplexers differ by an integer Δ, and there are two cases where the difference is I Δ and I+1 Δ, the pulse signal output by the final frequency synthesizer has T A and T B Two different cycles.

[0159] refer to Figure 8 , the output unit 23 includes a trigger circuit. The trigger circuit is used to generate a pulse train. The trigger circuit includes a D flip-flop 231, a first inverter 232 and a second inverter 233. The D flip-flop 231 includes a data input terminal, a clock input terminal and an output terminal. The first inverter 232 includes an input terminal and an output terminal. The second inverter 233 includes an input terminal and an output terminal. The clock input terminal of the D flip-flop 231 is connected to the 2→1 multiplexer 223, the data input terminal of the D flip-flop 231 is connected to the output terminal of the first inverter 232, and the output terminal of the D flip-flop 231 is respectively connected to the input terminal of the first inverter 232 and the input terminal of the second inverter 233. The output terminal of the D flip-flop 231 or the output terminal of the second inverter 233 can be used as the output terminal of the frequency synthesizer, that is, one end that generates a pulse signal. Therefore, the pulse signal output by the frequency synthesizer is also Figure 8 The first clock frequency CLK1 or the second clock frequency CLK2.

[0160] In the embodiment of the present disclosure, the first clock signal and the second clock signal are the first clock frequency CLK1 output by the frequency synthesizer when different first control words are input. Alternatively, the first clock signal and the second clock signal are the second clock frequency CLK2 output by the frequency synthesizer when different first control words are input.

[0161] The clock input terminal of the D flip-flop 231 receives the output from the output terminal of the 2→1 multiplexer 223, and outputs the first clock frequency CLK1 through the output terminal; the input terminal of the first inverter 232 receives the first clock frequency CLK1, and outputs the output signal to the data input terminal of the D flip-flop 231; the input terminal of the second inverter 233 receives the first clock frequency CLK1, and outputs the second clock frequency CLK2 through the output terminal.

[0162] Figure 9 This is a flow chart of a random calculation method provided by an embodiment of the present disclosure. Figure 9 , the random calculation method includes:

[0163] 901: Map two numbers to be calculated into a first control word respectively to obtain two first control words.

[0164] 902: Generate two sequences based on the two first control words, perform a logical operation on the two sequences, count result sequences output by the logical operation, and obtain a calculation result.

[0165] 903: When the two first control words meet the conditions, output the calculation result; when the two first control words do not meet the conditions, do not output the calculation result, and map the two numbers to be calculated into two second control words, which are different from the first control words; when the two second control words meet the conditions, output the calculation result obtained based on the two second control words.

[0166] When the two first control words meet a condition, the two sequences are unrelated; when the two first control words do not meet the condition, the two sequences are related.

[0167] In the disclosed embodiment, the number to be calculated is first mapped to two control words. On the one hand, the control words can be used to generate the sequence used in the random calculation; on the other hand, the control words can also be used to determine whether the sequence used in the random calculation has correlation. When the two first control words meet the conditions, it means that the two sequences are not correlated. At this time, the calculation result obtained by the calculation circuit using the two sequences for logical operation is accurate, and the control calculation circuit outputs the calculation result. When the two first control words do not meet the conditions, it means that the two sequences are correlated. At this time, the calculation result obtained by the calculation circuit using the two sequences for logical operation is inaccurate, and the control calculation circuit does not output the calculation result, and remaps the control words, and repeats the calculation and judgment process until an accurate calculation result can be finally output. This method can firstly ensure the accuracy of the random calculation. At the same time, when the calculation result is inaccurate, the control words are remapped and recalculated, which wastes less time and has high calculation efficiency. The random calculation circuit can be integrated into various chips as a digital intellectual property core, with low cost and good portability.

[0168] Figure 10 This is a flow chart of a random calculation method provided by an embodiment of the present disclosure. Figure 10 , the random calculation method includes:

[0169] 1001: Map two numbers to be calculated into a first control word respectively to obtain two first control words.

[0170] Exemplarily, mapping the two numbers to be calculated into a first control word respectively to obtain two first control words includes:

[0171] A mapping table of numbers and control words is obtained, and the two numbers to be calculated are mapped to the two first control words according to the mapping table, wherein one number in the mapping table corresponds to multiple control words, and the duty cycles of the sequences corresponding to the multiple control words are the same.

[0172] Optionally, the method further includes:

[0173] Record the mapping record of the numbers to be calculated in the current calculation task, so that when remapping is done later, repeated mapping to the same control word can be avoided.

[0174] This step is performed by the aforementioned mapping circuit 10 .

[0175] 1002: Generate two sequences based on the two first control words, perform a logic operation on the two sequences, count result sequences output by the logic operation, and obtain a calculation result.

[0176] Exemplarily, generating two sequences based on the two first control words includes:

[0177] In response to the two first control words, output two pulse signals, the pulse signals being used to represent the sequence, the pulse signals comprising a first frequency signal and a second frequency signal, the probabilities of the first frequency signal and the second frequency signal appearing in the pulse signals being controlled by the corresponding first control words;

[0178] Performing a logical operation on the two sequences represented by the two pulse signals, and outputting pulses representing the result sequence;

[0179] The high and low levels of the pulses representing the result sequence are counted to obtain the calculation result.

[0180] The two pulse signals are generated by two pulse sub-circuits, and each of the pulse sub-circuits generates a pulse signal according to one of the first control words. The generation process is as follows:

[0181] generating a reference pulse signal with uniform phase intervals in response to the initial pulse signal;

[0182] generating the pulse signal in response to the reference pulse signal and the first control word;

[0183] Wherein, the first control word includes a first coefficient and a second coefficient;

[0184] The pulse signal includes the first frequency signal generated based on the reference pulse signal and the first coefficient and the second frequency signal generated based on the reference pulse signal and the first coefficient. The proportion of the first frequency signal and the second frequency signal in the pulse signal is controlled by the second coefficient.

[0185] Exemplarily, generating the pulse signal in response to the reference pulse signal and the first control word includes:

[0186] generating a first control signal and a second control signal respectively based on the first control word;

[0187] selecting a first pulse signal from a reference pulse signal with uniform phase intervals based on the first control signal, and selecting a second pulse signal from the reference pulse signal based on the second control signal, and selecting one of the first pulse signal and the second pulse signal as an output signal;

[0188] The pulse signal is generated based on the output signal of the second processing unit.

[0189] In the embodiment of the present disclosure, random calculation can be used to implement a multiplication operation. When implementing the multiplication operation, the logical operation is an AND operation.

[0190] This step is performed by the aforementioned calculation circuit 11.

[0191] 1003: Convert the two first control words into two integer values ​​respectively.

[0192] Exemplarily, the first control word includes an integer part and a fractional part;

[0193] The converting the two first control words into two integer values ​​respectively includes:

[0194] The virtual decimal point between the integer part and the decimal part is moved to the end of the decimal part, and the digits with the end being 0 are removed to obtain the integer value.

[0195] 1004: Determine whether the two integer values ​​are mutually prime; if the two integer values ​​are mutually prime, it indicates that the two first control words meet the condition, and step 1005 is executed; if the two integer values ​​are not mutually prime, it indicates that the two first control words do not meet the condition, and step 1006 is executed.

[0196] Exemplarily, whether the two integer values ​​are coprime may be determined by a binary Euclidean algorithm.

[0197] 1005: When the two first control words meet a condition, output the calculation result.

[0198] 1006: If the two first control words do not meet the conditions, the calculation result is not output, and the two numbers to be calculated are mapped to two second control words, that is, step 1001 is re-executed, where the second control words are different from the first control word. If the two second control words meet the conditions, the calculation result obtained based on the two second control words is output.

[0199] When remapping the control words, only one of the control words may be remapped, or two of the control words may be remapped simultaneously.

[0200] Steps 1003 to 1006 are executed by the control circuit 12 .

[0201] Optionally, the method further includes: when mapping the two numbers to be calculated to the two second control words, stopping the calculation based on the two first control words.

[0202] Figure 11 The timing diagram provided by the embodiment of the present disclosure is shown in FIG. Figure 11 As shown, 20 represents the timing of the control circuit, 30 represents the timing of the calculation circuit, and T represents time.

[0203] In 20, A indicates that the control circuit determines that the two first control words meet the conditions, which is recorded as a hit. B indicates the control circuit's idle state. C indicates that the control circuit determines that the two first control words do not meet the conditions, which is recorded as a miss. In 30, P1, P2, P3, and P4 represent four computation tasks. These four computation tasks can correspond to four processes, or four computations of one or more processes.

[0204] See also Figure 11 When the control circuit determines that the hit is found, the calculation circuit calculates and outputs the calculation result, as shown in P1, P3, and P4. When the control circuit determines that the miss is found, the calculation circuit stops calculating and remaps the control word. The control circuit then re-judges. When the re-judgement is a hit, the calculation circuit calculates and outputs the calculation result, as shown in P2.

[0205] Since the control circuit will control the calculation circuit to stop calculation when a miss occurs, the lost time is very small, as shown by the time length D in the figure. Therefore, this calculation method causes a small miss penalty and has high calculation efficiency.

[0206] In the embodiment of the present disclosure, whether a hit is hit is determined by judging the mutual primality. Since the mutual primality of even numbers is easier to judge, and when the first control word contains a non-zero decimal, the converted integer value Iqp is usually an odd number (because Iqp=I*2m+p, I*2m is an even number, p is an odd number, and the sum of even and odd numbers is an odd number), when two odd numbers are given arbitrarily, the probability that the two numbers are mutually prime is generally greater than 80%, that is, the hit probability is high. A single computing task is defined as a process. When any process starts working, it assumes that the two integer values ​​Iqp1 and Iqp2 are mutually prime. At this time, the control circuit and the computing circuit start and process the rows. The control circuit will complete the mutual primality judgment within a few clock cycles, and then output the mutual primality result to the computing circuit. If the two numbers are mutually prime (hit), the calculation continues until the result is output. If the two numbers are not mutually prime (miss), the computing circuit stops the calculation and returns for remapping. The overall computing time is:

[0207] Total time = number of processes × (average execution time + miss probability × time lost due to miss).

[0208] The average execution time refers to the time it takes for the computation circuit to start calculating and output the result. Since the probability of coprime judgment is higher for control words with non-zero decimal places, the probability of a miss is lower. Furthermore, the judgment is faster for cases where all numbers are even, meaning the time lost due to a miss is smaller. In summary, this small time loss in the case of a miss results in shorter overall computation time and higher computational efficiency.

[0209] It should be noted that the random calculation method provided in the above embodiment and the random calculation circuit embodiment have the same concept, and their implementation process is detailed in the device embodiment, which will not be repeated here.

[0210] The above are merely exemplary embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection defined by the claims appended to the present disclosure.

Claims

1. A random computing circuit, characterized in that: The random calculation circuit includes: A mapping circuit, configured to map two numbers to be calculated into a first control word respectively, to obtain two first control words; a calculation circuit, configured to generate two sequences based on the two first control words, perform a logic operation on the two sequences, and count result sequences output by the logic operation to obtain a calculation result; a control circuit, configured to control the calculation circuit to output the calculation result when the two first control words satisfy a condition; control the mapping circuit to map the two numbers to be calculated into two second control words, where the second control words are different from the first control word, when the two first control words do not satisfy the condition; and control the calculation circuit to output the calculation result obtained based on the two second control words when the two second control words satisfy a condition; Wherein, when the two first control words meet a condition, the two sequences are unrelated; when the two first control words do not meet the condition, the two sequences are related; The control circuit comprises: a control word conversion subcircuit, configured to convert the two first control words or the two second control words into two integer values ​​respectively; The coprime determination subcircuit is configured to determine whether the two integer values ​​are coprime; if the two integer values ​​are coprime, it indicates that the two first control words or the two second control words meet a condition; if the two integer values ​​are not coprime, it indicates that the two first control words or the two second control words do not meet the condition.

2. The random calculation circuit according to claim 1, characterized in that The first control word includes an integer part and a fractional part; The control word conversion subcircuit is used to move the virtual decimal point between the integer part and the decimal part to the end of the decimal part, and remove the number of bits with the end being 0 to obtain the integer value.

3. The random calculation circuit according to claim 1, characterized in that The coprime determination subcircuit is configured to determine whether the two integer values ​​are coprime by using a binary Euclidean algorithm.

4. The random calculation circuit according to any one of claims 1 to 3, characterized in that: The mapping circuit stores a mapping table of numbers and control words, wherein one number in the mapping table corresponds to multiple control words, and the duty cycles of the sequences corresponding to the multiple control words are the same.

5. The random calculation circuit according to any one of claims 1 to 3, characterized in that: The computing circuit comprises: a sequence generating sub-circuit, connected to the mapping circuit, and outputting two pulse signals in response to the two first control words, wherein the pulse signals are used to represent the sequence, and the pulse signals include a first frequency signal and a second frequency signal, wherein the probability of the first frequency signal and the second frequency signal appearing in the pulse signals is controlled by the corresponding first control words; a logic operator, connected to the sequence generating sub-circuit, for performing a logic operation on the two sequences represented by the two pulse signals and outputting a pulse representing the result sequence; The counting subcircuit is connected to the logic operator and is used to count the high and low levels of the pulses representing the result sequence to obtain the calculation result.

6. The random calculation circuit according to claim 5, characterized in that: The sequence generation sub-circuit comprises: Two pulse sub-circuits, each of the pulse sub-circuits generates a pulse signal according to one of the first control words.

7. The random calculation circuit according to claim 6, characterized in that: The pulse subcircuit includes: a signal generator and a frequency synthesizer, wherein the frequency synthesizer is connected to the signal generator, the mapping circuit and the logic operator respectively; The signal generator generates a reference pulse signal with uniform phase intervals in response to the initial pulse signal; The frequency synthesizer generates the pulse signal in response to the reference pulse signal and the first control word; Wherein, the first control word includes a first coefficient and a second coefficient; The pulse signal includes the first frequency signal generated based on the reference pulse signal and the first coefficient and the second frequency signal generated based on the reference pulse signal and the first coefficient. The proportion of the first frequency signal and the second frequency signal in the pulse signal is controlled by the second coefficient.

8. The random calculation circuit according to claim 7, characterized in that: The frequency synthesizer includes: a first processing unit, a second processing unit and an output unit; a first processing unit, connected to the mapping circuit, and generating a first control signal and a second control signal based on the first control word; a second processing unit connected to the first processing unit, selecting a first pulse signal from a reference pulse signal with uniform phase intervals based on the first control signal, selecting a second pulse signal from the reference pulse signal based on the second control signal, and selecting one of the first pulse signal and the second pulse signal as an output signal; The output unit is connected to the second processing unit and generates the pulse signal based on the output signal of the second processing unit.

9. The random calculation circuit according to claim 5, characterized in that: The logic operator includes one of an AND gate, an OR gate, and a data selector.

10. The random calculation circuit according to any one of claims 1 to 3, characterized in that: The control circuit is further configured to control the calculation circuit to stop calculation based on the two first control words when controlling the mapping circuit to map the two numbers to be calculated into the two second control words.

11. A random computing method, characterized in that: The random calculation method comprises: Mapping two numbers to be calculated into a first control word respectively to obtain two first control words; generating two sequences based on the two first control words, performing a logic operation on the two sequences, and counting result sequences output by the logic operation to obtain a calculation result; When the two first control words meet a condition, output the calculation result; when the two first control words do not meet the condition, map the two numbers to be calculated into two second control words, where the second control words are different from the first control word; when the two second control words meet the condition, output the calculation result obtained based on the two second control words; Wherein, when the two first control words meet a condition, the two sequences are unrelated; when the two first control words do not meet the condition, the two sequences are related; The random calculation method further includes: converting the two first control words or the two second control words into two integer values ​​respectively; Determine whether the two integer values ​​are mutually prime; if the two integer values ​​are mutually prime, it indicates that the two first control words or the two second control words meet a condition; if the two integer values ​​are not mutually prime, it indicates that the two first control words or the two second control words do not meet the condition.

12. The random calculation method according to claim 11, characterized in that: The first control word includes an integer part and a fractional part; The converting the two first control words into two integer values ​​respectively includes: The virtual decimal point between the integer part and the decimal part is moved to the end of the decimal part, and the digits with the end being 0 are removed to obtain the integer value.

13. The random calculation method according to any one of claims 11 to 12, characterized in that: The step of mapping the two numbers to be calculated into a first control word respectively to obtain two first control words includes: A mapping table of numbers and control words is obtained, and the two numbers to be calculated are mapped to the two first control words according to the mapping table, wherein one number in the mapping table corresponds to multiple control words, and the duty cycles of the sequences corresponding to the multiple control words are the same.

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