Memory device with multiple row buffers

Abstract

An example memory sub-system includes a plurality of bank groups, where each bank group comprises a plurality of memory banks, a plurality of row buffers, where two or more of the plurality of row buffers are associated with each bank group, and processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising receiving a command from a host identifying a row buffer of the plurality of row buffers, and performing an operation with reference to the identified row buffer.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory systems, and more specifically, to implementing a dynamic random access memory (DRAM) device having multiple row buffers per memory bank or a set of contiguous memory banks. Background Technology

[0002] A DRAM device comprises multiple memory banks grouped into banks, such as sixteen memory banks grouped into four banks. Each memory bank is a memory array containing multiple memory cells, such that each memory cell can store one or more bits of information, depending on the memory cell type. Summary of the Invention Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed descriptions given below and from the accompanying drawings of some embodiments thereof.

[0004] Figure 1 A high-level component diagram of an instance memory subsystem implemented according to various aspects of this disclosure is schematically shown.

[0005] Figure 2A The interaction between the host and the memory subsystem executing the activation (ACT) command is illustrated schematically, with the host managing the allocation of the line buffer.

[0006] Figure 2B The interaction between the host and the memory subsystem executing the activation (ACT) command is illustrated schematically, with the line buffer allocation managed by the memory subsystem.

[0007] Figure 3A The diagram schematically illustrates the interaction between the host and the memory subsystem executing a read (RD) command, where the host manages the allocation of the line buffer.

[0008] Figure 3B The diagram schematically illustrates the interaction between the host and the memory subsystem executing a read (RD) command, where the line buffer allocation is managed by the memory subsystem.

[0009] Figure 4A The diagram schematically illustrates the interaction between the host and the memory subsystem executing a write (WR) command, where the host manages the allocation of the line buffer.

[0010] Figure 4B The diagram schematically illustrates the interaction between the host and the memory subsystem executing a write (WR) command, where the line buffer allocation is managed by the memory subsystem.

[0011] Figure 5AThe interaction between the host and memory subsystem executing the precharge (PRE) command is illustrated schematically, with the host managing the allocation of the line buffer.

[0012] Figure 5B The interaction between the host and the memory subsystem executing the precharge (PRE) command is illustrated schematically, with the line buffer allocation managed by the memory subsystem.

[0013] Figure 6A This is a flowchart of an example method for performing memory access operations by a memory subsystem operating according to embodiments of the present disclosure.

[0014] Figure 6B This is a flowchart of another example method for performing memory access operations by a memory subsystem operating according to embodiments of the present disclosure.

[0015] Figure 7 An example computing system is shown that includes a memory subsystem implemented according to some embodiments of the present disclosure.

[0016] Figure 8 This is a block diagram of an example host computer system in which embodiments of this disclosure may operate. Detailed Implementation

[0017] Embodiments of this disclosure relate to implementing a dynamic random access memory (DRAM) device having multiple row buffers per memory bank or a set of memory banks.

[0018] A DRAM device comprises multiple memory banks grouped into banks, such as sixteen memory banks grouped into four banks. Each memory bank is a memory array containing multiple memory cells, such that each memory cell can store one or more bits of information, depending on the memory cell type. A memory cell includes a capacitor that holds a charge and a transistor that acts as a switch to control access to the capacitor. Thus, a memory cell can be programmed (written) by applying a specific voltage, which generates the charge held by the capacitor. Memory cells are connected via word lines and bit lines, the word lines being wires electrically connected to the control gate of the memory cell and the bit lines being wires electrically connected to the drain electrode of the memory cell.

[0019] Memory access operations begin with an Activate (ACT) command, which selects the memory bank and row, and copies data from the memory cell of the selected row to the row buffer for subsequent access. A Read (RD) command, issued after the Activate command, specifies the starting column (bit line) position for the read operation and moves data from the specified column position in the row buffer to the memory controller. A Write (WR) command, issued after the Activate command, specifies the starting column (bit line) position for the write operation and stores data supplied by the memory controller at the specified column position in the row buffer.

[0020] The selected row remains open for access until a precharge (PRE) command is issued to the memory bank. The PRE command de-opens the open row by moving data from the row buffer to the memory cell containing the open row. Alternatively, instead of issuing an explicit precharge command to activate a row, automatic precharge read (RDA) and automatic precharge write (WRA) commands can be used to automatically precharge the row after a read or write operation is completed. Once the memory bank has been precharged, it is idle and should be activated before any read or write command is issued to the memory bank.

[0021] Therefore, line buffers efficiently cache data from selected lines. However, associating a single line buffer with each memory bank limits the efficiency of the caching scheme. The systems and methods of this disclosure address this and other drawbacks by employing multiple line buffers for each memory bank or group of memory banks. In an illustrative example, multiple line buffers (e.g., four or eight line buffers) may be dedicated to each memory bank. In another illustrative example, multiple line buffers may be shared among several co-located memory banks or among all memory banks on a die. Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, improved memory access efficiency by utilizing multiple line buffers that may be dedicated to a single memory bank or shared among multiple memory banks.

[0022] Figure 1 A high-level component diagram of an instance memory subsystem implemented according to various aspects of this disclosure is schematically shown. For example... Figure 1 As shown, the memory subsystem 100 includes one or more memory devices 110 coupled to a memory controller 120, which is compatible with a host computer system. Figure 1(Not shown in the text) Communication. Various other functional components of the memory controller 120 and / or memory subsystem 100 implement processing logic for performing the memory access operations described herein. "Coupled to" as used herein refers to an electrical connection between components, including indirect connections via one or more intermediate components and direct connections (i.e., without intermediate components). Memory device (e.g., DRAM device) 110 includes multiple memory banks 130A-130N, which are grouped into memory bank groups 140A-140K. Although... Figure 1 Sixteen memory banks are shown, grouped into four memory bank groups, but various other embodiments may employ other numbers of memory bank groups and memory banks. Each memory bank 130 is a memory array containing multiple memory cells, such that each memory cell can store one or more bits of information depending on the memory cell type.

[0023] As mentioned above herein, memory device 110 may further include a set of row buffers 150A-150L for storing data retrieved from a row of memory bank 130. In an illustrative example, one or more row buffers 150 may be dedicated to each memory bank 130. In another illustrative example, one or more row buffers 150 may be shared among several co-located memory banks 130 (e.g., among the banks of a single memory bank group 140). In yet another illustrative example, one or more row buffers 150 may be shared among all memory banks 130 of memory device 110.

[0024] For clarity and brevity, Figure 1 Various other components, such as sense amplifiers, input / output interfaces, and command interfaces, are omitted. In one embodiment, the memory device 110 may be implemented as one or more integrated circuits located on one or more dies. In another embodiment, the memory subsystem 100 may be implemented as a system-on-a-chip, which, in addition to Figure 1 In addition to the memory device 110 and the memory controller 120, it may also include one or more processing cores and one or more input / output (I / O) interfaces.

[0025] In some implementations, the host may be aware of the scheme that associates multiple line buffers with each memory bank or a set of memory banks. Therefore, the line buffers can be directly managed by the host, which specifies which line buffer should be used by providing a line buffer identifier in activation, read, write, and precharge commands, as referenced below. Figure 2A , 3A 4A and 5A are explained in further detail below. Alternatively, row buffer management can be performed by the memory subsystem and / or a single memory device, which will require the host to provide the row address in activation, read, and write commands, as referenced below. Figure 2B ,3B 4B and 5B are explained in further detail.

[0026] In some implementations, the host may be aware of a scheme that associates multiple line buffers with each memory bank or a set of memory banks, but the line buffer allocation can be managed by the memory device. Therefore, the host can issue an activation command and receive a returned line buffer identifier. The line buffer identifier can be used in subsequent request commands (e.g., read, write, and precharge) issued by the host to the memory subsystem.

[0027] As mentioned above in this document, memory access operations begin with an Activation (ACT) command, which selects the memory bank and row, and copies data from the memory cell of the selected row to the row buffer for subsequent access. Figure 2A-2B The interaction between the host 210, which executes the activation (ACT) command, and the memory subsystem 215 is illustrated schematically.

[0028] Specifically, Figure 2A The interaction between host 210 and memory subsystem 215 executing activation (ACT) commands, according to aspects of this disclosure, is illustrated schematically, wherein line buffer allocation is managed by host 210. In an illustrative example, host 210 may initiate a memory access operation by issuing activation (ACT) command 220.

[0029] Since row buffer allocation is managed by host 210, activation command 220 needs to identify the row buffer to be used by memory subsystem 215 for storing data retrieved from the selected row. Therefore, the parameters of activation command 220 may include bank group address 230, bank address 232, row address 234, and row buffer identifier 236. Each of these parameters may be encoded by a set of bits transmitted via a corresponding input to memory device 250.

[0030] The activation command 220 may involve the row decoder 255 decoding the physical address fields 230, 232 and 234, and moving data from the selected row 260 (identified by the row address 234) of the bank 265 (identified by the bank address 232) in the bank group identified by the bank group address 230 to the row buffer 270 identified by the row buffer identifier 236.

[0031] Figure 2B The interaction between host 210, executing an activation (ACT) command, and memory subsystem 215 according to various aspects of this disclosure is illustrated schematically, wherein line buffer allocation is managed by the memory subsystem. In an illustrative example, host 210 may initiate a memory access operation by issuing an activation (ACT) command 221.

[0032] Since row buffer allocation is managed by the memory subsystem, activation command 221 only needs to identify the row from which data will be transferred to the row buffer selected by the memory subsystem. Therefore, the parameters of activation command 221 may include bank address 230, bank address 232, and row address 234. Each of these parameters may be encoded by a set of bits transmitted via a corresponding input to memory device 250.

[0033] Processing activation command 221 may involve row decoder 255 decoding physical address fields 230, 232, and 234, and moving data from selected row 260 (identified by row address 234) of memory bank 265 (identified by memory bank address 232) within the memory bank group identified by memory bank group address 230 to row buffer 270, the data being selected by the memory subsystem from available row buffers associated with the memory bank specified by the activation command. In an illustrative example, row buffers are selected based on row allocation metadata 275, which reflects the temporary association of a row buffer with an activated row (e.g., by associating each row buffer with a row label identifying the row currently associated with that row buffer). In some embodiments, if all row buffers associated with the selected memory bank have already been allocated, the memory subsystem may evict data from one of the allocated row buffers to the corresponding row, thus making the row buffer available for activation command 231.

[0034] As mentioned above, the activation command copies data from the memory cell of the selected row to a specified row buffer for subsequent access by read or write commands. A read (RD) command issued after the activation command can specify the starting column (bit line) position for the read operation and move data from the specified column position in the row buffer to the memory controller. Figures 3A-3B The interaction between the host 210, which executes the read (RD) command, and the memory subsystem 215 is illustrated schematically.

[0035] Specifically, Figure 3A The interaction between host 210, executing a read (RD) command, and memory subsystem 215 according to aspects of this disclosure is illustrated schematically, wherein line buffer allocation is managed by the host. In an illustrative example, after completing activation command 220, host 210 can perform a memory access operation by issuing RD (read) command 222.

[0036] Since the row buffer allocation is managed by host 210, read command 222 does not need to identify the row from which data should be read, because the data from row 260 has already been moved to row buffer 270 by the previously executed activation command 220. Therefore, read command 222 only needs to identify the row buffer and specify column address 238, which is the starting address (i.e., bit line) for performing the read operation. Therefore, the parameters of read command 222 may include row buffer identifier 236 and column address 238. Each of these parameters may be encoded by a set of bits transmitted via the corresponding input to memory device 250.

[0037] Processing read command 222 may involve moving data from a specified row buffer 270 (identified by row buffer identifier 236) to a data input / output buffer 280, starting from the bit line identified by column address 238, from which the data is transferred to the memory controller.

[0038] Figure 3B The interaction between host 210, executing a read (RD) command, and memory subsystem 215 according to various aspects of this disclosure is illustrated schematically, wherein line buffer allocation is managed by memory subsystem 215. In an illustrative example, after completing activation command 221, host 210 can perform a memory access operation by issuing read (RD) command 223.

[0039] Since row buffer allocation is managed by memory subsystem 215, read command 223 needs to identify the row (e.g., by specifying bank set address 230, bank address 232, and row address 234), thus enabling memory subsystem 215 to identify row buffer 270, from which data from the previously executed activation command 221 has been moved. Furthermore, read command 223 needs to specify column address 238, which is the starting address (i.e., bit line) for performing the read operation. Therefore, the parameters of read command 223 may include bank set address 230, bank address 232, row address 234, and column address 238. Each of these parameters may be encoded by a set of bits transmitted via the corresponding input of memory device 250.

[0040] Processing read command 223 may involve (e.g., based on row allocation metadata 275) identifying row buffer 270 that has previously been associated with a row identified by bank group address 230, bank address 232, and row address 234. When identifying row buffer 270, memory subsystem 215 copies data from row buffer 270 to data input / output buffer 280, starting from the bit line identified by column address 238, from which the data is transferred to the memory controller.

[0041] As mentioned above in this article, a write (WR) command issued after the activation command can specify the starting column (bit line) position for the write operation and cause the data supplied by the memory controller to be stored at the specified column position in the row buffer. Figures 4A-4B The interaction between host 210 and memory subsystem 215, which execute write (WR) commands, is illustrated schematically.

[0042] Specifically, Figure 4A The interaction between host 210, which executes a write (WR) command, and memory subsystem 215 according to aspects of this disclosure is illustrated schematically, wherein line buffer allocation is managed by host 210. In an illustrative example, after completing activation command 220, host 210 can perform a memory access operation by issuing write (WR) command 224.

[0043] Since the row buffer allocation is managed by host 210, write command 224 does not need to identify the row to which data should be written, because row 260 has already been identified by the previously executed activation command 220 and associated with row buffer 270. Therefore, write command 224 only needs to identify the row buffer and specify column address 238, which is the start address (i.e., bit line) for performing the write operation. Thus, the parameters of write command 224 may include row buffer identifier 236, column address 238, and data 240 to be written to a specified location in memory device 250. Each of these parameters may be encoded by a set of bits transmitted via a corresponding input to memory device 250.

[0044] Processing write command 224 may involve moving data 240 provided by the write command parameters from the bit line identified by column address 238 to the specified row buffer 270 (identified by row buffer identifier 236) via input / output buffer 280.

[0045] Figure 4B The interaction between host 210 and memory subsystem 215, which execute write (WR) commands according to various aspects of this disclosure, is illustrated schematically, wherein line buffer allocation is managed by memory subsystem 215. In an illustrative example, after completing activation command 221, host 210 can perform a memory access operation by issuing write (WR) command 223.

[0046] Since row buffer allocation is managed by memory subsystem 215, write command 225 needs to identify rows (e.g., by specifying bank set address 230, bank address 232, and row address 234) so ​​that memory subsystem 215 can identify row buffer 270, which has been associated with the selected row via previously executed activation command 221. Furthermore, write command 225 needs to specify column address 238, which is the start address (i.e., bit line) for performing the write operation. Therefore, the parameters of write command 225 may include bank set address 230, bank address 232, row address 234, column address 238, and data 240 to be written to a specified location in memory device 250. Each of these parameters may be encoded by a set of bits transmitted via a corresponding input to memory device 250.

[0047] Processing write command 225 may involve (e.g., based on row allocation metadata 275) identifying row buffer 270 that has previously been associated with a row identified by bank group address 230, bank address 232, and row address 234. After identifying row buffer 270, memory subsystem 215 copies data 240 provided by write command parameters to the identified row buffer 270 via input / output buffer 280.

[0048] As mentioned above, the selected row remains open for access until the host sends a precharge (PRE) command, which closes the open row by moving data from the corresponding row buffer to the memory cell of the specified open row. Figures 5A-5B The interaction between the host 210, which executes the PRE (precharge) command, and the memory subsystem 215 is illustrated schematically.

[0049] Specifically, Figure 5A The interaction between host 210, which executes PRE (precharge) commands according to various aspects of this disclosure, and memory subsystem 215 is illustrated schematically, wherein host 210 manages line buffer allocation. In an illustrative example, host 210 can cause the contents of a specified line buffer to be written to memory device 250 by issuing PRE (precharge) command 226.

[0050] Since row buffer allocation is managed by host 210, precharge command 226 only needs to identify the row buffer from which data should be stored in the associated row. Therefore, the parameters of precharge command 226 may include row buffer identifier 236. These parameters may be encoded by a set of bits transmitted via a corresponding input to memory device 250.

[0051] Processing the precharge command 226 may involve identifying a row 260 associated with a row buffer 270 identified by a row buffer identifier 236 based on row allocation metadata 275 maintained by the memory device 250. After identifying row 260, the memory device 250 moves data from the row buffer 270 identified by the row buffer identifier 236 to row 260.

[0052] Figure 5B The interaction between a host 210 executing a PRE (precharge) command and a memory subsystem 215 according to various aspects of this disclosure is illustrated schematically, wherein the memory subsystem 215 manages line buffer allocation. In an illustrative example, the host 210 may cause the contents of one or more line buffers associated with the identified memory bank to be written to the memory device 250 by issuing a PRE command 227.

[0053] Since row buffer allocation is managed by the memory subsystem, the precharge command 227 only needs to identify the memory bank, and the memory subsystem can identify one or more row buffers associated with the memory bank based on the row allocation metadata 275 maintained by the memory subsystem. Therefore, the parameters of the activation command 221 may include a memory bank group address 230 and a memory bank address 232. Each of these parameters may be encoded by a set of bits transmitted via a corresponding input to the memory device 250.

[0054] Processing the precharge command 227 may involve (e.g., based on row allocation metadata 275) identifying one or more row buffers 270 that have previously been associated with a corresponding row at a memory address 232 within the memory bank group 230. After identifying one or more row buffers 270, the memory subsystem 215 (e.g., based on row allocation metadata 275) copies data from each identified row buffer 270 to the row associated with that row buffer.

[0055] As mentioned above in this document, the implementation of activation, read, write, and precharge commands allocated by the host-managed line buffer requires that the line buffer identifier be passed as a parameter to the memory subsystem for the corresponding command. The line buffer identifier may be encoded by a set of bits transmitted via a specified input of the memory device 250.

[0056] In some implementations, host 210 may associate each hardware thread (e.g., implemented by the processing core) with one or more line buffers of memory subsystem 215, such that each hardware thread serializes its memory access requests on a dedicated set of line buffers, thus enabling parallel processing of memory access requests initiated by multiple threads.

[0057] Figure 6AThis is a flowchart of an example method 600 for performing memory access operations on a memory subsystem operating according to embodiments of the present disclosure. As mentioned above herein, the memory subsystem may include multiple memory banks grouped into several memory bank groups. The memory subsystem may further include multiple line buffers. In an illustrative example, a subset of line buffers containing one or more line buffers may be dedicated to each memory bank. In another illustrative example, a subset of line buffers containing two or more line buffers may be dedicated to each memory bank. In yet another illustrative example, a subset of line buffers containing two or more line buffers may be shared among several co-located memory banks or among all memory banks of the memory subsystem.

[0058] As mentioned above herein, in some embodiments, the allocation of line buffers may be managed by a host communicating with the memory subsystem. Therefore, method 600 may be... Figure 2A , 3A The memory subsystems 215 of 4A and 5A are executed. Although the operations of the method are shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. In addition, in some embodiments, one or more operations may be omitted. Therefore, not all operations shown are required in each embodiment, and other processing flows are possible.

[0059] At operation 610, the memory subsystem implementing the method receives from the host (e.g., by providing a bank group address, bank address, and row address) an activation command specifying a row and identifying the row buffer associated with the row.

[0060] At operation 612, the memory subsystem copies data from the row to the row buffer.

[0061] At operation 614, the memory subsystem receives from the host a read command that identifies a previously activated row buffer (e.g., a row buffer activated by operation 620) and further specifies the column address (i.e., bit line) for performing the read operation.

[0062] At operation 616, the memory subsystem reads data from the row buffer starting at the column address.

[0063] At operation 618, the memory subsystem receives from the host a write command that identifies a previously activated row buffer (e.g., a row buffer activated by operation 620) and further specifies the column address (i.e., bit line) and data item to be written.

[0064] At operation 620, the memory subsystem writes data items into the row buffer starting from the column address.

[0065] At operation 622, the memory subsystem receives from the host a precharge command specifying the row buffer associated with the previously activated row.

[0066] At operation 624, the memory subsystem identifies the row associated with the row buffer specified by the precharge command based on row allocation metadata. After identifying the row, the memory subsystem moves data from the row buffer specified by the precharge command to the identified row.

[0067] Figure 6B This is a flowchart of an example method 650 of performing memory access operations on a memory subsystem operating according to embodiments of the present disclosure. As mentioned above herein, the memory subsystem may include multiple memory banks grouped into several memory bank groups. The memory subsystem may further include multiple line buffers. In an illustrative example, a subset of line buffers containing one or more line buffers may be dedicated to each memory bank. In another illustrative example, a subset of line buffers containing two or more line buffers may be dedicated to each memory bank. In yet another illustrative example, a subset of line buffers containing two or more line buffers may be shared among several co-located memory banks or among all memory banks of the memory subsystem.

[0068] As mentioned above herein, in some embodiments, the host may be unaware of the memory buffers available in the memory subsystem, and line buffer allocation may be managed by the memory subsystem. Therefore, method 650 may be... Figure 2B , 3B The memory subsystems 215 of 4B and 5B (e.g., by allocating metadata 275 using a line buffer) are executed. Although the operations of the method are shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. In addition, in some embodiments, one or more operations may be omitted. Therefore, not all operations shown are required in every embodiment, and other processing flows are possible.

[0069] At operation 670, the memory subsystem implementing the method receives from the host (e.g., by providing a bank group address, bank address, and row address) an activation command specifying a row.

[0070] At operation 672, the memory subsystem selects from the available row buffers associated with the memory bank specified by the activation command. In an illustrative example, the row buffer is selected based on row allocation metadata reflecting the temporary association between the row buffer and the activated row. In some implementations, if all row buffers associated with the selected memory bank have already been allocated, the memory subsystem may evict data from one of the allocated row buffers to the corresponding row, thus making the row buffer available for the activation command.

[0071] At operation 674, the memory subsystem copies the data of the row specified by the future free activation command to the selected row buffer.

[0072] At operation 676, the memory subsystem receives from the host (e.g., by providing the bank group address, bank address, and row address) a read command that identifies the row and specifies the column address (i.e., bit line) to perform the read operation.

[0073] At operation 678, the memory subsystem (e.g., based on row allocation metadata) identifies the row buffer that has previously been associated with the row identified by the parameters of the read command.

[0074] At operation 680, the memory subsystem reads data from the identified row buffer, starting at the column address specified by the read command.

[0075] At operation 682, the memory subsystem receives from the host a write command that identifies the row and specifies the column address (i.e., bit line) and the data item to be written, by providing the bank group address, bank address, and row address.

[0076] At operation 684, the memory subsystem (e.g., based on row allocation metadata) identifies a row buffer that has previously been associated with a row identified by the parameters of the write command.

[0077] At operation 686, the memory subsystem writes data items into the identified row buffer, starting from the column address specified by the write command.

[0078] At operation 688, the memory subsystem receives from the host (e.g., by providing the bank group address and the bank address) a precharge command specifying a bank containing previously activated rows.

[0079] At operation 690, the memory subsystem (e.g., based on row allocation metadata) identifies a row buffer that has previously been associated with a row of the memory bank identified by the parameters of the precharge command.

[0080] At operation 692, the memory subsystem copies data from the identified row buffer to the row associated with the identified row buffer.

[0081] Figure 7 An example computing system 700 is illustrated, comprising a memory subsystem 710 implemented according to some embodiments of the present disclosure. The memory subsystem 710 may include media, such as one or more volatile memory devices (e.g., memory device 740), one or more non-volatile memory devices (e.g., memory device 730), or a combination thereof. In some embodiments, the memory subsystem 710 corresponds to... Figure 1 The memory subsystem 100.

[0082] The memory subsystem 710 can be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0083] The computing system 700 can be a computing device such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a commercially available connected device), or such a computing device that includes memory and processing means (e.g., a processor).

[0084] The computing system 700 may include a host system 720 coupled to one or more memory subsystems 710. In some embodiments, the host system 720 is coupled to different types of memory subsystems 710. Figure 7 An example of a host system 720 coupled to a memory subsystem 710 is shown. The host system 720 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 720 uses the memory subsystem 710, for example, to write data to and read data from the memory subsystem 710.

[0085] The host system 720 can be coupled to the memory subsystem 710 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), etc. The physical host interface can be used to transfer data between the host system 720 and the memory subsystem 710. When the memory subsystem 710 is coupled to the host system 720 via the PCIe interface 105, the host system 720 can further utilize the NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 730). The physical host interface 105 provides an interface for transmitting control, address, data and other signals between the memory subsystem 710 and the host system 720. Figure 7 Memory subsystem 710 is shown as an example. Generally, host system 720 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0086] Memory devices 730 and 740 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 740) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0087] Some examples of non-volatile memory devices (e.g., memory device 730) include NAND type flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array for bit storage based on changes in volume resistance. Furthermore, unlike many flash-based memories, cross-point non-volatile memory allows for in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND type flash memory includes, for example, two-dimensional NAND (2DN NAND) and three-dimensional NAND (3D NAND).

[0088] Each of the memory devices 730 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each memory device 730 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 730 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0089] Although non-volatile memory devices, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 730 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0090] The memory subsystem controller 775 can communicate with the memory device 730 to perform operations such as reading data, writing data, or erasing data at the memory device 730, and other such operations. The memory subsystem controller 775 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic that performs the operations described herein. The memory subsystem controller 775 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0091] The memory subsystem controller 775 may include a processor 717 (e.g., a processing device) configured to execute instructions stored in local memory 719. In the illustrated example, the local memory 719 of the memory subsystem controller 775 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 710, including handling communication between the memory subsystem 710 and the host system 720. In some embodiments, the processor 717 may implement methods 600-650, as described in more detail above herein.

[0092] In some embodiments, local memory 719 may include memory registers that store memory pointers, fetched data, etc. Local memory 719 may also include read-only memory (ROM) for storing microcode. Although Figure 7 The instance memory subsystem 710 has been shown to include a controller 775, but in another embodiment of this disclosure, the memory subsystem 710 does not include a controller 775, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0093] Generally, the memory subsystem controller 775 can receive commands or operations from the host system 720 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 730. The memory subsystem controller 775 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 730. The memory subsystem controller 775 may further include a host interface circuitry for communicating with the host system 720 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 730, and translate responses associated with the memory device 730 into information for the host system 720.

[0094] The memory subsystem 710 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 710 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the controller 775 to access the memory device 730.

[0095] In some embodiments, memory device 730 includes a local media controller 735 that operates together with memory subsystem controller 775 to perform operations on one or more memory cells of memory device 730. An external controller (e.g., memory subsystem controller 775) may externally manage memory device 730 (e.g., perform media management operations on memory device 730). In some embodiments, memory subsystem 710 is a managed memory device, which is the original memory device 730 having on-die control logic (e.g., local media controller 735) and a controller (e.g., memory subsystem controller 775) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0096] Figure 8 An example machine of computer system 800 is shown, in which a set of instructions for causing the machine to perform any one or more of the methods discussed herein can be executed. In some embodiments, computer system 800 may correspond to a host system (e.g., Figure 7 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 100 or Figure 7 (Memory subsystem 710).

[0097] In alternative embodiments, the machine may be connected (e.g., coupled to network interface device 838 of network 820) to other computer systems in a LAN, corporate intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0098] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is shown, it should also be understood that the term "machine" includes any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0099] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 808 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0100] Processing device 802 represents one or more general-purpose processing devices, such as microprocessors, CPUs, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 802 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 802 is configured to execute instructions 828 for performing the operations and steps discussed herein (e.g., managing line buffer allocation, as described in more detail above).

[0101] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium) storing one or more sets of instructions 828 or software embodying any one or more methods or functions described herein. The instructions 828 may also reside wholly or at least partially within main memory 804 and / or processing device 802 during execution by computer system 800, the main memory 804 and processing device 802 also constituting machine-readable storage media. The machine-readable storage medium 824, the data storage system 818, and / or main memory 804 may correspond to... Figure 7 The memory subsystem 110.

[0102] In one embodiment, instruction 828 includes instructions for implementing line buffer allocation 834 according to some embodiments of the present disclosure. Although machine-readable storage medium 824 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0103] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that produce the desired result. Operations are those that require the physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0104] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0105] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (“ROM”), random access memory (“RAM”), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions and each coupled to a computer system bus.

[0106] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the teachings and procedures herein, or may be demonstrated to facilitate the construction of more specialized devices to perform the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0107] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0108] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A memory subsystem comprising: Multiple memory bank groups, wherein each memory bank group includes multiple memory banks; Multiple row buffers, wherein two or more of the multiple row buffers are shared between two or more memory banks in one of the multiple bank groups; Processing logic, communicatively coupled to the plurality of memory banks and the plurality of row buffers, performs operations including the following: Receive a command from the host that identifies a row of a memory bank; The row buffer allocation metadata identifies the row buffer associated with the row among the plurality of row buffers, wherein the row buffer allocation metadata includes: for each of the plurality of row buffers, a corresponding label identifying the row temporarily associated with the row buffer; as well as Memory access operations are performed using the row buffer.

2. The memory subsystem according to claim 1, wherein the plurality of memory banks are composed of dynamic random access memory (DRAM) devices.

3. The memory subsystem of claim 1, wherein the first row buffer and the second row buffer of the plurality of row buffers are exclusively associated with the first memory group of the plurality of memory groups.

4. The memory subsystem of claim 1, wherein the command is an activation command that further specifies a row of a memory bank, and wherein performing the memory access operation includes: Copy the data from the row to the row buffer.

5. The memory subsystem of claim 1, wherein the command is a read command that further specifies a column address, and wherein performing the memory access operation includes: Data is read from a position in the row buffer, where the position is identified by the column address.

6. The memory subsystem of claim 1, wherein the command is a write command that further specifies the column address and data item, and wherein performing the memory access operation includes: The data item is written to the position in the row buffer, where the position is identified by the column address.

7. The memory subsystem of claim 1, wherein the command is a precharge command that further specifies the line buffer, and wherein performing the memory access operation comprises: Copy the data from the row buffer to the row associated with the row buffer.

8. A memory subsystem comprising: Multiple memory bank groups, wherein each memory bank group includes multiple memory banks; Multiple row buffers, wherein two or more of the multiple row buffers are associated with each bank group; Processing logic, communicatively coupled to the plurality of memory banks and the plurality of row buffers, performs operations including the following: Receive a command from the host that identifies a row of a memory bank; The row buffer allocation metadata identifies the row buffer associated with the row among the plurality of row buffers, wherein the row buffer allocation metadata includes: for each of the plurality of row buffers, a corresponding label identifying the row temporarily associated with the row buffer; as well as Memory access operations are performed using the row buffer.

9. The memory subsystem of claim 8, wherein the plurality of memory banks comprises a dynamic random access memory (DRAM) device.

10. The memory subsystem of claim 8, wherein the first row buffer and the second row buffer of the plurality of row buffers are exclusively associated with the first memory group of the plurality of memory groups.

11. The memory subsystem of claim 8, wherein the first row buffer and the second row buffer of the plurality of row buffers are exclusively associated with the first memory bank of the plurality of memory banks associated with the first memory bank group.

12. The memory subsystem of claim 8, wherein the command is an activation command, and wherein performing the memory access operation comprises: Copy the data from the row to the row buffer.

13. The memory subsystem of claim 8, wherein the command is a read command that further specifies a column address, and wherein performing the memory access operation comprises: Data is read from a position in the row buffer, where the position is identified by the column address.

14. The memory subsystem of claim 8, wherein the command is a write command that further specifies the column address and data item, and wherein performing the memory access operation includes: The data item is written to the position in the row buffer, where the position is identified by the column address.

15. The memory subsystem of claim 8, wherein the command is a precharge command, and wherein performing the memory access operation comprises: Copy the data from the row buffer to the row.

16. A method for performing a memory access operation, comprising: A command is received from the host via a memory subsystem comprising multiple memory stores grouped into multiple memory stores, the command identifying a row of a particular memory store among the multiple memory stores; The row buffer allocation metadata identifies the row buffer associated with the row in a set of row buffers associated with the memory bank, wherein the row buffer allocation metadata includes: for each row buffer in the set of row buffers, a corresponding label identifying the row temporarily associated with the row buffer; as well as The memory access operation is performed using the row buffer.

17. The method of claim 16, wherein the command is an activation command, and wherein performing the memory access operation comprises: Copy the data from the row to the row buffer.

18. The method of claim 16, wherein the command is a read command that further specifies a column address, and wherein performing the memory access operation comprises: Data is read from a position in the row buffer, where the position is identified by the column address.

19. The method of claim 16, wherein the command is a precharge command, and wherein performing the memory access operation comprises: Copy the data from the row buffer to the row.

Images