Three-dimensional double-screw structure isolation transformer in silicon wafer and preparation method thereof

Abstract

The application discloses a silicon wafer inner three-dimensional double-screw structure isolation transformer and a preparation method thereof. The isolation transformer comprises a substrate, a primary metal coil and a secondary metal coil which are arranged in the substrate and cross each other. In the whole signal transmission process, the primary metal coil and the secondary metal coil are not directly connected with each other, so that the purpose of isolating the primary and the secondary and transmitting power or signals is achieved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits and microelectromechanical systems, and specifically relates to a three-dimensional twin-screw structure isolation transformer in a silicon wafer and its fabrication method. Background Technology

[0002] Electrical isolation, also known as isolation, cuts off the DC path between isolated sides during signal / power transmission. It protects critical circuits from grounding disturbances or other noise voltages and transmits energy or information through an insulating barrier. Common components used for isolating data and low-power power transmission are optocouplers or discrete transformers wound with copper enameled wire. Optocouplers typically encapsulate a light emitter (infrared LED) and a light receiver (photosensitive semiconductor tube) in the same housing. When an electrical signal is applied to the input, the light emitter emits light, and the light receiver generates a photocurrent, which flows out from the output, thus achieving an "electric-to-optical-to-electrical" conversion. Optocouplers suffer from technical drawbacks such as large size, slow internal photoelectric conversion speed, and limited energy transmission. Like discrete transformers that cannot achieve silicon-based integration, they cannot meet the current trend of miniaturized, high-speed, and high-power-density integrated electronic systems.

[0003] With the continuous advancement of semiconductor and MEMS technologies, electromagnetically coupled digital isolators (EMIs) based on on-chip integrated transformers have emerged. Unlike optocouplers, which use LEDs and photosensitive semiconductors, EMIs eliminate the inefficient and short-lifespan photoelectric conversion interface found in optocouplers. They are typically based on chip-level mutual inductance coils and are manufactured directly on-chip or within a chip using planar or bulk silicon processes. The number of channels can be increased by increasing the number of coil pairs to achieve low-cost, high-efficiency isolation. Therefore, they have wide applications in aerospace, consumer electronics, medical electronics, automotive electronics, and industrial automation. Based on advanced packaging technologies such as SiP, some of these applications can be achieved through fully integrated methods, meaning that isolation is provided on the chip and integrated into a single package without any discrete components. On-chip integrated transformer-based digital isolators are not only suitable for digital isolated transmission but also for isolated power transmission applications. Previous studies have reported various planar helical electromagnetic coupling coil devices based on electroplating processes and micromachined coreless single-layer integrated transformer chips for isolated power / signal transmission (CDMeyer, SSBedair, BCMorgan, and D.P. Arnold, “High-inductance-density, air-core, power inductors, and transformers designed for operation at 100-500MHz,” IEEE Trans. Magn., vol. 46, no. 6, pp. 2236-2239, 2010.) (F. Khan, Y. Zhu, J. Lu, J. Pal, and D. Viet Dao, “Micromachined Coreless Single-Layer Transformer Without Crossovers,” IEEE Magn. Lett., vol. 6, pp. 1-4, 2015.). However, these devices typically exhibit poor performance in terms of inductance and coupling coefficient. It is worth noting that in existing power transmission applications, the transformers integrated into the chip always require multiple electroplating of thick copper or even thick gold to obtain a sufficiently low equivalent series resistance or a sufficiently high inductance-resistance ratio (L / R), which significantly increases manufacturing costs.Furthermore, because planar on-chip integrated transformers have relatively low inductance, they need to operate at high frequencies to achieve the desired efficiency (B. Chen, “Fully integrated isolated DC-DC converter using micro-transformers,” in Conference Proceedings IEEE Applied Power Electronics Conference and Exposition, 2008, pp. 335-338.)(T. Zhao, Y. Zhuo, and B. Chen, “An isolated DC-DC converter with fully integrated magnetic core transformer,” in Proceedings of the Custom Integrated Circuits Conference, 2017, pp. 1-4.). Excessively high operating frequencies introduce significant switching and rectification losses to the associated isolated DC-DC circuitry, thus limiting the overall power and transmission efficiency of the chip. Summary of the Invention

[0004] To address the aforementioned and other issues, this invention provides a three-dimensional twin-screw structure isolation transformer within a silicon wafer and its fabrication method.

[0005] To address the aforementioned problems, according to a first aspect of the present invention, a three-dimensional twin-screw structure isolation transformer with an in-wafer structure is provided, comprising:

[0006] A substrate, in which primary and secondary metal coils are intertwined and arranged.

[0007] Optionally, both the primary metal coil and the secondary metal coil have solder pads on the surface of the substrate.

[0008] Optionally, the pad includes a first part and a second part connected together, a third part disposed between the first part and the second part, the second part being connected to one end of the corresponding coil, and the third part being connected to the other end of the corresponding coil.

[0009] Optionally, the substrate includes at least a first substrate and a second substrate stacked together, wherein both the primary metal coil and the secondary metal coil are partially located in the first substrate and partially located in the second substrate.

[0010] Optionally, an insulating dielectric layer is formed between the primary metal coil and the secondary metal coil and the substrate.

[0011] Optionally, an insulating dielectric layer is formed between the first substrate and the second substrate.

[0012] Optionally, the width of adjacent coils between the primary metal coil and the secondary metal coil is ≥10μm, the depth is ≥10μm, and the spacing is ≥10μm.

[0013] Optionally, both the primary metal coil and the secondary metal coil are square helical.

[0014] According to a second aspect of the present invention, a method for fabricating a three-dimensional twin-screw structure isolation transformer within a silicon wafer is also provided, comprising:

[0015] Two sets of coil channels that are intertwined and interwoven with each other, and molten metal filling channels corresponding to both ends of the coil channels are processed in the substrate;

[0016] Liquid metal is injected from the molten metal filling channel until it is completely filled;

[0017] Cooling and solidification.

[0018] Optionally, the step of fabricating two sets of intertwined coil channels and corresponding molten metal filling channels at both ends of the coil channels in the substrate includes:

[0019] A dielectric layer is formed on the surface of a wafer, and then the dielectric layer is patterned using photolithography and etching processes;

[0020] Photolithography is performed again on the surface of the dielectric layer to form a composite mask consisting of the dielectric layer and the photoresist layer;

[0021] A deep etching process is used to etch trenches on the wafer to form the pattern on the upper surface of the metal coil, and then the photoresist mask layer is removed.

[0022] Deep etching is performed again on the basis of the already etched grooves to obtain horizontal grooves and vertical holes;

[0023] A photolithography etching process is performed on the back side of the wafer to etch the dielectric layer on the back side of the wafer;

[0024] A deep etching process is performed to etch through the vertical hole to form a through hole;

[0025] After removing the remaining dielectric layer, an insulating dielectric layer is then formed on the upper and lower surfaces of the wafer, the trenches, and the sidewalls of the vias; and

[0026] Multiple wafers are aligned and stacked to form the substrate;

[0027] Preferably, in the step of injecting liquid metal into the molten metal filling channel at high temperature until it is completely filled, multiple wafers will self-bond together during the cooling process.

[0028] This invention provides a silicon-based three-dimensional twin-screw isolation transformer and its fabrication method. The transformer contains a pair of mutually inducting coils that spirally penetrate the substrate, forming a tightly interlocking twin-screw structure. Utilizing the principle of electromagnetic induction, the energy or pulse signal to be transmitted is applied to the primary metal coil, generating a magnetic field that alternates with the signal. This changing magnetic field alters the magnetic flux in the secondary metal coil, subsequently inducing an alternating signal output in the secondary metal coil related to the excitation signal applied to the primary coil, thus achieving an "electric-magnetic-electric" conversion. Throughout the signal transmission process, there is no direct electrical connection between the primary and secondary metal coils, achieving the purpose of isolating the primary and secondary windings while transmitting power or signals.

[0029] In addition, the main structure of the silicon wafer three-dimensional twin-screw structure isolation transformer of the present invention runs through the interior of the substrate, and the three-dimensional space of the entire substrate is efficiently utilized, thereby improving the integration and inductance density.

[0030] Furthermore, the three-dimensional thick metal coils prepared by deep etching and micro-casting processes have low resistance, high magnetic coupling coefficient between the primary and secondary metal coils, good overall device performance, and can achieve high-efficiency isolated signal / power transmission. Attached Figure Description

[0031] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0032] Figure 1 This is a schematic diagram of a three-dimensional twin-screw isolation transformer structure within a silicon wafer, according to one embodiment of the present invention.

[0033] Figure 2 for Figure 1 A schematic diagram of section A1-A1';

[0034] Figure 3 for Figure 1 A schematic diagram of section A2-A2';

[0035] Figure 4 for Figure 1 A schematic diagram of section B-B';

[0036] Figure 5 This is a schematic diagram of the structure obtained in one embodiment of the present invention under a scanning electron microscope;

[0037] Figure 6This is a schematic diagram showing the measured S-parameters and the simulated S-parameters as a function of frequency in one embodiment of the present invention.

[0038] Figure 7 This is a test graph showing the change of inductance and resistance values ​​of the primary and secondary metal coils with frequency in one embodiment of the present invention.

[0039] Figure 8 This is a schematic diagram showing the coupling coefficient and maximum energy transfer efficiency measured in one embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of the present invention to facilitate a better understanding of this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with and referenced by each other without contradiction.

[0041] In the following description, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being “on” a substrate, layer (or film), region, and / or pattern, it can be located directly on a layer or substrate, and / or may be wholly or partially located “in” a layer or substrate. Additionally, it should be understood that when a layer is referred to as being “under” a layer, it can be located directly under a layer, and / or may be wholly or partially located “in” a layer or substrate. Furthermore, references to “on” and “under” layers may be made based on the accompanying drawings.

[0042] Example 1

[0043] Embodiment 1 of this invention provides a three-dimensional twin-screw structure isolation transformer within a silicon wafer. The implementation details of this embodiment are described below. These details are provided for ease of understanding and are not essential for implementing this solution. The structure of this embodiment can be referenced... Figures 1-5 Specifically, this embodiment 1 includes the following:

[0044] A substrate, in which a primary metal coil 21 and a secondary metal coil 22 are intertwined.

[0045] In a preferred embodiment, the substrate may be, for example, a silicon substrate. Other types of substrates may be selected as needed, such as silicon-germanium substrates, glass substrates, SOI substrates, etc. In this embodiment, the substrate is a single-crystal silicon substrate.

[0046] Furthermore, the number of substrates is more than one. For example, in an embodiment of the invention, it is illustrated as two substrates, namely a first substrate 11 and a second substrate 12. Both the primary metal coil 21 and the secondary metal coil 22 are partially located in the first substrate 11 and partially located in the second substrate 12. In addition, for example, three substrates may be used, for example, in a stacked arrangement.

[0047] In a preferred embodiment, the primary metal coil 21 and the secondary metal coil 22 are made of materials such as elemental metals or alloys, such as gold, silver, copper, aluminum, zinc-aluminum alloys, tin alloys, high-lead alloys, aluminum alloys, etc.

[0048] Please continue to refer to this. Figure 1 The primary metal coil 21 and the secondary metal coil 22 both have solder pads 51 and 52 on the surface of the first substrate 11.

[0049] The pads 51 and 52 can be, for example, GSG pad structures for on-chip RF probe testing, which can simplify the testing process.

[0050] In addition, the pads 51 and 52 can also be electrically connected to the outside world.

[0051] The pads 51 and 52 include a first part and a second part connected to each other, and a third part is disposed between the first part and the second part. The second part is connected to one end of the corresponding coil, and the third part is connected to the other end of the corresponding coil.

[0052] The pads 51 and 52 can be formed simultaneously after cooling when molten metal is injected to form a coil.

[0053] In one embodiment, an insulating dielectric layer 41 (e.g., ...) is formed between the primary metal coil 21 and the secondary metal coil 22 and the substrates 11 and 12. Figure 2 ).

[0054] The insulating dielectric layer 41 may be, for example, a silicon oxide layer, or in other embodiments, a silicon nitride layer, a silicon oxynitride layer, or an ONO (silicon oxide / silicon nitride / silicon oxide) layer.

[0055] The substrates 11 and 12 and the insulating dielectric layer 41 can simultaneously provide considerable isolation for the primary metal coil 21 and the secondary metal coil 22.

[0056] In one embodiment, the coil width of the primary metal coil 21 and the secondary metal coil 22 is ≥10μm, for example, it can be 20μm, 25μm, 30μm, etc., and the depth is ≥10μm, for example, it can be 100μm to 200μm. The adjacent spacing between the primary metal coil 21 and the secondary metal coil 22 is ≥10μm, for example, 20μm. The number of turns of the coil can be set according to actual needs.

[0057] For example, both the primary metal coil 21 and the secondary metal coil 22 embedded inside the substrate have 20 turns each, a coil width of 25 μm, a depth of 200 μm, and a spacing of 15 μm. The primary metal coil 21 and the secondary metal coil 22 are intertwined to form a highly coupled mutual inductance structure, occupying an area of ​​only 1 mm * 2 mm. This effectively achieves high integration.

[0058] In this invention, the cross-wound twin-screw coil structure utilizes the three-dimensional space of the entire substrate, i.e., the height of the screw coil is equal to the thickness of the substrate, which is beneficial to improving the inductance per unit area.

[0059] In this embodiment of the invention, both the primary metal coil 21 and the secondary metal coil 22 are square helices. Alternatively, other helical shapes may also be used, and the invention does not impose any particular limitation on them.

[0060] Tests have shown that within a device with an area of ​​only 1mm*2mm, such as Figure 7 As shown, its coupling coil inductance is as high as 141.4 nH, its DC resistance is as low as 0.8 Ω, and its inductance-resistivity ratio (L / R) reaches 151.7 nH / Ω. The integrated inductance density is several times that of a planar integrated transformer. More importantly, as... Figure 8 As shown, the fabricated device exhibits excellent performance with a coupling coefficient and maximum efficiency of no less than 0.90 and 81% respectively in a wide frequency range of 30MHz to 200MHz. More specifically, at 100MHz, the device achieves a coupling coefficient of 0.93 and a maximum energy transfer efficiency of 87%.

[0061] This invention provides an on-chip integrated RF transformer design with a three-dimensional twin-screw cross-wound mutual inductance coil as the core, and a wafer-level process method for mass production of a three-dimensional integrated twin-screw structure RF isolation transformer. This transformer exhibits excellent electromagnetic performance, utilizes the entire three-dimensional space of the substrate for its coil structure, achieves high integrated inductance density, is compact, occupies a small area, and utilizes a high aspect ratio metal conductive cross-section to achieve low series DC resistance. It also possesses a high coupling coefficient (>0.90) and energy transfer efficiency (>81%) over a wide frequency range, significantly improving system efficiency and integration in isolated power / signal transmission applications.

[0062] Example 2

[0063] Embodiment 2 of this invention provides a method for fabricating a three-dimensional twin-screw structure isolation transformer within a silicon wafer. The implementation details of this embodiment are described below. The following content is for ease of understanding and is not essential for implementing this solution. Specifically, Embodiment 2 includes the following:

[0064] Step S1: Two sets of coil channels that are intertwined and interwoven with each other and corresponding molten metal filling channels at both ends of the coil channels are processed in the substrate;

[0065] Step S2: Inject liquid metal into the molten metal filling channel at high temperature and then cool and solidify it.

[0066] In one embodiment, step S1 includes:

[0067] Step S101: A dielectric layer is formed on the wafer surface, and then the dielectric layer is patterned by photolithography and etching processes; for example, the dielectric layer made of silicon oxide can be formed by thermal oxidation process.

[0068] Step S102: Photolithography is performed again on the surface of the dielectric layer to form a composite mask composed of the dielectric layer and the photoresist layer;

[0069] Step S103: Using a deep etching process, trenches for forming the upper surface pattern of the metal coil are etched on the wafer, and then the photoresist mask layer is removed;

[0070] Step S104: Using a deep etching process, a deep etching process is performed again on the basis of the already etched trenches to obtain horizontal trenches and vertical holes; at this time, the vertical holes are usually in a non-through state;

[0071] Step S105: Perform photolithography etching on the back side of the wafer to etch the dielectric layer on the back side of the wafer; in this step, the main task is to pattern the back dielectric layer. After patterning, the photoresist can be removed.

[0072] Step S106: Perform a deep etching process, using a patterned dielectric layer mask on the back of the wafer to etch through the vertical holes to form through holes;

[0073] Step S107: Remove the remaining dielectric layer, and then form an insulating dielectric layer on the upper and lower surfaces of the wafer, the trenches and the sidewalls of the vias; in this step, the remaining dielectric layer can be removed by a wet cleaning process; the insulating dielectric layer can be formed into silicon dioxide by a thermal oxidation process, or it can be obtained by a deposition process;

[0074] Step S108: Align and stack multiple wafers to form the substrate; for example, it can be two wafers, which serve as the first substrate 11 and the second substrate 12 in the embodiments of the present invention, respectively.

[0075] For step S2, the high-temperature environment can be above 350°C, such as 380°C, and can be set according to the actual selected metal melting point. After the molten metal fills the flow channel and the liquid metal is injected until it is completely filled, it is cooled. During the cooling process, multiple wafers will self-bond together, thus eliminating the need for an additional vacuum hot-pressing bonding process, which helps to simplify the process flow and reduce costs.

[0076] In this embodiment of the invention, the high aspect ratio metal conductive cross section obtained by deep etching process and molten metal micro casting process is beneficial to achieving a small series DC resistance.

[0077] Please refer to Figure 6 This represents the energy transfer and reflection characteristics of the device in the frequency domain. Figure 6 The measured curves were obtained using a two-port vector network analyzer and its associated RF probe station, where S21 represents the forward transmission coefficient from port 1 to port 2, and S11 represents the reflection coefficient of port 1. It is evident that the product obtained by the method of this application exhibits high-efficiency power transmission performance over a wide frequency range (30-200MHz). This also demonstrates that the measured results of the twin-screw isolation transformers mass-produced using the wafer-level process method in the embodiments are in good agreement with the simulation results, proving the stability of the process method.

[0078] In summary, the silicon-based three-dimensional twin-screw isolation transformer and its fabrication method provided by this invention involve a pair of mutually inducting coils spirally penetrating the substrate, forming a tightly interlocking twin-screw structure. Utilizing the principle of electromagnetic induction, the energy or pulse signal to be transmitted is applied to the primary metal coil, generating a magnetic field that alternates with the signal. This changing magnetic field alters the magnetic flux in the secondary metal coil, subsequently inducing an alternating signal output in the secondary metal coil related to the excitation signal applied to the primary metal coil, thus achieving an "electric-magnetic-electric" conversion. Throughout the signal transmission process, there is no direct electrical connection between the primary and secondary metal coils, achieving the purpose of isolating the primary and secondary windings while transmitting power or signals.

[0079] In addition, the main structure of the silicon wafer three-dimensional twin-screw structure isolation transformer of the present invention runs through the interior of the substrate, making efficient use of the three-dimensional space of the entire substrate, thereby improving the integration and inductance density.

[0080] Furthermore, the three-dimensional thick metal coils prepared by deep etching and micro-casting processes have low resistance, high magnetic coupling coefficient between the primary and secondary metal coils, good overall device performance, and can achieve high-efficiency isolated signal / power transmission.

[0081] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for fabricating a three-dimensional twin-screw structure isolation transformer within a silicon wafer, comprising: Two sets of intertwined coil channels and corresponding molten metal filling channels at both ends of the coil channels are fabricated in the substrate; liquid metal is injected into the molten metal filling channels at high temperature and then cooled and solidified. The steps of fabricating two sets of intertwined coil channels and corresponding molten metal filling channels at both ends of the coil channels in the substrate include: A dielectric layer is formed on the surface of a wafer, and then the dielectric layer is patterned using photolithography and etching processes; Photolithography is performed again on the surface of the dielectric layer to form a composite mask consisting of the dielectric layer and the photoresist layer; A deep etching process is used to etch trenches on the wafer to form the pattern on the upper surface of the metal coil, and then the photoresist mask layer is removed. Deep etching is performed again on the basis of the already etched grooves to obtain horizontal grooves and vertical holes; A photolithography etching process is performed on the back side of the wafer to etch the dielectric layer on the back side of the wafer; A deep etching process is performed to etch through the vertical hole to form a through hole; After removing the remaining dielectric layer, an insulating dielectric layer is then formed on the upper and lower surfaces of the wafer, the trenches, and the sidewalls of the vias; and Multiple wafers are aligned and stacked to form the substrate; In the step of injecting liquid metal into the molten metal filling channel at high temperature until it is completely filled, multiple wafers will self-bond together during the cooling process.

2. A three-dimensional twin-screw structure isolation transformer within a silicon wafer, characterized in that, The method for fabricating a three-dimensional twin-screw structure isolation transformer within a silicon wafer as described in claim 1 includes: a substrate, and a primary metal coil and a secondary metal coil intertwined and disposed within the substrate.

3. The silicon wafer three-dimensional twin-screw structure isolation transformer according to claim 2, characterized in that, Both the primary and secondary metal coils have solder pads on the substrate surface.

4. The silicon wafer three-dimensional twin-screw structure isolation transformer according to claim 3, characterized in that, The pad includes a first part and a second part connected together, and a third part disposed between the first part and the second part. The second part is connected to one end of the corresponding coil, and the third part is connected to the other end of the corresponding coil.

5. The silicon wafer three-dimensional twin-screw structure isolation transformer according to claim 2, characterized in that, The substrate includes at least a first substrate and a second substrate stacked together, wherein both the primary metal coil and the secondary metal coil are partially located in the first substrate and partially located in the second substrate.

6. The silicon wafer three-dimensional twin-screw structure isolation transformer according to claim 5, characterized in that, An insulating dielectric layer is formed between the primary metal coil and the secondary metal coil and the substrate.

7. The silicon wafer three-dimensional twin-screw structure isolation transformer according to claim 6, characterized in that, An insulating dielectric layer is formed between the first substrate and the second substrate.

8. The silicon wafer three-dimensional twin-screw structure isolation transformer according to claim 2, characterized in that, The width of adjacent coils between the primary metal coil and the secondary metal coil is ≥10μm, the depth is ≥10μm, and the spacing is ≥10μm.

9. The silicon wafer three-dimensional twin-screw structure isolation transformer according to claim 2, characterized in that, Both the primary metal coil and the secondary metal coil are square helical coils.

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