Defect detection for memory devices

Abstract

This application relates to defect detection for memory devices. A segmented digital die defect detector can include a plurality of signal lines and control circuitry each coupled with test circuitry to form a path. At least a portion of the path can extend through an interior portion of the die. The test circuitry can generate digital feedback signals indicative of a condition of a respective signal line. The control circuitry can generate a single output signal indicative of the condition of the signal lines. By utilizing digital test circuitry and a single digital output signal, a layout area of the segmented digital die defect detector can be reduced and power consumption associated with test operations can be reduced.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 089,180, filed November 4, 2020, entitled “DEFECT DETECTION FOR A MEMORY DEVICE”, which is assigned to its assignee and whose entire contents are expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to the detection of defects in memory devices. Background Technology

[0004] In the context of integrated circuits, a die is part of a wafer (e.g., a silicon wafer) on which one or more circuits can be fabricated. A memory device is an example of a type of integrated circuit that can be fabricated on a die. Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by logic "1" or logic "0". In other systems, more than two states can be stored. To access stored information, components of the electronic device can read or sense the stored states in the memory device. To store information, components of the electronic device can write or program states into the memory device.

[0005] Memory devices and other types of integrated circuits are typically fabricated on semiconductor materials and created using semiconductor manufacturing processes. During the manufacturing process, several identical integrated circuits are simultaneously formed on a wafer of semiconductor material and then separated into individual semiconductor dies. Each die represents a separate semiconductor device, which can be individually packaged and included in a larger electronic system. Examples of semiconductor devices include memory devices, multiprocessor devices, power semiconductor devices, and many other devices. Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-select memory, chalcogenide memory technology, and others. These memory devices can be produced as integrated circuits on semiconductor dies. Semiconductor dies can be sliced, diced, or "sliced" from a wafer of semiconductor material.

[0006] Generally, improvements to memory devices may include increasing memory cell density, increasing read / write speed, improving reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other things. Summary of the Invention

[0007] An apparatus is described. The apparatus may include a first signal line extending through a portion of a die and separating a first memory bank and a second memory bank of the die; a second signal line including a portion extending at least partially adjacent to the periphery of the die; a test circuit coupled to the first and second signal lines, the test circuit being configured to generate a first feedback signal at least partially based on a first condition of the first signal line and a second feedback signal at least partially based on a second condition of the second signal line; and a control circuit coupled to the first and second signal lines, the control circuit being configured to transmit a clock signal to the test circuit and to receive the first and second feedback signals at least partially based on the transmission of the clock signal.

[0008] Another device is described. The device may include a plurality of signal lines and control circuitry coupled to the plurality of signal lines. The plurality of signal lines may include a first signal line and a second signal line, the first signal line at least partially surrounding a first plurality of memory cells of a die, and the second signal line at least partially surrounding a second plurality of memory cells of the die. The control circuitry may be configured to transmit a clock signal through the first signal line and the second signal line, and to receive a first feedback signal at least partially based on a first condition of the first signal line and a second feedback signal at least partially based on a second condition of the second signal line, based at least in part on the transmission of the clock signal.

[0009] A method is described. The method may include transmitting a first clock signal via a signal line in a first direction, the signal line at least partially surrounding a region of a memory cell of a die; receiving a first feedback signal from the signal line at least partially based on the transmission of the first clock signal via the signal line in the first direction; transmitting a second clock signal via the signal line in a second direction at least partially based on the reception of the first feedback signal from the signal line; receiving a second feedback signal from the signal line at least partially based on the transmission of the second clock signal via the signal line in the second direction; performing a test operation on the memory cell of the region of the die at least partially based on the reception of the second feedback signal from the signal line; and identifying defects in the region of the die at least partially based on the first feedback signal, the second feedback signal, or the test operation, or any combination thereof. Attached Figure Description

[0010] Figure 1This document describes an example of a segmented digital die defect detector that supports defect detection for memory devices, based on the examples disclosed herein.

[0011] Figure 2 This document describes an example of a segmented digital die defect detector that supports defect detection for memory devices, based on the examples disclosed herein.

[0012] Figure 3 This document describes an example of a control circuit that supports defect detection for memory devices, based on the examples disclosed herein.

[0013] Figure 4 This document describes an example of a segmented digital die defect detector that supports defect detection for memory devices, based on the examples disclosed herein.

[0014] Figure 5 This document describes an example of a digital die defect detector that supports defect detection for memory devices, based on the examples disclosed herein.

[0015] Figure 6 The flowchart illustrates a method for defect detection of memory devices based on examples disclosed herein.

[0016] Figure 7 A block diagram illustrating a memory device supporting defect detection for memory devices, based on examples disclosed herein.

[0017] Figure 8 The flowchart illustrates a method for defect detection of memory devices based on examples disclosed herein. Detailed Implementation

[0018] Some integrated circuits are fabricated on semiconductor materials and using semiconductor manufacturing processes that produce several integrated circuits formed on a single wafer. The wafer can be manufactured (e.g., sliced ​​or otherwise cut) into individual semiconductor dies. Due to the properties of the semiconductor material and the process of manufacturing (e.g., cutting from the wafer) multiple dies (e.g., simultaneously), the dies can be susceptible to defects (e.g., cracks). For example, the manufacturing process can generate stress at the respective edges of two dies cut from the same wafer. This stress can cause cracks in the respective edges of one or both of the dies. Stress during or after manufacturing can also cause cracks in the interior of the die, away from the die edges.

[0019] In some cases, detecting defects in dies is challenging because visually inspecting wafers to check for cracks can be very slow and impractical for mass production. Furthermore, defects in dies may not be visually apparent (e.g., they may be visually apparent under stress, they may be too small, they may be present along features, and they may be difficult to detect). Therefore, structures and techniques for detecting defects in scalable dies are useful for more efficient and effective die production.

[0020] In some cases, conductive lines or loops (e.g., continuous conductive loops) can be formed on the outer edge of a die to determine the presence of defects within that die. However, detecting defects using such conductive lines may require generating one or more analog test signals, which is typically a time-consuming and power-intensive process. Furthermore, the components associated with generating the analog test signals may use components with large voltage tolerances (e.g., transistors), which may utilize a large portion of the die area. Therefore, a digital solution for detecting defects in the die is needed. Moreover, because some conductive lines are formed on the outer edge of the die, these lines may not be able to detect defects inside the die, away from the die edge. And due to other conductive lines and die components, the loop cannot extend into the die interior.

[0021] This document describes techniques for using a segmented digital die defect detector to determine defects (e.g., cracks) in a die (e.g., a memory die). For example, to determine the presence and / or location of a crack in a die, the segmented die defect detector may include control circuitry coupled to multiple test circuits and separate signal lines positioned throughout the die (e.g., around the periphery of the die and / or through the interior of the die) to form paths including portions along the periphery of the die and through the interior of the die. Each test circuit may include a multiplexer configured to selectively route feedback signals indicating the condition of one or more signal lines located between the test circuitry and the control circuitry in the path to the control circuitry, or to couple one or more signal lines located between the test circuitry and the control circuitry to one or more signal lines further removed from the control circuitry in the path.

[0022] Feedback signals can be routed to control circuitry that generates a single digital output signal indicating whether a defect is located at or around a specific signal line, or whether the die is free of cracks. By using a digital testing process, the testing process can take less time, and the die defect detector may consume less power (e.g., in contrast to testing processes using analog signals). Additionally, by extending the path into the die, defects that might be missed inside the die can now be detected. Alternatively or additionally, the components associated with generating the single digital output signal may consume a smaller portion of the die (e.g., in contrast to testing processes using analog signals).

[0023] The features of this disclosure were originally described in reference to Figures 1 to 3 The description is made in the context of the system, die, and circuit diagram. The features of this disclosure are described in the references. Figures 3 to 6 The system context and flowchart are described. See references below. Figures 7 to 8 The device diagrams and flowcharts described are intended to further illustrate and describe these and other features of this disclosure.

[0024] Figure 1 This document describes an example of a segmented digital die defect detector 100 for defect detection in memory devices, based on the examples disclosed herein. Using the die defect detector 100, signals can be propagated along a path and analyzed to detect defects in the die.

[0025] The segmented digital die defect detector 100 is fabricated on a die 101 of a memory device. One or more other circuits, including one or more memory cells, may be fabricated on the die 101. In some cases, the die 101 may be a memory die. The segmented digital die defect detector 100 may include control circuitry 105, one or more test circuits 110 (e.g., test circuits 110-a, 110-b, 110-c, 110-d, 110-e, 110-f, 110-g, and 110-h), and an output 115. In some instances, the output 115 may be referred to as an output signal 115. The segmented digital die defect detector 100 may further include one or more signal lines 120 (e.g., signal lines 120-a, 120-b, 120-c, 120-d, 120-e, 120-f, 120-g, 120-h, and 120-i) coupled to the test circuit 110 to form a path 140-a that begins and ends at the control circuit 105 and extends along the periphery of the die 101. The digital die defect detector 100 may also be referred to as a digital die ring. Each of the signal lines 120 may couple the test circuit 110 to the next test circuit 110 in the path 140-a, or, in the case of a test circuit 110 in the path 140-a immediately adjacent to the control circuit 105, couple the test circuit 110 to the control circuit 105. For example, signal line 120-a can couple control circuit 105 to test circuit 110-a, and signal line 120-b can couple test circuit 110-a to test circuit 110-b.

[0026] In some instances, the segmented digital die defect detector 100 may include control circuitry 105, which may be directly or indirectly coupled to one or more test circuits 110 via one or more signal lines 120. Control circuitry 105 may be configured to generate one or more signals for determining the presence of defects (e.g., cracks) in die 101 and transmit them to test circuits 110 via path 140-a. For example, control circuitry 105 may transmit enable signals and / or clock signals to one or more test circuits 110 to determine the presence of defects. For example, the enable signal may be referred to as a digital segment selection signal and may enable test circuits 110 upon arrival at test circuit 110. Additionally or alternatively, the clock signal may clock-control the operation of control circuitry 105 and one or more test circuits 110.

[0027] Each of the test circuits 110 can be formed along the edge of the die 101, enabling the detection of defects along the periphery of the die 101. By placing multiple test circuits 110 along the outer edge of the die 101, defects in the periphery of the die 101 can be located more effectively and accurately (e.g., the signal line 120 associated with the defect can be more precisely identified). By more effectively locating defects in the periphery of the die 101, the cause of the defect can be identified and remedied. For example, the process of detecting defects in the die 101 can prevent further defects caused in other dies using the same or similar manufacturing processes. Therefore, the layout of the segmented digital die defect detector 100 can be used to detect defects in the die, such as those caused by a specific manufacturing process of the die (e.g., blade slicing, laser cutting, etching) or by some other irregularity in the die.

[0028] Control circuitry 105 may be coupled to one or more test circuits 110 via one or more signal lines 120 along path 140-a. The number of test circuits 110 and signal lines 120 may depend on the size of die 101 and / or the accuracy or precision of defect detection along specific portions of die 101. For example, using additional test circuits 110 on die 101 allows for more accurate or precise detection of defect locations because each signal line 120 can cover a smaller portion of die 101.

[0029] By way of example, test circuit 110-a may be referred to as first test circuit 110-a, and test circuit 110-b may be referred to as second test circuit 110-b. Signal line 120-a may be referred to as first signal line 120-a, and signal line 120-b may be referred to as second signal line 120-b. To determine the status of first signal line 120-a and / or second signal line 120-b, control circuit 105 may first transmit a clock signal (e.g., clock cycle) and an enable signal to first test circuit 110-a. In some embodiments, the clock signal and enable signal may be transmitted along path 140-a in a first direction (e.g., in a counterclockwise direction; away from control circuit 105, as indicated by the arrow of path 140-a). The first test circuit 110-a may be configured to generate a feedback signal based on the receipt of an enable signal, and the first test circuit 110-a may be configured to transmit the feedback signal back to the control circuit 105 in a second direction (e.g., in a clockwise direction, opposite to the first direction; toward the control circuit 105).

[0030] To generate a first feedback signal, the first test circuit 110-a may first isolate the first signal line 120-a from the second signal line 120-b. After isolating the signal lines 120-a and 120-b, the test circuit 110-a may generate a feedback signal indicating the condition of the first signal line 120-a and transmit the feedback signal to the control circuit 105 via the first signal line 120-a. In some instances, the feedback signal may indicate a first state or a second state of the first signal line 120-a. For example, the first state may indicate the presence of a defect (e.g., a crack) associated with the first signal line 120-a, and the second state may indicate the absence of a defect associated with the first signal line 120-a.

[0031] In some instances, each test circuit 110 may include a multiplexer. Each of the multiplexers may assist in selectively isolating or coupling signal lines coupled to the same test circuit. For example, test circuit 110-a may include a multiplexer that, depending on the state of a selection signal (which may be based on an enable signal), may couple a first signal line 120-a to a second signal line 120-b, or route a feedback signal (e.g., a digital feedback signal) to control circuit 105, and thus ultimately to output 115.

[0032] Control circuit 105 may receive a feedback signal from first test circuit 110-a indicating the condition of first signal line 120-a. For example, the feedback signal may indicate the presence of a defect in die 101 along (e.g., near) the first signal line 120-a, or the absence of a defect in die 101 along (e.g., near) the first signal line 120-a. Control circuit 105 may be coupled to and control output 115. If a defect is present, output 115 may indicate this by outputting a "low" (e.g., 0V) signal. If no defect is present along the first signal line 120-a, output 115 may indicate this by outputting a "high" (e.g., 1V) signal, and control circuit 105 may transmit an enable signal to second test circuit 110-b.

[0033] When an enable signal is transmitted to a subsequent signal line 120 in path 140-a (e.g., relayed from the first test circuit 110-a to the second signal line 120-b), a multiplexer associated with the previous test circuit 110 in path 140-a can couple the subsequent signal line 120 to the previous signal line. For example, to determine whether a defect exists along the second signal line 120-b, control circuit 105 can transmit an enable signal to the first test circuit 110-a, and the first test circuit 110-a can relay the enable signal to the second test circuit 110-b, and a multiplexer associated with the first test circuit 110-a can couple the first signal line 120-a to the second signal line 120-b.

[0034] Therefore, the multiplexer associated with the second test circuit 110-b can selectively isolate the second signal line 120-b from the signal line 120-c (e.g., the third signal line). The second test circuit 110-b can generate a feedback signal associated with the condition of the second signal line 120-b and transmit the feedback signal back to the control circuit 105. The multiplexer associated with the first test circuit 110-a can route the feedback signal from the second signal line 120-b to the first signal line 120-a and ultimately to the control circuit 105. Therefore, each multiplexer associated with a respective test circuit 110 can selectively isolate the preceding and subsequent signal lines 120 in path 140-a and route the feedback signal (e.g., a return feedback signal) from the subsequent signal line 120 to the preceding signal line 120. Thus, the control circuit 105 can receive a feedback signal from the test circuit 110-b indicating the condition of the second signal line 120-b.

[0035] As discussed above regarding the first signal line 120-a, the feedback signal can indicate the presence of a defect in die 101 along (e.g., near) the second signal line 120-b, or the absence of a defect in die 101 along (e.g., near) the second signal line 120-b. If a defect is present, output 115 can indicate this by outputting a "low" (e.g., 0V) signal. If no defect is present along the second signal line 120-b, output 115 can indicate this by outputting a "high" (e.g., 1V) signal, and control circuitry 105 can transmit an enable signal to additional test circuitry (e.g., test circuitry 110-c). Thus, by way of example, after determining whether a defect exists on the second signal line 120-b, output 115 can output a corresponding signal level for each signal line. In other words, output 115 can output a single signal with a state that changes over time. For example, the signal can transition between "low" and "high" voltages to indicate the presence of a defect associated with a particular signal line, where a "high" voltage indicates the absence of a defect in the signal line. In other instances, a "low" voltage can indicate the absence of defects in a signal line, while a "high" voltage can indicate the presence of defects in a signal line.

[0036] In some instances, the process described above can continue sequentially for each test circuit in path 140-a. The testing process can continue, and a feedback signal associated with each signal line 120 can indicate that no defects are present along the corresponding signal line 120. In some cases, the testing process can stop once a defect is identified, or it can proceed in different directions around the segmented digital die defect detector 100 until some or all of the other signal lines 120 have been tested or additional defects have been identified. Once each signal line 120 has been tested, the control circuitry 105 can stop transmitting an enable signal, and the testing process can end. In some instances, the output signal can remain "high," thereby indicating that no defects are present along die 101.

[0037] The test operation of test circuit 110 can determine defects associated with signal lines 120 coupled to the corresponding test circuit 110. Test circuit 110 can be operated in conjunction with control circuit 105 and output 115 to determine whether defects exist along the edge of die 101. For example, output 115 can generate a single output signal (e.g., a single digital output signal, the state of which may change over time as feedback signals are received by control circuit 105 from each test circuit 110) based on the determination of the presence of defects in the associated signal lines 120 by one or more test circuits 110. In other words, a single output can be generated based on multiple feedback signals received by control circuit 105 from multiple test circuits 110.

[0038] In some instances, the output signal may be a single digital signal. The components of test circuit 110 and control circuit 105 may consist of circuit systems designed to perform their respective functions. This may include various circuit elements, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, multiplexers, latches, flip-flops, logic gates, or other active or passive components configured to perform the functions described herein.

[0039] In some instances, the testing process described above can occur in multiple directions. For example, control circuitry 105 may first transmit an enable signal to signal line 120-a, and the test may be performed counterclockwise (e.g., ending at signal line 120-i). In other instances, control circuitry 105 may first transmit an enable signal to signal line 120-i, and the test may be performed clockwise (e.g., ending at signal line 120-a). Additionally or alternatively, control circuitry 105 may configure the test to be performed in multiple directions—for example, determining a defect associated with the corresponding signal line 120 during testing in a first direction, followed by testing in a second direction. For example, if control circuitry 105 determines a defect associated with the second signal line 120-b during counterclockwise testing, the condition of the die 101 associated with signal lines 120-c, 120-d, 120-e, 120-f, 120-g, 120-h, and 120-i may be unknown. However, in some instances, the control circuit 105 may transmit an enable signal to signal line 120-i and perform this in a clockwise direction to determine the condition of such signal line 120.

[0040] In some instances, the path may extend through at least a portion of the die. For example, one or more signal lines may extend through at least a portion of the die to form an internal path (e.g., path 140-b). The internal path may or may not contain any number of test circuits. The internal path may or may not be combined with a peripheral path (e.g., peripheral path 140-a). The internal path may be controlled by the same control circuitry (e.g., control circuitry 105) as the peripheral path, or it may be controlled by a separate control circuitry.

[0041] Using the die defect detector 100, the presence and location of die defects can be determined both along the periphery of the die and through its interior. By using a digital testing process, the testing process may take less time, and the die defect detector may consume less power (e.g., unlike testing processes using analog signals). Additionally, the components associated with generating a single digital output signal may consume a smaller portion of the die (e.g., unlike testing processes using analog signals).

[0042] Figure 2This document describes an example of a segmented digital die defect detector 200 for defect detection of memory devices, based on the examples disclosed herein.

[0043] The segmented digital die defect detector 200 may include a plurality of signal lines 201 depicted in a cross-sectional view. For example, the segmented die defect detector 200 may include signal lines 201-a and 201-b, which may be respectively as shown in reference... Figure 1 Examples of signal lines 120-a and 120-b are described. Each of signal lines 201-a and 201-b may be coupled to test circuit 220, which may be as described in the reference. Figure 1 An example of the described test circuit 110-a. In some instances, the segmented digital die defect detector 200 may include multiple signal lines 201 coupled to multiple test circuits 220. Thus, signal line 201-c may represent the last signal line in the path of the segmented digital die defect detector 200 (e.g., reference...). Figure 1 The described signal line 120-i).

[0044] In some instances, the die of the memory device may comprise various signal layers (e.g., a polysilicon layer and layers M0, M1, M2, and M3), through which aspects of each signal line 201 may be located. For example, signal line 201-a may include a clock line 205-a that passes through one or more layers (e.g., layers M1, M2, and M3), a status line 210-a that passes through one or more layers (e.g., layers M0, M1, and M2), and an enable line 215-a that passes through one or more layers (e.g., polysilicon, M0, and M1). Each line may be connected to a test circuit 220. Metal or metallized layers may be represented by M0, M1, M2, and M3. In some cases, insulating layers may be positioned between the metal layers.

[0045] Test circuit 220 controls the test operations associated with signal lines 201-a and 201-b. In the example described herein, test circuit 220 may correspond to any of test circuits 110, and signal line 201 may correspond to any of signal lines 120, as referenced. Figure 1 describe.

[0046] Test circuit 220 may be coupled to signal lines 201-a and 201-b. In some instances, test circuit 220 may be coupled (e.g., may be configured to selectively couple or decouple) various signal lines (e.g., coupling aspects of signal line 201-a to aspects of signal line 201-b). For example, an enable signal may be transmitted to test circuit 220 via enable line 215-a, and a feedback signal may be returned to control circuit 105 via status line 210-a. If no defect is associated with signal line 201-a, then test circuit 220 may subsequently couple aspects of signal line 201-a to aspects of signal line 201-b, and the test procedure described above may continue (e.g., may proceed to include signal line 201-b).

[0047] In some instances, clock line 205-a may be coupled to one or more components of test circuitry 220. For example, clock line 205-a may be coupled to at least one inverter (e.g., inverter 235) that provides a clock signal (e.g., ClockF) to test circuitry 220 based on the Clock(x) signal provided by clock line 205. The logic value of ClockF may be complementary to the logic value of the Clock(x) signal. For example, the Clock(x) signal may be '1V', and the ClockF signal may be '0V'. In some instances, an additional inverter 235-a may generate a delayed clock signal (e.g., ClockD) that may be delayed relative to the Clock(x) signal but has the same logic value.

[0048] NAND gate 225 can be configured to receive the ClockD signal, and the output of NAND gate 225 can be coupled to another inverter 230, which can be coupled to a portion of the second signal line 201-b and configured to output a clock signal Clock(x+1) for the second signal line. Clock line 205-a can carry a clock signal that clocks the test circuit 220 during operation. Clock line 205-a can be a clock signal Clock(x) originating from an external system (e.g., tester circuitry) or an internal system (e.g., control circuitry 105) that generates the clock signal. For example, the clock line 205-a signal can be internally generated when the die's test mode is activated. In this test mode, the clock line 205 signal can be received at the test circuit 220 from the internal or external system that generates the clock signal to provide the clock line 205-a signal.

[0049] In some instances, test circuit 220 may include latch circuit 240, which may be or is referred to as D latch circuit 240, and latch circuit 245, which may be or is referred to as SR latch circuit 245. Enable line 215-a may be coupled to latch circuit 240 and inverter 250, and the output of inverter 250 may be coupled to latch circuit 245 and inverter 255. In some instances, latch circuit 240 may be coupled to a portion of signal line 201-a (e.g., portion of enable line 215-a), and the output of inverter 255 may be coupled to a portion of a second (e.g., additional) signal line 201-b (e.g., portion of enable line 215-b). Enable line 215-a may transmit an enable signal that enables testing of the signal line controlled by test circuit 220. An enable signal may be generated when a test mode is activated. For example, an enable signal may be generated at an external system when the die's test mode is activated. An enable signal can be received from, for example, an external system that generates a signal, at enable line 215-a.

[0050] In some instances, latch circuit 240 may receive inputs and output various signals related to test operations controlling the die. Latch circuit 240 may receive a SegTog signal, which may be generated by latch circuit 245 as described below, and may instruct test circuit 220 to include the die's signal lines in the test operation. In some instances, the SegTog signal may be set to a "high" logic level (e.g., 1V) before the test operation, such that the "high" logic level is latched when a clock signal is received at latch circuit 240 (e.g., a rising edge). For example, latch circuit 240 may receive a ClockD signal (as described above) and an enable signal, which may enable test circuit 220 to test at least one signal line (e.g., signal line 201-a). The latch circuit 240 can output a signal line selection signal to the AND gate 260, which can also be called a test stage selection signal (e.g., StageSel signal). The output of the AND gate 260 can be input to the second latch circuit 245.

[0051] In some instances, latch circuit 240 may also output the StageSel signal to additional components of test circuit 220, such as multiplexer 265. Multiplexer 265 may be a two-to-one multiplexer, and the StageSel signal may control which input of multiplexer 265 is output by multiplexer 265 (e.g., which input is routed by multiplexer 265 to the previous signal line 201-a). Although described in terms of latch circuitry, it will be understood that any combination of circuitry or latch circuitry that receives and transmits the signals described herein for controlling test operations may be used to perform the functionality of latch circuit 240.

[0052] In some instances, the second latch circuit 245 may receive input based on an enable signal (e.g., an inverted version of the enable signal output by inverter 250), a clock signal (e.g., the output of AND gate 260, which may be based on the StageSel and ClockF signals), and various signals related to test operations controlling the die. The latch circuit 245 may output a NextSegEn signal. In some instances, the NextSegEn signal may be received at NAND gate 225 as described above, which may transmit the clock signal Clock(x+1) to adjacent signal line 201-b or adjacent test circuitry via clock line 205-b. Additionally or alternatively, the NextSegEn signal may be received at AND gate 270, and the output of AND gate 270 may include a feedback signal indicating the state of the previous signal line 201-a. Although described in accordance with the SR latch circuit, it is understood that any combination of circuit systems or latch circuits that receive and transmit signals described herein for controlling test operations can be used to perform the functionality of latch circuit 245.

[0053] Depending on the logic value of StageSel (which controls the operation of multiplexer 265), multiplexer 265 can route the feedback signal output from AND gate 270 to control circuitry 105 via state line 210-a, or couple subsequent signal line 201-b to previous signal line 201-a. For example, an input to multiplexer 265 can be coupled to state line 210-b of subsequent signal line 201-b, and the output of multiplexer 265 can be coupled to state line 210-a of previous signal line 201-a. Therefore, when StageSel has a first logic value (e.g., logic "0"), multiplexer 265 can route an input coupled to state line 210-b of subsequent signal line 201-b to the output of multiplexer 265.

[0054] This could cause subsequent signal line 201-b to couple with previous signal line 201-a. And when StageSel has a second logic value (e.g., a logic "1"), multiplexer 265 can route the input coupled to the output of AND gate 270 to the output of multiplexer 265. This could cause feedback signals to be routed to control circuitry 105 via state line 210-a of previous signal line 201-a and the state lines of any additional previous signal lines.

[0055] In some instances, latch circuit 245 may also output a SegTog signal that can be received at latch circuit 240, as described above. Receiving the SegTog signal at latch circuit 240 can change the logic state of latch circuit 240. For example, the SegTog signal can be set by latch circuit 245 to a "low" logic level (e.g., 0V) such that the "low" logic level can be latched by latch circuit 240 when a clock signal is received at the edge of the clock signal. In some instances, locking the "low" logic level can terminate a test operation performed by test circuit 220 (e.g., can change the state of StageSel and therefore the state of multiplexer 265), configuring multiplexer 265 to couple subsequent signal line 201-b to previous signal line 201-a instead of routing the feedback signal generated by AND gate 270. Although described with reference to SR latch circuit 245, it is understood that any combination of circuitry or latch circuitry that receives and transmits signals described herein for controlling test operations may be used to perform the functionality of latch circuit 245.

[0056] In some instances, state line 210-a may return a feedback signal associated with a specific signal line to control circuitry 105. As described above, state line 210-a of the preceding signal line 201-a may be coupled to the output of multiplexer 265, the input of which may be coupled to AND gate 270 and state line 210-b of subsequent signal line 201-b.

[0057] AND gate 270 can receive the NextSegEn signal and the clock signal ClockF from latch circuit 245. Based on the received NextSegEn signal, AND gate 270 can generate a feedback signal that multiplexer 265 can route to control circuit 105 when multiplexer 265 is configured by StageSel signal. In some cases, the feedback signal can be a "high" (e.g., 1V) value or a "low" (e.g., 0V) value. In some instances, a "high" value can indicate that there is no defect in the previous signal line 201-a (or any other additional intermediate signal line 201 between the previous signal line 201-a and the control circuit), and a "low" value can indicate that there is at least one defect in the previous signal line 201-a. If the feedback signal associated with each intermediate signal line 201 is "high", then it can be determined that a defect is isolated to the previous signal line 201-a. After returning the "high" value to the control circuit, the enable signal can be transmitted to the subsequent test circuit (e.g., via inverter 255, whose output can be coupled to enable line 215-b of subsequent signal line 201-b) to determine the status of subsequent signal line 201 as described above.

[0058] In some instances, the bare die may contain no defects. For example, see reference... Figure 1 The clock signal and enable signal can be transmitted along path 140-a to each test circuit 110, and each test circuit can transmit a feedback signal indicating that the condition of the corresponding signal line is not associated with a defect back to the control circuit 105.

[0059] In some instances, clock line 205 may correspond to the topmost metal layer of the die. For example, the metal layer may be an aluminum layer. Clock line 205 may represent a conductive path (e.g., a single conductive path) for propagating signals around the die. Some signal lines on the die may span one or more layers, which may be referred to as vertical segmentation of the die. For example, the die may be vertically segmented according to the different signal lines described herein. Thus, signal lines can form conductive paths within the die. In some instances, enable line 215 may comprise several layers of the die, which may be or may comprise metal layers and / or polysilicon layers formed on the substrate of the die. Figure 2 As shown, when the enabled line 215-a spans three layers, the line can carry additional signals, such as a "reset" signal, which can reset some values ​​coupled to the test circuit 220 of the enabled line 215-a. Figure 2 As shown, some intermediate connections between layers of the die can couple layers to form a single conductive path for signal propagation on enable line 215-a. For example, a "reset" signal can be activated on a different layer than the enable signal, but both signals can propagate along a single conductive path. In some instances, the "reset" signal can reset latch circuits 240 and 245, such that the values ​​of the respective latch circuits are reset to a uniform value (e.g., a "0" value) in each test circuit 220.

[0060] Test circuit 220 can be configured to generate a feedback signal at least in part based on the condition of the corresponding signal line 201. Testing of the condition of the corresponding signal line 201 can be included in control circuitry (e.g., as referenced). Figure 1 The control circuit 105 described receives a feedback signal. In some instances, multiple signal lines (e.g., 201-a, 201-b) may be coupled to each other, which may result in multiple feedback signals being returned to the control circuit. As previously described, an output signal may be generated based on the feedback signal and a clock cycle, which may indicate the status of one or more signal lines 201. For example, a "high" output signal (e.g., 1V) may indicate that no defect is associated with the corresponding signal line 201. In other instances, a "low" output signal (e.g., 0V) may indicate that one or more defects are associated with the corresponding signal line 201.

[0061] Therefore, test circuit 220 can be configured to receive clock signal 205-a and enable signal 215-a via previous signal line 201-a. In the initial operating state (e.g., the first half of a cycle of clock signal 205-a or based on the first half of a cycle of clock signal 205-a), test circuit 220 can generate a feedback signal, also referred to as a status signal, and transmit the feedback signal back towards the control circuit via status line 210-a. Test circuit 220 can transmit the feedback signal of previous signal line 201-a in the opposite direction to the direction in which test circuit 220 receives clock signal 205-a and enable signal 215-a. In the initial operating state of the test circuit 220, the feedback signal generated and transmitted by the test circuit 220 can be based on and thus indicate the condition of the previous signal line 201-a, because if there is a defect in the previous signal line 201-a, the clock signal 205-a and the enable signal 215-a cannot reach the test circuit 220 (and therefore the test circuit 220 cannot generate a feedback signal), or the feedback signal generated by the test circuit 220 cannot reach the control circuit 105 via the status line 210-a.

[0062] If the previous test circuit (i.e., the test circuit between test circuit 220 and control circuit 105) generates a feedback signal successfully received by control circuit 105, and test circuit 220 does not generate a feedback signal successfully received by control circuit 105, then it can be determined (e.g., by control circuit 105 or by an external device operating the segmented digital die defect detector 200) that a defect in the die is located at signal line 201-a. Conversely, if test circuit 220 does not generate a feedback signal successfully received by control circuit 105, then it can be determined (e.g., by control circuit 105 or by an external device operating the segmented digital die defect detector 200) that signal line 201-a and any previous signal lines are defect-free.

[0063] In a subsequent operating state (e.g., the latter half of a cycle of clock signal 205-a or based on the latter half of a cycle of clock signal 205-a), test circuit 220 may generate an enable signal NextSegEn for the subsequent test circuit, and may generate a clock signal Clock(x+1) for the subsequent test circuit based on the enable signal for the subsequent test circuit. Test circuit 220 may transmit the clock signal Clock(x+1) for the subsequent test circuit and relay the enable signal received via the previous signal line 201-a (or, alternatively, on the enable signal for the subsequent test circuit) to the subsequent test circuit. Also in a subsequent operating state, test circuit 220 may couple the subsequent signal line 201-b to the previous signal line 201-a via multiplexer 265 (e.g., based on the enable signal NextSegEn for the subsequent test circuit) and route any feedback signals received via the subsequent signal line 201-b back to control circuit 105 via status line 210-b.

[0064] Using test circuit 220, the presence and location of die defects can be determined along the periphery of the die and through its interior. By using a digital testing process, the testing process may take less time, and the die defect detector may consume less power (e.g., unlike testing processes using analog signals). Additionally, the components associated with generating a single digital output signal may consume a smaller portion of the die (e.g., unlike testing processes using analog signals).

[0065] Figure 3 This document describes an example of a control circuit 300 for defect detection in a memory device, based on the examples disclosed herein. The control circuit 300 may be as described above (referenced). Figure 1 An example of the control circuit 105. See above for reference. Figure 1 The description states that clock signals, enable signals, and status signals can be routed via a die ring path (e.g., as described in the reference). Figure 1 The segmented digital modulus defect detector 100 described or as referenced Figure 2 The segmented digital die defect detector 200 is described. In some instances, control circuitry 300 may transmit a clock signal to clock line 304, an enable signal to enable line 306, and a status signal to status line 308. Clock line 304, enable line 306, and status line 308 may be associated with a first signal line in the path of the segmented digital die ring (e.g., as described in Reference 200). Figure 1 The described signal line is 120-a). In some instances, the control circuit 300 may receive a return clock signal from the return clock line 310 and a return enable signal from the return enable line 315. The return clock line 310 and the return enable line 315 may be associated with the last signal line in the path of the segmented digital die ring (e.g., see reference 120-a). Figure 1The described signal line 120-i).

[0066] The control circuit 300 may include a master clock component 350, a master enable component 355, and a master status component 375, which can transmit clock signals, enable signals, and status signals to first signal lines (e.g., to reference 375). Figure 1 The description is for signal line 120-a).

[0067] In some instances, the master clock component 350 may include an AND gate 377 coupled to amplifier 379. The inputs to the AND gate 377 may be, for example, a DetectionMode signal and a master clock signal. At the start of the test mode, the DetectionMode signal and the master enable signal may be driven high to initiate the test operation. The master clock component 350 may output a clock signal.

[0068] The main state component 375 may include an inverter 381 coupled to the AND gate 383 and the amplifier 385. In some instances, the input to the inverter 381 may be or may include a DetectionMode signal, and the inverter 381 may output an inverted DetectionMode signal to one input of the AND gate 383. In some instances, the second input of the AND gate 383 may be a master clock signal. The main state component 375 may output a state signal.

[0069] Receiving the return clock signal and the return enable signal can be partially based on the control circuitry 300 transmitting the clock signal and enable signal to a first signal line in the path (e.g., to signal line 120-a). For example, the clock signal and enable signal can be transmitted from the master clock component 350 and the master enable component 355, respectively. See reference... Figure 1 The description states that a first test circuit in the path (e.g., test circuit 110-a) can receive an enable signal and return a feedback signal indicating the condition associated with a corresponding first signal line (e.g., signal line 120-a). The test circuit can also couple a previous signal line (e.g., signal line 120-a) to a subsequent signal line (e.g., signal line 120-b) so that a clock signal and an enable signal can be transmitted to a subsequent test circuit in the path (e.g., to test circuit 110-b).

[0070] In some instances, this process can continue such that the final signal line in the path (e.g., signal line 120-i) can transmit a clock signal (i.e., a return clock signal) and an enable signal (i.e., a return enable signal) to the control circuit 300. As described above, the return clock signal and the return enable signal can be received by return clock line 310 and return enable line 315, respectively. When there are no defects (e.g., cracks) in the die, these signals can be received at the control circuit 300 (e.g., from signal line 120-i). For example, if there are defects in the die, the return feedback signal will indicate this, and the test process (e.g., the clock signal and enable signal transmitted by the control circuit 300) can end.

[0071] In some instances, the return clock line 310 may be coupled to at least one inverter (e.g., inverter 360) that provides a clock signal ClockF to the AND gate 325. In some instances, the logic value of ClockF may be complementary to the logic value of the received return clock signal. For example, the return clock signal may be '1V', and the ClockF signal may be '0V'. In some instances, an additional inverter (e.g., inverter 360-a) may generate a delayed clock signal ClockD, which may be delayed relative to the return clock signal but have the same logic value.

[0072] In some instances, control circuitry 300 may include latch circuitry 320, which may be or may be referred to as D latch circuitry 320, and latch circuitry 330, which may be or may be referred to as SR latch circuitry 330. Return enable line 315 may be coupled to latch circuitry 320 and inverter 365, and the output of inverter 365 may be coupled to second latch circuitry 330.

[0073] In some instances, latch circuit 320 may receive inputs and output various signals related to the test operations of the die. Latch circuit 320 may receive a SegTog signal, which may be output by latch circuit 330. In some instances, the SegTog signal may be set to a "high" logic level (e.g., 1V) before receiving the return clock signal and return enable signal at control circuit 300, such that the "high" logic level is latched when the clock signal is applied at latch circuit 320 at an edge (e.g., a rising edge). For example, latch circuit 320 may receive a ClockD signal (as described above) and a return enable signal. Latch circuit 320 may output a signal line select signal to AND gate 325, which may also be referred to as a test stage select signal (e.g., StageSel signal), and the output of AND gate 325 may be input to second latch circuit 330. Although described with reference to latch circuit 320, it is understood that any combination of circuit systems or latch circuits that receive and transmit signals described herein for controlling test operations may be used to perform the functionality of latch circuit 320.

[0074] In some instances, the second latch circuit 330 may receive an input based on a return enable signal and the output of AND gate 325, the output of which may be based on the StageSel and ClockF signals. The second latch circuit 330 may receive an inverted version of the return enable signal output by inverter 365 and may output various signals related to other aspects of the control circuit 300. For example, along with the SegTog signal, the latch circuit 330 may output a signal indicating the completion of the test sequence for the segmented digital die ring, which may be called the FinalFlag signal, and may be generated based on the return clock signal and return enable signal received by the control circuit 300 from the final signal line.

[0075] In some instances, the FinalFlag signal along with the inverted version of the DetectionMode signal can be received at AND gate 335. As described above, the DetectionMode signal can be driven high (e.g., to 1V) at the start of a test operation. The inverted version of the DetectionMode signal can be, for example, 0V. Therefore, since both the FinalFlag signal and the inverted version of the DetectionMode signal can be received at AND gate 335, the output of AND gate 335 can have the same logic value as the FinalFlag signal as long as DetectionMode is high. The output of AND gate 335 can be referred to as the FlagMode signal and can control multiplexer 340.

[0076] Multiplexer 340 can be a two-to-one multiplexer, and the FlagMode signal controls which input of multiplexer 340 is output by multiplexer 340. In some instances, multiplexer 340 may receive an input (e.g., the FinalFlag signal) and a feedback signal 345 from latch circuitry 330. Feedback signal 345 may be received from one or more test circuits (e.g., from reference circuitry). Figure 1 The described test circuit 110-a receives the data, which can also correspond to the reference. Figure 2 The output of the described multiplexer 265). As described above, each test circuit can receive a clock signal and an enable signal, and can return a feedback signal indicating the status of the corresponding signal line segment. For example, see reference... Figure 1 The test circuit 110-a is described as receiving a clock signal and an enable signal, and returning a feedback signal indicating the status of the signal line 120-a. Therefore, the feedback signal 345 can return feedback from multiple test circuits and can transition between a "high" value (e.g., 1V) and a "low" value (e.g., 0V).

[0077] Therefore, the multiplexer 340 can output a StatusFlag signal that reflects either the FinalFlag signal or the StatusFlag signal of the feedback signal 345, depending on the status of the FlagMode signal. Thus, the StatusFlag signal can reflect the feedback signal 345 before the FlagMode signal selects the logic value of the FinalFlag signal to be output by the multiplexer 340. That is, during the first clock cycle, the status of the StatusFlag signal can reflect the feedback signal generated and transmitted by the first test circuit, then during the second clock cycle, it reflects the feedback signal generated and transmitted by the second test circuit, and so on, thus reflecting the status of the associated signal lines.

[0078] Once the FlagMode signal selects the logic value of the FinalFlag signal output by multiplexer 340 (e.g., once the signal carried by return clock line 310 and return enable line 315 arrives at control circuit 300, and the output of second latch circuit 330 changes its logic value), then the StatusFlag signal can reflect the FinalFlag signal. Therefore, if the StatusFlag signal is configured to have a "high" value (e.g., 1V) once the test sequence is complete, then the StatusFlag signal can be latched as having a high value once the test sequence is complete. In other words, when the corresponding signal is transmitted around the entire segmented digital die ring (e.g., the die is defect-free), return clock line 310 and return enable line 315 can return the return clock signal and return control signal to control circuit 300. Therefore, the FinalFlag signal can be generated when the die is defect-free and can be used to generate the StatusFlag signal. When the die is free of defects, the StatusFlag signal can be output to output line 370, which can output a "high" value (e.g., 1V) (or a low value in other instances) to indicate the absence of defects. The StatusFlag signal may correspond to, as referenced... Figure 1 The output signal 115 is discussed, or as referenced. Figure 1 The output signal 115 can be based on the StatusFlag signal.

[0079] Therefore, the control circuit 300 may be configured to transmit an original clock signal (e.g., a clock signal generated by the master clock component 350) and an original enable signal (e.g., an enable signal generated by the master enable component 355) to the first test circuit via a first signal line in a first direction, and to receive a feedback signal (e.g., feedback signal 345) via (at least partially) the first signal line in a second different direction, wherein the feedback signal may be at least partially based on the state of one or more signal lines traversed by the feedback signal (e.g., based on the state of the first signal line during a first cycle of the clock signal, then based on the state of the first and second signal lines during a second cycle of the clock signal, then based on the state of the first, second, and third signal lines during a third cycle of the clock signal, and so on). The control circuit 300 may be configured to generate or drive the output signal 115 (e.g., modify its state) based on the feedback signal (e.g., feedback signal 345).

[0080] The control circuit 300 may also be configured to receive a return clock signal and a return enable signal via return clock line 310 and return enable line 315, respectively, once the original clock signal and the original enable signal, or at least signals based thereon, have traversed the entire path of the segmented digital die ring. The control circuit 300 may then be configured to modify the output signal 115 (e.g., modify its state) to reflect the successful completion of the test sequence (e.g., reflect the value of the FinalFlag signal).

[0081] Using control circuitry 300, the presence and location of die defects can be determined along the periphery of the die and through its interior. By using a digital testing process, the testing process may take less time, and the die defect detector may consume less power (e.g., unlike testing processes using analog signals). Additionally, the components associated with generating a single digital output signal can consume a smaller portion of the die (e.g., unlike testing processes using analog signals).

[0082] Figure 4 This document describes an example of a segmented digital die defect detector 400 for defect detection in memory devices, based on the examples disclosed herein. Similar to the die defect detectors discussed above, using the die defect detector 400, signals can be routed through paths and analyzed to detect defects in the die.

[0083] The die defect detector 400 is fabricated on a die 401 of a memory device. One or more other circuits may be fabricated on the die 401, including one or more memory cells or one or more memory banks of memory cells. In some cases, the die 401 may be an instance of a memory die. For example, the die 401 may include one or more memory cells grouped into one or more memory banks 430 (e.g., memory banks 430-a, 430-b, ..., 430-p). The die defect detector 400 may be similar in many respects to the digital die defect detector 100 (see reference 100). Figure 1 (Discussion). For example, similar to the digital die defect detector 100, the die defect detector 400 may include control circuitry 405 and one or more test circuits 410 (e.g., test circuits 410-a, 410-b, ..., 410-f), wherein one or more signal lines 420 (e.g., signal lines 420-a, 420-b, ..., 420-g) couple one test circuit to the next (or couple a test circuit to the control circuit) to form a path from the control circuitry 405 through the test circuits 410 and back to the control circuitry 405.

[0084] In some instances, control circuitry 405 may correspond to or be incorporated into, as referenced. Figure 1 and 3The control circuit 105 or control circuit 300 described herein; the test circuit 410 may correspond to or be incorporated into as referenced. Figure 1 and 2 The aspects of the described test circuit 110 or test circuit 220; and the signal line 420 may correspond to or be incorporated into as referenced. Figure 1 and 2 The aspects of signal lines 120 or 201 are described.

[0085] Similarly, similar to the digital die defect detector 100, one or more of the signal lines 420 (e.g., signal lines 420-b, 420-c, ..., 420-f) may be formed along or adjacent to the edge or periphery 402 of the die 401, making it possible to detect defects along the periphery of the die 401. In this context, the term "adjacent" may refer to components that are close to each other. In some cases, adjacent components may be coupled together (electrically or physically), or adjacent components may not be coupled together (electrically or physically). In some instances, signal lines adjacent to the edge of the die may be located between one or more memory cells and the edge of the die. As discussed above, by placing multiple test circuits and their associated wiring segments along the outer edge of the die, defects in the periphery of the die can be located more effectively and accurately. However, this placement of the test circuits and wiring segments can detect or identify defects along the outer edge of the die. It cannot detect or identify defects inside the die (e.g., away from the edge or periphery of the die).

[0086] Therefore, in the digital die defect detector 100, a subset (e.g., one or more) of the signal lines 420 along the path (e.g., signal lines 420-a and 420-g) may extend into the die (viewed from above) or through a portion of the die (e.g., away from the edge or periphery 402), such that at least a portion of the path passes through the interior of the die. To distinguish between signal lines extending into the die and signal lines extending adjacent to the periphery of the die, the signal lines herein may be referred to as internal signal lines (e.g., signal lines 420-a and 420-g) and peripheral signal lines (e.g., signal lines 420-b, 420-c, ..., 420-f), respectively. In some cases, internal signal lines may be instances of portions of signal lines extending between or above the memory banks of memory cells and away from the edge of the die.

[0087] Similar to the digital die defect detector 100, clock, enable, and status signals can be initiated by the control circuit 405 and routed along the path from one test circuit to the next via signal line 420, with feedback signals returning to the control circuit 405, as shown in the reference. Figures 1 to 3Discussion. Using the die defect detector 400, a signal can pass through an internal portion of the die (e.g., the signal can pass through internal signal line 420-a), but the concept can be the same: the signal line can extend between adjacent test circuits in the path, or between a control circuit and the first or last test circuit in the path, regardless of whether the line extends along the periphery or into the internal portion of the die. By doing so, defects inside the die can be detected or identified in the same way as defects along the periphery of the die.

[0088] In some instances, the test circuit can be positioned at the intersection of internal and external signal lines, for example, such that the internal signal lines and peripheral signal lines are coupled to the test circuit. This can help distinguish the location of detected defects (e.g., whether the defect is located on the internal portion or the periphery of the die). For example, test circuit 410-a can be positioned such that internal signal line 420-a and peripheral signal line 420-b are coupled to the test circuit, and test circuit 410-f can be positioned such that internal signal line 420-g and peripheral signal line 420-f are coupled to the test circuit.

[0089] Internal signal lines can pass through the internal portion of a die in many different ways. For example, when viewed from above, the signal line can pass through generally straight lines. In some instances, the signal line may comprise multiple segments extending in different directions. In some instances, the signal line may form a specific geometry. In some instances, the signal line may enter and exit the internal portion of the die from the same side (as depicted) or from opposite sides of the die. In some instances, when viewed from above, internal signal lines may enter between components.

[0090] In some cases, internal signal lines may extend through a portion of a die separating one or more circuit elements (e.g., a memory bank) (as viewed from above). For example, as in... Figure 4 As shown, signal line 420-a can extend to a portion of die 401 separated from memory bank 430-m by memory bank 430-j. In some instances, internal signal lines can separate the die into multiple regions. For example, as in... Figure 4 As shown, signal line 420-a can separate die 401 into four separate regions, each containing four memory banks 430.

[0091] In one instance, the placement and / or design of signal lines can help mitigate potential collisions with other signal lines and / or components that may also be placed within the internal portions of the die. A die containing memory cells and supporting circuitry may be very small, and the routing layer may contain numerous signal lines for operating the memory cells. In some portions of the die, it may be difficult to route signal lines for detecting defects in the internal portions of the die without shifting or interfering with other signals. In some cases, the die may contain a redistribution layer positioned above other layers of the die. In some instances, the redistribution layer may be an example of an iRDL layer, which can be used to route signaling lines containing internal signal lines for defect detection. An iRDL layer may refer to a redistribution layer formed in a semiconductor process prior to assembly to contain low-resistivity lines to provide power and other signals to locations within the device. The iRDL layer may be located on the topmost layer of the die (e.g., on...). Figure 2 The iRDL layer (above layer M3) can be the lowest resistivity layer in the device. The pathway can couple the iRDL layer to other layers of the die (e.g., polysilicon layers M0, M1, M2, and M3). The die defect detector 400 can use one or more signal lines located in layers that pass through the interior portion of the die.

[0092] In some instances, gaps may exist around the periphery of the die, through which one or more signal lines enter the internal portion of the die. For example, a gap may exist between test circuits 410-a and 410-f, which are coupled to internal signal lines 420-a and 420-g, respectively. To avoid potentially missing defects in the peripheral gap portion, test circuits 410-a and 410-f may be positioned physically close together. For example, test circuits 410-a and 410-f may be positioned even closer together at the periphery of the die.

[0093] although Figure 4 Two internal signal lines 420-a and 420-g are shown, but any number of internal signal lines can be used. For example, one, three, or more internal signal lines can be used. Furthermore, although internal signal lines 420-a and 420-g are entirely within the internal portion of die 401, the signal lines may alternatively include a portion traveling along the periphery of the die and a second portion passing through the internal portion of the die, as discussed in more detail below.

[0094] In some instances, the test circuitry can handle more than one signal line. For example, test circuits 410-b and 410-e can be configured to each handle two signal lines, and internal signal line 420-a can be divided into three segments passing through the internal portion of the die. The first segment can pass internally between control circuit 405 and test circuit 410-e; the second segment can pass internally between test circuits 410-e and 410-b; and the third segment can pass internally between test circuits 410-b and 410-a. In some instances, internal signal lines 420-a and 420-g can be coupled to test circuits 410-b, 410-c, 410-d, or 410-e, or any other test circuitry or any combination thereof.

[0095] Figure 5 This document describes another example of a digital die defect detector 500 that supports defect detection for memory devices, based on the examples disclosed herein. Similar to the die defect detectors discussed above, with the die defect detector 500, signals can be routed through paths and analyzed to detect defects in the die.

[0096] The die defect detector 500 is fabricated on a die 501 of a memory device, and one or more other circuits including one or more memory cells may be fabricated on the die 501. In some cases, the die 501 may be a memory die. For example, the die 501 may include one or more memory cells grouped into one or more memory banks 530 (e.g., memory banks 530-a, 530-b, ..., 530-p). The die defect detector 500 may be similar in many respects to the die defect detector 400 (see reference 400). Figure 4 (Discussion). For example, similar to the die defect detector 400, the die defect detector 500 may include control circuitry 505 and one or more test circuits 510 (e.g., test circuits 510-a, 510-b, ..., 510-f), wherein one or more signal lines 520 (e.g., signal lines 520-a, 520-b, ..., 520g) couple the test circuitry and control circuitry to form a path from control circuitry 505 through test circuitry 510 and back to control circuitry 505, at least a portion of said path passing through an internal portion of the die.

[0097] However, the die defect detector 500 may include control circuitry 505 through which multiple paths of the routed signal are possible, not just a single path. And one or more of these paths may not contain any test circuitry. For example, as in... Figure 5As shown, control circuitry 505 can route signals via four separate paths 540. The first path 540-a may include a single signal line 520-a extending to and from control circuitry 505. The second path 540-b may include test circuits 510-a and 510-b, and signal lines 520-b, 520-c, and 520-d extending to and from control circuitry 505. The third path 540-c may include test circuits 510-c and 510-d, and signal lines 520-e, 520-f, and 520-g extending to and from control circuitry 505. The fourth path 540-d may include a single signal line 520-h extending to and from control circuitry 505. Each of these paths is an example of a different configuration of signal lines. Any of the illustrated configurations can be used to configure any signal line 520 on the die.

[0098] By using multiple paths, multiple defects in a die can be detected. Furthermore, any detected defect can be located more precisely. Additionally, defect searches can be performed simultaneously along individual paths, thereby saving time.

[0099] In some cases, each signal line 520 may include a portion passing through the interior of the die 501 and a portion extending along the periphery of the die 501 (or adjacent to the periphery of the die 501). In such cases, each signal line 520 may be incorporated as referenced. Figure 4 The internal signal lines discussed and also referenced Figure 4 The discussion focuses on the peripheral signal lines.

[0100] In one instance, the die may include individual regions, and each path may at least partially surround or otherwise define one of the regions. For example, paths 540-a, 540-b, 540-c, and 540-d may define four individual regions (denoted as 1 to 4) of die 501. Thus, using path 540, each region can be tested individually. A region can be any area of ​​the die. For example, a region may be a group of memory blocks (e.g., as in...). Figure 5 (A region can be a single memory bank or a group of other types of circuitry.) In some instances, the region can be determined based on the importance of the on-chip circuitry.

[0101] The control circuit 505 can be located anywhere on the die 501. In some instances, the control circuit 505 can be located where zones converge. For example, the control circuit can be located where zones 1 through 4 meet. Regarding paths containing test circuits (e.g., paths 540-b and 540-c), clock, enable, and status signals can be initiated by the control circuit 505 and routed via signal line 520 along the path from one test circuit to the next, and feedback signals can be returned to the control circuit 505, as referenced. Figures 1 to 4 Discussion. Regarding paths that do not have test circuitry (e.g., paths 540-a and 540-d), control circuitry 505 may be incorporated into the test circuitry system (e.g., regarding...). Figure 3 The circuit system described is used to detect and identify defects along a single signal line 520.

[0102] In some instances, control circuitry 505 can coordinate some or all of the tests in the area. In some instances, some or all of the tests in the area can occur simultaneously. In some instances, control circuitry 505 may include multiple logic units (e.g., test circuitry) that individually control the corresponding path 540.

[0103] In some instances, gaps may exist around the periphery of the die between adjacent paths. For example, a gap may exist between signal line 520-a of path 540-a and signal line 520-h of path 540-d. To avoid potentially overlooking defects in the peripheral gap portion, portions of the adjacent paths at the periphery may be positioned physically close together. For example, portions of signal lines 520-a and 520-h may be positioned even closer together where the signal lines meet at the periphery of the die, such as... Figure 5 As shown in the illustration.

[0104] although Figure 5 Four paths are displayed, but any number of paths can be used. For example, two, four, eight, or sixteen paths can be used. Other numbers of paths can also be used. For each path, any number of signal lines can be used. Similarly, any number of zones can be defined. For example, two, four, eight, or sixteen zones can be defined. Other numbers of zones can also be defined.

[0105] Figure 6 The flowchart illustrates a method 600 for defect detection of a memory device, based on examples disclosed herein. The operation of method 600 can be implemented by a die defect detector as described herein. For example, the operation of method 600 can be implemented by, as referenced... Figures 4 to 5The described die defect detector 400 or die defect detector 500 is executed. In some instances, the memory system may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively or additionally, the memory device may use dedicated hardware to perform aspects of the described functions. Method 600 facilitates the detection and identification of defects along the periphery of the die and within the internal portion of the die.

[0106] Method 600 can be used to detect defects, and various tests can be used to determine the location and severity of defects. In some instances, multiple locations (e.g., areas) on the die can be tested. Reference Figure 5 Zone 1 will be used as an instance of this method.

[0107] At position 605, a first test can be performed on the area in the first direction. For example, as discussed above, the control circuitry can transmit clock, status, and / or enable signals along the path in the first direction (e.g., counterclockwise). As the signals continue to propagate in the first direction, any test circuitry in the path can perform its action. The test circuitry can transmit feedback signals back to the control circuitry along the path in the opposite direction (e.g., clockwise). The control circuitry can determine the presence of defects on the die based on the feedback signals.

[0108] For example, clock, status, and / or enable signals can be transmitted by control circuitry 505 to signal line 520-b on port 555, allowing the signals to travel counterclockwise around path 540-b. Test circuits 510-a and 510-b on path 540-b can perform their actions and send feedback signals back to control circuitry 505 via port 555, as described above. After propagating around path 540-b, other signals can be received by control circuitry 505 from signal line 520-d on port 550. Based on the feedback signals, control circuitry 505 can determine whether die defects exist in the area.

[0109] If the first hardware test indicates that there may be no defect in the area (e.g., the test passed), as indicated at 620, then the method may continue to 635. If the first hardware test indicates that a defect may exist in the area (e.g., the test failed), then the method may continue to 610.

[0110] At 610, a second test can be performed on the area in a second direction. In some cases, the second hardware test may be the same type of test performed in the second direction but using the same path as the first hardware test. In some cases, the second direction may be opposite to the first direction. For example, control circuitry may transmit clock, status, and / or enable signals along the path in the second direction (e.g., clockwise). As the signals continue to propagate in the second direction, any test circuitry in the path may perform its actions. Test circuitry may transmit feedback signals back to the control circuitry along the path in the opposite direction (e.g., counterclockwise). The control circuitry may determine the presence of die defects based on the feedback signals.

[0111] For example, clock, status, and / or enable signals can be transmitted by control circuitry 505 to signal line 520-a on port 550, allowing the signal to travel clockwise around signal line 520-a. Test circuitry on signal line 520-a (if present) can perform its operation and send feedback signals back to control circuitry 505 via port 550, as described above. Other signals can be received by control circuitry 505 from signal line 520-a on port 555. Based on the feedback signals, control circuitry 505 can determine whether defects exist in areas of the die.

[0112] If the second hardware test indicates that there may be no defect in the area (e.g., the test passed), such as at 620, then the method may continue to 635. Therefore, in some cases, if the second hardware test passes at 610, then even if the first hardware test fails at 605, there may be no defect in the area. If the second hardware test indicates that there may be a defect in the area (e.g., the test failed), then both the first and second hardware tests have failed. Therefore, there may be a defect in the area. To determine the location of the defect in the area, the method may continue to 615.

[0113] At 615, a test operation (e.g., a functional memory test) can be performed on the memory in the region. In one case, the test operation may involve writing data (e.g., a data pattern) to one or more memory cells in the region, followed by reading one or more memory cells. The data read from the memory cells can be compared with the data written to the memory cells. If the read data matches the written data, then the memory cell may be error-free, and the test may indicate that the memory has passed the test operation. If the read data does not match the written data (or the expected value of the data), then the memory cell may contain one or more errors, and the test may indicate that the memory has failed the test operation. Other types of test operations may also be used.

[0114] If the test operation indicates that the memory passes, then the defect in the region may not affect the memory and is therefore likely located on the periphery of the region, as shown at 625. In this case, the die is still usable. If the test operation indicates that the memory fails, then the defect in the region may affect the memory and is therefore likely located in the inner part of the region, as indicated at 630. In either case, the method can continue to 635.

[0115] At 635, the overall assessment and corresponding severity of defects can be determined. If the entry point is from 605 or 610 to 635, there may be no defects in the region. If the entry point is from 615 to 635, there may be defects in the region, and depending on the result at 615, the defects may be on the periphery or inner portion of the region. In some instances, the die may contain more than one region. At 635, the overall defects of the die (if present) can be determined based on the defects found in each region. In some instances, defects in other regions can be determined using, for example, one or more of 605, 610, and 615 in a manner similar to that described above.

[0116] In some cases, upon completion of method 600, a message may be sent to the host system, for example. The message may contain information about the defects, such as the number of defects detected, the location of the defects detected on the die, and whether memory cells were affected. In some cases, a message may be sent if a defect is detected on the die after method 600 has completed.

[0117] Figure 7 This describes another example of a segmented digital die defect detector 700 for defect detection of memory devices, based on the examples disclosed herein. The memory device 705 may be as described in the references... Figures 1 to 6 Examples of aspects of the described memory device. Memory device 705 may include a transmitter 710, a receiver 715, a memory operation component 720, an identification component 725, and a comparator 730. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0118] Transmitter 710 can transmit a first clock signal via a signal line in a first direction, the signal line at least partially surrounding a region of a memory cell on the die. In some instances, transmitter 710 can transmit a second clock signal via the signal line in a second direction based on receiving a first feedback signal from the signal line. In some instances, transmitter 710 can transmit a third clock signal via the second signal line in a third direction, the second signal line at least partially surrounding a second region of the memory cell on the die. In some instances, transmitter 710 can transmit a fourth clock signal via the second signal line in a fourth direction based on receiving a third feedback signal from the second signal line.

[0119] Receiver 715 may receive a first feedback signal from the signal line based on the transmission of a first clock signal via the signal line in a first direction. In some instances, receiver 715 may receive a second feedback signal from the signal line based on the transmission of a second clock signal via the signal line in a second direction. In some instances, receiver 715 may receive a third feedback signal from the second signal line based on the transmission of a third clock signal via the second signal line in a third direction. In some instances, receiver 715 may receive a fourth feedback signal from the second signal line based on the transmission of a fourth clock signal via the second signal line in a fourth direction.

[0120] The memory operation component 720 can perform test operations on memory cells of a region of the die based on receiving a second feedback signal from a signal line. In some instances, the memory operation component 720 can write a data pattern to one or more memory cells of the region. In some instances, the memory operation component 720 can read one or more memory cells based on writing a data pattern to one or more memory cells. In some instances, the memory operation component 720 can write a data pattern to one or more memory cells of the region. In some instances, the memory operation component 720 can read one or more memory cells based on writing a data pattern to one or more memory cells. In some instances, the memory operation component 720 can perform a second test operation on memory cells of a second region of the die based on receiving a fourth feedback signal from a second signal line.

[0121] The identification component 725 can identify defects in a region of the die based on a first feedback signal, a second feedback signal, a test operation, or any combination thereof. In some instances, the identification component 725 can determine that a defect has occurred in a region of the die based on the first feedback signal. In some instances, the identification component 725 can determine that a defect has occurred in a region of the die based on a second feedback signal. In some instances, the identification component 725 can identify a second defect in a second region of the die based on a third feedback signal, a fourth feedback signal, or performing a second test operation, or any combination thereof.

[0122] Comparator 730 can determine that a memory cell in a region contains one or more errors based on reading one or more memory cells, wherein identifying defects in the region is based on determining that the memory cell in the region contains said one or more errors. In some instances, comparator 730 can compare data read from one or more memory cells with data patterns written to one or more memory cells, wherein determining that the memory cell in a region contains one or more errors is based on said comparison. In some instances, comparator 730 can determine that the memory cell in a region does not contain errors based on reading one or more memory cells.

[0123] Figure 8The flowchart illustrates a method 800 for defect detection of a memory device, based on examples disclosed herein. Operation of method 800 can be implemented using a memory device or its components as described herein. For example, operation of method 800 can be achieved using references... Figures 1 to 6 The described memory device is used to perform the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively or additionally, the memory device may use dedicated hardware to perform aspects of the described function.

[0124] At 805, the memory device can transmit a first clock signal in a first direction via signal lines, said signal lines at least partially surrounding a region of the memory cell on the die. Operation 805 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 7 The described transmitter is used to perform operation 805.

[0125] At 810, the memory device can receive a first feedback signal from the signal line based on the transmission of a first clock signal via the signal line in a first direction. Operation 810 can be performed according to the method described herein. In some instances, aspects of operation 810 can be derived from, as referenced... Figure 7 The receiver described is used to perform this action.

[0126] At point 815, the memory device may transmit a second clock signal in a second direction via the signal line based on receiving a first feedback signal from the signal line. Operation 815 may be performed according to the method described herein. In some instances, aspects of operation 815 may be as described in reference... Figure 7 The described transmitter is used to perform this.

[0127] At 820, the memory device can receive a second feedback signal from the signal line based on the transmission of a second clock signal via the signal line in a second direction. Operation 820 can be performed according to the method described herein. In some instances, aspects of operation 820 can be derived from, as referenced... Figure 7 The receiver described is used to perform this action.

[0128] At 825, the memory device can perform a test operation on the memory cells of a region of the die based on receiving a second feedback signal from the signal line. Operation 825 can be performed according to the method described herein. In some instances, aspects of operation 825 can be performed by a memory operation component, as referenced... Figure 7 describe.

[0129] At 830, the memory device can identify defects in a region of the die based on a first feedback signal, a second feedback signal, a test operation, or any combination thereof. Operation 830 can be performed according to the methods described herein. In some instances, aspects of operation 830 can be derived from, as referenced... Figure 7The described identification component is used to perform this.

[0130] In some instances, the device described herein can perform, for example, the method of method 800. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transmitting a first clock signal via a signal line in a first direction, the signal line at least partially surrounding a region of a memory cell of a die; receiving a first feedback signal from the signal line based on transmitting the first clock signal via the signal line in the first direction; transmitting a second clock signal via the signal line in a second direction based on receiving the first feedback signal from the signal line; receiving a second feedback signal from the signal line based on transmitting the second clock signal via the signal line in the second direction; performing a test operation on the memory cell of the region of the die based on receiving the second feedback signal from the signal line; and identifying defects in the region of the die based on the first feedback signal, the second feedback signal, or the test operation, or any combination thereof.

[0131] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for determining, based on a first feedback signal, that a defect may have occurred in an area of ​​the die.

[0132] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for determining, based on a second feedback signal, that a defect may have occurred in an area of ​​the die.

[0133] In some instances of the method 800 and apparatus described herein, performing a test operation may include operations, features, components, or instructions for: writing a data pattern to one or more memory cells in the region; reading the one or more memory cells based on writing the data pattern to the one or more memory cells; and determining, based on reading the one or more memory cells, that the memory cells in the region contain one or more errors, wherein identifying the defects in the region may be based on determining that the memory cells in the region contain the one or more errors.

[0134] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for comparing data read from the one or more memory cells with data patterns written to the one or more memory cells, wherein determining that the memory cell containing the one or more errors may be based on the comparison.

[0135] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: writing a data pattern to one or more memory cells in the region; reading the one or more memory cells based on writing the data pattern to the one or more memory cells; and determining, based on reading the one or more memory cells, that the memory cells in the region may be free of errors.

[0136] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: transmitting a third clock signal in a third direction via a second signal line, the second signal line at least partially surrounding a second region of a memory cell of the die; receiving a third feedback signal from the second signal line based on the transmission of the third clock signal in the third direction via the second signal line; transmitting a fourth clock signal in a fourth direction via the second signal line based on receiving the third feedback signal from the second signal line; receiving a fourth feedback signal from the second signal line based on the transmission of the fourth clock signal in the fourth direction via the second signal line; performing a second test operation on the memory cell of the second region of the die based on receiving the fourth feedback signal from the second signal line; and identifying a second defect in the second region of the die based on the third feedback signal, the fourth feedback signal, or the performance of the second test operation, or any combination thereof.

[0137] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions of two or more of the methods may be combined.

[0138] An apparatus is described. The apparatus may include a first signal line extending through a portion of a die and separating a first memory bank from a second memory bank of the die; a second signal line including a portion extending at least partially adjacent to the perimeter of the die; a test circuit coupled to the first and second signal lines, the test circuit being configured to generate a first feedback signal based on a first condition of the first signal line and a second feedback signal based on a second condition of the second signal line; and a control circuit coupled to the first and second signal lines, the control circuit being configured to transmit a clock signal to the test circuit and receive the first and second feedback signals based on the transmission of the clock signal.

[0139] In some instances, the first state of the first signal line may indicate the presence of a defect in the die and the absence of the defect in the die; and the first feedback signal may include a first state indicating the presence of the defect or a second state indicating the absence of the defect.

[0140] In some instances, the control circuitry may be configured to identify defects in the die based on the first feedback signal and the second feedback signal. In some instances, the control circuitry may be configured to identify defects in internal portions of the die based at least in part on the first feedback signal, and the control circuitry may be configured to identify defects adjacent to the periphery of the die based at least in part on the second feedback signal.

[0141] In some instances, the control circuitry may be configured to identify defects in the portion of the die that separates the first memory bank from the second memory bank, based on the first feedback signal.

[0142] In some instances, the test circuit may include operations, features, components, or instructions for a first test circuit and a second test circuit, the first test circuit being coupled to the first signal line and configured to generate the first feedback signal based on the first condition of the first signal line, and the second test circuit being coupled to the second signal line and configured to generate a second feedback signal based on the second condition of the second signal line.

[0143] Some examples may further include isolating the first signal line from the second signal line based on the clock signal, and generating the first feedback signal based on isolating the first signal line from the second signal line.

[0144] In some instances, the control circuit may be configured to transmit the clock signal in a first direction via the first signal line, and the test circuit may be configured to transmit the first feedback signal in a second direction via the first signal line, wherein the second direction is different from the first direction.

[0145] In some instances, the clock signal and the first feedback signal can be transmitted simultaneously.

[0146] An apparatus is described. The apparatus may include a set of signal lines, including a first signal line and a second signal line, the first signal line at least partially surrounding a first set of memory cells on a die, and the second signal line surrounding a second set of memory cells on the die; and control circuitry coupled to the set of signal lines, the control circuitry being configured to transmit a clock signal through the first signal line and the second signal line, and to receive a first feedback signal based on a first state of the first signal line and a second feedback signal based on a second state of the second signal line based on the transmission of the clock signal.

[0147] Some instances of the device may include a first region containing the first set of memory cells, wherein the first signal line may at least partially surround the first region; and a second region containing the second set of memory cells, wherein the second signal line may at least partially surround the second region.

[0148] In some instances, the first signal line may be at least partially adjacent to the periphery of the die and at least partially extended by a portion of the die separating the first region from the second region.

[0149] In some instances, the group of signal lines may contain two, four, eight, or sixteen signal lines.

[0150] In some instances, the control circuit may be configured to transmit the clock signal in a first direction via the first signal line and in a second direction via the first signal line.

[0151] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, wherein the bus may have various bit widths.

[0152] The terms “electronic connectivity,” “conductive contact,” “connection,” and “coupling” refer to the relationship between components that support signal flow between them. Components are considered electronically connected (or electrically contacted, connected, or coupled) to each other if there is any conductive path between them that can support signal flow at any given time. At any given time, the conductive path between electronically connected (or electrically contacted, connected, or coupled) components can be open or closed, depending on the operation of the device that may include the connected components. The conductive path between connected components can be a direct conductive path between the components or an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0153] The term "coupling" refers to a change from an open-circuit relationship between components (where signals cannot currently be transmitted between components via conductive paths) to a closed-circuit relationship between components (where signals can be transmitted between components via conductive paths). When a component, such as a controller, couples other components together, the component triggers a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0154] The term "isolation" as used in this article refers to a relationship between components in which signals are currently unable to flow between them. If there is an open circuit between components, then they are isolated from each other. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from each other. When a controller isolates two components, the controller causes a change that prevents signals from flowing between the components using the conductive paths that previously allowed signal flow.

[0155] As used herein, the term "layer" or "level" refers to a hierarchical or sheet-like geometric structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0156] As used in this article, the term “generally” means that the modified characteristic (e.g., a verb or adjective modified by the term “generally”) does not need to be absolute, but is close enough to achieve the advantage of the characteristic.

[0157] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or substrate subregions can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0158] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degraded) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0159] The exemplary configurations described herein, in conjunction with the accompanying drawings, do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous over other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concept of the described instances.

[0160] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a dash after the reference numeral and a second numeral to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, without regard to the second reference numeral.

[0161] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, including portions distributed such that the functions are implemented at different physical locations.

[0162] For example, the various illustrative blocks and modules described herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternative examples, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0163] As used herein, the word "or," included in the claims, or used in a list of items (e.g., a list of items preceded by phrases such as "at least one of" or "one or more of"), indicates that the list includes items such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an instance step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "at least partially based on".

[0164] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is consistent with the broadest scope of the principles and novel features disclosed herein.

Claims

1. A memory device comprising: A first signal line extends through an internal portion of the die and separates the first memory bank of the die from the second memory bank, wherein the first signal line couples the control circuitry to the test circuitry and includes; The first segment is located between the first group of memory storage and the second group of memory storage. The second segment is located between the second group of memory storage and the third group of memory storage. The third segment is located between the third group of memory storage and the fourth group of memory storage. The fourth segment is located between the fourth group of memory storage and the first group of memory storage; The second signal line includes at least a portion that extends adjacent to the periphery of the bare die; The test circuit is coupled to the first signal line and the second signal line. The test circuit is configured to generate a first feedback signal based at least in part on a first condition of the first signal line and a second feedback signal based at least in part on a second condition of the second signal line. The first feedback signal indicates a die defect state of the internal portion of the die coupled to the first signal line. and The control circuit is coupled to the first signal line and the second signal line, and is configured to transmit a clock signal to the test circuit and to receive the first feedback signal and the second feedback signal at least in part based on the transmission of the clock signal.

2. The memory device according to claim 1, wherein: The first condition of the first signal line indicates the presence or absence of a defect in the die; and The first feedback signal includes a first state indicating the presence of the defect or a second state indicating the absence of the defect.

3. The memory device of claim 1, wherein the control circuitry is configured to identify die defects in the internal portion of the die based at least in part on the first feedback signal, and the control circuitry is configured to identify die defects adjacent to the periphery of the die based at least in part on the second feedback signal.

4. The memory device of claim 1, wherein the control circuitry is configured to identify die defects in a portion of the die separating the first memory bank from the second memory bank, based at least in part on the first feedback signal.

5. The memory device according to claim 1, further comprising: A second test circuit is coupled to the second signal line and configured to generate a third feedback signal at least in part based on the second condition of the second signal line, wherein the test circuit is configured to obtain the third feedback signal from the second test circuit and generate the second feedback signal at least in part based on the third feedback signal.

6. The memory device of claim 5, wherein the test circuit is further configured to: The first signal line is isolated from the second signal line at least in part based on the clock signal; and The first feedback signal is generated at least in part by isolating the first signal line from the second signal line.

7. The memory device according to claim 1, wherein: The control circuit is configured to transmit the clock signal in a first direction via the first signal line; and The test circuit is configured to transmit the first feedback signal in a second direction via the first signal line, and the second direction is different from the first direction.

8. The memory device according to claim 1, wherein the clock signal and the first feedback signal are transmitted simultaneously.

Images