Semiconductor package structure

Abstract

This invention relates to a semiconductor packaging structure, comprising: a substrate having a core layer; a top transformer and a bottom transformer located on opposite sides of the core layer; and a first connector connecting the top transformer and the bottom transformer. Each of the top transformer and the bottom transformer consists of two interleaved and spaced coils.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure. Background Technology

[0002] A transformer is an electronic device that converts electrical energy from one circuit to another via induction coils. The time-varying current in the primary coil of the induction coil generates a time-varying magnetic field within the transformer's coils. This magnetic field then induces a time-varying voltage or electromotive force in the secondary coil; this effect is called mutual inductance. If the secondary coil is connected to a load, it will generate current, and electrical energy will be transferred from the primary coil to the load. In an ideal transformer, the induced voltage V in the secondary coil is... s It will be related to the voltage V of the primary coil p They are directly proportional, and the ratio will be equal to the number of turns N of the secondary coil. s With the number of turns N of the primary coil p The ratio of N s >N p This allows the voltage of alternating current to gradually increase; if N s <N p This allows the voltage of alternating current to gradually decrease.

[0003] refer to Figure 1A As shown, in a typical 48V system, depending on the voltage requirements, the 48V voltage may need to be changed by multiple transformers 14 before the signal enters the package structure 30. For example... Figure 1B As shown, the 48V voltage is first regulated by voltage regulator 12, and then stepped down to 1V by transformer 14, with a corresponding current of 240A. Combined with... Figure 1A and Figure 1B The transformer 14 is located outside the package structure 30 and is also mounted on the printed circuit board (PCB) 20 along with the package structure 30. The regulated 48V voltage is converted by the transformer 14 to the voltage required by the SoC on the package structure 30, such as 1V, before entering the package structure 30 to perform related electrical operations. However, the path of the voltage signal from the transformer 14 to the package structure 30 on the PCB 20 is too long, which will lead to a decrease in the power quality of the overall package structure and voltage instability. Summary of the Invention

[0004] To address the aforementioned problems in related technologies, this invention proposes a semiconductor packaging structure that can shorten the signal transmission path and improve energy consumption.

[0005] According to an embodiment of the present invention, a semiconductor package structure is provided. The semiconductor package structure includes: a substrate having a core layer; a top transformer and a bottom transformer located on opposite sides of the core layer; and a first connector connecting the top transformer and the bottom transformer. Each of the top transformer and the bottom transformer consists of two interleaved and spaced coils.

[0006] In some embodiments, the substrate has a first surface and a second surface opposite to each other, with the top transformer adjacent to the first surface and the bottom transformer adjacent to the second surface.

[0007] In some embodiments, the top transformer or the bottom transformer also includes a magnetic core.

[0008] In some embodiments, the magnetic core is surrounded by two coils.

[0009] In some embodiments, the two coils are wound around an axis parallel to the core layer.

[0010] In some embodiments, the two coils are wound around an axis perpendicular to the core layer.

[0011] In some embodiments, the first connector includes a through-hole located in the substrate.

[0012] In some embodiments, the semiconductor package structure further includes: a die located on a first surface of the substrate; and an external connector located on a second surface of the substrate.

[0013] In some embodiments, the semiconductor package structure further includes a second connector, through which the bottom transformer is electrically connected to an external connector.

[0014] In some embodiments, the second connector includes a through-hole located in the substrate.

[0015] In some embodiments, the semiconductor package structure further includes a third connector, through which the top transformer is electrically connected to the die.

[0016] In some embodiments, the third connector includes a through-hole located in the substrate.

[0017] In some embodiments, the die has a bump connector on a first surface adjacent to the substrate, and the top transformer is electrically connected to the bump connector via a third connector.

[0018] In some embodiments, the external connector is connected to a power source outside the semiconductor package structure.

[0019] In some embodiments, the bottom transformer reduces the voltage from the power supply to a first voltage.

[0020] In some embodiments, the top transformer reduces the first voltage to a second voltage.

[0021] In some embodiments, the external connector is a solder ball.

[0022] In some embodiments, the bottom transformer is positioned opposite the top transformer. Attached Figure Description

[0023] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0024] Figure 1A This is a schematic diagram of using an external power source to power the package structure in existing technology.

[0025] Figure 1B This is a schematic diagram of the processing of external power in existing technology.

[0026] Figure 2 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention. Specific Implementation

[0027] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0028] Figure 2 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention. Figure 2As shown, the semiconductor package structure 100 includes a substrate 110, in which a core layer 115 is present. The semiconductor package structure 100 also includes a top transformer 124, a bottom transformer 122, and a first connector 126. The top transformer 124 and the bottom transformer 122 are located on opposite sides of the core layer 115. The top transformer 124 may consist of two interleaved coils 1242 and 1244, which are separated from each other without actual physical contact. The bottom transformer 122 may consist of two interleaved coils 1222 and 1224, which are separated from each other without actual physical contact. The first connector 126 connects the top transformer 124 and the bottom transformer 122. Specifically, one of the first connectors 126 connects a coil 1222 of the bottom transformer 122 to a coil 1242 of the top transformer 124, and the other of the first connectors 126 connects another coil 1224 of the bottom transformer 122 to another coil 1244 of the top transformer 124.

[0029] The semiconductor package structure 100 provided by the present invention effectively integrates transformers 122 and 124 into the package structure by forming a top transformer 124 and a bottom transformer 122 within the substrate 110, which can shorten the signal transmission path and significantly improve energy consumption. Furthermore, by distributing the top transformer 124 and the bottom transformer 122 on opposite sides of the core layer 115 of the substrate 110, the two transformers 122 and 124 will not interfere with each other when their respective coils are coupled.

[0030] On opposite sides of the core layer 115, the substrate 110 has a first surface 111 and a second surface 112. The first surface 111 may be the front side of the substrate 110, and the second surface 112 may be the back side of the substrate 110. The top transformer 124 and the bottom transformer 122 may be disposed adjacent to the first surface 111 and the second surface 112, respectively. The bottom transformer 122 is disposed opposite to the top transformer 124, that is, the area where the bottom transformer 122 is disposed is approximately aligned with the area where the top transformer 124 is disposed in the vertical direction.

[0031] In some embodiments, the coils 1242, 1244 constituting the top transformer 124 and the coils 1222, 1224 constituting the bottom transformer 122 can be formed using a circuit layer (metal layer, such as a copper layer) within the substrate 110. The first connector 126 can be formed by a through-hole in the substrate 110; in other words, the coils 1242, 1244 of the top transformer 124 and the coils 1222, 1224 of the bottom transformer 122 can be interconnected via the through-hole in the substrate 110.

[0032] The bottom transformer 122 also includes a magnetic core 1226 made of magnetic material, and the top transformer 124 may further include a magnetic core 1246 made of magnetic material. The magnetic cores 1226 and 1246 can be used to enhance magnetic conductivity. Core 1226 is surrounded by two corresponding coils 1222 and 1224, and core 1246 is surrounded by two corresponding coils 1242 and 1244. The two coils 1222 and 1224 and the two coils 1242 and 1244 are each wound around an axis. In the illustrated embodiment, the axis around which coils 1222 and 1224 are wound is parallel to the core layer 115, and the axis around which coils 1242 and 1244 are wound is parallel to the core layer 115. In other embodiments, the axes around which the two coils of the two transformers are wound may be configured to be perpendicular to the core layer.

[0033] An external connector 132 is provided on the second surface 112 of the substrate 110. The external connector 132 may be a solder ball. A second connector 128 is provided between the bottom transformer 122 and the external connector 132. The second connector 128 may include a through hole located in the substrate 110. The two coils 1222 and 1224 in the bottom transformer 122 are each electrically connected to the external connector 132 through a second connector 128.

[0034] A die 140 is disposed on the first surface 111 of the substrate 110. In some embodiments, the die 140 is a system-on-a-chip (SoC), or it may be other types of dies. A top transformer 124 is located below the die 140. The bottom surface of the die 140 is adjacent to the first surface 111 of the substrate 110, and the bottom surface of the die 140 has a bump connector 134, such as a solder ball. A third connector 129 is disposed between the bump connector 134 of the die 140 and the top transformer 124. The third connector 129 may include a through-hole located in the substrate 110. The coils 1242 and 1244 in the top transformer 124 may be electrically connected to the bump connector 134 of the die 140 through a third connector 129, respectively. In this way, the coil structures of the top transformer 124 and the bottom transformer 122 can be electrically connected to the die 140 above the substrate 110 and the external connector 132 below the substrate 110 respectively through the through holes in the substrate 110.

[0035] External connector 132 connects to a power source outside the semiconductor package structure 100. In some embodiments, the external power source and the semiconductor package structure 100 can be mounted on a PCB, and the voltage of the power source can be transmitted to the semiconductor package structure 100 via the PCB and received by the external connector 132 of the semiconductor package structure 100. Bottom transformer 122 reduces the voltage from the power source to a first voltage lower than the power source voltage. The stepped-down first voltage is transmitted to top transformer 124 via first connector 126. Top transformer 124 can then reduce the first voltage to a second voltage lower than the first voltage. In one example, the external power supply can have a voltage of 48V. When the 48V voltage enters the semiconductor package structure 100 via the PCB from the external connector 132 (solder ball), the bottom transformer 122 near the external connector 132 first steps down the 48V voltage to 5V (first voltage). The 5V voltage is then transmitted via the first connector 126 (e.g., a via in the substrate 110) to the top transformer 124 near the die 140. The top transformer 124 steps down the 5V voltage to 1V (second voltage), thereby providing the required voltage for the operation of the die 140. Because the 48V is first stepped down to 5V before being transmitted via the via in the substrate 110, compared to the conventional transmission of the stepped-down 1V voltage in the package structure, the 5V voltage is higher, resulting in a smaller current. Therefore, less power is consumed during transmission.

[0036] In summary, the semiconductor packaging structure provided by this invention mainly utilizes the circuit layer (such as the copper layer) of the substrate to prepare the upper and lower coil structures, and combines them with a magnetic core to form a top transformer and a bottom transformer within the substrate. This effectively integrates the transformer into the packaging structure, shortens the signal transmission path, and significantly improves energy consumption.

[0037] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor packaging structure, characterized in that, include: The substrate has a core layer; A top transformer and a bottom transformer are located on opposite sides of the core layer. The substrate has opposite first and second surfaces, with the top transformer adjacent to the first surface and the bottom transformer adjacent to the second surface. The first connector connects the top transformer and the bottom transformer; Each of the top transformer and the bottom transformer consists of two interleaved and spaced coils. A die, located on the first surface of the substrate; An external connector is located on the second surface of the substrate and is connected to a power source outside the semiconductor package structure. The second connector is used to electrically connect the bottom transformer to the external connector. The third connector is used to electrically connect the top transformer to the core.

2. The semiconductor packaging structure according to claim 1, characterized in that, The top transformer or the bottom transformer also includes a magnetic core.

3. The semiconductor packaging structure according to claim 2, characterized in that, The magnetic core is surrounded by the two coils.

4. The semiconductor packaging structure according to claim 1, characterized in that, The two coils are wound around an axis parallel to the core layer.

5. The semiconductor packaging structure according to claim 1, characterized in that, The two coils are wound around an axis perpendicular to the core layer.

6. The semiconductor packaging structure according to claim 1, characterized in that, The first connector includes a through hole located in the substrate.

7. The semiconductor packaging structure according to claim 1, characterized in that, The second connector includes a through hole located in the substrate.

8. The semiconductor packaging structure according to claim 1, characterized in that, The third connector includes a through hole located in the substrate.

9. The semiconductor packaging structure according to claim 1, characterized in that, The die has a bump connector on a first surface adjacent to the substrate, and the top transformer is electrically connected to the bump connector via the third connector.

10. The semiconductor packaging structure according to claim 1, characterized in that, The bottom transformer reduces the voltage from the power source to a first voltage.

11. The semiconductor packaging structure according to claim 10, characterized in that, The top transformer reduces the first voltage to the second voltage.

12. The semiconductor packaging structure according to claim 1, characterized in that, The external connector is a solder ball.

13. The semiconductor packaging structure according to claim 1, characterized in that, The bottom transformer is positioned opposite to the top transformer.

Images