Analog signal repair circuit and repair method

Abstract

The application provides a repair circuit and a repair method of an analog signal. The repair circuit comprises a shift register, a plurality of patch units, a first input end of each of the plurality of patch units is connected to a signal line of an input signal, a second input end of each of the patch units is connected to the shift register, the shift register is used for inputting a negated signal into a corresponding patch unit according to a shift signal, a third input end of each of the patch units is used for inputting an enable signal, and the patch unit is used for controlling whether to negate the input signal according to the enable signal and the negated signal. Thus, the polarity correction of input and output signals between analog and digital in a digital-analog hybrid chip is realized.

Description

Analog signal repair circuit and repair method Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a circuit and method for repairing analog signals. Background Technology

[0002] In mixed-signal integrated circuit design, the connection of mixed-signal interfaces is very prone to errors. Especially during the startup (POR) process of a mixed-signal chip, incorrect signal polarity may cause the chip's power supply, clock, and other components to fail to start properly. Summary of the Invention

[0003] This application provides an analog signal repair circuit for correcting the polarity of input and output signals between analog and digital signals.

[0004] This application provides an analog signal repair circuit, including:

[0005] Shift register;

[0006] Multiple patch units are provided, with their first input terminals connected one-to-one to the signal lines of multiple input signals; the second input terminal of each patch unit is connected to the shift register, which is used to input the inverted signal into the corresponding patch unit according to the shift signal.

[0007] The third input terminal of each patch unit is used to input an enable signal; the patch unit is used to control whether to invert the input signal according to the enable signal and the invert signal.

[0008] In one embodiment, the patching unit includes:

[0009] An AND gate, one input of which is used to input an enable signal, and the other input of which is connected to the shift register to input an inverted signal;

[0010] An XOR gate is used, with one input connected to the output of an AND gate and the other input connected to a signal line to receive the input signal; the output of the XOR gate is used to output the repaired output signal.

[0011] In one embodiment, the shift register and the plurality of patch units constitute a patch module;

[0012] All input signal lines are divided into several groups, and each group is connected to at least one patch module.

[0013] In one embodiment, multiple signal lines of the same functional module are distributed into multiple groups, and multiple patch modules corresponding to the multiple groups correct the input signals of the multiple signal lines of the same functional module.

[0014] In one embodiment, each group connects multiple patch modules, and the multiple patch modules are cascaded, with the input signal being input to the next patch module after one patch module has finished processing it.

[0015] In one embodiment, the repair circuit further includes:

[0016] The first register is connected to the shift register and the patch unit;

[0017] The read circuit is connected to the first register and is used to load the stored shift signal and enable signal into the first register, provide the shift signal to the shift register through the first register, and provide the enable signal to the patch unit.

[0018] In one embodiment, the repair circuit further includes:

[0019] The second register is used to store an indication signal as to whether the patch unit is enabled in sleep mode;

[0020] The second AND gate has one input terminal for inputting a sleep signal and the other input terminal connected to the second register for inputting the indication signal;

[0021] The OR gate has one input terminal for inputting an enable signal and the other input terminal connected to the output terminal of the second AND gate. The output terminal of the OR gate is connected to the third input terminal of the patch unit, and the updated enable signal is input to the third input terminal of the patch unit.

[0022] This application embodiment also provides a method for repairing analog signals, the method being applied to the aforementioned analog signal repair circuit, the method comprising:

[0023] For each signal line, the enable signal and the inverted signal corresponding to the signal line are ANDed to obtain the repair signal;

[0024] The input signal of the signal line is XORed with the repair signal to obtain the repaired output signal.

[0025] In one embodiment, the method further includes:

[0026] The signal lines of all input signals are divided into several groups, and multiple signal lines of the same functional module are distributed into multiple groups; each group is connected to at least one patch module; the shift register and multiple patch units constitute a patch module;

[0027] The input signals of multiple signal lines of the same functional module are corrected by multiple patch modules corresponding to multiple groups.

[0028] In one embodiment, the repair circuit further includes: a first register connected to the shift register and the patch unit; and a read circuit connected to the first register. The method further includes:

[0029] The stored shift signal and enable signal are loaded into the first register by the read circuit;

[0030] The first register provides a shift signal to the shift register and an enable signal to the patch unit.

[0031] The technical solution provided in the above embodiments of this application can connect patch units to each signal line of the input signal. Multiple patch units can determine whether to invert the input signal based on the enable signal and the invert signal passing through the shift register, thereby realizing polarity correction of the input and output signals between analog and digital signals in the mixed-signal chip. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly described below.

[0033] Figure 1 is a schematic diagram of an analog signal repair circuit provided in an embodiment of this application;

[0034] Figure 2 is a schematic diagram illustrating the principle of grouping and interleaving input signals according to an embodiment of this application;

[0035] Figure 3 is a schematic diagram illustrating the principle of multiple cascaded patch modules provided in an embodiment of this application;

[0036] Figure 4 is a schematic diagram of an analog signal repair circuit provided in another embodiment of this application;

[0037] Figure 5 is a schematic diagram of an analog signal repair circuit provided in another embodiment of this application. Detailed Implementation

[0038] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0039] Similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0040] Figure 1 is a schematic diagram of an analog signal repair circuit provided in an embodiment of this application. As shown in Figure 1, the repair circuit includes a shift register 10 and multiple patching units 20.

[0041] The first input terminals of the multiple patch units 20 are connected one-to-one to the signal lines of multiple input signals; the second input terminal of each patch unit 20 is connected to the shift register 10, which is used to input the inverted signal into the corresponding patch unit 20 according to the shift signal.

[0042] The third input terminal of each patch unit 20 is used to input an enable signal. The patch unit 20 is used to control whether to invert the input signal according to the enable signal and the invert signal.

[0043] For example, the input signal of a signal line may be 0 or 1. The patch unit 20 can invert the input signal under the action of an enable signal and an invert signal, for example, when both the enable signal and the invert signal are 1, changing the original 1 to 0 and the original 0 to 1. One signal line can be connected to one patch unit 20.

[0044] In one embodiment, as shown in FIG1, each patch unit 20 includes an AND gate and an XOR gate.

[0045] One input of the AND gate (i.e., the third input of patch unit 20) is used to input an enable signal, and the other input of the AND gate (i.e., the second input of patch unit 20) is connected to the shift register 10 to input an inverted signal. One input of the XOR gate is connected to the output of the AND gate, and the other input of the XOR gate (i.e., the first input of patch unit 20) is connected to a signal line to receive the input signal; the output of the XOR gate is used to output the output signal after the input signal is repaired.

[0046] The specific description is as follows. For any input signal wire_in, its output signal wire_out can be expressed as follows: Wire_out = wire_in ^ patch_point. "^" represents exclusive OR. If patch_point = 1, then wire_out is the inversion of the wire_in signal; otherwise, wire_out is the same as wire_in, thereby achieving the repair of the input signal. Therefore, the patch unit 20 can generate patch_point (repair signal), and after performing an exclusive OR operation with the input signal, the repaired output signal wire_out is output.

[0047] For example, when wire_in is equal to 1, patch_point = 1, Wire_out = 0; when wire_in is equal to 0, patch_point = 1, Wire_out = 1, thereby achieving signal inversion. When wire_in is equal to 1, patch_point = 0, Wire_out = 1; when wire_in is equal to 0, patch_point = 0, Wire_out = 0, and the input signal and the output signal are the same.

[0048] As shown in Figure 1, taking a group of 32-bit wire_in (input signal) as an example, assuming that a certain root signal line in the wire_in group needs to be inverted and other inputs remain unchanged, then it is required that a certain bit in patch_point is 1 and other bits are 0. This embodiment of the present application uses a shift register 10 to achieve this:

[0049] The output signal of the shift register 10 is wire_inv_shift_out[31:0] = {31’h0,1’h1} << wire_inv_sel[4:0]. In this way, only a 5-bit variable wire_inv_sel[4:0] (i.e., the shift signal) can shift 1 (inversion signal) to any position of the 32 inputs.

[0050] Adding an enable signal to each bit of the output signal of the shift register 10, the 32-bit repair signal Patch_point[31:0] = path_en[31:0] & wire_inv_shift_out[31:0]; finally, the logic implemented by the circuit shown in Figure 1 can be: Wire_out = wire_in ^ (path_en[31:0] & ({31’h0,1’h >> wire_inv_sel[4:0]))).

[0051] In one embodiment, the shift register 10 shown in Figure 1 and the plurality of patch units 20 constitute a patch module. Since the actual input signal is often more than 32 bits, a grouping technique can be used to divide the signal lines of all input signals into several groups, with each group connected to at least one patch module. For example, an N-bit analog input signal can be grouped into M groups, each group containing N / M connections. Generally, N / M is a power of 2, such as 16, 32, 64, etc. By inserting a patch module into each group of connections, the independent polarity correction within each group of connections is completed. It should be noted that if N is not an integer power of M, the high bits of N can be padded to make up the difference.

[0052] In one embodiment, interleaving technology can be used to distribute multiple signal lines of the same functional module into multiple groups, and multiple patch modules corresponding to multiple groups can correct the input signals of multiple signal lines of the same functional module.

[0053] It's important to note that in actual mixed-signal design, the probability of polarity errors is very small; usually, only one or a few lines have incorrect polarity, or there's a need for later modification. Furthermore, such signals are generally concentrated within a single module. In this case, besides choosing a larger N / M ratio to reduce the number of patch modules, interleaving can be used. Analog input signals can be grouped and shuffled according to functional modules, and interleaving distributes signals from the same functional module across different groups. Although there are only M patch modules, when signals from a single functional module experience concentrated errors or require polarity modification, the problem can be distributed across multiple patch modules for processing, fully utilizing the capabilities of these M patch modules.

[0054] As shown in Figure 2, the functional modules can include USB (Universal Serial Bus), DC-DC (Digital-to-DC Converter), RF (Radio Frequency Module), etc. The input signals of these functional modules can consist of N bits, with N signal lines divided into M groups. The signal lines of the same functional module are distributed across different groups, and each group connects to one patch module. As shown in Figure 2, repair can be performed using N patch modules. The repaired output signal of the USB functional module is transmitted to the USB controller, the repaired output signal of the DC-DC functional module is transmitted to the DC-DC controller, and the repaired output signal of the RF functional module is transmitted to the DC-DC controller.

[0055] In one embodiment, each group connects multiple patch modules, and the multiple patch modules are cascaded, with the input signal being input to the next patch module after one patch module has finished processing it.

[0056] In other words, a group can be not limited to a single patch module; multiple patch modules can be cascaded to support the repair of multiple signals by a single group. The signal delay introduced by each patch module is an XOR gate, which can be ignored. As shown in Figure 3, Wire_out1 = wire_in^patch_point1; Wire_out2 = wire_out1^patch_point2. A group can be a 31-bit input signal, with the output signal processed by the first patch module serving as the input signal for the second patch module.

[0057] In one embodiment, as shown in FIG4, the repair circuit provided in this application embodiment may further include: a first register 40 and a read circuit 30. The first register 40 is connected to the shift register 10 and the patch unit 20; the read circuit 30 is connected to the first register 40. The read circuit 30 is used to load the stored shift signal and enable signal into the first register 40, and to provide the shift signal to the shift register 10 and the enable signal to the patch unit 20 through the first register 40.

[0058] It should be noted that the most dangerous part of the chip's POR (Startup) phase is the mixed-signal circuit startup phase. During this phase, most digital circuits are not yet operational, software cannot intervene, or the code executed is in ROMCode (Read-Only Memory Code) and cannot be modified. Therefore, the chip's built-in OTP (OTP is a type of memory in a microcontroller) (such as efuse one-time programmable memory) can be used for analog signal repair. During the POR phase, a POR read circuit (30) can automatically load efuse data (i.e., the data stored in efuse) into a set of registers, referred to as the first register 40 for distinction. This set of registers directly controls the patch_en signal (enable signal) and the wire_inv_sel signal (shift signal). Thus, after chip startup, efuse data can be automatically loaded into the first register 40, which provides a shift signal to the shift register 10 and an enable signal to the patch unit 20, thereby completing the repair of the specified signal. The read circuit 30 can be an existing data readout circuit used to read data from memory.

[0059] In one embodiment, as shown in FIG5, the repair circuit provided in this application embodiment may further include: a second register 50, an AND gate 60 (referred to as the second AND gate 60 to distinguish it from the AND gate in the patch unit 20 above), and an OR gate 70.

[0060] The second register 50 stores an indication signal indicating whether the patch unit 20 is enabled in sleep mode. One input of the second AND gate 60 is used to input the sleep signal, and the other input is connected to the second register 50 to input the indication signal. One input of the OR gate 70 is used to input an enable signal, and the other input is connected to the output of the second AND gate 60. The output of the OR gate 70 is connected to the third input of the patch unit 20, inputting an updated enable signal to the third input of the patch unit 20.

[0061] It's important to note that if the circuit already supports inverting the input signal of a certain signal line, the `wire_inv_sel` signal (shift signal) can be pre-configured, and the polarity of the output signal can be switched by toggling the `patch_en` signal (enable signal). For example, a low-power chip often has an extremely low-power "sleep" mode, which is usually indicated by a `chip_sleep` mode, corresponding to several sets of low-power settings. The `chip_sleep` signal can be used to switch these low-power settings, thereby automatically shutting down certain modules or putting these modules into low-power mode. However, pre-configuring low-power modes has drawbacks: some considerations may be insufficient, and some signals may not have corresponding low-power configurations in low-power mode.

[0062] Therefore, the chip_sleep signal can be used to control patch_en, thus solving this problem universally: Patch_en_all = patch_en | (chip_sleep & chip_sleep_path_en).

[0063] Here, "&" represents the "AND" operation, and "|" represents the "OR" operation. chip_sleep_path_en is a pre-configured register (i.e., the second register 50) used to indicate whether a patch unit 20 is automatically turned on when chip_sleep=1.

[0064] For example, for a 4-bit input signal, assuming the enable signal patch_en was originally 1001, in chip_sleep = 1, i.e. sleep mode, assuming chip_sleep_path_en is 1100, indicating that the patch units for the third and fourth bits are enabled in sleep mode, based on the above calculation logic, the updated enable signal Patch_en_all is 1101. The updated enable signal is input to the four patch units 20 to repair the input signal.

[0065] Conversely, assuming chip_sleep = 0, meaning not in sleep mode, even if chip_sleep_path_en is 1100, Patch_en_all will still be 1001 based on the above logic formula.

[0066] Therefore, based on the repair circuit shown in Figure 5, the output signal of each signal line can be specified, with different configurations in sleep mode.

[0067] This application embodiment also provides a method for repairing analog signals. This method can be applied to the above-mentioned analog signal repair circuit. The method includes: performing an AND operation on the enable signal and the inverted signal corresponding to each signal line to obtain a repair signal; and performing an XOR operation on the input signal of the signal line and the repair signal to obtain a repaired output signal.

[0068] Referring to the embodiment corresponding to Figure 1, the above-mentioned AND and XOR operations can be performed through the AND gate and XOR gate included in the patch unit 20. See the description of the embodiment corresponding to Figure 1 for details.

[0069] In one embodiment, the method provided in this application further includes: dividing all input signal signal lines into several groups, and distributing multiple signal lines of the same functional module into multiple groups; each group is connected to at least one patch module; the shift register 10 and multiple patch units 20 constitute a patch module; and correcting the input signals of multiple signal lines of the same functional module through multiple patch modules corresponding to multiple groups.

[0070] Referring to the corresponding embodiment in Figure 2, the input signals can be grouped using grouping and interleaving techniques, and the input signals of the same functional module can be distributed to different groups. Thus, when an anomaly occurs in the input signals of a certain functional module, it can be repaired by multiple patch modules, thereby achieving load balancing.

[0071] In one embodiment, the method provided in this application further includes: loading a stored shift signal and an enable signal into a first register 40 via a read circuit 30; providing a shift signal to the shift register 10 and an enable signal to the patch unit 20 via the first register 40.

[0072] Referring to the corresponding embodiment in Figure 4, shift signals and enable signals can be automatically loaded into the first register 40 during the chip startup phase, thereby directly providing shift signals to the shift register 10 and enabling signals to the patch unit 20, which can achieve power-on self-repair and improve efficiency.

[0073] Furthermore, referring to the embodiment corresponding to Figure 5, an updated enable signal can also be generated in sleep mode to control the patch unit 20, so that the output signal can have different configurations in sleep mode and achieve automatic mode switching.

[0074] The apparatuses and methods disclosed in the several embodiments provided in this application can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0075] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0076] If a function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

Claims

1. A circuit for repairing analog signals, characterized in that, This invention is applied to a mixed-signal chip and includes: a shift register; multiple patch units, wherein the first input terminals of the multiple patch units are connected one-to-one to the signal lines of multiple input signals; the second input terminal of each patch unit is connected to the shift register, and the shift register is used to input an inverted signal to the corresponding patch unit according to the shift signal; the third input terminal of each patch unit is used to input an enable signal; and the patch unit is used to control whether to invert the input signal according to the enable signal and the inverted signal.

2. The repair circuit according to claim 1, characterized in that, The patching unit includes: an AND gate, one input of which is used to input an enable signal, and the other input of which is connected to the shift register to input an inverted signal; an XOR gate, one input of which is connected to the output of the AND gate, and the other input of which is connected to a signal line to receive the input signal; and the output of which is used to output the repaired output signal.

3. The repair circuit according to claim 1, characterized in that, The shift register and the multiple patch units constitute a patch module; the signal lines of all input signals are divided into several groups, and each group is connected to at least one patch module.

4. The repair circuit according to claim 3, characterized in that, Multiple signal lines of the same functional module are distributed into multiple groups, and multiple patch modules corresponding to multiple groups correct the input signals of multiple signal lines of the same functional module.

5. The repair circuit according to claim 3, characterized in that, Each group connects to multiple patch modules, and the multiple patch modules are cascaded. The input signal is input to the next patch module after the input signal has been processed by one patch module.

6. The repair circuit according to claim 1, characterized in that, Also includes: A first register is connected to the shift register and the patch unit; a read circuit is connected to the first register and is used to load the stored shift signal and enable signal into the first register, and to provide the shift signal to the shift register and the enable signal to the patch unit through the first register.

7. The repair circuit according to claim 1, characterized in that, Also includes: The second register is used to store an indication signal indicating whether the patch unit is turned on in sleep mode; the second AND gate has one input for inputting the sleep signal and the other input connected to the second register for inputting the indication signal; the OR gate has one input for inputting an enable signal and the other input connected to the output of the second AND gate, and the output of the OR gate is connected to the third input of the patch unit to input the updated enable signal to the third input of the patch unit.

8. A method for repairing analog signals, characterized in that, The method is applied to the analog signal repair circuit according to any one of claims 1-7. The method includes: performing an AND operation on the enable signal and the inverted signal corresponding to each signal line to obtain a repair signal; and performing an XOR operation on the input signal of the signal line and the repair signal to obtain a repaired output signal.

9. The method according to claim 8, characterized in that, The method further includes: dividing all input signal lines into several groups, and distributing multiple signal lines of the same functional module into multiple groups; each group is connected to at least one patch module; the shift register and multiple patch units constitute a patch module; and the input signals of multiple signal lines of the same functional module are corrected by multiple patch modules corresponding to multiple groups.

10. The method according to claim 8, characterized in that, The repair circuit further includes: a first register connected to the shift register and the patch unit; and a read circuit connected to the first register. The method further includes: loading a stored shift signal and an enable signal into the first register through the read circuit; and providing a shift signal to the shift register and an enable signal to the patch unit through the first register.

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