Layout processing method, layout processing system and electronic device
By adjusting the gate pattern distance and circuit connection of NMOS and PMOS transistors in the CMOS digital IC layout, the resulting layout is generated, solving the problem of difficult layout parameter adjustment in full-custom design and realizing automated design and layout flexibility and scalability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-02-08
- Publication Date
- 2026-06-19
AI Technical Summary
Fully custom-designed CMOS digital IC layouts are difficult to automate, layout parameter adjustments are challenging, and scalability is limited.
By generating a standard cell layout and adjusting the gate pattern distance of NMOS and PMOS transistors, as well as the circuit connection relationship, according to the layout and circuit parameters, a result layout is generated and output as a database format file.
It improves the flexibility and scalability of layout creation and enables automated design.
Smart Images
Figure CN114462349B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a layout processing method, layout processing system and electronic device. Background Technology
[0002] CMOS (Complementary Metal Oxide Semiconductor) digital IC (Integrated Circuit) design can generally be divided into full-custom and semi-custom design. Full-custom design is a transistor-level design approach where all components, interconnects, and layout of the circuit are designed directly. Full-custom design can improve device performance, but it is time-consuming, difficult to fully automate, and the layout is usually of fixed size with limited parameter adjustment and scalability. Summary of the Invention
[0003] This disclosure provides a layout processing method, a layout processing system, and an electronic device.
[0004] A first aspect of this disclosure provides a layout processing method, comprising: generating a standard cell layout based on a plurality of layout parameters, the standard cell layout including a first inverter layout for forming a first inverter, wherein the first inverter layout includes a first NMOS transistor layout and a first PMOS transistor layout, the layout parameters including the distance between the gate patterns of the first NMOS transistor layout and the first PMOS transistor layout, the distance referring to the length between one end of the gate pattern of the first NMOS transistor layout and an adjacent end of the gate pattern of the first PMOS transistor layout; generating a result layout based on a plurality of circuit parameters and the standard cell layout; and outputting a database format file of the result layout.
[0005] In some embodiments, the circuit parameters include a series number of stages M, where M is an integer greater than or equal to 2; generating a result layout based on several circuit parameters and the standard cell layout includes: generating M series-connected standard cell layouts based on the series number of stages M; wherein, the output terminal of the first inverter layout of each standard cell layout is electrically connected to the input terminal of the first inverter layout of the next series-connected standard cell layout, and the result layout is used to form an inverter chain.
[0006] In some embodiments, the number of series stages M is odd, and the output of the first inverter layout of the last standard cell layout is electrically connected to the input of the first inverter layout of the first standard cell layout, the resulting layout being used to form a ring oscillator.
[0007] In some embodiments, the layout parameters further include: the width or length of the first NMOS transistor layout, the width-to-length ratio of the first NMOS transistor layout, the width or length of the first PMOS transistor layout, and the width-to-length ratio of the first PMOS transistor layout; the width of the first NMOS transistor layout refers to the width of the N-type active region pattern, the length of the first NMOS transistor layout refers to the length of the overlapping area between the N-type active region pattern and the gate pattern of the first NMOS transistor layout, the width of the first PMOS transistor layout refers to the width of the P-type active region pattern, and the length of the first PMOS transistor layout refers to the length of the overlapping area between the N-type active region pattern and the gate pattern of the first NMOS transistor layout. The length of the overlapping area between the active region pattern and the gate pattern of the first PMOS transistor layout; the step of generating a standard cell layout based on several layout parameters further includes: calculating the length of the first NMOS transistor layout based on the aspect ratio and width of the first NMOS transistor layout, or calculating the width of the first NMOS transistor layout based on the aspect ratio and length of the first NMOS transistor layout; calculating the length of the first PMOS transistor layout based on the aspect ratio and width of the first PMOS transistor layout, or calculating the width of the first PMOS transistor layout based on the aspect ratio and length of the first PMOS transistor layout.
[0008] In some embodiments, the layout parameters further include: the width and length of the first NMOS transistor layout, and the width and length of the first PMOS transistor layout; wherein, the width of the first NMOS transistor layout refers to the width of the N-type active region pattern, the length of the first NMOS transistor layout refers to the length of the overlapping area between the N-type active region pattern and the gate pattern of the first NMOS transistor layout, the width of the first PMOS transistor layout refers to the width of the P-type active region pattern, and the length of the first PMOS transistor layout refers to the length of the overlapping area between the P-type active region pattern and the gate pattern of the first PMOS transistor layout.
[0009] In some embodiments, generating a standard cell layout based on a plurality of layout parameters further includes: generating an N-type active region pattern of the first NMOS transistor layout in the standard cell layout based on the width of the first NMOS transistor layout, wherein the width of the N-type active region pattern is equal to the width of the first NMOS transistor layout; generating a gate pattern of the first NMOS transistor layout in the standard cell layout based on the length of the first NMOS transistor layout, wherein the length of the gate pattern of the first NMOS transistor layout is equal to the length of the first NMOS transistor layout; generating a P-type active region pattern of the first PMOS transistor layout in the standard cell layout based on the width of the first PMOS transistor layout, wherein the width of the P-type active region pattern is equal to the width of the first PMOS transistor layout; and generating a gate pattern of the first PMOS transistor layout in the standard cell layout based on the length of the first PMOS transistor layout, wherein the length of the gate pattern of the first PMOS transistor layout is equal to the length of the first PMOS transistor layout.
[0010] In some embodiments, the length of the N-type active region pattern is equal to the length of the gate pattern of the first NMOS transistor layout plus a first preset length; the length of the P-type active region pattern is equal to the length of the gate pattern of the first PMOS transistor layout plus a second preset length.
[0011] In some embodiments, the first preset length is equal to the second preset length.
[0012] In some embodiments, the layout parameters further include: power line pattern width and ground line pattern width.
[0013] In some embodiments, the layout parameters further include: the number of first contact plug patterns 2P in the contact plug layout, the contact plug layout being located on the N-type active region pattern and the P-type active region pattern, and the first contact plug patterns being symmetrically distributed on both sides of the gate pattern.
[0014] In some embodiments, when a plurality of the standard cell layouts are connected in series, the contact plug layout further includes a second contact plug pattern; the second contact plug pattern is located on the output terminal of the first inverter layout of each of the standard cell layouts, and is used to connect to the input terminal of the first inverter layout of the next series-connected standard cell layout.
[0015] In some embodiments, the circuit parameters include the fan-in / fan-out ratio N, where N is an integer greater than or equal to 2; the resulting layout further includes a plurality of second inverter layouts; wherein the input terminals of N-1 second inverter layouts are shared with the input terminal of one of the corresponding first inverter layouts.
[0016] In some embodiments, the output of the second inverter layout is floating.
[0017] In some embodiments, several layout parameters of the second inverter layout are the same as the corresponding layout parameters in the first inverter layout.
[0018] The layout processing method provided in this disclosure has at least the following advantages:
[0019] The layout processing method in this embodiment includes: generating a standard cell layout based on several layout parameters, generating a result layout based on several circuit parameters and the standard cell layout, and outputting the result layout. The standard cell layout includes a first inverter layout, which forms a first inverter. The first inverter layout includes a first NMOS transistor layout and a first PMOS transistor layout. The layout parameters include the distance between the gate patterns of the first NMOS transistor layout and the first PMOS transistor layout. By adjusting the layout parameters, the length between the closest ends of the gate patterns of the first NMOS transistor layout and the first PMOS transistor layout in the standard cell layout can be adjusted. By adjusting the circuit parameters, the circuit structure formed by the standard cell layout can be adjusted, thereby obtaining different result layouts, improving the flexibility and scalability of layout fabrication.
[0020] A second aspect of this disclosure provides a layout processing system, comprising: a first generation module, configured to generate a standard cell layout based on a plurality of layout parameters, the standard cell layout including a first inverter layout for forming a first inverter, wherein the first inverter layout includes a first NMOS transistor layout and a first PMOS transistor layout, the layout parameters including the distance between the gate patterns of the first NMOS transistor layout and the first PMOS transistor layout, the distance referring to the length between one end of the gate pattern of the first NMOS transistor layout and an adjacent end of the gate pattern of the first PMOS transistor layout; a second generation module, configured to generate a result layout based on a plurality of circuit parameters and the standard cell layout; and an output module, configured to output a database format file of the result layout.
[0021] The layout processing system provided in this disclosure has at least the following advantages:
[0022] The layout processing system in this embodiment includes a first generation module, a second generation module, and an output module. The first generation module generates a standard cell layout based on several layout parameters. The second generation module generates a result layout based on several circuit parameters and the standard cell layout. The output module outputs a database format file of the result layout. By adjusting the layout parameters, the structure of the standard cell layout can be adjusted. By adjusting the circuit parameters, the circuit structure formed by the standard cell layout can be adjusted, thereby obtaining different result layouts, improving the flexibility and scalability of layout creation.
[0023] A third aspect of this disclosure provides an electronic device, comprising: at least one processor and a memory, the memory storing computer execution instructions; the at least one processor executes the computer execution instructions stored in the memory, causing the at least one processor to perform the method described above, thus having at least the advantages of the method described above, the specific effects of which are as described above and will not be repeated here. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a flowchart of the layout processing method in the embodiments of this disclosure;
[0026] Figure 2 This is a schematic diagram of the first inverter in an embodiment of this disclosure;
[0027] Figure 3 This is a schematic diagram of a layout in an embodiment of this disclosure;
[0028] Figure 4 This is another schematic diagram of the layout in an embodiment of this disclosure;
[0029] Figure 5 This is a circuit schematic diagram of a layout in an embodiment of this disclosure;
[0030] Figure 6 This is another circuit schematic diagram of the layout in the embodiments of this disclosure;
[0031] Figure 7 This is another circuit schematic diagram of the layout in the embodiments of this disclosure;
[0032] Figure 8 This is yet another schematic diagram of the layout in an embodiment of this disclosure;
[0033] Figure 9 This is a schematic diagram of the layout processing system in an embodiment of this disclosure.
[0034] Explanation of reference numerals in the attached figures:
[0035] 1-First inverter; 10-Layout of the first inverter;
[0036] 110 - First PMOS transistor layout; 111 - P-type active region pattern;
[0037] 112 - Gate pattern of the first PMOS transistor layout; 113 - Power line pattern;
[0038] 120 - Layout of the first NMOS transistor; 121 - Pattern of the N-type active region;
[0039] 122 - Gate pattern of the first NMOS transistor; 123 - Ground line pattern;
[0040] 130 - Contact plug layout; 131 - First contact plug pattern;
[0041] 132 - First conductive pattern; 133 - Second contact plug pattern;
[0042] 134 - Second conductive pattern; 135 - Connecting wire;
[0043] 2-Second inverter; 210-Second PMOS transistor layout;
[0044] 220 - Second NMOS transistor layout; 30 - First generation module;
[0045] 40 - Second generation module; 50 - Output module. Detailed Implementation
[0046] This disclosure provides a layout processing method that generates a standard cell layout based on several layout parameters, and generates a final layout based on several circuit parameters and the standard cell layout. By adjusting the layout parameters, the length between the closest ends of the gate patterns of the first NMOS transistor layout and the gate patterns of the first PMOS transistor layout in the standard cell layout can be adjusted. By adjusting the circuit parameters, the circuit structure formed by the standard cell layout can be adjusted, thereby obtaining different final layouts, improving the scalability of the layout, and thus realizing automated design.
[0047] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0048] refer to Figure 1 This disclosure provides a layout processing method, which may include the following steps:
[0049] Step S100: Generate a standard cell layout based on several layout parameters. The standard cell layout includes a first inverter layout, used to form a... Figure 2 The first inverter 1 shown includes a first NMOS transistor layout and a first PMOS transistor layout. The layout parameters include the distance between the gate patterns of the first NMOS transistor layout and the first PMOS transistor layout. The distance refers to the length between one end of the gate pattern of the first NMOS transistor layout and the adjacent end of the gate pattern of the first PMOS transistor layout.
[0050] refer to Figure 3 The standard cell layout includes a first inverter layout 10 for forming a first inverter. The first inverter layout 10 includes a first NMOS (N-type Metal Oxide Semiconductor) transistor layout 120 and a first PMOS (P-type Metal Oxide Semiconductor) transistor layout 110. For example, the first PMOS transistor layout 110 may be located above the first NMOS transistor layout 120.
[0051] Both the first NMOS transistor layout 120 and the first PMOS transistor layout 110 include a gate pattern, a source pattern, and a drain pattern. The gate pattern 122 of the first NMOS transistor layout is connected to the gate pattern 112 of the first PMOS transistor layout, and the connected gate pattern forms the input terminal of the first inverter layout 10. The drain pattern of the first NMOS transistor layout 120 is connected to the drain pattern of the first PMOS transistor layout 110, and the connected drain pattern forms the output terminal of the first inverter layout 10.
[0052] refer to Figure 3The first NMOS transistor layout 120 also includes an N-type active region pattern 121. The gate pattern of the first NMOS transistor layout 120 is disposed on the N-type active region pattern 121, that is, the gate pattern of the first NMOS transistor layout 120 and the N-type active region pattern 121 have an overlapping area. The source pattern and drain pattern of the first NMOS transistor layout 120 are located on both sides of the gate pattern 122 of the first NMOS transistor layout 120, and are spaced apart.
[0053] Specifically, the length of the N-type active region pattern 121 is equal to the length of the gate pattern 122 of the first NMOS transistor layout 120 plus a first preset length, and the width of the N-type active region pattern 121 is less than the width of the gate pattern 122 of the first NMOS transistor layout 120. The length direction is perpendicular to the extension direction of the gate pattern 122 of the first NMOS transistor layout 120, such as... Figure 3 The X-direction shown is parallel to the extension direction of the gate pattern 122 of the first NMOS transistor layout 120, as shown below. Figure 3 Y direction shown.
[0054] With this configuration, the length of the N-type active region pattern 121 is greater than the length of the gate pattern 122 of the first NMOS transistor layout 120. This allows for a more reasonable setting of the size and position of the source and drain patterns of the first NMOS transistor layout 120, improving the electrical characteristics of the generated first inverter. Furthermore, when there are multiple first NMOS transistor layouts 120, the N-type active region patterns 121 of the multiple first NMOS transistor layouts 120 can be integrated into one unit, facilitating layout fabrication.
[0055] The first PMOS transistor layout 110 also includes a P-type active region pattern 111. The gate pattern of the first PMOS transistor layout 110 is disposed on the P-type active region pattern 111, that is, the gate pattern of the first PMOS transistor layout 110 and the P-type active region pattern 111 have an overlapping area. The source pattern and drain pattern of the first PMOS transistor layout 110 are located on both sides of the gate pattern 112 of the first PMOS transistor layout 110, and are spaced apart.
[0056] Specifically, the length of the P-type active region pattern 111 is equal to the length of the gate pattern 112 of the first PMOS transistor layout 110 plus a second preset length, and the width of the P-type active region pattern 111 is less than the width of the gate pattern 112 of the first PMOS transistor layout 110. This configuration allows for the reasonable setting of the size and position of the source and drain patterns of the first PMOS transistor layout 110, further improving the electrical characteristics of the generated first inverter. Furthermore, when there are multiple first PMOS transistor layouts 110, the P-type active region patterns 111 of the multiple first PMOS transistor layouts 110 can be integrated into one unit to facilitate layout fabrication.
[0057] In one possible embodiment, the first preset length is equal to the second preset length, so that the first PMOS transistor layout 110 and the first NMOS transistor layout 120 have a high degree of consistency, thereby facilitating the alignment of the gate pattern 112 of the first PMOS transistor layout 110 and the gate pattern 122 of the first NMOS transistor layout 120, and thus facilitating the connection of the corresponding two gate patterns.
[0058] The aforementioned P-type active region pattern 111 and N-type active region pattern 121 can be located on the same layer of the layout and arranged opposite to each other. That is, the source pattern of the first NMOS transistor layout 120 and the source pattern of the first PMOS transistor layout 110 can be located on the same layer and arranged opposite to each other, the drain pattern of the first NMOS transistor layout 120 and the drain pattern of the first PMOS transistor layout 110 can be located on the same layer and arranged opposite to each other, and the gate pattern 122 of the first NMOS transistor layout 120 and the gate pattern 112 of the first PMOS transistor layout 110 can be located on the same layer and arranged opposite to each other, so as to facilitate the fabrication of standard cell layouts.
[0059] Continue to refer to Figure 3 The layout parameters include the distance Gs between the gate pattern 112 of the first PMOS transistor layout 110 and the gate pattern 122 of the first NMOS transistor layout 120, where the distance Gs refers to the length between one end of the gate pattern 122 of the first NMOS transistor layout 120 and the adjacent end of the gate pattern 112 of the first PMOS transistor layout 110. For example... Figure 3 As shown, the distance Gs is the length between the upper end of the gate pattern 122 of the first NMOS transistor layout 120 and the lower end of the gate pattern 112 of the first PMOS transistor layout 110, that is, the length between the closest ends of the gate patterns 122 of the first NMOS transistor layout 120 and the gate patterns 112 of the first PMOS transistor layout 110.
[0060] By adjusting the distance Gs between the gate pattern 112 of the first PMOS transistor layout 110 and the gate pattern 122 of the first NMOS transistor layout 120, the layout of the first PMOS transistor layout 110 and the first NMOS transistor layout 120 can be adjusted, thereby adjusting the size and layout of the standard cell layout. Specifically, the smaller the distance Gs, the closer the first PMOS transistor layout 110 and the first NMOS transistor layout 120 are, the more compact the standard cell layout generated according to this parameter is, and the stronger the driving capability of the gates of the PMOS transistors and NMOS transistors in the formed first inverter is.
[0061] Step S200: Generate the resulting layout based on several circuit parameters and standard cell layout.
[0062] Circuit parameters are used to define the electrical connections in the resulting layout. For example, multiple standard cell layouts are connected according to circuit parameters. Circuit parameters include the number of series stages M, which refers to the number of first inverter layouts 10 connected in series. M is an integer greater than or equal to 2. For example, M can be 2, 3, 10, or 30, etc.
[0063] In some possible embodiments, a resulting layout is generated based on several circuit parameters and standard cell layouts, including: generating M series-connected standard cell layouts based on the number of series stages M; wherein the output terminal of the first inverter layout 10 of each standard cell layout is electrically connected to the input terminal of the first inverter layout 10 of the next series-connected standard cell layout, and the generated resulting layout is used to form an inverter chain.
[0064] like Figure 4 As shown, M standard cell layouts are connected in series, and each standard cell layout includes a first inverter layout 10. Multiple first inverter layouts 10 are arranged horizontally. Figure 4 (shown in the X direction), and these first inverter layouts 10 are connected in series. Specifically, the output terminal of the first inverter layout 10 of each standard cell layout is electrically connected to the input terminal of the first inverter layout 10 of the next standard cell layout connected in series, and the resulting layout can be used to create an inverter chain.
[0065] like Figure 4 As shown, three first inverters 10 are arranged sequentially from left to right. The output terminal of the first inverter 10 on the left is electrically connected to the input terminal of the first inverter 10 on the right, thus forming a standard cell layout with a series stage of 3. Based on this standard cell layout, a... Figure 5 The inverter chain shown has an input terminal of the first inverter 1 in the first stage for input signals and an output terminal of the first inverter 1 in the last stage for output signals. By comparing the input and output signals, the delay time of the inverter chain can be tested.
[0066] Based on the above embodiments, in one possible implementation, the number of cascade stages M is odd, and the output terminal of the first inverter layout 10 of the last standard cell layout is electrically connected to the input terminal of the first inverter layout 10 of the first standard cell layout. The resulting layout is used to form a ring oscillator. This resulting layout can be used to form... Figure 6 The ring oscillator shown has M first inverters 1 connected in series to form a closed loop. The oscillation period is obtained by testing the propagation delay time Tpd of the first inverter 1 of the ring oscillator.
[0067] Step S300: Output the database format file of the result layout.
[0068] After generating the resulting layout, a database format file can be output. This file contains information such as the layers and geometry of the layout, which can be used to create a photomask. The database format file can be a CIF or GDSII file, etc.
[0069] In the layout processing method of this disclosure embodiment, a standard cell layout is generated based on several layout parameters, a result layout is generated based on several circuit parameters and the standard cell layout, and the result layout is output. The standard cell layout includes a first inverter layout 10, which includes a first NMOS transistor layout 120 and a first PMOS transistor layout 110. The layout parameters include the distance between the gate patterns of the first NMOS transistor layout 120 and the first PMOS transistor layout 110. By adjusting the layout parameters, the length between the closest ends of the gate patterns 122 of the first NMOS transistor layout 120 and 112 of the first PMOS transistor layout 110 in the standard cell layout can be adjusted. By adjusting the circuit parameters, the circuit structure in the result layout can be adjusted, thereby obtaining different result layouts, improving the flexibility and scalability of layout fabrication.
[0070] In one possible embodiment of this disclosure, the layout parameters may further include parameters for defining the shape or size of the first NMOS transistor layout 120 and / or the first PMOS transistor layout 110. That is, the size of the first NMOS transistor layout and / or the first PMOS transistor layout can also be adjusted according to design needs, further improving the flexibility of layout fabrication and the scalability of the layout.
[0071] In one possible implementation, the layout parameters further include: the width or length of the first NMOS transistor layout 120, the aspect ratio of the first NMOS transistor layout 120, the width or length of the first PMOS transistor layout 110, and the aspect ratio of the first PMOS transistor layout 110. That is, the layout parameters include one of the width and length of the first NMOS transistor layout 120, the aspect ratio of the first NMOS transistor layout 120, one of the width and length of the first PMOS transistor layout 110, and the aspect ratio of the first PMOS transistor layout 110. With this configuration, the length and width of the first NMOS transistor layout 120, and the length and width of the first PMOS transistor layout 110 can be calculated to generate the first NMOS transistor layout 120 and the first PMOS transistor layout 110.
[0072] In this context, the width of the first NMOS transistor layout 120 refers to the width of the N-type active region pattern 121, the length of the first NMOS transistor layout 120 refers to the length of the overlapping area between the N-type active region pattern 121 and the gate pattern 122 of the first NMOS transistor layout 120, and the width-to-length ratio of the first NMOS transistor layout 120 refers to the ratio of its width to its length. Similarly, the width of the first PMOS transistor layout 110 refers to the width of the P-type active region pattern 111, the length of the first PMOS transistor layout 110 refers to the length of the overlapping area between the P-type active region pattern 111 and the gate pattern 112 of the first PMOS transistor layout 110, and the width-to-length ratio of the first PMOS transistor layout 110 refers to the ratio of its width to its length.
[0073] Correspondingly, generating a standard unit layout based on several layout parameters also includes:
[0074] The length of the first NMOS transistor layout 120 is calculated based on its width-to-length ratio and width, or the width of the first NMOS transistor layout 120 is calculated based on its width-to-length ratio and length.
[0075] The length of the first PMOS transistor layout 110 is calculated based on its aspect ratio and width, or the width of the first PMOS transistor layout 110 is calculated based on its aspect ratio and length.
[0076] For example, when the layout parameters include the width and aspect ratio of the first NMOS transistor layout 120, and the length and aspect ratio of the first PMOS transistor layout 110, the quotient of the width of the first NMOS transistor layout 120 and its aspect ratio is the length of the first NMOS transistor layout 120, and the product of the length of the first PMOS transistor layout 110 and its aspect ratio is the width of the first PMOS transistor layout 110. The length in the first NMOS transistor layout 120 and the width in the first PMOS transistor layout 110 are obtained through calculation, while the width in the first NMOS transistor layout 120 and the length in the first PMOS transistor layout 110 can be obtained directly, thereby determining the dimensions of the first NMOS transistor layout 120 and the first PMOS transistor layout 110.
[0077] In another possible implementation, the layout parameters further include the width and length of the first NMOS transistor layout 120, and the width and length of the first PMOS transistor layout 110. The width of the first NMOS transistor layout 120 refers to the width of the N-type active region pattern 121, and the length of the first NMOS transistor layout 120 refers to the length of the overlapping area between the N-type active region pattern 121 and the gate pattern 122 of the first NMOS transistor layout 120. The width of the first PMOS transistor layout 110 refers to the width of the P-type active region pattern 111, and the length of the first PMOS transistor layout 110 refers to the length of the overlapping area between the P-type active region pattern 111 and the gate pattern 112 of the first PMOS transistor layout 110. In other words, the width and length of the first NMOS transistor layout 120 and the first PMOS transistor layout 110 can be obtained directly without calculation.
[0078] Based on the two implementation methods described above, and after calculating or directly obtaining the width and length of the first NMOS transistor layout 120 and the width and length of the first PMOS transistor layout 110, a standard cell layout is generated according to several layout parameters, further including:
[0079] Based on the width of the first NMOS transistor layout 120, an N-type active region pattern 121 of the first NMOS transistor layout 120 in the standard cell layout is generated, and the width WN of the N-type active region pattern 121 is equal to the width of the first NMOS transistor layout 120.
[0080] Based on the length of the first NMOS transistor layout 120, the gate pattern 122 of the first NMOS transistor layout 120 in the standard cell layout is generated, and the length LN of the gate pattern 122 of the first NMOS transistor layout 120 is equal to the length of the first NMOS transistor layout 120.
[0081] Based on the width of the first PMOS transistor layout 110, a P-type active region pattern 111 of the first PMOS transistor layout 110 in the standard cell layout is generated, and the width WP of the P-type active region pattern 111 is equal to the width of the first PMOS transistor layout 110.
[0082] Based on the length of the first PMOS transistor layout 110, a gate pattern 112 of the first PMOS transistor layout 110 in the standard cell layout is generated, and the length LP of the gate pattern 112 of the first PMOS transistor layout 110 is equal to the length of the first PMOS transistor layout 110.
[0083] The length of the N-type active region pattern 121, the length of the P-type active region pattern 111, the width of the gate pattern 122 of the first NMOS transistor layout 120, and the width of the gate pattern 112 of the first PMOS transistor layout 110 are determined according to the layout design rules and are not specifically limited here.
[0084] The generation order of the above-mentioned N-type active region pattern 121, the gate pattern 122 of the first NMOS transistor layout 120, the P-type active region pattern 111, and the gate pattern 112 of the first PMOS transistor layout 110 is not limited and can be adjusted according to manufacturing needs. Of course, the above four patterns can also be generated simultaneously.
[0085] In the above embodiments, the length and width of the first NMOS transistor layout 120 and / or the first PMOS transistor layout 110 can be adjusted by the layout parameters, thereby generating standard cell layouts of the first NMOS transistor layout 120 and / or the first PMOS transistor layout 110 with different sizes, further improving the flexibility of layout fabrication and the scalability of the layout.
[0086] In other possible embodiments of this disclosure, the layout parameters also include the power line pattern width W. VDD and grounding wire pattern width W VSS According to the width W of the power cord pattern. VDD A power line pattern can be generated, which is used to form the power lines in the first inverter, providing the power supply voltage. The width W of the ground line pattern is determined accordingly. VSS A grounding pattern can be generated to form the grounding wire in the first inverter, which provides a grounding voltage, such as a high level for the power supply voltage and a low level for the grounding wire.
[0087] refer to Figure 3 P-type active area pattern 111 covers power line pattern 113, and N-type active area pattern 121 covers grounding pattern 123. The width of the power line pattern is W. VDD This refers to the dimension of the power line pattern 113 along the extension direction of the gate pattern 112 of the first PMOS transistor layout 110, and the ground line width W. VSS This refers to the dimension of the ground line pattern 123 along the extension direction of the gate pattern 122 of the first NMOS transistor layout 120. The length of the power line pattern and the length of the ground line pattern are determined according to the layout design rules and are not specifically limited here.
[0088] Accordingly, generating a standard unit layout based on several layout parameters also includes: based on the power line pattern width W VDD Generate the power line pattern 113 in the standard cell layout, and based on the ground line pattern width W VSS Generate grounding wire pattern 123 in the standard cell layout.
[0089] The power line pattern 113 and the P-type active area pattern 111 are located on different layers, and the grounding pattern 123 and the N-type active area pattern 121 are located on different layers. The power line pattern 113 and the grounding pattern 123 can be located on the same layer or on different layers.
[0090] In the above embodiments, the width W of the power line pattern can be adjusted by adjusting the layout parameters. VDD and grounding wire pattern width W VSS The dimensions are adjusted to generate power line patterns 113 and ground line patterns 123 with different sizes, thereby further improving the flexibility and scalability of the layout.
[0091] In some other possible embodiments of this disclosure, the layout parameters also include the number 2P of the first contact plug patterns in the contact plug layout 130, the contact plug layout 130 being located on the N-type active region pattern 121 and the P-type active region pattern 111, and the first contact plug patterns being symmetrically distributed on both sides of the gate pattern.
[0092] The contact plug pattern 130 overlaps with the N-type active region pattern 121 and also overlaps with the P-type active region pattern 111. Specifically, the contact plug pattern 130 located in the N-type active region pattern 121 is connected to both the drain and source regions of the first NMOS transistor pattern 120, and the contact plug pattern 130 located in the P-type active region pattern 111 is connected to both the source and drain regions of the first PMOS transistor pattern 110.
[0093] In some possible examples, the first contact plug pattern is symmetrically distributed on both sides of the gate pattern. For example... Figure 3 As shown, the P first contact plug patterns 131 on the N-type active region pattern 121 are symmetrically distributed on both sides of the gate pattern 122 of the first NMOS transistor layout 120, and the P first contact plug patterns 131 on the P-type active region pattern 111 are symmetrically distributed on both sides of the gate pattern 112 of the first PMOS transistor layout 110, so that the 2P first contact plug patterns are symmetrically distributed on both sides of the gate pattern.
[0094] Specifically, the contact plug layout 130 includes a plurality of spaced-apart first contact plug patterns 131, which are respectively located in the drain region of the first NMOS transistor layout 120, the source region of the first NMOS transistor layout 120, the drain region of the first PMOS transistor layout 110, and the source region of the first PMOS transistor layout 110. At least one first contact plug pattern 131 can be provided on each drain region or source region. For example, if two first contact plug patterns 131 are provided on each drain region and source region, then four first contact plug patterns 131 are provided on both the N-type active region pattern 121 and the P-type active region pattern 111. With this configuration, when a contact plug is formed according to the first contact plug patterns 131, at least two contact plugs are connected to both the source and drain regions. These at least two contact plugs are connected in parallel, which can reduce the total resistance of the at least two contact plugs and increase the drive current of the formed transistor.
[0095] The contact plug layout 130 also includes a plurality of spaced-apart first conductive patterns 132. Each first conductive pattern 132 is connected to a first contact plug pattern 131 located in the drain region of the first NMOS transistor layout 120, and to a first contact plug pattern 131 on the drain region of the first PMOS transistor layout 110 corresponding to the first NMOS transistor layout 120. This arrangement allows the drain regions of the first NMOS transistor layout 120 and the first PMOS transistor layout 110 to be connected, forming the output terminal of the first inverter layout.
[0096] In one possible embodiment, when several standard cell layouts are connected in series, the contact plug layout further includes a second contact plug pattern 133. The second contact plug pattern 133 is located at the output terminal of the first inverter layout of each standard cell layout and is connected to the input terminal of the first inverter layout of the next series-connected standard cell layout.
[0097] For details, please refer to Figure 4 In each first inverter layout 10, the gate pattern 112 of the first PMOS transistor layout 110 and the gate pattern 122 of the first NMOS transistor layout 120 are connected to form the input terminal of the first inverter layout 10, which is also connected to the second conductive line pattern 134. For example... Figure 4 As shown, the gate pattern 112 of the first PMOS transistor layout 110 and the gate pattern 122 of the first NMOS transistor layout 120 are connected by a connecting wire 135, and the connecting wire 135 is in contact with the second conductive pattern 134.
[0098] The second contact plug pattern 133 is located on the first conductive pattern 132 of each first inverter layout 10, and on the second conductive pattern 134 of the next series-connected first inverter layout 10. That is, the second contact plug pattern 133 of each first inverter layout 10, the first conductive line pattern 132 of the first inverter layout 10, and the second conductive pattern 134 of the next first inverter layout all have a partially overlapping area. In this configuration, in the first inverter layout 10, the drain patterns of the first PMOS transistor layout 110 and the first NMOS transistor layout 120 are connected to the first conductive line pattern 132 through the first contact plug pattern 131, and the first conductive line pattern 132 and the second conductive line pattern 134 are connected through the second contact plug pattern 133, and then connected to the connecting wire 135 in the next stage first inverter layout 10, thereby connecting to the gate pattern 112 of the first PMOS transistor layout 110 and the gate pattern 12 of the first NMOS transistor layout 120 in the next stage first inverter layout 10, so as to connect these M first inverter layouts in series sequentially.
[0099] In the above embodiments, by adjusting the layout parameters, the number of first contact plug patterns in the contact plug layout can be adjusted to obtain different contact plug layouts, thereby obtaining different standard unit layouts, further improving the flexibility of layout production and the scalability of the layout.
[0100] In some possible embodiments of this disclosure, see [link to relevant documentation]. Figure 7 and Figure 8 The circuit parameters also include the fan-in / fan-out ratio N, where N is an integer greater than or equal to 2; the resulting layout also includes at least one second inverter layout; wherein the input terminals of the N-1 second inverter layouts are connected together with the input terminal of one of the corresponding first inverter layouts 10.
[0101] The fan-in / fan-out ratio N refers to the ratio of the number of data input terminals to the number of data output terminals in a single stage of a circuit. For example, such as... Figure 7 As shown, this is the first stage of a circuit formed by a first inverter 1 and two second inverters 2. In this stage, there are three data input terminals: one for the first inverter 1 and one for each of the two second inverters 2. There is one data output terminal, which is the output of the first inverter 1. In the example above, specifically the example corresponding to two second inverters 2 and one first inverter 1, the fan-in / fan-out ratio N is 3.
[0102] Specifically, the second inverter layout includes a second NMOS transistor layout 220 and a second PMOS transistor layout 210. The gate pattern of the second NMOS transistor layout 220 is connected to the gate pattern of the second PMOS transistor layout 210, and the connected gate pattern forms the input terminal of the second inverter layout. The drain pattern of the second NMOS transistor layout 220 is connected to the drain pattern of the second PMOS transistor layout 210, and the connected drain pattern forms the output terminal of the second inverter layout.
[0103] Each first inverter layout 10 can correspond to N-1 second inverter layouts, and the input terminals of these N-1 second inverter layouts are connected to the same input terminal as their corresponding first inverter layout 10. For example... Figure 7 and Figure 8 As shown, when the resulting layout includes M series-connected first inverter layouts 10, each of these M first inverter layouts 10 is connected to N-1 second inverter layouts. With this configuration, each stage of the formed circuit structure corresponds to N-1 second inverters 2, allowing for flexible adjustment of the circuit's load capacity and improving its driving capability.
[0104] Specifically, N-1 corresponding second inverter layouts are generated beside the first inverter layout 10. These second inverter layouts can be distributed on one side of the first inverter 10. For example, as shown... Figure 8 As shown, the fan-in / fan-out ratio N is 3, and each first inverter layout 10 corresponds to 2 second inverter layouts. These 2 second inverter layouts are distributed on one side of the first inverter layout 10, that is, there are two second inverter layouts on the left side of the first inverter layout 10.
[0105] In some possible examples, the output of the second inverter layout, which is shared with the first inverter layout 10, is floating. For example... Figure 8 As shown, the output of the second inverter layout is not connected to any structure or device.
[0106] In some possible examples, the layout parameters of the second inverter layout can be the same as those of the first inverter layout 10. For example, the distance between the gate patterns of the second NMOS transistor layout 220 and the second PMOS transistor layout 210 is equal to the distance between the gate patterns of the first NMOS transistor layout 120 and the first PMOS transistor layout 110; the second NMOS transistor layout 220 has the same size and structure as the first NMOS transistor layout 120, and the second PMOS transistor layout 210 has the same size and structure as the first PMOS transistor layout 110, and so on. With this configuration, the second inverter 2 formed by the second inverter layout is identical to the first inverter 1 formed by the first inverter layout 10.
[0107] In some possible examples, adjacent inverter layouts may share common sections. For example, adjacent first NMOS transistor layouts 120 and 220 may share a drain or source pattern, adjacent second NMOS transistor layouts 220 may share a drain or source pattern, adjacent first PMOS transistor layouts 110 and 210 may share a drain or source pattern, and adjacent second PMOS transistor layouts 210 may share a drain or source pattern, thereby improving the compactness of the resulting layout.
[0108] Specifically, in the example where the fan-in / fan-out ratio N is 3 and the two second inverter layouts are located on the same side of the first inverter layout 10, in each stage of the standard layout cell, adjacent inverter layouts share a source region or a drain region. Specifically, the second NMOS transistor layout 220 in the second inverter layout farther from the first inverter layout shares a drain region with the second NMOS transistor layout 220 in the second inverter layout closer to the first inverter layout; the second NMOS transistor layout 220 in the second inverter layout closer to the first inverter layout shares a source region with the first NMOS transistor layout 210 in the first inverter layout. The first NMOS transistor layout 120 and the second NMOS transistor layout 220 are respectively referenced to their corresponding first PMOS transistor layout 110 and second PMOS transistor layout 220, and will not be described further here.
[0109] In the above embodiments, by adjusting the layout parameters, the fan-in / fan-out ratio N can be adjusted, so that the first inverter layout 10 and its corresponding second inverter layout form different result layouts, further improving the flexibility of layout production and the scalability of the layout.
[0110] This disclosure also provides a layout processing system, with reference to... Figure 9 The map processing system includes a first generation module 30, a second generation module 40, and an output module 50.
[0111] Specifically, the first generation module 30 is used to generate a standard cell layout based on several layout parameters. The standard cell layout includes a first inverter layout, which is used to form a first inverter. The first inverter layout includes a first NMOS transistor layout and a first PMOS transistor layout. The layout parameters include the distance between the gate patterns of the first NMOS transistor layout and the first PMOS transistor layout. The distance refers to the length between one end of the gate pattern of the first NMOS transistor layout and the adjacent end of the gate pattern of the first PMOS transistor layout.
[0112] The second generation module 40 is used to generate the resulting layout based on several circuit parameters and standard cell layout.
[0113] Output module 50 is used to output the database format file of the result layout.
[0114] In some possible embodiments, the circuit parameters include the number of series stages M, where M is an integer greater than or equal to 2, and the second generation module 40 is specifically used for:
[0115] M series-connected standard cell layouts are generated based on the series series number M; wherein, the output terminal of the first inverter layout of each standard cell layout is electrically connected to the input terminal of the first inverter layout of the next series-connected standard cell layout, and the resulting layout is used to form an inverter chain.
[0116] In some possible embodiments, the layout parameters further include: the width or length of the first NMOS transistor layout, the width-to-length ratio of the first NMOS transistor layout, the width or length of the first PMOS transistor layout, and the width-to-length ratio of the first PMOS transistor layout; wherein, the width of the first NMOS transistor / PMOS transistor layout refers to the width of the N-type / P-type active region pattern layout, and the length of the first NMOS transistor / PMOS transistor layout refers to the length of the overlapping area between the N-type / P-type active region pattern and the gate pattern. The first generation module 30 is specifically used for:
[0117] The length of the first NMOS transistor layout is calculated based on its width-to-length ratio and width, or the width of the first NMOS transistor layout is calculated based on its width-to-length ratio and length.
[0118] The length of the first PMOS transistor layout is calculated based on its width-to-length ratio and width, or the width of the first PMOS transistor layout is calculated based on its width-to-length ratio and length.
[0119] In some possible embodiments, the first generation module 30 further has the function of:
[0120] Based on the width of the first NMOS transistor layout, an N-type active region pattern of the first NMOS transistor layout in the standard cell layout is generated, and the width of the N-type active region pattern is equal to the width of the first NMOS transistor layout.
[0121] Based on the length of the first NMOS transistor layout, the gate pattern of the first NMOS transistor layout in the standard cell layout is generated, and the length of the gate pattern of the first NMOS transistor layout is the length of the first NMOS transistor layout.
[0122] Based on the width of the first PMOS transistor layout, a P-type active region pattern of the first PMOS transistor layout in the standard cell layout is generated, and the width of the P-type active region pattern is equal to the width of the first PMOS transistor layout.
[0123] Based on the length of the first PMOS transistor layout, the gate pattern of the first PMOS transistor layout in the standard cell layout is generated, and the length of the gate pattern of the first PMOS transistor layout is the length of the first PMOS transistor layout.
[0124] The layout processing system in this embodiment can execute the technical solution shown in the above method embodiment. Its principle and beneficial effects are similar, and will not be described again here.
[0125] This disclosure also provides an electronic device, which can be a computer or a server, including at least one processor and a memory. The memory stores computer-executable instructions, and the at least one processor executes the computer-executable instructions stored in the memory, causing the at least one processor to perform the layout processing method described above. The memory can be independent or integrated with the processor. When the memory is independently configured, the device also includes a bus for connecting the memory and the processor.
[0126] It is understood that the above division of modules is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. These modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. They can be separate processing elements, integrated into a chip within the aforementioned device, or stored as program code in the device's memory, invoked and executed by a processing element. The implementation of other modules is similar. Furthermore, these modules can be fully or partially integrated together, or implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. During implementation, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.
[0127] For example, these modules can be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs). As another example, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together to implement a system-on-a-chip (SOC).
[0128] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this disclosure is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).
[0129] The processor mentioned above can be a Central Processing Unit (CPU), or other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), etc. The memory may include high-speed RAM, and may also include non-volatile memory (NVM), such as at least one disk drive, or a USB flash drive, external hard drive, read-only memory, hard disk, or optical disk. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc.
[0130] The aforementioned storage medium can be implemented using any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disks, or optical disks. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.
[0131] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0132] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A layout processing method, characterized in that, The method includes: A standard cell layout is generated based on several layout parameters. The standard cell layout includes a first inverter layout for forming a first inverter. The first inverter layout includes a first NMOS transistor layout and a first PMOS transistor layout. The layout parameters include the distance between the gate patterns of the first NMOS transistor layout and the first PMOS transistor layout. The distance refers to the length between one end of the gate pattern of the first NMOS transistor layout and an adjacent end of the gate pattern of the first PMOS transistor layout. The first NMOS transistor layout also includes an N-type active region pattern, and the first PMOS transistor layout also includes a P-type active region pattern. The distance between the gate patterns of the first NMOS transistor layout and the first PMOS transistor layout is smaller than the distance between the N-type active region pattern and the P-type active region pattern. Based on several circuit parameters and the standard cell layout, a result layout is generated; Output the database format file of the resulting layout.
2. The method according to claim 1, characterized in that, The circuit parameters include the number of series stages M, where M is an integer greater than or equal to 2; The step of generating the resulting layout based on several circuit parameters and the standard cell layout includes: M series-connected standard cell layouts are generated according to the series series number M; wherein, the output terminal of the first inverter layout of each standard cell layout is electrically connected to the input terminal of the first inverter layout of the next series-connected standard cell layout, and the resulting layout is used to form an inverter chain.
3. The method according to claim 2, characterized in that, The series stage M is an odd number, and the output terminal of the first inverter layout of the last standard cell layout is electrically connected to the input terminal of the first inverter layout of the first standard cell layout. The resulting layout is used to form a ring oscillator.
4. The method according to claim 1, characterized in that, The layout parameters also include: the width or length of the first NMOS transistor layout, the width-to-length ratio of the first NMOS transistor layout, the width or length of the first PMOS transistor layout, and the width-to-length ratio of the first PMOS transistor layout. Wherein, the width of the first NMOS transistor layout refers to the width of the N-type active region pattern, the length of the first NMOS transistor layout refers to the length of the overlapping area between the N-type active region pattern and the gate pattern of the first NMOS transistor layout, the width of the first PMOS transistor layout refers to the width of the P-type active region pattern, and the length of the first PMOS transistor layout refers to the length of the overlapping area between the P-type active region pattern and the gate pattern of the first PMOS transistor layout. The process of generating a standard unit layout based on several layout parameters also includes: The length of the first NMOS transistor layout is calculated based on the aspect ratio and width of the first NMOS transistor layout, or the width of the first NMOS transistor layout is calculated based on the aspect ratio and length of the first NMOS transistor layout. The length of the first PMOS transistor layout is calculated based on its width-to-length ratio and width, or the width of the first PMOS transistor layout is calculated based on its width-to-length ratio and length.
5. The method according to claim 1, characterized in that, The layout parameters also include: the width and length of the first NMOS transistor layout, and the width and length of the first PMOS transistor layout; Wherein, the width of the first NMOS transistor layout refers to the width of the N-type active region pattern, the length of the first NMOS transistor layout refers to the length of the overlapping area between the N-type active region pattern and the gate pattern of the first NMOS transistor layout, the width of the first PMOS transistor layout refers to the width of the P-type active region pattern, and the length of the first PMOS transistor layout refers to the length of the overlapping area between the P-type active region pattern and the gate pattern of the first PMOS transistor layout.
6. The method according to claim 4 or 5, characterized in that, The process of generating a standard unit layout based on several layout parameters also includes: Based on the width of the first NMOS transistor layout, the N-type active region pattern of the first NMOS transistor layout in the standard cell layout is generated, and the width of the N-type active region pattern is equal to the width of the first NMOS transistor layout. Based on the length of the first NMOS transistor layout, a gate pattern of the first NMOS transistor layout in the standard cell layout is generated, wherein the length of the gate pattern of the first NMOS transistor layout is equal to the length of the first NMOS transistor layout. Based on the width of the first PMOS transistor layout, the P-type active region pattern of the first PMOS transistor layout in the standard cell layout is generated, and the width of the P-type active region pattern is equal to the width of the first PMOS transistor layout. Based on the length of the first PMOS transistor layout, a gate pattern of the first PMOS transistor layout in the standard cell layout is generated, wherein the length of the gate pattern of the first PMOS transistor layout is equal to the length of the first PMOS transistor layout.
7. The method according to claim 6, characterized in that, The length of the N-type active region pattern is equal to the length of the gate pattern of the first NMOS transistor layout plus a first preset length; the length of the P-type active region pattern is equal to the length of the gate pattern of the first PMOS transistor layout plus a second preset length.
8. The method according to claim 7, characterized in that, The first preset length is equal to the second preset length.
9. The method according to claim 1, characterized in that, The layout parameters also include: power line pattern width and ground line pattern width.
10. The method according to claim 1, characterized in that, The layout parameters also include: the number of first contact plug patterns in the contact plug layout is 2P, the contact plug layout is located on the N-type active region pattern and the P-type active region pattern, and the first contact plug patterns are symmetrically distributed on both sides of the gate pattern.
11. The method according to claim 10, characterized in that, When several of the aforementioned standard unit layouts are connected in series, the contact plug layout also includes a second contact plug pattern; The second contact plug pattern is located on the output terminal of the first inverter layout of each of the standard cell layouts, and is used to connect to the input terminal of the first inverter layout of the next series-connected standard cell layout.
12. The method according to claim 1, characterized in that, The circuit parameters include the fan-in / fan-out ratio N, where N is an integer greater than or equal to 2; The resulting layout also includes multiple second inverter layouts; The input terminals of N-1 of the second inverter layouts are connected together with the input terminal of one of the corresponding first inverter layouts.
13. The method according to claim 12, characterized in that, The output of the second inverter layout is floating.
14. The method according to claim 13, characterized in that, Several layout parameters of the second inverter layout are the same as the corresponding layout parameters in the first inverter layout.
15. A layout processing system, characterized in that, include: A first generation module is configured to generate a standard cell layout based on several layout parameters. The standard cell layout includes a first inverter layout for forming a first inverter. The first inverter layout includes a first NMOS transistor layout and a first PMOS transistor layout. The layout parameters include the distance between the gate patterns of the first NMOS transistor layout and the first PMOS transistor layout. The distance refers to the length between one end of the gate pattern of the first NMOS transistor layout and an adjacent end of the gate pattern of the first PMOS transistor layout. The first NMOS transistor layout also includes an N-type active region pattern, and the first PMOS transistor layout also includes a P-type active region pattern. The distance between the gate patterns of the first NMOS transistor layout and the first PMOS transistor layout is less than the distance between the N-type active region pattern and the P-type active region pattern. The second generation module is used to generate a result layout based on several circuit parameters and the standard cell layout; The output module is used to output the database format file of the resulting layout.
16. An electronic device, characterized in that, include: At least one processor and a memory, the memory storing instructions to be executed by the computer; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method according to any one of claims 1-14.