Apparatus having data rate based voltage control mechanism and method of operation thereof

Abstract

This application relates to devices with data rate based voltage control mechanisms and methods of operation thereof. Methods, devices, and systems related to voltage management of memory devices / systems are described. A memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or upcoming memory operation. The memory device can generate a control indicator to increase a system voltage for higher operating frequencies, decrease the system voltage for lower operating frequencies, or a combination thereof.

Description

Technical Field

[0001] The disclosed embodiments relate to apparatuses, and more specifically, to an apparatus and a method of operating thereof having a voltage control mechanism that depends on the data rate. Background Technology

[0002] Memory devices can be provided as modules with standard physical formats and electrical characteristics to facilitate easier installation and deployment across multiple computing systems. One such module is a dual in-line memory module (DIMM), which is commonly used to provide volatile memory, such as dynamic random access memory (DRAM), to a computing system. Because DRAM can be fast, DRAM-based memory systems are well-suited for use as the main memory of computing systems. Some memory systems, such as non-volatile dual in-line memory modules (NVDIMMs), also include non-volatile memory (e.g., flash memory) as well as DRAM.

[0003] Technological improvements to computing systems and their devices / subsystems (such as memory systems) are typically associated with increased operating speed and / or reduced circuit size / footprint. For memory systems, improvements can be achieved by increasing the density of memory circuitry and / or operating speed (e.g., clock speed). However, increasing density and / or operating speed presents increasing challenges in managing power, performance, and / or errors. Summary of the Invention

[0004] On one hand, this application provides an apparatus comprising: a memory array; a connector coupled to the memory array and combustible to the output of a power management integrated circuit (PMIC), the connector being configured to receive a variable input voltage from the PMIC; a mode register programmable by a memory controller to manage an operating frequency for the memory array; and logic coupled to the connector and the mode register, the logic being configured to: generate signaling corresponding to a voltage level for the memory array based on the operating frequency; and transmit the signaling to the PMIC to adjust the variable input voltage provided by the PMIC to the connector.

[0005] On the other hand, this application further provides a memory system comprising: a memory array; a power management integrated circuit (PMIC) coupled to the memory array and configured to provide a voltage for memory operation by the memory array; and a feedback circuit coupled to the PMIC and configured to: determine an operating frequency of a clock signal provided to the memory array; and generate signaling based on the determined operating frequency; wherein the PMIC is configured to adjust the voltage provided to the memory array according to the signaling.

[0006] In another aspect, this application further provides a method for operating a memory device, the method comprising: receiving an operating voltage at a dynamic random access memory (DRAM); determining an operating frequency of a clock signal for an upcoming memory operation; and generating signaling from the DRAM based on the operating frequency, wherein the signaling is used to adjust the operating voltage according to the operating frequency. Attached Figure Description

[0007] Figure 1 This describes an instance environment of an operable device according to an embodiment of the present technology.

[0008] Figure 2 A block diagram illustrating an example memory device according to an embodiment of the present technology.

[0009] Figure 3 A block diagram illustrating a voltage management circuit according to an embodiment of the present technology.

[0010] Figure 4A This is a flowchart illustrating an example method of operating a device according to an embodiment of the present technology.

[0011] Figure 4B This is a flowchart illustrating an example method for manufacturing an apparatus according to an embodiment of the present technology.

[0012] Figure 5 This is a schematic diagram of a system including a device according to an embodiment of the present technology. Detailed Implementation

[0013] As described in more detail below, the technology disclosed herein relates to an apparatus, such as for a memory system, a system having memory devices, and related methods, to manage the voltage level of the apparatus according to the data rate of an operation performed by the apparatus. The apparatus (e.g., DRAM, DIMM, a system containing DRAM / DIMM, and / or a portion thereof) may include voltage-speed management circuitry (e.g., logic) configured to dynamically adjust the internal system voltage level according to the data rate associated with a command / request memory operation.

[0014] Unlike conventional memory systems that are typically programmed at production time to provide a single supply level for all operating modes / frequencies, embodiments of this technology are configured to dynamically change the supply level to the memory circuitry based on ongoing and / or upcoming operations. For example, a memory system (e.g., a Double Data Rate 5 (DDR5) DIMM) may include a power management integrated circuit (PMIC) configured to provide operating voltages to the DRAM within the system. The PMIC and / or DRAM may include circuitry forming voltage-speed management circuitry configured to dynamically adjust the operating voltages supplied to the DRAM. The voltage-speed management circuitry can determine the operating speed (e.g., data rate) of ongoing and / or upcoming operations. Based on this determination, the voltage-speed management circuitry can generate voltage control indicators (e.g., commands / sets and / or voltage feedback for the supply level). The voltage-speed management circuitry (at, for example, the PMIC) can process the voltage control indicators and thus adjust the supply level. The voltage-speed management circuitry can increase the supply level to achieve and / or improve the higher speed performance of the DRAM. Furthermore, when the ongoing / upcoming operation does not require higher speed performance, the voltage-speed management circuitry can decrease the supply level and corresponding power consumption.

[0015] In the following description, numerous specific details are set forth to provide a thorough and possible description of embodiments of the present technology. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details stated herein. In other instances, well-known structures or operations typically associated with semiconductor devices have not been shown or described in detail so as not to obscure other aspects of the present technology. In general, it should be understood that various other devices, systems, and methods may also be within the scope of this technology in addition to the specific embodiments disclosed herein.

[0016] Figure 1This illustration schematically depicts a DIMM 100 comprising multiple DRAMs 120 (e.g., memory dies, memory chips, memory packages, or the like). The DIMM 100 includes edge connectors 102 along the edge of its substrate 101 (e.g., a printed circuit board (PCB) or the like) for connecting a data bus 104 and a service bus 106 (illustrated in bold) to a host device. The data bus 104 connects the DRAMs 120 to the edge connectors 102 and receives and transmits data signals from and to the connected host during memory access operations (e.g., read and write). The service bus 106 includes electrical connections configured to transmit information associated with the data transmitted via the data bus 104. For example, the service bus 106 may include a command bus and / or an address bus. The service bus 106 may further include connections for transmitting control information for dynamically adjusting power / voltage levels / levels on corresponding connections. The substrate 101 may include voltage connections (e.g., planes, a set of dedicated traces, a set of paths, etc.) for supplying voltage to circuitry thereon. The following section describes the details of dynamic voltage adjustment and the corresponding circuit system.

[0017] DIMM 100 further includes control circuitry, such as a registered clock driver (RCD) 110. RCD 110 may include circuitry configured to receive command / address signals from service bus 106 and generate memory command / address signals for DRAM 120. RCD 110 can present predictable electrical loads (e.g., for matching impedance, reactance, capacitance, etc.) to the host device and can redrive memory command / address signals to DRAM 120, which helps achieve higher density and increased signal integrity. RCD 110 can also buffer command / address signals provided by the host and then transmit the buffered signals as memory command / address signals to DRAM 120.

[0018] DIMM 100 may further include a PMIC 130 configured to provide power / voltage load for granular systems. For example, a DDR5 DIMM may include a PMIC 130 that receives external power (e.g., 12V) and distributes internal voltage (e.g., 1.1V). DDA PMIC 130 is provided. The PMIC 130 can be configured to stabilize the internal voltage across variations or fluctuations in the level of an external voltage. The PMIC 130 can provide the internal voltage to the DRAM 120 via a voltage connection on substrate 101. In some embodiments, the PMIC 130 can further receive control-related information from the DRAM 120 to adjust the internal voltage level (e.g., the onboard supply level). As described in detail below, the DRAM 120 and / or PMIC 130 may include circuitry configured to dynamically adjust the internal voltage level according to a target performance level (e.g., data rate).

[0019] Figure 2 A block diagram illustrating an example memory device 200 (e.g., a semiconductor die assembly comprising a three-dimensional integrated (3DI) device or a die stack package) according to an embodiment of the present technology. For example, device 200 may include... Figure 1 DRAM120 or a portion thereof.

[0020] Device 200 may include an array of memory cells, such as memory array 250. Memory array 250 may include multiple memory banks (e.g., memory banks 0 to 15), and each memory bank may include multiple word lines (WL), multiple bit lines (BL), and multiple memory cells arranged at the intersections of the word lines and bit lines. Memory cells may include any of several different memory media types, including capacitors, magnetoresistive, ferroelectric, phase-change, or similar media. The selection of word lines WL may be performed by row decoder 240, and the selection of bit lines BL may be performed by column decoder 245. A sense amplifier (SAMP) may be provided for a corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which may be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG) (which may be used as a switch). The sensing amplifier and the transmission gate can operate based on control signals from the decoder circuitry, which may include any control circuitry of the command decoder 215, row decoder 240, column decoder 245, and memory array 250, or any combination thereof. The memory array 250 may also include board lines and corresponding circuitry for managing its operation.

[0021] Device 200 may employ multiple external terminals, including command and address terminals respectively coupled to the command bus and address bus to receive command signals (CMD) and address signals (ADDR). Device 200 may further include a chip select terminal for receiving a chip select signal (CS), clock terminals for receiving clock signals CK and CKF, data clock terminals for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI, and DMI, and a power supply terminal V. DD V SS and VDDQ .

[0022] Command terminals and address terminals can be supplied with address signals and memory address signals from external sources. Figure 2 (Not shown in the diagram). The address signals and memory address signals supplied to the address terminals can be transmitted to the address decoder 210 via the command / address input circuit 205. The address decoder 210 can receive the address signals and supply the decoded row address signal (XADD) to the row decoder 240 and the decoded column address signal (YADD) to the column decoder 245. The address decoder 210 can also receive the memory address signal and supply the memory address signal to both the row decoder 240 and the column decoder 245.

[0023] Command and address terminals may be supplied with command signals (CMD), address signals (ADDR), and chip select signals (CS) from the memory controller. Command signals may represent various memory commands from the memory controller (e.g., access commands, which may include read and write commands). Chip select signals may be used to select whether device 200 responds to commands and addresses provided to the command and address terminals. When a valid chip select signal is provided to device 200, commands and addresses can be decoded and memory operations can be performed. Command signals may be provided as internal command signals ICMD to command decoder 215 via command / address input circuitry 205. Command decoder 215 may include circuitry to decode internal command signals ICMD to generate various internal signals and commands for performing memory operations, such as row command signals for selecting word lines and column command signals for selecting bit lines. Command decoder 215 may further include one or more registers for tracking various counts or values ​​(e.g., counts of refresh commands received by device 200 or counts of self-refresh operations performed by device 200).

[0024] Data can be read from memory cells in memory array 250 specified by row address (e.g., the address to which a valid command is provided) and column address (e.g., the address to which the read is provided). The read command can be received by command decoder 215, which can provide an internal command to input / output (I / O) circuitry 260, such that read data can be output from data terminals DQ, RDQS, DBI, and DMI via read / write amplifier 255 and I / O circuitry 260 according to the RDQS clock signal. Read data can be provided at a time defined by read delay RL information programmable in device 200 (e.g., programmable in mode register 207). The read delay RL information can be defined based on the clock cycle of the CK clock signal. For example, the read delay RL information can be the number of clock cycles of the CK signal after the read command is received by device 200 when the associated read data is provided.

[0025] Write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. Write commands can be received by command decoder 215, which can provide internal commands to I / O circuit 260, allowing write data to be received by the data receiver in I / O circuit 260 and supplied to memory array 250 via I / O circuit 260 and read / write amplifier 255. Write data can be written to memory cells specified by row and column addresses. Write data can be provided to the data terminals at a time defined by write delay information WL. Write delay information WL can be programmed into device 200, for example, programmed into mode register 207. Write delay information WL can be defined according to the clock cycle of the CK clock signal. For example, write delay information WL can be the number of clock cycles of the CK signal after the write command is received by device 200 when the associated write data is received.

[0026] The clock terminal and data clock terminal can be supplied with external clock signals and complementary external clock signals. External clock signals CK, CKF, WCK, and WCKF can be supplied to clock input circuit 220. CK and CKF signals can be complementary, and WCK and WCKF signals can also be complementary. Complementary clock signals can have opposite clock levels and simultaneously transition between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0027] An input buffer included in clock input circuit 220 can receive an external clock signal. For example, the input buffer can receive a clock / enable signal when enabled by a clock / enable signal from command decoder 215. Clock input circuit 220 can receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to internal clock circuit 230. Internal clock circuit 230 can provide various phase and frequency control internal clock signals based on the internal clock signal ICLK received from command / address input circuit 205 and clock enable CKE. For example, internal clock circuit 230 may include a clock path ( Figure 2(Not shown in the diagram), it receives the internal clock signal ICLK and provides various clock signals to the command decoder 215. The internal clock circuit 230 can further provide I / O clock signals. The I / O clock signals can be supplied to I / O circuit 260 and can be used as timing signals to determine the output timing for reading data and / or the input timing for writing data. The I / O clock signals can be provided at multiple clock frequencies, allowing data to be output from and input to device 200 at different data rates. Higher clock frequencies are desired when high memory speed is desired. Lower clock frequencies are desired when low power consumption is desired. The internal clock signal ICLK can also be supplied to timing generator 235 and thus various internal clock signals can be generated.

[0028] The desired clock frequency and / or its impending change can correspond to values ​​in other registers. For example, one or more of the mode registers 207 can provide information associated with the target or desired frequency range for an upcoming memory operation. Furthermore, one or more of the mode registers 207 (e.g., mode register 13) can be set before changing the frequency or rate of the clock associated with the upcoming operation (e.g., data clock signals WCK / WCKF, CK clock signal, and / or internal clock signal ICLK). Therefore, the corresponding mode register 207 can be used to determine the impending change in clock rate and / or the target range of the changed clock rate.

[0029] The power supply terminals can be obtained from, for example, an onboard voltage source (e.g., Figure 1 The PMIC 130 is supplied with power and voltage V from an external source. DD The power supply terminal can further access the voltage reference V. SS (e.g., electrical grounding). These power supply potentials V DD and V SS It can be supplied to the internal voltage generator circuit 270. The internal voltage generator circuit 270 can be based on the power supply potential V. DD and V SS Various internal potentials V are generated OD V ARY V PERI and similar items. V PP It can be used in the line decoder 240, internal potential V OD and V ARY It can be used in a sensing amplifier contained in a memory array 250, and the internal potential V PERI It can be used in many other circuit blocks.

[0030] The power supply terminal can also be supplied with a power supply potential V. DDQ Electricity supply potential V DDQ Can be connected to the power supply potential V SSTogether, they are supplied to I / O circuit 260. In embodiments of this technology, the power supply potential V DDQ It can be the same as the power supply potential V DD The potential of the power supply. In another embodiment of this technology, the power supply potential V DDQ It can be different from the power supply potential V DD The potential of the dedicated power supply. However, the potential V of the dedicated power supply. DDQ It can be used in I / O circuit 260 to prevent power supply noise generated by I / O circuit 260 from propagating to other circuit blocks.

[0031] In some embodiments, the internal voltage generator circuit 270 may include a feedback circuit 271 configured to generate a feedback control indicator via a voltage feedback VFDBK connector / pad. The feedback circuit 271 may be configured to determine and transmit information associated with the operating voltage / power, such as an external source level (e.g., V). DD One or more of the internal voltage levels (e.g., V) DD ) and / or its derivation. For example, feedback circuit 271 may generate a feedback control indicator that includes a command or setting of an external source level. Furthermore, feedback circuit 271 may generate a feedback control indicator that includes a feedback reference voltage associated with the external source level. Feedback circuit 271 may be configured to transmit the feedback control indicator to an external supply (e.g., PMIC 130).

[0032] Feedback circuit 271 can be configured to determine a desired or required operating range of clock frequency for ongoing and / or impending operations. For example, feedback circuit 271 can access or monitor one or more of the mode registers 207 to determine an indication of a target clock frequency and / or an impending frequency change. Alternatively or additionally, feedback circuit 271 may include internally available information (e.g., a counter, asynchronous timeout circuit, matched filter, etc.) configured to analyze, for example, clock speed, an impending command, and / or its predetermined pattern to determine the clock frequency. Furthermore, feedback circuit 271 may include components configured to work with phase-locked loop (PLL) circuitry and / or... Figure 1 The RCD 110 interacts with the circuit system to determine the clock frequency.

[0033] Feedback circuit 271 can be configured to generate a feedback control indicator based on a determined clock frequency. The generated feedback control indicator may reflect a desired voltage level rather than a current level corresponding to a target clock frequency. For example, feedback circuit 271 can be configured (via, for example, a passive / active circuit system and / or a processor / firmware / software) to generate a command / set to increase the external supply voltage for a higher operating frequency, for example, when the operating mode matches one or more predetermined mode settings and / or the target frequency is above an upper threshold. Feedback circuit 271 can be configured to generate a command / set to decrease the external supply voltage for a lower operating frequency, for example, when the operating mode matches one or more other mode settings and / or the target frequency is below a lower threshold. Moreover, for example, feedback circuit 271 can be configured (via, for example, a voltage divider with taps and output switches) to generate decreasing feedback (e.g., a level lower than the actual current condition) for a higher operating frequency and / or increasing feedback (e.g., a level higher than the actual current condition) for a lower operating frequency. Therefore, the external supply can respond to the adjusted feedback and increase the external supply level for higher operating frequencies and / or decrease the external supply level for lower operating frequencies. In some embodiments, the feedback circuit 271 can be configured to provide an operating frequency range to an external source (e.g., PMIC 130). The external source can increase and / or decrease the voltage according to the provided operating frequency range.

[0034] Device 200 can be connected to any of or components of several electronic devices capable of using memory for temporary or permanent storage of information. For example, the host device of device 200 can be a computing device, such as a desktop or portable computer, server, handheld device (e.g., mobile phone, tablet computer, digital reader, digital media player), or components thereof (e.g., central processing unit, coprocessor, dedicated memory controller, etc.). The host device can be a networking device (e.g., switch, router, etc.) or any of a digital image, audio, and / or video recorder, vehicle, appliance, toy, or several other products. In one embodiment, the host device can be directly connected to device 200; however, in other embodiments, the host device can be indirectly connected to a memory device (e.g., via a network connection or through an intermediary device).

[0035] Figure 3 A block diagram illustrating a voltage management circuit 300 according to an embodiment of the present technology is provided. The voltage management circuit 300 may include a DRAM 120, a PMIC 130, a service bus 106, and / or one or more of these components. For example, the voltage management circuit 300 may include... Figure 2 Feedback circuit 271 and / or Figure 2 Mode register 207.

[0036] Alternatively or additionally, the voltage management circuitry 300 may include one or more portions of the logic block 302, local memory 304, external supply interface 306, communication interface 308, and / or voltage output circuitry 310 of the PMIC 130. The logic block 302 may be configured to control the operation of the PMIC 130. In some embodiments, the logic block 302 may operate according to circuit system configurations and / or instructions stored in the local memory 304. The local memory 304 may be further configured to store information (e.g., received data and / or processing results) during operation. The external supply interface 306 may be configured to receive and process (via, for example, a filter and / or voltage converter) input voltage, such as from... Figure 1 The system voltage / current of the external source of the DIMM 100.

[0037] The voltage output circuit 310 may include circuitry (e.g., low dropout (LDO) circuitry and / or buck switching regulators (SWA, SWB, etc.)) configured to generate / supply a variable memory voltage 332 for the DIMM 100. The service bus 106 may include one or more voltage supply connections 322 that will supply the variable memory voltage 332 (e.g., V... DD and / or V SS The voltage output circuit 310 provides power to the DRAM 120 (e.g., where...). Figure 2 The internal voltage generator circuit 270 of the DRAM 120 provides a variable memory voltage 332 based on a voltage control indicator 334 transmitted to the communication interface 308 via one or more voltage control connections 324 within the service bus 106. As described above, the voltage control indicator 334 may include commands, settings, feedback voltage levels, and / or upcoming frequency ranges from the DRAM 120. The PMIC 130 can adjust the output level of the variable memory voltage 332 based on the voltage control indicator 334. For example, based on the voltage control indicator 334, the PMIC 130 can increase the onboard voltage for higher operating frequencies and / or decrease the voltage for lower operating frequencies, as described above.

[0038] Figure 4A This describes the operation of a device (e.g., according to embodiments of the present technology). Figure 1 DIMM 100 Figure 1 DRAM120, Figure 1 PMIC 130 Figure 3 A flowchart of an example method 400 (including voltage management circuitry 300 and / or one or more portions thereof). For example, method 400 can be used to dynamically adjust the onboard voltage of DIMM 100 (e.g., based on a target clock frequency, such as a data rate). Figure 3 (Variable memory voltage 332).

[0039] In box 402, the memory device can determine the frequency associated with performing memory operations (e.g., read or write). In other words, the DRAM 120 or other circuitry on DIMM 100 (e.g., ...) Figure 1 The RCD 110 can determine the target or current frequency, such as the data rate, for ongoing and / or upcoming memory operations. For example, as illustrated in box 412, the DRAM 120 (via, for example, feedback circuitry 271) can detect mode register settings updates corresponding to the target frequency or changes thereof. The DRAM 120 can monitor as described above. Figure 2 The DRAM 120 can use one or more of the mode registers 207 to detect changes in the stored value. The DRAM 120 can use the detected changes to determine the upcoming frequency range. Furthermore, as explained in box 414, the DRAM 120 and / or other circuitry can use analysis circuitry to determine the frequency of the clock signal.

[0040] In box 404, the memory device can generate Figure 3 The voltage control indicator 334 is used to adjust the operating voltage supplied to the DRAM 120. In block 422, the memory device can determine a target operating voltage corresponding to a determined frequency. For example, the memory device can target a higher voltage when the determined frequency is above a threshold (e.g., an upper threshold) and / or when the operating mode corresponds to a higher frequency. The memory device can target a higher operating voltage to support higher frequencies and corresponding performance characteristics. Furthermore, the memory device can target a lower voltage when the determined frequency is below a threshold (e.g., a lower threshold) and / or when the operating mode corresponds to a lower frequency. The memory device can target a lower voltage to reduce power consumption while supplying sufficient voltage to meet reduced performance characteristics corresponding to lower operating frequencies.

[0041] In some embodiments, such as those illustrated in block 424, the memory device may generate commands or settings (e.g., voltage control indicator 334) based on a target operating voltage. For example, in some embodiments, PMIC 130 may be configured to adjust the output / onboard voltage (e.g., variable memory voltage 332) based on the generated commands / settings. DRAM 120 may generate commands / settings for the target operating voltage and send commands / settings to PMIC 130.

[0042] In other embodiments, such as those illustrated in block 426, the memory device may generate adjusted voltage feedback (e.g., voltage control indicator 334) based on a target operating voltage. For example, in some embodiments, PMIC 130 may be configured to maintain a target voltage at DRAM 120 based on a feedback / reference voltage. PMIC 130 may use the feedback / reference voltage as a representation of the output / onboard voltage supplied to DRAM 120. Feedback circuitry 271 may generate reduced voltage feedback to increase the variable input voltage when the operating frequency is above a threshold (e.g., an upper threshold). Feedback circuitry 271 may generate increased voltage feedback to decrease the variable input voltage when the operating frequency is below a threshold (e.g., a lower threshold). In other words, feedback circuitry 271 may generate a voltage control indicator 334 that tricks or forces PMIC 130 to increase the output voltage above or decrease the output voltage below the target operating voltage.

[0043] As an illustrative example, PMIC 130 can be configured to maintain an operating voltage of 'nV' at DRAM 120. PMIC 130 can be configured to receive or anticipate a voltage control indicator 334 (e.g., a scaling level of the operating voltage) representing the operating voltage measured at DRAM 120. When it is determined that the current / imminent operating frequency is above a threshold or when a corresponding operating mode is determined, feedback circuitry 271 can generate (via, for example, a voltage divider with selectable taps) a voltage control indicator 334 corresponding to 'n-xV', even if the operating voltage of DRAM 120 is 'nV'. When PMIC 130 receives an adjusted voltage indication, PMIC 130 can increase the output voltage by 'xV' in an attempt to maintain 'nV' at DRAM 120. In fact, PMIC 130 can output an increased voltage such that the operating voltage at DRAM 120 is 'n+xV' according to the adjusted feedback. Similarly, when it is determined that the current / imminent operating frequency is below a threshold or when a corresponding operating mode is determined, the feedback circuit 271 can generate a voltage control indicator 334 corresponding to 'n+xV', even if the DRAM 120 operating voltage is 'nV'. When the PMIC 130 receives the adjusted voltage indication, the PMIC 130 can reduce the output voltage by 'xV' to maintain 'nV' at the DRAM 120. In fact, the PMIC 130 can output a reduced voltage such that the operating voltage at the DRAM 120 is 'n-xV' according to the adjusted feedback.

[0044] In block 406, the memory device can adjust its operating voltage according to voltage control indicator 334. For example, as illustrated in block 432, PMIC 130 can increase the variable memory voltage 332 for higher frequencies (e.g., a determined frequency) associated with upcoming and / or ongoing operations. By increasing the variable memory voltage 332, the memory device can meet increased performance requirements associated with higher operating frequencies (by, for example, reducing slew rates and / or voltage transitions). Furthermore, as illustrated in block 434, PMIC 130 can decrease the variable memory voltage 332 for lower frequencies (e.g., a determined frequency) associated with upcoming and / or ongoing operations. By decreasing the variable memory voltage 332, the memory device can reduce power consumption while maintaining reduced performance requirements associated with lower operating frequencies. In block 436, the dynamically generated / adjusted variable memory voltage 332 can be provided to and received at DRAM 120. Figure 4A The feedback loop in the diagram illustrates that device 100 can repeat method 400 and continuously adjust the operating voltage to optimally balance performance characteristics and power consumption.

[0045] Figure 4B This describes an apparatus for manufacturing an embodiment of the present technology (e.g., Figure 1 DIMM 100 Figure 1 DRAM120, Figure 1 PMIC 130 Figure 3 A flowchart of an example method 450 (including voltage management circuitry 300 and / or one or more portions thereof). In block 452, a frequency detection circuit may be provided. For example, a frequency detection circuit may be provided. Figure 2 Mode register 207 Figure 2 The circuit includes a feedback circuit 271 or a portion thereof, a frequency analysis circuit, and / or associated connections. In some embodiments, the circuit may include circuit system components formed using semiconductor or integrated circuit manufacturing processes (including, for example, doping, layering, metal deposition, planarization, etc.). The provided or formed circuit may be configured to determine an operating frequency or variations thereof, as described above.

[0046] In block 454, reporting circuitry (e.g., feedback circuitry 271 or one or more portions thereof) may be provided. The provided reporting circuitry may be configured to generate a report based on a determined frequency or variations thereof. Figure 3 The voltage control indicator 334. The provided reporting circuitry can be configured to transmit the voltage control indicator 334 (via, for example, one or more drivers) to another circuit (e.g., an external device, such as...). Figure 1 (PMIC 130).

[0047] In block 456, voltage control circuitry (e.g., a variable voltage supply, such as PMIC 130) may be provided. The provided voltage control circuitry may have a feedback input for receiving a voltage control indicator 334. The voltage control circuitry may be configured to adjust the supplied output voltage using the voltage control indicator 334, as described above.

[0048] Control connections can be provided in box 458. For example, Figure 1 The substrate 101 may have a comprising Figure 3 Voltage supply connection 322 and Figure 3 The voltage control connection of 324 Figure 1 Service bus 106. Alternatively, voltage supply connection 322 and / or voltage control connection 324 (e.g., metal traces) may be formed (via, for example, metal deposition) on substrate 101. The provided connections may be configured to electrically couple and / or directly connect DRAM 120 and PMIC 130. In some embodiments, providing control connections may include rerouting sensing lines on DIMM substrate 101 to or from DRAM 120 to sensing lines on DIMM substrate 101. For example, when PMIC 130 is configured to sense operating voltages from the PCB and / or receive control indicators, substrate 101 may be reconfigured to connect voltage feedback VFDBK connectors / pads to voltage control connection 324 and / or PMIC 130.

[0049] In box 460, a memory system (e.g., DIMM 100) can be assembled. For example, as illustrated in box 472, a memory (e.g., DRAM 120) can be attached to substrate 101. Furthermore, as illustrated in box 474, a voltage source (e.g., PMIC 130) can be attached to substrate 101. PMIC 130 and DRAM 120 can be connected to service bus 106.

[0050] Figure 5 This is a schematic diagram of a system including a device according to an embodiment of the present technology. (See above reference) Figure 1 Any of the aforementioned devices (e.g., memory devices) described in section 4 can be incorporated into any of a variety of larger and / or more complex systems, a representative example of which is... Figure 5 The system 580 is illustrated schematically. System 580 may include a memory device 500, a power supply 582, a driver 584, a processor 586, and / or other subsystems or components 588. The memory device 500 may include components generally similar to those described in the reference above. Figure 1The features of the device described in section 4 are included, and therefore may include various features for executing direct read requests from a host device. The resulting system 580 can perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative systems 580 may include (but are not limited to) handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. Components of system 580 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 580 may also include remote devices and any of a variety of computer-readable media.

[0051] As should be understood from the foregoing, specific embodiments of the present technology have been described herein for illustrative purposes, but various modifications may be made without departing from this disclosure. Furthermore, certain aspects of the new technology described in the context of specific embodiments may be combined with or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of certain embodiments, other embodiments may also exhibit such advantages, and not all embodiments need to necessarily exhibit such advantages to fall within the scope of the present technology. Therefore, this disclosure and related technologies may cover other embodiments not explicitly shown or described herein.

[0052] In the embodiments described above, the device has been described in the context of DIMM and DRAM devices. However, devices configured according to other embodiments of the present technology may include other types of suitable storage media attached to or replacing DIMM and DRAM devices, such as devices incorporating NAND-based or NOR-based non-volatile storage media (e.g., NAND flash), magnetic storage media, phase-change storage media, ferroelectric storage media, etc.

[0053] As used herein, the term "processing" includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, calculating results, executing instructions, assembling, transmitting, and / or manipulating data structures. The term "data structure" includes information arranged as bits, words or codewords, blocks, files, input data, system-generated data (e.g., calculated or generated data), and program data. Furthermore, as used herein, the term "dynamic" describes processes, functions, actions, or implementations that occur during the operation, use, or deployment of the corresponding device, system, or embodiment, and after or while running manufacturer's or third-party firmware. Dynamic processes, functions, actions, or implementations may occur after design, manufacturing, and initial testing, setup, or configuration.

[0054] The above embodiments have been described in sufficient detail to enable those skilled in the art to make and use them. However, those skilled in the art will understand that the technology may have additional embodiments, and may be implemented without the foregoing reference. Figures 1 to 5 The present technology is practiced in several cases, as detailed in the described embodiments.

Claims

1. A memory device comprising: Memory array; A connector coupled to the memory array and also coupled to the output of a power management integrated circuit (PMIC), the connector being configured to receive a variable input voltage from the PMIC; A mode register, which can be programmed by the memory controller to manage the operating frequency for the memory array; and Logic, coupled to the connector and the mode register, is configured to... Based on the operating frequency, signaling corresponding to the voltage level used for the memory array is generated; and The signaling is transmitted to the PMIC to adjust the variable input voltage provided by the PMIC to the connector.

2. The memory device according to claim 1, wherein: The variable input voltage can be configured by the PMIC based at least in part on the operating frequency of the memory array; The signaling indicates the voltage level, the operating frequency, or both; and The mode register can be programmed by the controller to manage the variable input voltage.

3. The memory device of claim 1, wherein the logic is configured to determine the operating frequency based on the settings of the mode register, wherein the operating frequency corresponds to a clock signal provided to the memory array.

4. The memory device of claim 3, wherein the logic is configured to: Determine the operating frequency of the clock signal for an upcoming memory operation, a variation of the operating frequency of the clock signal, or a combination thereof; and The signaling is generated to adjust the variable input voltage for the upcoming memory operation.

5. The memory device of claim 4, wherein the logic is configured to generate the signaling comprising commands, settings, or a combination thereof for: (1) increasing the variable input voltage when the operating frequency is above an upper threshold; or (2) decreasing the variable input voltage when the operating frequency is below a lower threshold.

6. The memory device of claim 4, wherein the logic includes or is coupled to a voltage divider having a plurality of output taps configured to selectively provide the signaling indicating a feedback voltage to the PMIC.

7. The memory device of claim 6, wherein the voltage divider is configured to provide the feedback voltage in response to determining the operating frequency, the feedback voltage representing a voltage level different from the current level of the variable input voltage received at the connector.

8. The memory device of claim 7, wherein the voltage divider is configured to selectively provide reduced voltage feedback when the operating frequency is above an upper limit threshold, wherein the reduced voltage feedback is a feedback voltage representing a voltage level below the current level of the variable input voltage and is configured such that the PMIC increases the variable input voltage.

9. The memory device of claim 7, wherein the voltage divider is configured to selectively provide an amplified voltage feedback when the operating frequency is below a lower threshold, wherein the amplified voltage feedback is a feedback voltage representing a voltage level higher than the current level of the variable input voltage and is configured to cause the PMIC to reduce the variable input voltage.

10. The memory device of claim 1, wherein the memory device comprises dynamic random access memory (DRAM).

11. The memory device of claim 10, wherein the DRAM is a double data rate (DDR) device.

12. A memory system comprising: Memory array; A power management integrated circuit (PMIC) coupled to the memory array and configured to provide voltages for memory operations by the memory array; and Feedback circuitry, coupled to the PMIC and configured to: Determine the operating frequency of the clock signal provided to the memory array, and Signaling is generated based on the determined operating frequency; in: The PMIC is configured to adjust the voltage supplied to the memory array according to the signaling.

13. The memory system according to claim 12, wherein: The memory array includes dynamic random access memory (DRAM); and The memory system includes dual in-line memory modules (DIMMs).

14. The memory system according to claim 13, wherein: The signaling indicates the frequency of the upcoming memory operation; and The PMIC is configured to: Receive the operating frequency, and The voltage supplied to the DRAM is adjusted according to the operating frequency.

15. The memory system according to claim 13, wherein: The feedback circuit includes the DRAM; and The PMIC is configured to: Receive the signaling from the DRAM, and The voltage supplied to the DRAM is adjusted according to the operating frequency.

16. The memory system of claim 15, wherein the feedback circuit is configured to generate the signaling comprising commands, settings, or a combination thereof for: (1) increasing the voltage supplied to the DRAM when the operating frequency is above an upper threshold; or (2) decreasing the voltage supplied to the DRAM when the operating frequency is below a lower threshold.

17. The memory system according to claim 15, wherein: The PMIC is configured to maintain an operating voltage at the DRAM based on a voltage sensed from the DRAM, wherein the voltage sensed from the DRAM represents the operating voltage received at the DRAM; and The feedback circuit is configured to generate a signaling that includes a voltage sensed from the DRAM that corresponds to an adjusted voltage different from the operating voltage at the DRAM, thereby forcing the PMIC to increase or decrease the voltage.

18. A method of operating a memory device, the method comprising: Determine the operating frequency for one or more memory operations of a dynamic random access memory (DRAM) device; Determine a target operating voltage for the DRAM device corresponding to the determined operating frequency; A setting for a power management device is generated based on the target operating voltage, wherein the power management device adjusts the supply voltage provided to the DRAM device according to the setting; and Signals are transmitted to the DRAM device to perform one or more memory operations according to the determined operating frequency and the target operating voltage.

19. The method of claim 18, wherein determining the operating frequency includes monitoring a mode register associated with the DRAM device, wherein the value of the mode register indicates the operating frequency.

20. The method of claim 18, wherein the target operating voltage for the DRAM device includes the lowest operating voltage from a set of operating voltages supported by the operating frequency of the DRAM device.

21. The method of claim 18, wherein the operating frequency corresponds to a clock signal associated with the DRAM device.

22. The method of claim 18, wherein the target operating voltage is lower than the previous operating voltage of the DRAM device, based at least in part on the operating frequency being lower than the previous operating frequency of the DRAM device.

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