Fast charging protocol chip and system thereof

Abstract

Embodiments of the present application provide a fast charging protocol chip and a system thereof. According to the fast charging protocol chip provided by the embodiments of the present application, the fast charging protocol chip comprises: an internal power supply module configured to generate an internal power supply voltage for powering internal circuits of the fast charging protocol chip based on an input voltage of the fast charging protocol chip; a power switch tube connected between the internal power supply module and an internal power supply pin of the fast charging protocol chip; and a slope detection module configured to detect a change slope of the input voltage of the fast charging protocol chip and control turn-on and turn-off of the power switch tube based on the change slope of the input voltage of the fast charging protocol chip. By using the slope detection module to control turn-on and turn-off of the power switch tube, the internal power supply voltage of the chip can be prevented from being powered off, that is, the chip will not be out of control, and the area of the chip can be saved.

Description

Technical Field

[0001] This invention relates generally to the field of integrated circuits, and more particularly to a fast charging protocol chip and its system. Background Technology

[0002] In fast charging applications, situations may arise where the output VBUS is short-circuited to ground. In such cases, increasingly more applications require that the fast charging protocol chip itself not become uncontrollable; that is, the internal supply voltage powering the chip's internal circuitry should not drop below the power supply reset voltage threshold. Existing technologies typically address this issue by utilizing the inverting blocking properties of Schottky diodes to prevent the internal supply voltage from dropping rapidly.

[0003] However, in some process technologies, these Schottky diodes require additional masks, which increases the cost of the system. In addition, even if no additional masks are needed in the process technology, as the power consumption of the chip increases, the area of ​​the Schottky diode needs to be increased in order to meet the voltage drop requirements, which in turn increases the chip area and the cost of the chip. Summary of the Invention

[0004] This invention provides a fast charging protocol chip and system that can use a slope detection module to control the on and off of the power switch, which can save chip area and cost. In the event of an output short circuit, the power switch can be turned off to prevent the internal power supply voltage of the chip from dropping, so that the internal circuit of the chip can work normally and will not cause the chip to malfunction.

[0005] On one hand, embodiments of the present invention provide a fast charging protocol chip, including: an internal power supply module configured to generate an internal power supply voltage for powering the internal circuitry of the fast charging protocol chip based on the input voltage of the fast charging protocol chip; a power switch connected between the internal power supply module and the internal power supply pin of the fast charging protocol chip; and a slope detection module configured to detect the slope of the change in the input voltage of the fast charging protocol chip, and control the on and off of the power switch based on the slope of the change in the input voltage of the fast charging protocol chip.

[0006] On the other hand, embodiments of the present invention provide a fast charging system, including the fast charging protocol chip as described in the first aspect.

[0007] The fast charging protocol chip and system provided in this embodiment of the invention can control the conduction and cutoff of the power switch by using a slope detection module, which can prevent the internal power supply voltage of the chip from dropping, that is, it will not cause the chip to run out of control, and can save the chip area. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of the flyback pulse width modulation control architecture is shown.

[0010] Figure 2 A schematic diagram of the fast charging control system based on the flyback pulse width modulation control architecture is shown.

[0011] Figure 3 A schematic diagram illustrating the short-circuit protection implementation method of fast charging protocol chips provided by the prior art is shown;

[0012] Figure 4 This diagram illustrates a short-circuit protection implementation method for a fast charging protocol chip provided in an embodiment of the present invention; and

[0013] Figure 5 It shows Figure 4 The illustrated embodiment is a schematic diagram of the sampling loop for the input voltage. Detailed Implementation

[0014] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the invention.

[0015] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0016] To better understand the fast charging protocol chip and system provided in this embodiment of the invention, the architecture and basic working principle of the AC / DC fast charging system are first introduced below. As an example, the fast charging system can adopt a flyback architecture, for example, Figure 1 A schematic diagram of the flyback pulse width modulation control architecture is shown.

[0017] like Figure 1 The fast charging system shown adopts a flyback architecture, with the primary and secondary inductors of transformer T1 being opposite terminals. During the conduction of power switch M1, the primary inductor Np stores energy; during the turn-off of power switch M1, the primary inductor Np transfers the stored energy to the secondary inductor Nsec, which demagnetizes and provides its energy to the load.

[0018] As another example, Figure 2 A schematic diagram of a fast-charging control system based on a flyback pulse width modulation control architecture is shown. Figure 2 As shown, the AC / DC fast charging system mainly includes: a primary-side pulse width modulation (PWM) controller 210, a secondary-side synchronous rectifier (SR) 220, and a fast charging protocol chip 230, etc. The fast charging protocol chip 230 can integrate a fast charging protocol and a constant voltage / constant current (CV / CC) loop.

[0019] like Figure 2 As shown, the PWM controller 210 can be used to control the turn-on and turn-off of the primary-side power switch M1. Figure 1 The Schottky diode in the middle was replaced with Figure 2 The synchronous rectifier in the system can greatly improve the efficiency of the fast charging system.

[0020] In addition, from Figure 2 As can be seen, the input voltage VIN can be converted into voltage VBUS by a controlled transistor MN_ext (e.g., an NMOS transistor) located outside chip 230 to power subsequent devices. Specifically, if any fault is detected before power-on initialization is complete or during operation, transistor MN_ext is disconnected to cut off the path from input voltage VIN to VBUS, thus protecting the entire fast-charging system.

[0021] It should be noted that among all the above protections, the one with the most stringent requirements on the turn-off time of transistor MN_ext is the output short-circuit (VBUS and GND short-circuit) protection.

[0022] To achieve short-circuit protection, a Schottky diode can be placed inside chip 230 to prevent the internal supply voltage AVDD from dropping rapidly along with the VIN voltage. Specifically, as shown... Figure 3 As shown, Figure 3 A schematic diagram illustrating the short-circuit protection implementation method of fast charging protocol chips provided by the prior art is shown.

[0023] As an example, the fast charging protocol chip 230 may include an internal power supply module (e.g., a low dropout regulator (LDO)) 2301, an input voltage detection module 2302, a fault detection circuit 2303, a gate driver 2304, a Schottky diode Dsb, etc. The chip 230 may include an input pin VIN, a power supply pin AVDD, and a gate drive pin GATE.

[0024] like Figure 3 As shown, the LDO 2301 can generate an internal low-voltage supply voltage AVDD to power the internal circuitry of the chip based on the input voltage VIN, and output it to the AVDD pin through the Schottky diode Dsb for voltage regulation and filtering by the external capacitor Cavdd.

[0025] exist Figure 3 In the example shown, when the system is in normal working condition and no fault is detected, the power switch MN_ext located outside the chip remains in the on state. During system operation, if a short circuit to ground occurs in VBUS, the VIN voltage will also drop rapidly as VBUS decreases. However, due to the reverse blocking of the Schottky diode Dsb, the internal supply voltage AVDD will not drop rapidly as the voltage VIN decreases. Therefore, the input voltage detection module 2302, which is powered by the internal supply voltage AVDD, can normally detect the low level of VIN and output a high-level (e.g., "1") vin_low signal. Then, the power switch MN_ext is turned off by the subsequent gate driver 2304.

[0026] visible, Figure 3 The provided fast charging protocol chip, by adding a Schottky diode Dsb to utilize its reverse blocking, can effectively block the discharge path from the internal supply voltage AVDD to the input voltage VIN when a VBUS short circuit occurs. This reduces the requirement for the turn-off time of the power switch MN_ext, allowing the chip to protect the entire system under complete control.

[0027] In conclusion, Figure 3The circuit shown can achieve short-circuit protection and is relatively simple and reliable. However, the above circuit has several drawbacks: First, many Schottky diodes supplied by various processes often require additional masks, which increases costs. Second, as fast charging protocol chips become more complex, the minimum output voltage setting of VIN will get closer and closer to the AVDD reset voltage threshold, and the chip's clock frequency will further increase, leading to increased power consumption. In order to ensure that the voltage drop across the Schottky diode meets these stringent requirements, the area of ​​the Schottky diode will increase, which in turn increases the chip area and thus the chip cost.

[0028] To address the problems of existing technologies, embodiments of the present invention provide a novel short-circuit protection implementation method for fast charging protocol chips. The fast charging protocol chip provided in these embodiments is described below.

[0029] It should be noted that, for ease of explanation, the following embodiments are based on a fast charging protocol chip suitable for a flyback architecture. It is understood that they are provided as examples only and should not be construed as restrictive.

[0030] As an example, this embodiment of the invention provides a more effective short-circuit protection implementation for fast charging protocol chips. Specifically, as... Figure 4 As shown, Figure 4 A schematic diagram of the short-circuit protection implementation method of the fast charging protocol chip provided in an embodiment of the present invention is shown.

[0031] As an example, the fast charging protocol chip 430 may include an internal power supply module (e.g., LDO) 4301, an input voltage detection module 4302, a fault detection circuit 4303, a gate driver 4304, a slope detection module 4305, and a power switch MP0, etc. The chip 430 may include an input pin VIN, a power supply pin AVDD, and a gate drive pin GATE.

[0032] Figure 4 The chip shown is Figure 3 The main difference between the chips shown lies in: by utilizing Figure 4 The controlled power switch MP0 (e.g., PMOS) shown is used to replace Figure 3 The Schottky diode Dsb is used to achieve short-circuit protection. The power switch MP0 is connected between the internal power supply module 4301 and the internal power supply pin AVDD. A slope detection module 4305 is added to detect the slope of the chip's input voltage change and control the power switch MP0 to turn on and off based on the slope of the chip's input voltage change.

[0033] Understandably, if the VSG voltage of the power switch MP0 is high enough, a smaller voltage drop than Dsb can be achieved with the same chip area.

[0034] As an example, the slope detection module 4305 can be configured to control the power switch MP0 to switch off from on when the negative slope of the input voltage of the fast charging protocol chip is greater than the negative slope threshold, and to control the power switch MP0 to switch on from off when the positive slope of the input voltage of the fast charging protocol chip is greater than the positive slope threshold.

[0035] As an example, the slope detection module 4305 may include a voltage divider unit (including resistors Rup and Rdw), a low-pass filter unit (including resistor Rlp and capacitor Clp), a shift unit (including, for example, two transistors MP1 and MP2 of the same size, resistors R1 and R2, switch SW1, switch SW2 and current source I0), a first comparator comp1, a second comparator comp2, and logic units (including AND gates and inverters), etc.

[0036] The voltage divider unit can be configured to divide the input voltage VIN of the fast charging protocol chip to generate a divided voltage vin_div; the filtering unit can be configured to filter the divided voltage vin_div to generate a filtered voltage vin_div_lpf; the shifting unit can be configured to shift the filtered voltage vin_div_lpf and the divided voltage vin_div to generate a first shift level vin_div_lpf_shift and a second shift level vin_div_shift; the first comparator comp1 can be configured to compare the first shift level vin_div_lpf_shift and the second shift level vin_div_shift to generate a first comparison result slope_det; the second comparator comp2 can be configured to compare the divided voltage vin_div and the reference voltage vref_scp to generate a second comparison result slope_en; and the logic unit can be configured to generate a switching control signal sw_ctl for controlling the on and off of the power switch MP0 based on the first comparison result slope_det and the second comparison result slope_en.

[0037] Similar to Figure 3 The fast charging protocol chip shown is Figure 4 The fast charging protocol chip shown also includes an internal power supply module 4301, which can be used to generate a low-voltage supply voltage AVDD; and an input voltage detection circuit 4302 powered by the internal supply voltage AVDD, which can be used to turn off MN_ext located outside the chip when a low voltage VIN is detected.

[0038] As an example, the shift unit may include: a first shift branch, which may include a first PMOS transistor MP1, a first switch sw1, and a first resistor R1, and may be configured to perform different level shifts on the filter voltage vin_div_lpf when the first switch sw1 is in the on state and in the off state, respectively; and a second shift branch, which may include a second PMOS transistor MP2, a second switch sw2, and a second resistor R2, and may be configured to perform different level shifts on the voltage divider voltage vin_div when the second switch sw2 is in the on state and in the off state, respectively; wherein the on and off states of the first switch sw1 and the second switch sw2 may be controlled by the inverted switch control signal sw_ctli and the switch control signal sw_ctl, respectively.

[0039] As an example, the first shift branch may further include a first current source I0 and a first transistor MP1, wherein the first current source I0 may be connected between the internal power supply pin AVDD of the fast charging protocol chip and the first resistor R1, the source and drain of the first transistor MP1 may be connected to the first resistor R1 and the reference ground respectively, and the gate of the first transistor MP1 may receive the filtered voltage vin_pin_lpf; and the second shift branch may further include a second current source I0 and a second transistor MP2, wherein the second current source I0 may be connected between the internal power supply pin AVDD of the fast charging protocol chip and the second resistor R2, the source and drain of the second transistor MP2 may be connected to the second resistor R2 and the reference ground respectively, and the gate of the second transistor MP2 may receive the divided voltage vin_div.

[0040] Specifically, the input voltage VIN is divided by a voltage divider unit to generate a divided voltage vin_div. This divided voltage is then filtered by a low-pass filter unit to generate a filtered voltage vin_div_lpf. The divided voltage vin_div and the filtered voltage vin_div_lpf are respectively provided to the two input terminals of the subsequent shift units, namely the gates of MP2 and MP1, to generate level-shifted voltages vin_div_shift and vin_div_lpf_shift, respectively. Next, voltages vin_div_shift and vin_div_lpf_shift are respectively provided to the two input terminals of comparator comp1 (e.g., the negative input terminal and the positive input terminal), so that comparator comp1 can compare the two to generate the first comparison result slope_det. At the same time, the divided voltage vin_div can be provided to one input terminal of comparator comp2. (For example, the negative input terminal), the other input terminal of comparator comp2 (for example, the positive input terminal) can receive the reference voltage vref_scp, so that comparator comp2 can compare the two to generate a second comparison signal slope_en. After the first comparison signal slope_det and the second comparison signal slope_en are logically ANDed by an AND gate, a switch control signal sw_ctl can be generated. The switch control signal sw_ctl can be used to control the power switch MP0 to turn on and off. The switch control signal sw_ctl can also be inverted by an inverter to generate an inverted switch control signal sw_ctli. The signals sw_ctl and sw_ctli can be provided to the switches sw2 and sw1 in the shift unit respectively to control the turn-on and turn-off of these two switches, thereby generating the positive slope threshold, the negative slope threshold, and the necessary hysteresis voltage, etc. (which will be described in detail below).

[0041] Specifically, when the signal sw_ctl is high, switch sw2 is in the on state, and when the signal sw_ctl is low, switch sw2 is in the off state; when the signal sw_ctli is high, switch sw1 is in the on state, and when the signal sw_ctli is low, switch sw1 is in the off state.

[0042] exist Figure 4 In the illustrated embodiment, when a VBUS short circuit occurs, the chip can detect that the negative slope of VIN is greater than the negative slope threshold, and then disconnect the power switch MP0 to prevent the internal power supply voltage AVDD from dropping, thereby enabling the voltage detection circuit to work normally, that is, to detect the low voltage of VIN; then, when the VIN voltage recovers, the chip can detect that the positive slope of VIN is greater than the positive slope threshold, and then turn on the power switch MP0.

[0043] The following provides a detailed explanation of the working principle of the fast charging protocol chip. For example, this fast charging protocol chip can include three operating states: normal operating state, short circuit protection state, and voltage recovery state. The following mainly describes these three states separately.

[0044] As an example, under normal operating conditions, when the power switch MP0 is on, the first switch sw1 is on, the second switch sw2 is off, and the voltage divider vin_div equals the filter voltage vin_div_lpf, the second shift level vin_div_shift is greater than the first shift level vin_div_lpf_shift, the first comparison result slope_det is low, and the second comparison result slope_en is related to the voltage divider vin_div and the reference voltage vref_scp.

[0045] Specifically, when the fast charging system is in normal working condition, the transistor MN_ext located outside the chip is in the on state. The chip's input voltage VIN supplies power to VBUS through the transistor MN_ext. The switching control signal sw_ctl of the power switch MP0 is "0", meaning MP0 is in the on state. The inverted switching control signal sw_ctli is "1", and the switching control signals sw_ctl and sw_ctli are used to control switch sw2 to be in the off state and switch sw1 to be in the on state. When the input voltage VIN is stable, the voltage divider voltage vin_div and the filter voltage vin_div_lpf are equal. Since the first resistor R1 in the shift unit is short-circuited by the first switch sw1, and since the second switch sw2 is off, there is a voltage drop of I0*R2 across the second resistor R2. Therefore, the voltage divider... The voltage vin_div and the filtered voltage vin_div_lpf are both generated by the shift unit. The voltage vin_div_shift is higher than the voltage vin_div_lpf_shift, causing comparator comp1 to compare the two and output a comparison result slope_det = "0". At the same time, the voltage divider vin_div is compared with the reference voltage vref_scp by comparator comp2. The purpose is to ensure that the slope detection module 4305 only operates when the input voltage VIN is lower than a preset value, thereby avoiding false triggering of this slope detection when the input voltage VIN is output normally. Therefore, during normal operation, the voltage divider vin_div is higher than the reference voltage vref_scp, causing comparator comp2 to output a comparison result slope_en = "0".

[0046] Furthermore, when the fast charging system is in normal working condition, the output signal vin_low of the input voltage detection module 4302 is “0”. If the fault detection circuit 4303 does not detect any other faults, it outputs a detection result indicating that there is no fault. The gate driver 4304 can maintain the transistor MN_ext in the on state based on the output signal vin_low from the input voltage detection module 4302 and the detection result from the fault detection circuit 4303.

[0047] As an example, for the VBUS short-circuit state, when the voltage divider vin_div is less than the filter voltage vin_div_lpf by a first preset threshold, the second shift level vin_div_shift is less than the first shift level vin_div_lpf_shift, the first comparison result slope_det is at a high level, and the second comparison result slope_en is at a high level, the switch control signal sw_ctl is at a high level, and the power switch MP0 is in the off state.

[0048] Specifically, when a short circuit occurs between VBUS and ground, the input voltage VIN will drop rapidly along with the decrease in VBUS, resulting in a negative slope for the input voltage VIN. At this time, the voltage divider vin_div after being divided by the voltage divider resistors Rup and Rdw drops faster than the voltage divider vin_div_lpf after being filtered by the low-pass filter. If the negative slope of the input voltage VIN is large enough, then there will inevitably be a moment when the voltage divider vin_div is lower than the filtered voltage vin_div_lpf by a voltage drop of I0*R2. This will cause the second shift level vin_div_shift to be lower than the first shift level vin_div_lpf_shift, and the output signal slope_det of the first comparator comp1 will change from "0" to "1". At this time, if the input voltage VIN is low enough to make the voltage divider vin_div lower than the reference voltage vref_scp, then the second shift level vin_div_shift will be lower than the reference voltage vref_scp. The output signal slope_en of comparator comp2 also changes from "0" to "1". The output signals slope_det and slope_en from comparators comp1 and comp2 are ANDed by an AND gate, and the resulting switch control signal sw_ctl changes from "0" to "1". When the switch control signal sw_ctl is high, the power switch MP0 is turned off. At the same time, the high-level switch control signal sw_ctl and the low-level inverted switch control signal sw_ctli can be used to control the second switch sw2 to turn on and the first switch sw1 to turn off, respectively. This makes the first shift level vin_div_lpf_shift momentarily higher than the second shift level vin_div_shift by I0*(R1+R2) voltage drop, which introduces hysteresis. This can improve the anti-interference capability of the slope detection module 4305 near the detection threshold. Because of this slope detection method, detection can be completed quickly when the input voltage VIN is high, blocking the discharge path from the internal supply voltage AVDD to the input voltage VIN when a short circuit occurs in VBUS. Therefore, the input voltage detection module 4302 can complete the VIN low voltage detection when the internal supply voltage AVDD is normal, so that the output signal vin_low of the input voltage detection module 4302 changes from "0" to "1". The gate driver 4304 has enough time to turn off the transistor MN_ext, and the input voltage VIN no longer decreases with the decrease of VBUS.

[0049] As an example, regarding the voltage recovery state, there are two scenarios: In one scenario, during the input voltage VIN recovery process, the voltage divider vin_div is greater than the filter voltage vin_div_lpf by a second preset threshold, causing the second shift level vin_div_shift to be greater than the first shift level vin_div_lpf_shift, resulting in the first comparison result slope_det being low. In this case, the switch control signal sw_ctl is low, and the power switch MP0 is in the on state. In the other scenario, during the input voltage VIN recovery process, the voltage divider vin_div fails to be greater than the filter voltage vin_div_lpf by the second preset threshold, causing the second shift level vin_div_shift to not be greater than the first shift level vin_div_lpf_shift, resulting in the first comparison result slope_det remaining high. However, when the input voltage VIN rises to the point where the voltage divider vin_div is greater than the reference voltage vref_scp, causing the comparator comp2 output signal slope_en to be low, the power switch MP0 can also be restored to the on state. For those skilled in the art, the second scenario is relatively easy to understand. For ease of description, the control principle of the first scenario will be described in detail below.

[0050] Specifically, since the VIN short-circuit protection will disconnect the external transistor MN_ext, the energy provided by the primary-side PWM controller will cause the input voltage VIN to rise. At this time, the voltage divider vin_div after being divided by the voltage divider resistors Rup and Rdw rises faster than the filtered voltage vin_div_lpf after being filtered by the low-pass filter. If the positive slope of the input voltage VIN is large enough, there will inevitably be a moment when the voltage divider vin_div is higher than the filtered voltage vin_div_lpf by I0*R1, which will cause the second shift level vin_div_shift to be higher than the first shift level vin_div_lpf_shift. The output signal slope_det of comparator comp1 changes from "1" to "0". At this time, regardless of the value of the output signal slope_en of comparator comp2, the AND gate will output a low-level switch control signal sw_ctl, which will cause the switch control signal sw_ctl to control the power switch MP0 to turn on, and the input voltage VIN will supply power to the internal power supply voltage AVDD again. Simultaneously, the low-level switch control signal sw_ctl and the high-level inverted switch control signal sw_ctli can respectively control the second switch sw2 to turn off and the first switch sw1 to turn on, causing the first shift level vin_div_lpf_shift to be momentarily lower than the second shift level vin_div_shift by I0*(R1+R2) voltage drop, thus introducing hysteresis and improving the anti-interference capability of the slope detection module 4305 near the detection threshold. Next, if the input voltage detection module 4302 detects that the input voltage VIN has recovered to above the normal value, the output signal vin_low of the input voltage detection module 4302 changes from "1" to "0". Based on this output signal vin_low, the gate driver 4304 turns on the external transistor MN_ext again, so that all circuits return to their initial state during normal operation, preparing for the next short-circuit detection.

[0051] Furthermore, it is necessary to further determine which circuit parameters determine the negative slope threshold during short-circuit protection and the positive slope threshold during input voltage recovery. This will allow circuit designers to select appropriate circuit parameters to obtain suitable negative and positive slope thresholds during circuit design. Specifically, the following formula is derived based on Kirchhoff's voltage law, such as... Figure 5 As shown, Figure 5 It shows Figure 4 The illustrated embodiment is a schematic diagram of the sampling loop for the input voltage.

[0052] VR(t)+Vlpf(t)=Vdiv(t)………………(1)

[0053] Formula (1) can be further refined to obtain Formula (2):

[0054]

[0055] Where Vin(t) is a function of the input voltage VIN as a function of time, and when a VBUS short circuit occurs, Vin(t) can be approximated as a linear function as shown below:

[0056] Vin(t)=V0-k·t……………………(3)

[0057] In formula (3), V0 is the initial voltage of VIN when the VBUS short circuit occurs, and k is the decreasing slope of VIN when the VBUS short circuit occurs. Substituting formula (3) into formula (2), we get:

[0058]

[0059] In formula (4), Rlp and Clp are Figure 4 The resistance values ​​of the resistors and the capacitance values ​​of the capacitors in the low-pass filter shown are given. Rdw and Rup are the voltage divider resistors of VIN. By solving the first-order differential equation of formula (4), the function Vlpf(t) can be obtained:

[0060]

[0061] When an output short circuit occurs Figure 4 The following conditions must be met at the detection point:

[0062] Vlpf(t)-Vdiv(t)=I0·R2…………(6)

[0063] Substituting formulas (3) and (5) into formula (6), we get:

[0064]

[0065] In formula (7), when t >> Rlp·Clp is satisfied, the correspondence between the negative slope threshold of short-circuit detection and the circuit parameters can be obtained, as shown in formula (8):

[0066]

[0067] Furthermore, the correspondence between the detection time of comparator comp1 and the VIN slope k under different negative VIN slopes can also be obtained from formula (7), as shown in formula (9):

[0068]

[0069] As can be seen from formula (9), when an output short circuit occurs, the faster the input voltage VIN drops and the larger k is, the shorter the detection time of comparator comp1 will be.

[0070] Similarly, when the input voltage VIN is recovering, the corresponding relationship between the positive slope threshold and the circuit parameters can be obtained, as shown in formula (10):

[0071]

[0072] k in formulas (8) and (10) thn and k thp These are the negative slope threshold and positive slope threshold of VIN when the short circuit protection occurs and the input voltage recovers, respectively, obtained from the actual test of the system. By quantifying with formulas (8) and (10), the parameters of the circuit components can be reasonably selected so as to effectively realize the short circuit protection of the output VBUS.

[0073] In summary, the fast charging protocol chip and the fast charging system including the chip provided by the embodiments of the present invention can reduce the cost of the chip and achieve a reliable and effective output short-circuit protection scheme.

[0074] Specifically, compared to traditional short-circuit protection methods that utilize the reverse blocking of Schottky diodes, the fast charging protocol chip and system provided in this invention offer the following advantages: It saves chip costs; it converts the input voltage slope into a real-time voltage difference for comparison, providing a fast slope detection method that effectively prevents the chip's internal power supply voltage from dropping, i.e., it does not cause chip malfunction; it allows for setting separate negative slope thresholds when an output short circuit occurs and positive slope thresholds when VIN recovers, improving flexibility; it introduces hysteresis near both negative and positive slope threshold detection points, improving anti-interference capabilities; and it adds the judgment of the absolute value of VIN voltage as a condition for enabling slope detection, i.e., only when the input voltage VIN is below a preset threshold and above the safe operating level... When the voltage is within specified limits, the slope detection module is allowed to disconnect the power switch MP0 during negative slope detection. This prevents accidental triggering of short-circuit protection during dynamic output or VIN bucking operations under typical VIN output conditions. In short-circuit protection mode, the slope detection module can disconnect the power switch MP0 between the internal power supply module LDO and the internal supply voltage AVDD. Even if MP0 is accidentally turned off during normal operation, the output signal of the internal power supply module LDO can still supply power to AVDD through the parasitic diode D0 of MP0 (although the short-term voltage drop will increase). D0 also has a reverse blocking function similar to the Schottky diode Dsb in traditional methods. Furthermore, the output of the slope detection module is not used to directly turn off the external transistor MN_ext. Therefore, it has better anti-interference capabilities against external shocks such as ESD.

[0075] This invention also provides a short-circuit protection scheme for a fast charging system, including the fast charging protocol chip provided in this invention as described above. The details of the chip have been described in detail above, so they will not be repeated here for ease of description.

[0076] In summary, the embodiments of the present invention provide a short-circuit protection scheme applicable to flyback architecture AC / DC secondary-side fast charging chips. In applications with higher reliability requirements for fast charging systems, the fast charging protocol chip and system provided by the embodiments of the present invention can effectively detect output short circuits, thereby effectively protecting the entire fast charging system.

[0077] It should be clarified that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of the present invention.

[0078] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this invention are programs or code segments used to perform the required tasks. The programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0079] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0080] The above description is merely a specific embodiment of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.

Claims

1. A fast charging protocol chip, characterized in that, include: An internal power supply module is configured to generate an internal power supply voltage for powering the internal circuitry of the fast charging protocol chip based on the input voltage of the fast charging protocol chip. A power switching transistor is connected between the internal power supply module and the internal power supply pin of the fast charging protocol chip; as well as The slope detection module is configured to detect the slope of the input voltage change of the fast charging protocol chip, and control the power switch to change from on to off when the negative slope of the input voltage of the fast charging protocol chip is greater than the negative slope threshold. When the power switch is in the off state, the power switch blocks the discharge path from the internal power supply pin of the fast charging protocol chip to the internal power supply module.

2. The fast charging protocol chip according to claim 1, characterized in that, The slope detection module is further configured to: When the positive slope of the input voltage of the fast charging protocol chip is greater than the positive slope threshold, the power switch is controlled to change from off to on.

3. The fast charging protocol chip according to claim 2, characterized in that, The slope detection module includes: The voltage divider unit is configured to generate a voltage divider voltage by dividing the input voltage of the fast charging protocol chip; The filtering unit is configured to generate a filtered voltage by filtering the divided voltage; The shift unit is configured to generate a first shift level and a second shift level by shifting the level of the filtered voltage and the divided voltage, respectively; A first comparator is configured to generate a first comparison result by comparing the first shift level and the second shift level; A second comparator is configured to generate a second comparison result by comparing the divided voltage and the reference voltage; and The logic unit is configured to generate a switching control signal for controlling the on and off of the power switch transistor based on the first comparison result and the second comparison result.

4. The fast charging protocol chip according to claim 3, characterized in that, The shifting unit includes: A first shift branch, including a first switch and a first resistor, is configured to perform different level shifts on the filtered voltage when the first switch is in an on state and an off state, respectively; and The second shifting branch, including a second switch and a second resistor, is configured to perform different level shifts on the voltage divider when the second switch is in an on state and an off state, respectively; wherein... The on / off states of the first and second switches are controlled by the switching control signal of the power switching transistor.

5. The fast charging protocol chip according to claim 4, characterized in that, The first shift branch further includes a first current source and a first transistor, wherein the first current source is connected between the internal power supply pin of the fast charging protocol chip and the first resistor, the source and drain of the first transistor are respectively connected to the first resistor and a reference ground, and the gate of the first transistor receives the filtered voltage; and, The second shift branch further includes a second current source and a second transistor, wherein the second current source is connected between the internal power supply pin of the fast charging protocol chip and the second resistor, the source and drain of the second transistor are respectively connected to the second resistor and the reference ground, and the gate of the second transistor receives the voltage divider.

6. The fast charging protocol chip according to claim 4, characterized in that, When the switching control signal of the power switch is at a high level, the first switch is in the off state and the second switch is in the on state. When the switching control signal of the power switch is at a low level, the first switch is in the on state and the second switch is in the off state.

7. The fast charging protocol chip according to claim 3, characterized in that, When the voltage divider voltage is less than the filter voltage by a first preset threshold, the second shift level is less than the first shift level, the first comparison result is at a high level, and the second comparison result is at a high level, the switching control signal of the power switch is at a high level, and the power switch is in the off state.

8. The fast charging protocol chip according to claim 3, characterized in that, When the voltage divider voltage is greater than the filter voltage by a second preset threshold, the second shift level is greater than the first shift level, and the first comparison result is at a low level, the switching control signal of the power switch is at a low level, and the power switch is in the on state.

9. The fast charging protocol chip according to claim 4, characterized in that, When the power switch is in the ON state, the first switch is in the ON state, the second switch is in the OFF state, and the voltage divider is equal to the filter voltage, the second shift level is greater than the first shift level, the first comparison result is at a low level, and the second comparison result is related to the voltage divider and the reference voltage.

10. The fast charging protocol chip according to claim 5, characterized in that, The negative slope threshold is determined according to the following formula: in, The negative slope threshold is... The current value provided by the first current source or the second current source. This is the resistance value of the second resistor. These are the resistance values ​​of the resistors and the capacitance values ​​of the capacitors included in the filtering module, respectively. These are the resistance values ​​of the resistors included in the voltage divider module, which are respectively connected to the input voltage and the reference ground.

11. The fast charging protocol chip according to claim 5, characterized in that, The positive slope threshold is determined according to the following formula: in, The positive slope threshold is... The current value provided by the first current source or the second current source. Let be the resistance value of the first resistor. These are the resistance values ​​of the resistors and the capacitance values ​​of the capacitors included in the filtering module, respectively. These are the resistance values ​​of the resistors included in the voltage divider module, which are respectively connected to the input voltage and the reference ground.

12. A fast charging protocol system, characterized in that, Includes the fast charging protocol chip as described in any one of claims 1 to 11.

Images