Point light source type light emitting diode and method for manufacturing the same

Abstract

Provided are a point light source type light emitting diode capable of simplifying a manufacturing process and reducing light emission from outside a light release window in a light emitting pattern, and a method for manufacturing the same. The point light source type light emitting diode of the present invention includes: a substrate, an n-type cladding layer, a light emitting layer, a p-type cladding layer, an n-type current confinement layer having an opening, a p-type contact layer provided on the n-type current confinement layer, and a p-type electrode having a light release window, wherein the center of the light release window is the same as that of the opening, the window opening width of the light release window is greater than or equal to the opening width of the opening, the point light source type light emitting diode has a hydrogen ion implantation portion extending from the p-type contact layer to the light emitting layer in the thickness direction, the light emitting layer has a non-implantation region and a hydrogen ion implantation region, the center of the non-implantation region is the same as that of the light release window and has a region width greater than the opening width of the light release window, and the hydrogen ion implantation region surrounds the non-implantation region.

Description

Technical Field

[0001] The present invention relates to a point light source type light emitting diode and a method for manufacturing the same. Background Art

[0002] In recent years, light emitting diodes (LEDs; Light Emitting Diodes) have been used for various applications such as sensors, gas analysis, in-vehicle cameras, lighting, signals, sterilization, and resin curing according to their emission wavelengths. Among these, when using a light emitting diode for a sensor light source application or the like, a point light source type light emitting diode that emits light having a uniform light emission intensity distribution is used. A general light emitting diode emits light in all directions from the light emitting region, but a point light source type light emitting diode extracts only the light directed toward a specific direction. For example, Patent Document 1 discloses such a point light source type light emitting diode.

[0003] The point light source type light emitting diode disclosed in Patent Document 1 sequentially has a metal layer, a first conductive type layer, a light emitting layer, a second conductive type layer including a current confinement structure, and a top surface electrode formed with a light release window for extracting the light generated in the light emitting layer on a support substrate. In the point light source type light emitting diode of Patent Document 1, in order to confine the current-carrying region in the light emitting layer to a part of its plane, a current blocking region formed by hydrogen ion implantation is provided in the second conductive type layer above the active layer, thereby forming a current confinement structure. Further, a part of the light from the active layer toward the support substrate side below it is reflected by the metal reflection surface below the active layer and extracted from the light release window, and is absorbed by the light reflection reduction surface below the active layer.

[0004] In Patent Document 1, the above-described point light source type light emitting diode is manufactured through a crystal growth process, a dielectric layer formation process, an intermediate electrode formation process, a metal layer formation process, a diffusion prevention isolation layer formation process, a support substrate bonding process, a growth substrate separation process, a current confinement structure formation process, and an electrode formation process.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2015-170717 Summary of the Invention

[0008] Problems to be Solved by the Invention

[0009] In the technology of Patent Document 1, since the above-described metal reflection surface and light reflection reduction surface are formed below the light emitting layer, the manufacturing process is complicated. In addition, in recent years, there has been a demand for a point light source type light emitting diode that can minimize the light emission from outside the light release window in the light emission pattern.

[0010] Accordingly, an object of the present invention is to provide a point light source type light emitting diode capable of simplifying the manufacturing process and reducing light emission from areas other than the light release window in the light emitting pattern, and a method for manufacturing the same.

[0011] Solutions for Solving the Problems

[0012] The inventors of the present invention have repeatedly conducted in-depth research to solve the above problems. And it was conceived to form a hydrogen ion implantation portion in a point light source type light emitting diode, in which an n-type cladding layer, a light emitting layer, a p-type cladding layer, an n-type current confinement layer having an opening portion, and a p-type contact layer are sequentially formed on a substrate, and further a p-type electrode having a light release window is provided. And it was found that by providing a hydrogen ion implantation portion extending from the p-type contact layer to the light emitting layer in the thickness direction, light emission from areas other than the light release window in the light emitting pattern can be reduced. The present invention has been completed based on the above insights, and its main configuration is as follows.

[0013] (1) A point light source type light emitting diode, characterized in that it comprises:

[0014] A substrate;

[0015] An n-type cladding layer on the substrate;

[0016] A light emitting layer on the n-type cladding layer;

[0017] A p-type cladding layer on the light emitting layer;

[0018] An n-type current confinement layer provided on the p-type cladding layer and having an opening portion for exposing a part of the p-type cladding layer;

[0019] A p-type contact layer provided on the exposed surface of the p-type cladding layer and on the n-type current confinement layer; and

[0020] A p-type electrode provided on the p-type contact layer and having a light release window with the same center as the opening portion,

[0021] The size of the window opening width of the light release window is equal to or greater than the opening width of the opening portion,

[0022] The point light source type light emitting diode has a hydrogen ion implantation portion extending from the p-type contact layer to the light emitting layer in the thickness direction,

[0023] The light emitting layer has a non-implanted region and a hydrogen ion implanted region, the center of the non-implanted region is the same as the light release window, and it has a region width larger than the window opening width of the light release window, and the hydrogen ion implanted region surrounds the non-implanted region.

[0024] (2) The point light source type light emitting diode according to (1) above, wherein the hydrogen concentration in the hydrogen ion implantation region in the light emitting layer is 3.0 times or more the hydrogen concentration in the non-implanted region, and the hydrogen concentration in the hydrogen ion implantation region is 5.0×10 17 atoms / cm 3 or more.

[0025] (3) The point light source type light emitting diode according to (2) above, wherein the hydrogen concentration in the hydrogen ion implantation region is 2.0×10 19 atoms / cm 3 or less.

[0026] (4) A method for manufacturing a point light source type light emitting diode, characterized by comprising the following steps:

[0027] A semiconductor layer forming step of sequentially forming an n-type cladding layer, a light emitting layer, a p-type cladding layer, and an n-type semiconductor layer on a substrate;

[0028] An n-type current confinement layer forming step of forming an opening portion with an opening width A in the n-type semiconductor layer to form an n-type current confinement layer that exposes a part of the p-type cladding layer;

[0029] A p-type contact layer forming step of forming a p-type contact layer on the exposed surface of the p-type cladding layer and on the n-type current confinement layer;

[0030] A mask forming step of forming a mask having the same center as the opening portion and a mask width B on the p-type contact layer;

[0031] A hydrogen ion implantation step of implanting hydrogen ions from the surface of the p-type contact layer to form a hydrogen ion implantation portion extending from the p-type contact layer to the light emitting layer in the thickness direction; and

[0032] A p-type electrode forming step of removing the mask, and then forming a p-type electrode having a light release window on the p-type contact layer, the center of the light release window being the same as the opening portion, and having a window opening width C that is equal to or greater than the opening width A of the opening portion and less than the mask width B.

[0033] (5) The method for manufacturing a point light source type light emitting diode according to (4) above, wherein the dose of hydrogen ions in the hydrogen ion implantation step is 1.0×10 13 atoms / cm 2 or more.

[0034] (6) The method for manufacturing a point light source type light emitting diode according to (5) above, wherein the dose of hydrogen ions in the hydrogen ion implantation step is 2.0×10 15atoms / cm 2 as follows

[0035] Effects of the Invention

[0036] According to the present invention, a point light source type light emitting diode capable of simplifying a manufacturing process and reducing light emission from outside a light release window in a light emitting pattern and a manufacturing method thereof can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 FIG. is a schematic cross-sectional view showing an example of the point light source type light emitting diode of the present invention.

[0038] Figure 2 FIG. is a schematic cross-sectional view for explaining an example of a manufacturing process of the point light source type light emitting diode of the present invention.

[0039] Figure 3 is for subsequent Figure 2 FIG. is a schematic cross-sectional view for continuously explaining an example of a manufacturing process of the point light source type light emitting diode of the present invention.

[0040] Figure 4 is for subsequent Figure 3 FIG. is a schematic cross-sectional view for continuously explaining an example of a manufacturing process of the point light source type light emitting diode of the present invention.

[0041] Figure 5 is for subsequent Figure 4 FIG. is a schematic cross-sectional view for continuously explaining an example of a manufacturing process of the point light source type light emitting diode of the present invention.

[0042] Figure 6 FIG. is a graph showing hydrogen concentration and Ga, Al, In intensity curves in the depth direction obtained by SIMS in Examples 1 to 2 and Comparative Example 1.

[0043] Figure 7 FIG. is a graph showing a light emission intensity distribution and a light emission photograph when the point light source type light emitting diode of Example 1 emits light.

[0044] Figure 8 FIG. is a graph showing a light emission intensity distribution and a light emission photograph when the point light source type light emitting diode of Comparative Example 1 emits light..

[0045] Figure 9 FIG. is a light emission photograph when the point light source type light emitting diode of Example 2 emits light.

[0046] Figure 10 FIG. is a light emission photograph when the point light source type light emitting diode of Comparative Example 2 emits light. DETAILED DESCRIPTION OF THE INVENTION

[0047] Before describing the embodiments of the present invention, the definitions in this specification are described.

[0048] (Each definition)

[0049] <III-V compound semiconductor>

[0050] First, when simply referred to as "III-V compound semiconductor" in this specification, its composition is represented by the general formula (In a Ga b Al c )(P x As y Sb z ). Here, regarding the composition ratio of each element, the following relationship holds.

[0051] Regarding group III elements, c = 1 - a - b, 0 ≤ a ≤ 1, 0 ≤ b ≤ 1, 0 ≤ c ≤ 1.

[0052] Regarding group V elements, z = 1 - x - y, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1.

[0053] <p-type, n-type, undoped, and dopant concentration>

[0054] In this specification, a layer that functions as a p-type electrically is called a p-type semiconductor layer (sometimes simply referred to as "p-type layer"), etc., and a layer that functions as an n-type electrically is called an n-type semiconductor layer (sometimes simply referred to as "n-type layer"), etc. On the other hand, the case where impurities such as Si, Zn, S, Sn, Mg, Se, and C are not actively added is called "undoped". In an undoped III-V compound semiconductor layer, inevitable impurities in the manufacturing process may be mixed in. Specifically, when the dopant concentration is low (for example, less than 7.6×10 15 atoms / cm 3 ), it is regarded as "undoped" in this specification. The impurity concentration values of Si, Zn, S, Sn, Mg, Se, C, etc. are obtained based on SIMS analysis. It should be noted that since the dopant concentration value near the boundary of each semiconductor layer changes significantly, the dopant concentration value at the center in the film thickness direction of each layer is used as the dopant concentration value.

[0055] <Film thickness and composition of each layer>

[0056] In addition, the overall film thickness of each formed layer can be measured using an optical interference film thickness measuring instrument. Further, the film thickness of each layer can be calculated separately based on the observation of the growth layer cross-section using an optical interference film thickness measuring instrument and a transmission electron microscope. In addition, when the film thickness of each layer is as small as about several nm to the extent of a superlattice structure, TEM-EDS can be used to measure the film thickness. It should be noted that in the cross-sectional view of each layer, even when a mesa (inclined surface) is present in a specified layer, the film thickness of this layer does not consider the mesa, but uses the maximum height starting from the flat surface of the layer directly below this layer.

[0057] <Hydrogen concentration>

[0058] The hydrogen concentration is determined by SIMS (Secondary Ion Mass Spectrometry), and the average concentration in the depth direction of each layer is used. It should be noted that the hydrogen concentration value in the present invention uses the hydrogen concentration value in the light-emitting layer that is easy to determine the position in the depth direction in SIMS. The entire region subjected to hydrogen ion implantation is called the hydrogen ion implantation portion, and the in-plane direction range in the light-emitting layer within the hydrogen ion implantation portion is called the hydrogen ion implantation region. And, the range in the light-emitting layer other than the above hydrogen ion implantation region is called the non-implantation region. In the light-emitting layer just after epitaxial growth, there is almost no difference in the hydrogen concentration in the in-plane direction of the wafer. By forming a mask and performing hydrogen ion implantation, a difference in the hydrogen concentration in the in-plane direction is generated, and the hydrogen concentration in the hydrogen ion implantation region becomes 3.0 times or more that of the non-implantation region where no hydrogen ions are implanted directly below the mask. Thus, the hydrogen ion implantation region and the non-implantation region can be distinguished by measuring the in-plane distribution of the hydrogen concentration. The hydrogen concentration of the light-emitting layer just after epitaxial growth without hydrogen ion implantation (non-implantation region) is preferably 2.0×10 17 atoms / cm 3 or less.

[0059] Hereinafter, the point light source type light-emitting diode of the present invention and its manufacturing method will be described in sequence with reference to the drawings. It should be noted that the same reference numerals are assigned to the same components in principle, and repeated descriptions are omitted. In each figure, for the sake of convenience of explanation, the aspect ratios of the substrate and each layer are exaggerated compared to the actual ratios. In addition, "the same" mentioned in this specification does not mean strictly equal in the mathematical sense, but is naturally understood to include errors that are acceptable within the range of achieving the effects of the present invention, including inevitable errors generated in the manufacturing process.

[0060] (Point light source type light-emitting diode)

[0061] Refer to Figure 1, an example of the point light source type light emitting diode 100 of the present invention is described. The point light source type light emitting diode 100 at least includes: a substrate 10; an n-type cladding layer 31 on the substrate 10; a light emitting layer 35 on the n-type cladding layer 31; a p-type cladding layer 37 on the light emitting layer 35; an n-type current confinement layer 42 provided on the p-type cladding layer 37 and having an opening 42A that exposes a part of the p-type cladding layer 37; a p-type contact layer 60 provided on the exposed surface 37A of the p-type cladding layer 37 and on the n-type current confinement layer 42; and a p-type electrode 91 provided on the p-type contact layer 60 and having a light release window 92 with the same center as the opening 42A.

[0062] It should be noted that, between the respective layers on the substrate 10, there may be Figure 1 layers other than those described above not shown in Figure 1 . For example, there may be an initial growth layer, an n-type DBR layer, a spacer layer, a p-type DBR layer, etc. described later. In addition, there may be an n-type electrode not shown.

[0063] And, the light release window 92 in the point light source type light emitting diode 100 has a window opening width C that is equal to or greater than the opening width A of the opening 42A (therefore, C≥A). In addition, the point light source type light emitting diode 100 has a hydrogen ion implantation portion 80 from the p-type contact layer 60 to the light emitting layer 35 in the thickness direction. The hydrogen ion implantation portion 80 divides the light emitting layer 35 into a hydrogen ion implantation region 33 and a non-implantation region 34. The light emitting layer 35 has a hydrogen ion implantation region 33 and a non-implantation region 34. Among them, the center of the non-implantation region 34 is the same as that of the light release window 92, and has a region width B larger than the window opening width C of the light release window 92 (therefore, B>C). In addition, the hydrogen ion implantation region 33 surrounds the non-implantation region 34. If the relationship between the opening width A of the opening 42A, the region width B of the non-implantation region 34, and the window opening width C of the light release window 92 is sorted out, then A≤C<B.

[0064] Here, when looking down at the opening 42A, the light release window 92, and the non-implantation region 34, the shapes can be set to circular, elliptical, polygonal, or rounded rectangular, and their respective centers (geometric centers) are the same. In addition, it is preferable that the shapes of the opening 42A, the light release window 92, and the non-implantation region 34 are similar shapes. Regarding the values of A, B, and C of the respective widths, in the case of a circle, it refers to the diameter, in the case of an ellipse, it refers to the major axis, and in the case of a polygon or a rounded rectangle, it refers to the diameter of the circumscribed circle.

[0065] The point light source type light emitting diode 100 has the above-described configuration. In particular, since the hydrogen ion implantation portion 80 that constitutes the hydrogen ion implantation region 33 is provided in the light emitting layer 35, it is possible to reduce the light emission from outside the light release window 92 in the light emission pattern. If the relationship of the widths is A≤C<B, then the current flows from Figure 1Near the inner circumference of the p-type electrode 91 surrounded by the region width B and the window opening width C, current flows through the opening 42A of the n-type current confinement layer 42 with the opening width A to the light-emitting layer 35 via the p-type contact layer 60. The region directly below the opening 42A in the light-emitting layer 35 becomes the substantial light-emitting region. Since the n-type current confinement layer 42 has the effect of current confinement, the hydrogen ion implantation portion 80 does not have the current confinement effect as disclosed in the above Patent Document 1. That is, if the purpose of hydrogen ion implantation is the current confinement effect, there is no need to provide the hydrogen ion implantation portion 80 in the configuration of the present invention having the n-type current confinement layer 42 between the light-emitting layer 35 and the p-type electrode 91 having the light release window 92. The reason why the hydrogen ion implantation portion 80 reduces the light emission from outside the light release window 92 in the light-emitting pattern is not clear, but it is known that by deliberately providing the hydrogen ion implantation portion 80, the light emission from outside the light release window 92 can be effectively reduced.

[0066] In order to more reliably obtain the effect of reducing the light emission from outside the light release window in the above light-emitting pattern, it is preferable that the hydrogen concentration in the hydrogen ion implantation region 33 in the light-emitting layer 35 is 3.0 times or more the hydrogen concentration in the non-implantation region 34, and the hydrogen concentration in the hydrogen ion implantation region 33 is 5.0×10 17 atoms / cm 3 or more, and more preferably 6.0×10 17 atoms / cm 3 or more. Further, the hydrogen concentration in the hydrogen ion implantation region 33 is preferably 2.0×10 19 atoms / cm 3 or less.

[0067] Hereinafter, with reference to Figures 2 to 5 , by describing an example of an embodiment of a method for manufacturing a point light source type light-emitting diode 200 further including the configuration preferably included in the above point light source type light-emitting diode 100, each configuration applicable to the point light source type light-emitting diode based on the present invention will be described. The two-digit symbols and the symbols attached thereto refer to the common configurations in Figures 1 to 5 and repeated descriptions are omitted.

[0068] (Method for manufacturing a point light source type light-emitting diode)

[0069] The method for manufacturing the point light source type light-emitting diode 200 includes at least the following steps: a semiconductor layer forming step of sequentially forming an n-type cladding layer 31, a light-emitting layer 35, a p-type cladding layer 37, and an n-type semiconductor layer 41 on a substrate 10 (refer to Figure 2 S10 and S20 in Figure 2; p-type contact layer formation step of forming a p-type contact layer 60 on the exposed surface 37A of the p-type cladding layer 37 and on the n-type current confinement layer 42 (see Figure 3 ; mask formation step of forming a mask 70 having the same center as the opening 42A and a mask width B on the p-type contact layer 60 (see Figure 3 ; hydrogen ion implantation step of implanting hydrogen ions from the surface of the p-type contact layer 60 to form a hydrogen ion implantation portion 80 extending from the p-type contact layer 60 to the light-emitting layer 35 in the thickness direction (see Figure 4 ; S70 and S80); and p-type electrode formation step of removing the mask 70 and then forming a p-type electrode 91 having a light release window 92 on the p-type contact layer 60, the center of the light release window 92 being the same as that of the opening 42A and having a window opening width C that is equal to or greater than the opening width A of the opening 42A and smaller than the mask width B (see Figure 5 ; S90, S100). As Figure 2 ; exemplified in S20, in the semiconductor layer formation step, it is also preferable to separately form an initial growth layer 21 and an n-type DBR (Distributed Bragg Reflector) layer 23 between the substrate 10 and the n-type cladding layer 31 or to form both of them. Further, as Figure 3 ; exemplified in S40 and S50, the manufacturing method of the point light source type light-emitting diode 200 preferably further includes a p-type DBR layer formation step of forming a p-type DBR layer 50 between the exposed surface 37A of the p-type cladding layer 37 and the n-type current confinement layer 42 and the p-type contact layer 60. Hereinafter, the details of each step and each component will be described in sequence.

[0070] <Semiconductor layer formation step>

[0071] See Figure 2 ; S10 and S20. In the semiconductor layer formation step, an initial growth layer 21, an n-type DBR layer 23, an n-type cladding layer 31, a light-emitting layer 35, a p-type cladding layer 37, and an n-type semiconductor layer 41 are sequentially formed on the substrate 10. It should be noted that the formation of the initial growth layer 21 and the n-type DBR layer 23 may be omitted.

[0072] In this process, the layers formed on the substrate 10 are III-V compound semiconductor layers. These layers can be formed by known thin film growth methods such as metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), sputtering method, etc. The same applies to the III-V compound semiconductor layers formed after this process. If an AlInGaAsP-based semiconductor layer is to be formed, for example, trimethylaluminum (TMA) as an Al source, trimethylindium (TMIn) as an In source, trimethylgallium (TMGa) as a Ga source, arsine (AsH3) as an As source, phosphine (PH3) as a P source, etc. are used in a specified mixing ratio, and these source gases are subjected to vapor growth using a carrier gas, so that the AlInGaAsP-based semiconductor layer can be epitaxially grown to a desired film thickness according to the growth time. Further, when Sb is used as a group V element, it is only necessary to use TMSb (trimethylantimony) etc. as an Sb source. In addition, when each semiconductor layer is doped into a p-type or n-type, it is only necessary to grow the semiconductor layer by using a gas of a dopant source containing a p-type dopant (Zn, C, Mg, etc.) or an n-type dopant (Te, Si, Se, etc.) in the constituent elements according to the desire. In addition, the composition of each layer may be fixed in the crystal growth direction, may have a compositional gradient along the crystal growth direction, or may have a composition modulation (including discontinuous changes).

[0073] <<Substrate>>

[0074] First, the substrate 10 is prepared. The substrate 10 can be appropriately selected from GaAs substrates, InP substrates, GaSb substrates, InSb substrates, etc. according to the composition and lattice constant of the semiconductor layer grown thereon. In this embodiment, in order to form the n-type cladding layer 31 on the substrate 10, an n-type semiconductor substrate is preferably used, but the conductivity type of the substrate 10 can be undoped or p-type. Hereinafter, for the sake of convenience of explanation, the case where the substrate 10 is a GaAs substrate will be taken as an example to illustrate the composition of each semiconductor layer.

[0075] <<Initial growth layer>>

[0076] Preferably, an initial growth layer 21 is formed on the substrate 10. The initial growth layer 21 can prevent the influence of the oxide film and contamination on the surface of the substrate 10, and can also be used as a buffer layer for buffering the lattice strain between the semiconductor layer formed thereon. For example, when the substrate 10 is an n-type GaAs substrate, the initial growth layer 21 can be made into an n-type GaAs layer, or the composition ratio of group III elements and group V elements can be adjusted within the range of lattice matching with the substrate 10. The initial growth layer 21 can be a single layer, or can be a composite layer (such as a superlattice layer) with other layers. The film thickness of the initial growth layer 21 is arbitrary, and can be set to 10 nm to 100 nm, for example.

[0077] <<n-type DBR layer>>

[0078] Preferably, an n-type DBR layer 23 is formed on the substrate 10. Figure 2 In S20, an example in which an n-type DBR layer 23 is formed on the initial growth layer 21 is illustrated. The n-type DBR layer 23 is a reflective layer that can be formed by repeatedly laminating a low refractive index layer and a high refractive index layer. The film thickness of each layer of the low refractive index layer and the high and low refractive index layers constituting the n-type DBR layer 23 can be appropriately determined according to their respective refractive indices and emission wavelengths. One end of the stacked structure can be set as a low refractive index layer, and a repeating structure of a high and low refractive index layer and a low refractive index layer can be set, and the other end can be set as a low refractive index layer. Or, conversely, both ends can be set as high and low refractive index layers. In this case, the number of groups of the low refractive index layer and the high and low refractive index layers is expressed as n (n is a natural number), and is called n.5 groups. The number of groups of each layer of the low refractive index layer and the high and low refractive index layers can be set to about 5 to 40 groups, and the layer film thickness can be set to about 500 nm to 4000 nm. The composition of the low refractive index layer and the high and low refractive index layers is arbitrary. For example, two types of n-type AlGaAs layers with different composition ratios can be used.

[0079] <<n-type cladding layer>>

[0080] An n-type cladding layer 31 is formed on the substrate 10. Figure 2 In S20, an example in which an n-type cladding layer 31 is formed on the n-type DBR layer 23 is illustrated. The composition of the group III-V compound semiconductor constituting the n-type cladding layer 31 can be appropriately determined according to the composition of the group III-V compound semiconductor of the light emitting layer 35, and n-type AlInP can be exemplified. The n-type cladding layer 31 can be a single layer structure or a composite layer stacked with multiple layers. The film thickness of the n-type cladding layer 31 is not particularly limited, and can be set to 50 nm to 500 nm, for example.

[0081] <<Light emitting layer>>

[0082] The light-emitting layer 35 is formed on the n-type cladding layer 31. The light-emitting layer 35 can have a single-layer structure, or can be a single quantum well structure (SQW) in which a well layer and a barrier layer are stacked, or can also be a multi-quantum well (MQW) structure. In order to improve the light output by suppressing crystal defects, the light-emitting layer 35 more preferably has a quantum well structure. The emission wavelength can be set, for example, in the range of 580 to 4000 nm, and preferably the emission wavelength is set in the range of 630 to 1100 nm.

[0083] The light-emitting layer 35 can be composed of a III-V compound semiconductor. Hereinafter, the composition of the III-V compound semiconductor of the light-emitting layer 35 is expressed as (In a1 Ga b1 Al c1 )(P x1 As y1 Sb z1 ); c1 = 1 - a1 - b1, z1 = 1 - x1 - y1, 0 ≤ a1 ≤ 1, 0 ≤ b1 ≤ 1, 0 ≤ c1 ≤ 1, 0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1, 0 ≤ z1 ≤ 1. For example, when the emission center wavelength is set to 630 to 1100 nm, the composition ratio a1 of In in the light-emitting layer (when in the form of including a well layer and a barrier layer, for each layer) is set to 0.0 to 1.0, the composition ratio b1 of Ga is set to 0.0 to 1.0, the composition ratio c1 of Al is set to 0.0 to 0.5, the composition ratio x1 of P is set to 0.0 to 1.0, the composition ratio y1 of As is set to 0.0 to 1.0, and the composition ratio z1 of Sb is set to 0.0 to 0.5. For example, the well layer can be formed of InGaP, and the barrier layer can be formed of AlGaInP.

[0084] The film thickness of the light-emitting layer 35 is not particularly limited, and can be set, for example, to 10 to 500 nm. In addition, the film thickness of the well layer of the quantum well structure can be set to 3 nm to 17 nm, and the film thickness of the barrier layer can be set to 5 to 20 nm. The number of groups when in a multi-quantum well structure is not particularly limited, and can be set to about 5 to 50 groups, and the two ends of the multi-quantum well structure can be set as barrier layers.

[0085] <<p-type cladding layer>>

[0086] The p-type cladding layer 37 is formed on the light-emitting layer 35. The composition of the III-V compound semiconductor constituting the p-type cladding layer 37 can be appropriately determined according to the composition of the III-V compound semiconductor of the light-emitting layer 35, and p-type AlInP can be exemplified. The p-type cladding layer 37 can have a single-layer structure, or can be a composite layer in which multiple layers are stacked. The film thickness of the p-type cladding layer 37 is not particularly limited, and can be set, for example, to 50 nm to 500 nm.

[0087] <<n-type semiconductor layer>>

[0088] An n-type semiconductor layer 41 is formed on the p-type cladding layer 37. After an opening 42A is formed in the n-type semiconductor layer 41 in a subsequent process, it becomes an n-type current confinement layer 42. The composition of the III-V compound semiconductor constituting the n-type semiconductor layer 41 can be appropriately determined according to the composition of the III-V compound semiconductor of the light-emitting layer 35. For example, n-type AlInP can be exemplified. The film thickness of the n-type semiconductor layer 41 is not particularly limited as long as the opening 42A can be formed in a subsequent process. For example, it can be set to 10 nm to 200 nm.

[0089] <<Spacer layer>>

[0090] Note that, although not shown, an undoped spacer layer can be formed in one or both of the regions between the light-emitting layer 35 and the n-type cladding layer 31 and between the light-emitting layer 35 and the p-type cladding layer 37. By providing the spacer layer, diffusion of unnecessary dopants can be prevented. The film thickness of the spacer layer is not limited. For example, it can be set to 5 to 500 nm.

[0091] <n-type current confinement layer forming process>

[0092] Refer to Figure 2 S30 of. After the semiconductor layer forming process, an opening 42A having an opening width A is then formed in the n-type semiconductor layer 41 to form an n-type current confinement layer 42 that exposes a part of the p-type cladding layer 37. After forming a mask on the surface of the n-type semiconductor layer 41, the n-type semiconductor layer 41 is etched or the like, and an exposed surface 37A is provided on the p-type cladding layer 37. The opening width A of the opening 42A is not particularly limited and can be appropriately determined according to the use. For example, it can be set to 10 μm to 300 μm. Note that the above opening width A corresponds to the exposure width of the exposed surface 37A. The opening 42A is preferably formed in a circular shape in plan view, but is not particularly limited and can be an ellipse, a polygon, or a rounded rectangle. Note that the side surface of the exposed n-type current confinement layer 42 can be a vertical surface or a mesa (inclined surface). Figure 2 A cis-mesa in which the inclined surface faces the growth direction is exemplified. The mesa can be a cis-mesa or a trans-mesa. Note that when there is a mesa, the opening width A is set to the width measured for the minimum shape when looking down at the opening 42A.

[0093] <p-type DBR layer forming process>

[0094] Refer to Figure 3S40. A p-type DBR layer 50 is formed on the exposed surface 37A of the p-type cladding layer 37 and the n-type current confinement layer 42. The p-type DBR layer 50 can be omitted if necessary. The p-type DBR layer 50 is a reflective layer formed by repeatedly laminating a low refractive index layer and a high refractive index layer. Except for the n-type DBR layer 23 and the dopant being different, the stacking structure, the number of layers, and the adjustable range of the composition are the same as those of the above p-type DBR layer 50, and can be appropriately determined within the range where a DBR structure can be formed. A resonator can also be obtained between the light-emitting layer and the p-type DBR layer 50 and the n-type DBR layer 23. By determining an appropriate number of layers, etc. for adjusting the reflection force for light release, a vertical resonator type light-emitting diode can be fabricated.

[0095] <p-type contact layer formation process>

[0096] Refer to Figure 3 S50. A p-type contact layer 60 is formed on the exposed surface 37A of the p-type cladding layer 37 and the n-type current confinement layer 42. Figure 3 In S50, a p-type contact layer 60 is formed on the p-type DBR layer 50. The p-type contact layer 60 is a p-type semiconductor layer that exhibits ohmic contact with the p-type electrode 91 formed thereon. The composition of the III-V compound semiconductor constituting the p-type contact layer 60 can be appropriately determined according to the composition of the III-V compound semiconductor of the light-emitting layer 35, and p-type GaAs can be exemplified. The p-type contact layer 60 can be a single-layer structure or a composite layer laminated with multiple layers. The film thickness of the p-type contact layer 60 is not particularly limited, and can be set to, for example, 10 nm to 100 nm.

[0097] <Mask formation process>

[0098] Refer to Figure 3of S60. A mask 70 having the same center as the opening 42A and a mask width B which is the same as the opening width of the opening 42A is formed on the p-type contact layer 60. The mask 70 can be formed using a photosensitive resin or the like. The mask width B determines the formation position of the hydrogen ion implantation portion formed by subsequent processes in the in-plane direction. Therefore, the mask width B is made larger than the opening width A of the opening 42A and the light release window 92 having a window opening width C formed later. Note that since the opening 42A can be confirmed in the exposure machine, it is easy to perform the alignment of the photomask when forming the mask. The thickness of the formed mask is arbitrary, and for example, it may be set to 1 μm to 5 μm. In addition, as long as the mask width B is larger than the opening width A of the opening 42A and the light release window 92 having a window opening width C formed later, the size of the mask width B is not limited. Note that as a reference for the upper limit of the mask width B, it does not exceed the chip size, and considering the electrode width and the collimator width, for example, it may be in the range of C + 5 μm ≤ B < chip size - 5 μm. In order to reliably reduce the light emission from other than the light release window 92 in the light emission pattern, the hydrogen ion implantation region is preferably set to be 5 μm or more from the outer periphery of the chip size, and more preferably 10 μm or more from the outer periphery of the chip size.

[0099] <Hydrogen ion implantation process>

[0100] Refer to Figure 4 of S70 and S80. After forming the above-described mask 70, hydrogen ions are implanted from the surface of the p-type contact layer 60 to form a hydrogen ion implantation portion 80 that extends from the p-type contact layer 60 to the light-emitting layer 35 in the thickness direction. Since hydrogen ions pass straight through the interstitial sites of the lattice, they deeply penetrate into the semiconductor layer or the like having a regular atomic arrangement. On the other hand, they cannot pass through the mask 70 having a random atomic arrangement. Therefore, the hydrogen ion implantation portion 80 is formed in a portion where the mask 70 is not formed in the in-plane direction. Since the hydrogen ion implantation portion 80 extends from the p-type contact layer 60 to the light-emitting layer 35 in the thickness direction, the hydrogen ion implantation portion 80 divides the light-emitting layer 35 into a hydrogen ion implantation region 33 and a non-implantation region 34. And since hydrogen ions move straight forward without bending midway, the center of the non-implantation region 34 is the same as the opening 42A, and it has a region width B that is the same as the width of the mask width B, and the hydrogen ion implantation region 33 surrounds the non-implantation region 34. Note that as shown in the figure, the hydrogen ion implantation portion 80 can reach the n-type cladding layer 31 and beyond in the thickness direction beyond the light-emitting layer 35.

[0101] In order to reliably reduce the light emission from other than the light release window in the light emission pattern, the dose of hydrogen ions in this process is preferably 1.0×10 13 atoms / cm 2 or more, and more preferably 1.9×10 13 atoms / cm2 The above. In addition, in order to prevent the modification of the mask 70 accompanying the implantation of hydrogen ions, the dose of hydrogen ions in the mask 70 is preferably set to 2.0×10 15 atoms / cm 2 or less, more preferably set to 1.0×10 15 atoms / cm 2 or less. The dose can be appropriately adjusted by adjusting the irradiation time during hydrogen ion implantation, etc. The acceleration voltage of hydrogen ions affects the implantation depth of hydrogen ions. Therefore, it can be appropriately determined according to the formation range in the thickness direction of the hydrogen ion implantation portion 80 and the film thickness of each layer. For example, it can be set to 10 keV to 300 keV.

[0102] <p-Type Electrode Formation Process>

[0103] Refer to Figure 5 S90 and S100 of Figure 5 . After forming the hydrogen ion implantation portion 80, the mask 70 is removed (S90). Next, a p-type electrode 91 having a light release window 92 is formed on the p-type contact layer 60. The center of the light release window 92 is the same as that of the opening 42A, and it has a window opening width C that is equal to or greater than the opening width A of the opening 42A and less than the mask width B (S100). The p-type electrode 91 can be formed by forming a photoresist layer, etc. and using a sputtering method, an electron beam evaporation method, a resistance heating method, etc. In

[0104] S100 of Figure 5 , the p-type electrode 91 is formed to surround the concave portion of the p-type contact layer 60 formed in association with the opening 42A. As long as the relationship between the opening width A, the mask width B, and the window opening width C is satisfied, the formation position is not limited to the example in this figure. The window opening width C is not particularly limited as long as it is equal to or greater than the opening width A of the opening 42A and less than the mask width B. For example, it can be set to 10 μm to 310 μm.

[0104] In addition, if necessary, an n-type electrode 99 can also be formed. Figure 5 In S100 of

[0105] , an n-type electrode 99 is formed on the back surface of the substrate 10, but this is just an example. The formation position can be appropriately determined according to the conductivity type of the substrate 10, etc. The n-type electrode 99 can also be formed by a sputtering method, etc.

[0105] In the point light source type light emitting diode 200 described above, the hydrogen ion implantation portion 80 is formed using the mask width B of the mask 70, and the hydrogen ion implantation portion 80 can be formed relatively simply. And the point light source type light emitting diode obtained in this way can reduce the light emission from outside the light release window 92 in the light emission pattern.

[0106] It should be noted that the embodiments of the manufacturing method of the above point light source type light emitting diode 200 are merely examples for manufacturing the point light source type light emitting diode 100. In order to manufacture the point light source type light emitting diode 100, methods other than the embodiments of the manufacturing method of the above point light source type light emitting diode 200 can be applied as long as its structure can be specifically realized.

[0107] Example

[0108] Hereinafter, the present invention will be described in more detail using examples, but the present invention is not limited to the following examples at all.

[0109] (Example 1)

[0110] According to the reference Figures 2 to 5 in the order, the point light source type light emitting diode described in Example 1 was manufactured. Specifically as follows.

[0111] An n-type GaAs layer (film thickness: 75 nm, initial growth layer) was formed on the (100) surface of an n-type GaAs substrate (substrate thickness: 350 μm). Then, an n-type Al 0.45 Ga 0.55 As layer (film thickness: 48 nm) and an n-type AlAs layer (film thickness: 53 nm) were stacked 20.5 groups (with n-type Al 0.45 Ga 0.55 As layers at both ends) to obtain an n-type DBR layer (total film thickness: 2068 nm). Then, an Se-doped n-type Al 0.5 In 0.5 P cladding layer (film thickness: 148 nm), a three-layer quantum well (3QW) structure light emitting layer (total film thickness: 43 nm) including an undoped In 0.5 Ga 0.5 P layer (film thickness: 8 nm, well layer) and an Al 0.35 Ga 0.15 In 0.5 P layer (film thickness: 5 nm, barrier layer) with a main emission wavelength of 650 nm, and a Mg-doped p-type Al 0.5 In 0.5 P layer (film thickness: 250 nm, p-type cladding layer) were sequentially formed on the n-type DBR layer by MOCVD method.

[0112] Then, an n-type Al 0.5 In 0.5 P layer (film thickness: 20 nm) was formed on the p-type cladding layer, resist patterning was performed, and etching was performed to expose a part of the p-type cladding layer, and a circular opening with an opening width of 80 μm (diameter: 80 μm) was formed to obtain an n-type current confinement layer.

[0113] Next, on the exposed surface of the p-type cladding layer and the n-type current confinement layer, a p-type Al that is uniformly C-doped is formed. 0.45 Ga 0.55 As layer (film thickness: 50 nm) and a p-type Al 0.95 Ga 0.05 As layer (film thickness: 63 nm) are stacked 10.5 groups (with p-type Al 0.45 Ga 0.55 As layers at both ends) to obtain a p-type DBR layer (total film thickness: 1180 nm).

[0114] Furthermore, a p-type contact layer formed of a Zn-doped p-type GaAs layer (film thickness: 20 nm) is formed on the p-type DBR layer.

[0115] Next, on the p-type contact layer, a circular resist mask with a mask width of 180 μm (diameter: 180 μm) is formed on the concentric axis of the opening of the n-type current confinement layer. And, hydrogen ions are implanted from the surface of the p-type contact layer at an acceleration voltage of 145 keV and a dose of 2.0×10 14 atoms / cm 2 to form a hydrogen ion implantation portion. The hydrogen ion implantation portion extends from the p-type contact layer to the n-type cladding layer in the thickness direction.

[0116] Furthermore, after removing the mask, on the p-type contact layer, on the concentric axis of the opening of the n-type current confinement layer, a p-type electrode (electrode material: AuZn alloy) with a light release window having a window opening width of 160 μm (diameter: 160 μm) is formed in a size of 200 μm×350 μm. Thereafter, a mask is applied in a range of 220 μm×370 μm in such a way that the edge is exposed by 10 μm and the p-type electrode is completely covered, and the semiconductor layer on the substrate outside the mask region is removed by etching. In addition, an n-type electrode (electrode material: AuGe alloy) is formed over the entire back surface of the n-type GaAs substrate. After performing heat treatment for forming an ohmic contact, the substrate at the position after removing the semiconductor layer is cut to be in the chip size (250 μm×400 μm) and separated into individual chips. A 10-μm-wide portion around the periphery of the p-contact layer on the top surface of the obtained chip is not covered by the p-type electrode. By operating in this way, the point light source type light-emitting diode described in Example 1 is fabricated.

[0117] (Example 2)

[0118] In Example 1, the mask width for ion implantation was set to 180 μm, the window opening width of the light release window was set to 160 μm, and the hydrogen ion dose was set to 2.0×10 14 atoms / cm 2, except that the mask width was changed to 100 μm, the window opening width was changed to 80 μm, and the hydrogen ion dose was changed to 2.0×10 13 atoms / cm 2 , the same operations as in Example 1 were performed to fabricate the point light source type light emitting diode described in Example 2.

[0119] (Comparative Example 1)

[0120] A hydrogen ion implantation portion was formed in Example 1. Except for not forming this hydrogen ion implantation portion, the same operations as in Example 1 were performed to fabricate the point light source type light emitting diode described in Comparative Example 1.

[0121] (Comparative Example 2)

[0122] A hydrogen ion implantation portion was formed in Example 2. Except for not forming this hydrogen ion implantation portion, the same operations as in Example 2 were performed to fabricate the point light source type light emitting diode described in Comparative Example 2.

[0123] (Evaluation of hydrogen concentration)

[0124] The hydrogen concentration in the depth direction of the hydrogen ion implantation portion in Example 1 was measured by SIMS. The results are shown in the figure of Figure 6 . Figure 6 The horizontal axis of the figure of Figure 6 is relative depth, and the marks of each semiconductor layer are labeled in the depth range corresponding to the p-type cladding layer, the light emitting layer, and the n-type cladding layer. Furthermore, for Example 2 and Comparative Examples 1 and 2, the hydrogen concentration at the same position as in Example 1 was also measured by SIMS. The results of Example 2 and Comparative Example 1 are shown together in the figure of 17 atoms / cm 3 . Since the hydrogen concentration in the light emitting layer is the same, the figure of Comparative Example 2 in Figure 6 is omitted. In Example 1, the hydrogen concentration in the hydrogen ion implantation region of the light emitting layer was 5.0×10 18 atoms / cm 3 , and in Example 2, the hydrogen concentration in the hydrogen ion implantation region of the light emitting layer was 6.0×10 17 atoms / cm 3 . In addition, different from Figure 6 , as a result of measuring the hydrogen concentration in the non-implanted region of hydrogen ions in the light emitting layers of Examples 1 and 2 by SIMS, the hydrogen concentration in the non-implanted regions of Examples 1 and 2 was at the same level as that of Comparative Examples 1 and 2 without hydrogen ion implantation.

[0125] (Evaluation of luminous intensity distribution)

[0126] The point light source type light emitting diode described in Example 1 was operated by pulse driving (pulse forward current Ifp: 300 mA, frequency: 10 kHz, duty ratio: 1.0%). The light emission intensity distribution of the cross section including the opening part at this time is shown in Figure 7 . In addition, in order to emphasize the light emission, a photograph was taken when the point light source type light emitting diode described in Example 1 was made to emit light with a DC current of 1 mA. The relative position in the figure of the taken photograph was made to correspond to Figure 7 , and they are shown together in Figure 7 . It should be noted that Figure 7 in the vertical axis of the figure represents the light emission intensity (relative intensity), and the horizontal axis represents an arbitrary relative position of the cross section. Similarly, the light emission intensity distribution was also measured for the point light source type light emitting diode described in Comparative Example 1, and a photograph was taken during light emission at the same time. The results are shown in Figure 8 . Furthermore, for Example 2 and Comparative Example 2, photographs of light emission were taken when the DC current was 1 mA. The results are shown in Figure 9 and Figure 10 respectively.

[0127] When comparing Figures 7 to 10 , it can be confirmed that: in Examples 1 and 2, most of the light emission is emitted from the opening part. On the other hand, in Comparative Examples 1 and 2, light also slightly leaks from outside the opening part (the outer periphery of the p - contact layer not covered by the p - electrode). It can be confirmed that by providing the hydrogen ion implantation part, it is possible to reduce the light emission from outside the light release window in the light emission pattern of the point light source type light emitting diode.

[0128] Industrial Applicability

[0129] According to the present invention, it is possible to provide a point light source type light emitting diode and a manufacturing method thereof that can simplify the manufacturing process and reduce the light emission from outside the light release window in the light emission pattern.

[0130] Explanation of Reference Numerals

[0131] 10 Substrate

[0132] 21 Buffer layer

[0133] 23 n - type DBR layer

[0134] 31 n - type cladding

[0135] 33 Hydrogen ion implantation region

[0136] 34 Non - implantation region

[0137] 35 Light emitting layer

[0138] 37 p - type cladding

[0139] Exposed surface of the 37A p-type cladding

[0140] 41 n-type current confinement layer

[0141] 42 n-type current confinement layer

[0142] 42A Opening

[0143] 50 p-type DBR layer

[0144] 60 p-type contact layer

[0145] 70 Mask

[0146] 80 Hydrogen ion implantation region

[0147] 91 p-type electrode

[0148] 92 Light release window

[0149] 99 n-type electrode

[0150] 100 Point light source light emitting diode

[0151] 200 Point light source light emitting diode

Claims

1. A point light source type light emitting diode, characterized in that, It includes: a substrate; an n-type cladding layer on the substrate; a light-emitting layer on the n-type cladding layer; a p-type cladding layer on the light-emitting layer; an n-type current confinement layer disposed on the p-type cladding layer and having an opening portion exposing a part of the p-type cladding layer; a p-type contact layer disposed on the exposed surface of the p-type cladding layer and on the n-type current confinement layer; a p-type electrode disposed on the p-type contact layer and having a light release window with the same center as the opening portion; The light-emitting layer is represented by the general formula (In a Ga b Al c )(P x As y Sb z ), where, for group III elements, c = 1 - a - b, 0 ≤ a ≤ 1, 0 ≤ b ≤ 1, 0 ≤ c ≤ 1, and for group V elements, z = 1 - x - y, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1. the window opening width of the light release window is equal to or greater than the opening width of the opening portion; the point light source type light-emitting diode has a hydrogen ion implantation portion extending from the p-type contact layer to the light-emitting layer in the thickness direction; the light-emitting layer has a non-implantation region and a hydrogen ion implantation region. The center of the non-implantation region is the same as that of the light release window, and it has a region width larger than the window opening width of the light release window. The hydrogen ion implantation region surrounds the non-implantation region; The hydrogen concentration in the hydrogen ion implantation region is 5.0×10 17 atoms / cm 3 or more, and the hydrogen concentration in the non-implanted region is 2.0×10 17 atoms / cm 3 or less.

2. The point light source type light emitting diode according to claim 1, wherein, the hydrogen concentration in the hydrogen ion implantation region in the light-emitting layer is 3.0 times or more that in the non-implantation region; 3. The point light source type light emitting diode according to claim 2, wherein, The hydrogen concentration in the hydrogen ion implantation region is 2.0×10 19 atoms / cm 3 or less.

4. A manufacturing method of a point light source type light emitting diode, characterized in that, It includes the following steps: A semiconductor layer forming step of sequentially forming an n-type cladding layer, a light-emitting layer, a p-type cladding layer, and an n-type semiconductor layer on a substrate, wherein the light-emitting layer is represented by the general formula (In a Ga b Al c )(P x As y Sb z ), where, with respect to group III elements, c = 1 - a - b, 0 ≤ a ≤ 1, 0 ≤ b ≤ 1, 0 ≤ c ≤ 1, and with respect to group V elements, z = 1 - x - y, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1; an n-type current confinement layer formation step of forming an opening portion with an opening width A in the n-type semiconductor layer to form an n-type current confinement layer exposing a part of the p-type cladding layer; a p-type contact layer formation step of forming a p-type contact layer on the exposed surface of the p-type cladding layer and on the n-type current confinement layer; a mask formation step of forming a mask with the same center as the opening portion and a mask width B on the p-type contact layer; a hydrogen ion implantation step of implanting hydrogen ions from the surface of the p-type contact layer to form a hydrogen ion implantation portion extending from the p-type contact layer to the light-emitting layer in the thickness direction; and a p-type electrode formation step of removing the mask, and then forming a p-type electrode with a light release window on the p-type contact layer. The center of the light release window is the same as that of the opening portion, and it has a window opening width C that is equal to or greater than the opening width A of the opening portion and less than the mask width B. The hydrogen concentration in the hydrogen ion implantation region is 5.0×10 17 atoms / cm 3 or more.

5. The manufacturing method of a point light source type light emitting diode according to claim 4, wherein, The dose of hydrogen ions in the hydrogen ion implantation process is 1.0×10 13 atoms / cm 2 or more.

6. The manufacturing method of a point light source type light emitting diode according to claim 5, wherein, The dose of hydrogen ions in the hydrogen ion implantation process is 2.0×10 15 atoms / cm 2 or less.

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