A system and method for improving the accuracy of SPAD laser radar

Abstract

The present invention relates to the field of laser ranging technology, and in particular to a system and method for improving the accuracy of a SPAD laser radar, comprising a clock unit for providing a clock signal, characterized in that it also includes a phase-locked loop circuit, a TDC data bit-filling module and a data comparison circuit; the phase-locked loop circuit includes a clock input port and a clock output port for outputting two n The clock signal output port of the phase-locked loop circuit is connected to the clock unit, 2 n The clock signal output ports are connected to 2 n The TDC data filling module is used to fill in the 2 n The output end of the TDC circuit adds a TDC clock identification code of different phases, the output end of the TDC data filling module is connected to the input end of the data comparison circuit; the output end of the data comparison circuit outputs a signal with 2 n The present invention can multiply the TDC resolution without increasing the main frequency.

Description

Technical Field

[0001] The present invention relates to the field of laser ranging technology, and in particular to a system and method for improving the accuracy of a SPAD laser radar. Background Art

[0002] Currently, lidar systems generally consist of a laser emission system, an optical control system, an echo reception system, and a processing system. LiDAR technology actively transmits a laser beam, which, after passing through the optical control system, strikes the object being measured, generating a diffusely reflected echo. This echo is then received by a receiving system, which primarily consists of various photodetectors, such as CCD light sensors, CMOS sensors, PD photodiodes, APD avalanche diodes, and SPADs. LiDARs based on SPAD (Single Photon Avalanche Diode) array detectors offer significant advantages and broad prospects due to their high sensitivity and extended range.

[0003] The receiving system of a SPAD-based lidar includes a SPAD array. Each pixel in the array is a basic optical sensing unit. Under an external high voltage differential, it enters an avalanche state. In this state, the pixel is excited by signal light and outputs a value of "1". If it is not excited, it outputs nothing or a value of "0". The SPAD chip is connected to a TDC module (Time Distance Converter). During a measurement cycle, the lidar emits N laser pulses toward the target area. With each laser pulse, the lidar's internal clock starts counting. The TDC module records the output time of the SPAD chip and, after N laser pulses have been emitted, generates a histogram. The time corresponding to the highest value in the histogram is selected. This represents the timing signal difference and time difference between when the light source emitted the light and when the photodetector detected the image light. The distance to the measured object is directly calculated using the formula: S = speed of light × time difference / 2. This eliminates the signal transformation process from the photosensitive element's light signal to analog signal and then to digital signal, thereby achieving higher efficiency.

[0004] The existing TDC circuit modules mainly include dual-port RAM structure and dual RAM structure.

[0005] Circuit such as Figure 1 As shown, the dual RAM structure TDC circuit is as follows Figure 2As shown. Since the 500MHz master clock is used for time measurement, the time resolution of Tof (Time Offlight, light flight time) is one clock unit (CLOCK), that is, 2ns. Since the flight distance of 2ns light is about 30cm, the laser radar resolution is about 30cm. The time measurement value is also used to generate the address signal of RAM. Therefore, the measurement result of Tof time is the address value corresponding to the unit with the highest value in RAM, as shown Figure 1 and Figure 2 The resolution of this TDC circuit is limited by the unit length of the clock cycle. In applications requiring high resolution, a 30 cm resolution is too coarse.

[0006] The current practice is usually to directly improve the main frequency by increasing the Figure 1 The dual-port RAM structure TDC circuit shown in FIG. Figure 2 The resolution of the dual RAM structure TDC circuit shown in the figure. However, the increase in main frequency is limited by the characteristics of components and will significantly increase the circuit cost. Summary of the Invention

[0007] To solve the above problems, the present invention proposes a system and method for improving the accuracy of SPAD laser radar, which can improve the distance resolution without increasing the main frequency.

[0008] The technical solution adopted by the present invention to solve its technical problem is:

[0009] The first aspect of the present invention provides a system for improving the accuracy of a SPAD laser radar, comprising a clock unit for providing a clock signal, a phase-locked loop circuit, a TDC data bit-filling module, and a data comparison circuit;

[0010] The phase-locked loop circuit includes a clock input port and two output ports. n The clock signal output port of the phase-locked loop circuit is connected to the clock unit, 2 n The clock signal output ports are connected to 2 n The input terminals of the TDC data filling modules are connected;

[0011] The TDC data filling module is used to n The output end of each TDC circuit is added with a TDC clock identification code of a different phase, and the output end of the TDC data filling module is connected to the input end of the data comparison circuit;

[0012] The output terminal of the data comparison circuit has a 2 n Clock address information of times the resolution value.

[0013] As a technical solution of the present invention, the identification code string is composed of n-bit binary data arranged in sequence.

[0014] A second aspect of the present invention provides a method for improving the resolution of a SPAD laser radar, comprising the following steps:

[0015] Step S01: The laser radar emits a laser pulse, and at the same time, the laser radar clock sends a start timing signal to the phase-locked loop circuit;

[0016] Step S02: The phase-locked loop circuit receives a timing start signal and starts the 0-degree phase TDC circuit to start timing. Start the TDC circuit corresponding to the corresponding clock signal output port until 2 n 2 corresponding to the clock signal output port n All TDC circuits are started up;

[0017] Step S03, the TDC data filling module is connected to 2 n The identification code is added to the output end of each TDC circuit. The identification code is composed of n-bit binary data arranged in sequence. n Identification code and 2 n The clock signals correspond one to one;

[0018] Step S04: the 2 n The TDC data is input to the comparator, which first selects the clock address corresponding to the maximum value in each TDC circuit, wherein each clock address contains 2 n phases;

[0019] Step S05: the comparator compares the clock addresses corresponding to the maximum values in each TDC circuit, and selects the phase with the largest number in the clock addresses as the final output result. The output result has 2 n Clock address information of times the resolution value.

[0020] As a technical solution of the present invention, the timing signal starts in step S01 and acts on both n When a TDC circuit is activated and the TDC circuit starts timing, the counter is cleared.

[0021] As a technical solution of the present invention, 2 n After the TDC circuit is started, the laser radar echo signal is measured simultaneously.

[0022] The above technical solution of the present invention has the following beneficial technical effects:

[0023] The present invention connects the clock unit via the clock input port of the phase-locked loop circuit, 2 nThe clock signal output ports are connected to 2 n The TDC data filling module input terminal is 2 n The output end of each TDC circuit is added with a TDC clock identification code of different phases, and the output end of the TDC data filling module is connected to the input end of the data comparison circuit, so that the output of the data comparison circuit has 2 n The clock address information of the resolution value can be multiplied to improve the TDC resolution without increasing the main frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a dual-port RAM structure TDC circuit in the prior art;

[0025] Figure 2 It is a dual RAM structure TDC circuit in the prior art;

[0026] Figure 3 This is an example of Example 1 of the present invention. Figure 1 ;

[0027] Figure 4 This is an example of Example 1 of the present invention. Figure 2 ;

[0028] Figure 5 This is a schematic diagram of Example 2 of the present invention;

[0029] Figure 6 This is a schematic diagram of Example 3 of the present invention. DETAILED DESCRIPTION

[0030] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further described below in conjunction with specific embodiments and drawings, but the following embodiments are only preferred embodiments of the present invention, not all. Based on the embodiments in the implementation manner, other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.

[0031] Example 1

[0032] A system for improving the accuracy of a SPAD laser radar includes a clock unit for providing a clock signal, a phase-locked loop circuit, a TDC data bit-filling module, and a data comparison circuit; the phase-locked loop circuit includes a clock input port and a clock output port. n The clock signal output port of the phase-locked loop circuit is connected to the clock unit, 2 n The clock signal output ports are connected to 2 nThe TDC data filling module is used to fill in the 2 n The output end of each TDC circuit adds a TDC clock identification code of different phases, and the identification code string is composed of n-bit binary data arranged in sequence. The output end of the TDC data filling module is connected to the input end of the data comparison circuit; the output end of the data comparison circuit outputs a 2 n The clock address information of the multiple resolution value. (n≥1).

[0033] refer to Figure 3 In this embodiment, n=2, the data comparison circuit output has a quadruple resolution, and the phase-locked loop circuit PLL has four clock signal output ports, which respectively output clock signals with a phase of 0 degrees, a phase of 90 degrees, a phase of 180 degrees, and a phase of 270 degrees. Accordingly, four Tof end padding modules are provided.

[0034] In this embodiment, the method for improving the resolution of a SPAD laser radar includes the following steps:

[0035] Step S01: The laser radar emits a laser pulse, and at the same time, the laser radar clock sends a start timing signal (ST) to the phase-locked loop circuit;

[0036] Step S02: The phase-locked loop circuit receives a timing start signal, starts the 0-degree phase TDC circuit to start timing, and starts the TDC circuit corresponding to the corresponding clock signal output port every 90 degrees until all four TDC circuits corresponding to the four clock signal output ports are started.

[0037] Step S03: The TDC data padding module adds identification codes to the output tails (RAM clock addresses) of the four TDC circuits. The identification codes are composed of two-bit binary data arranged in sequence, namely 00 / 01 / 10 / 11. The four identification codes correspond to the four clock signals one-to-one.

[0038] Step S04: The four TDC data after being padded by the TDC data padding module are input to a comparator. The comparator first selects a clock address corresponding to the maximum value in each TDC circuit, wherein each clock address includes four phases.

[0039] In step S05 , the comparator compares the clock addresses corresponding to the maximum values in each TDC circuit, and selects the phase with the largest number in the clock addresses as the final output result. The output result has clock address information with a 4-fold resolution value.

[0040] Furthermore, in step S01, when the start timing signal acts on the four TDC circuits simultaneously and the TDC circuits start timing, the counter is reset to zero. After the four TDC circuits are started, they measure the laser radar's echo signal simultaneously.

[0041] refer to Figure 4 While maintaining a constant main frequency of 500MHz (2ns clock), the system is divided into four identical TDC circuits via a phase-locked loop (PLL) to form a TDC array. Each clock unit is simultaneously divided into four identical phases. When the lidar emits a laser pulse, the four TDC circuits simultaneously detect the echo signal, differing only in phase (start time). When the lidar laser strikes the object, the reflected light is detected by the four TDC circuits. The resulting histogram peaks are located at addresses 3&00 for the 0-phase TDC circuit, 3&01 for the 90-phase TDC circuit, 2&10 for the 180-phase TDC circuit, and 2&11 for the 270-phase TDC circuit. The comparator selects the phase with the largest number of time addresses as the final output, which is the 90-phase of clock 3. This achieves four times the resolution of the original TDC.

[0042] Example 2

[0043] refer to Figure 5 , which is different from Example 1:

[0044] In this embodiment, n=1, the clock signal generated by the clock unit is input into the phase-locked loop circuit PLL, and the phase-locked loop circuit PLL has two clock signal output ports. The two clock signal output ports respectively output a clock signal with a phase of 0 degree and a clock address signal with a phase of 180 degrees. The two clock signal output ports of the phase-locked loop circuit PLL are respectively connected to the Tof end padding module (TDC data padding module), which are 0 and 1 respectively. Through the Tof end padding module, the outputs of the two Tof end padding modules are connected to the input end of the data comparator, and the output end of the data comparator outputs a clock signal with a 2 times resolution value.

[0045] Example 3,

[0046] refer to Figure 6 , which is different from Examples 1 and 2:

[0047] In this embodiment, n=3, the phase-locked loop circuit PLL has 8 clock signal output ports, and the 8 clock signal output ports respectively output a clock signal with a phase of 0 degrees, a clock signal with a phase of 45 degrees, a clock signal with a phase of 90 degrees, a clock signal with a phase of 135 degrees, a clock signal with a phase of 180 degrees, a clock signal with a phase of 225 degrees, a clock signal with a phase of 270 degrees, and a clock signal with a phase of 315 degrees. Four Tof end padding modules are provided accordingly. A terminal binary serial number can be added after each Tof measurement value (RAM address), which is 000, 001, 010, 011, 100, 101, 110, 111.

[0048] The present invention improves the TDC resolution by multiples without increasing the main frequency. In actual tests, under the premise of 500MHz counter and RAM clock, the 4-fold TDC measurement resolution is about 7cm, and the 8-fold resolution is about 4cm.

[0049] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely preferred examples of the present invention and are not intended to limit the present invention. Various changes and improvements may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and improvements fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for improving the resolution of a SPAD laser radar, wherein the system for improving the accuracy of the SPAD laser radar includes a clock unit for providing a clock signal, a phase-locked loop circuit, a TDC data bit-filling module, and a data comparison circuit; The phase-locked loop circuit includes a clock input port and two output ports. n The clock signal output port of the phase-locked loop circuit is connected to the clock unit, 2 n The clock signal output ports are connected to 2 n The input terminals of the TDC data filling modules are connected; The TDC data filling module is used to n The output end of each TDC circuit is added with a TDC clock identification code of a different phase, and the output end of the TDC data filling module is connected to the input end of the data comparison circuit; The output terminal of the data comparison circuit has a 2 n Clock address information of times the resolution value; It is characterized by: The steps include: Step S01: The laser radar emits a laser pulse, and at the same time, the laser radar clock sends a start timing signal to the phase-locked loop circuit; Step S02: The phase-locked loop circuit receives a timing start signal and starts the 0-degree phase TDC circuit to start timing. Start the TDC circuit corresponding to the corresponding clock signal output port until 2 n 2 corresponding to the clock signal output port n All TDC circuits are started up; Step S03, the TDC data filling module is connected to 2 n The identification code is added to the output end of each TDC circuit. The identification code is composed of n-bit binary data arranged in sequence. n Identification code and 2 n The clock signals correspond one to one; Step S04: the 2 n The TDC data is input to the comparator, which first selects the clock address corresponding to the maximum value in each TDC circuit, wherein each clock address contains 2 n phases; Step S05: the comparator compares the clock addresses corresponding to the maximum values in each TDC circuit, and selects the phase with the largest number in the clock addresses as the final output result. The output result has 2 n Clock address information of times the resolution value.

2. A method for improving the resolution of a SPAD laser radar according to claim 1, characterized in that: The identification code string is composed of n-bit binary data arranged in sequence.

3. The method for improving the resolution of a SPAD laser radar according to claim 1, wherein: In step S01, the timing signal starts acting on both n When a TDC circuit is activated and the TDC circuit starts timing, the counter is cleared.

4. The method for improving the resolution of a SPAD laser radar according to claim 1, wherein: 2 n After the TDC circuit is started, the laser radar echo signal is measured simultaneously.

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