Time-interleaved sampling method, apparatus, device, and storage medium
By performing phase-frequency analysis and fractional delay deviation compensation on the sub-channel signals, the sampling time mismatch problem of ideal time-interleaved ADC under high-frequency signals is solved, improving sampling accuracy and expanding the frequency application range.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 迅芯微电子(苏州)股份有限公司
- Filing Date
- 2022-02-11
- Publication Date
- 2026-06-16
Smart Images
Figure CN114553228B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of signal sampling technology, specifically to a time-interleaved sampling method, apparatus, device, and storage medium. Background Technology
[0002] High-speed analog-to-digital converters (ADCs) have a wide range of applications and promising prospects. Currently, ADCs are a very hot field.
[0003] For an ideal time-interleaved ADC (TI ADC), the m sub-channels of the ADC sample at equal intervals, meaning the sampling time of adjacent sub-channels is 1 / m clock cycles apart. However, in practice, TI ADCs suffer from sampling time mismatch, meaning that the actual ADC does not sample at equal intervals; the sampling time of adjacent sub-channels is (1 / m + Δ) clock cycles apart. To eliminate sampling time mismatch, the industry common practice is to adjust the clock line in the analog domain or use variable delay devices. However, for ultra-high-speed TI ADC analog devices, there are issues with adjustment accuracy and instability, limiting its applicability. In this case, a method can be used to compensate for the fractional delay deviation of the signal in the digital domain. The fractional interval is the difference between the signal of each sub-channel and the target time within the same time period. After calculating the deviation of the fractional interval, the actual fractional delay deviation can be compensated, thus ensuring that the TI ADC samples according to the specified fractional interval. This method offers higher adjustment accuracy and greater stability.
[0004] In the above scheme, the fractional interval between each sub-channel ADC is usually set as the sampling interval. When sampling high-frequency signals, the sampling interval is no longer the ideal fractional interval, and the accuracy of the signal obtained by interleaving sampling is low. Summary of the Invention
[0005] This application provides a time-interleaved sampling method, apparatus, device, and storage medium, which increases the frequency range applicable to an ideal time-interleaved ADC. The technical solution is as follows.
[0006] On the one hand, this application provides a time-interleaved sampling method, the method comprising:
[0007] The signals output by each sub-channel are acquired, and phase frequency analysis is performed on each sub-channel signal to obtain the phase frequency characteristics corresponding to each sub-channel signal; the phase frequency characteristics include phase characteristics and frequency characteristics.
[0008] Based on the phase frequency characteristics corresponding to each sub-channel signal, calculate the actual fractional interval corresponding to each sub-channel.
[0009] Based on the frequency characteristics of each sub-channel signal, the ideal fractional interval corresponding to each sub-channel is obtained.
[0010] Based on the ideal decimal interval and the actual decimal interval corresponding to each sub-channel, extract the decimal delay deviation corresponding to each sub-channel.
[0011] Based on the fractional delay deviation corresponding to each sub-channel, fractional delay deviation compensation is performed on the analog-to-digital converter chip of each sub-channel to calibrate the time interleaving sampling results of the analog-to-digital converter chip of each sub-channel.
[0012] In another aspect, a time-interleaved sampling device is provided, the device comprising:
[0013] The phase frequency analysis module is used to acquire the signals output by each sub-channel and perform phase frequency analysis on each sub-channel signal to obtain the phase frequency characteristics corresponding to each sub-channel signal; the phase frequency characteristics include phase characteristics and frequency characteristics.
[0014] The actual interval acquisition module is used to calculate the actual fractional interval corresponding to each sub-channel based on the phase frequency characteristics corresponding to each sub-channel signal.
[0015] The ideal interval acquisition module is used to acquire the ideal fractional interval corresponding to each sub-channel based on the frequency characteristics corresponding to each sub-channel signal.
[0016] The delay deviation extraction module is used to extract the decimal delay deviation corresponding to each sub-channel based on the ideal decimal interval and the actual decimal interval corresponding to each sub-channel.
[0017] The time delay deviation compensation module is used to compensate the decimal time delay deviation of the analog-to-digital converter chip of each sub-channel according to the decimal time delay deviation corresponding to each sub-channel, so as to calibrate the time interleaving sampling results of the analog-to-digital converter chip of each sub-channel.
[0018] In one possible implementation, the ideal interval acquisition module is further configured to:
[0019] When the frequency characteristics of the sub-channel signal are less than the target threshold, the target ideal fractional interval is obtained.
[0020] In one possible implementation, the target ideal fractional interval is the ratio of the target time period to the number of sub-channels; the target time period is the time period of the analog-to-digital converter chip.
[0021] In one possible implementation, the ideal interval acquisition module further includes:
[0022] An ideal signal reconstruction unit is used to construct the phase of the ideal signal of each sub-channel according to the ratio of the frequency characteristics of each sub-channel signal to the target sampling rate when the frequency characteristics of each sub-channel signal are greater than the target threshold, so as to generate each ideal sub-channel signal.
[0023] The main frequency phase acquisition unit is used to perform phase frequency analysis on each ideal sub-channel signal to obtain the main frequency phase of each ideal sub-channel.
[0024] An ideal interval acquisition unit is used to acquire the ideal fractional interval based on the main frequency phase of each ideal sub-channel.
[0025] In one possible implementation, the ideal signal reconstruction unit is further used for,
[0026] For each sub-channel signal, obtain the frequency characteristics and the target ratio of the target sampling rate;
[0027] The phase of the ideal signal of the sub-channel is constructed by multiplying the target ratio by the ideal sampling time; the ideal sampling time includes the ideal sampling time of the sub-channel signal in each time period; the sampling time interval between the ideal sampling times of each sub-channel in each time period is the ratio of the clock period to the number of sub-channels.
[0028] The ideal sub-channel signal is constructed based on the phase and amplitude of the ideal signal of the sub-channel.
[0029] In one possible implementation, the phase frequency analysis is a Fast Fourier Transform (FFT) analysis.
[0030] In one possible implementation, the time delay deviation extraction module is further configured to:
[0031] For each sub-channel, the difference between the ideal decimal interval corresponding to the sub-channel and the actual decimal interval corresponding to the sub-channel is used to obtain the decimal delay deviation corresponding to the sub-channel.
[0032] In another aspect, a computer device is provided, the computer device including a processor and a memory, the memory storing at least one instruction, at least one program, code set or instruction set, the at least one instruction, at least one program, code set or instruction set being loaded and executed by the processor to implement the above-described time-interleaved sampling method.
[0033] In another aspect, a computer-readable storage medium is provided, wherein at least one instruction is stored therein, the at least one instruction being loaded and executed by a processor to implement the time-interleaved sampling method described above.
[0034] The technical solution provided in this application may include the following beneficial effects:
[0035] When controlling an ideal time-interleaved ADC to perform interleaved sampling, the signals of each sub-channel can be acquired first, and phase-frequency analysis can be performed on the sub-channel signals to obtain their phase and frequency characteristics. The phase difference between each sub-channel is then the actual fractional time delay deviation between them at the current moment. Next, the ideal fractional interval at that frequency is calculated using the frequency characteristics of each sub-channel signal. The ideal fractional interval is compared with each actual fractional interval to calculate the fractional time delay deviation. This deviation is then used to compensate for the fractional time delay deviation in the sub-channel ADC, allowing the compensated sub-channel ADC to perform time-interleaved sampling according to the ideal fractional interval. In this scheme, the corresponding ideal fractional interval is determined based on the frequency characteristics of the sub-channel signals. Different ideal time intervals can be used at low and high frequencies, ensuring that the ideal time-interleaved ADC can be compensated to the ideal time interval at different frequencies, thus increasing the applicable frequency range of the ideal time-interleaved ADC. Attached Figure Description
[0036] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0037] Figure 1 This is a schematic diagram illustrating the structure of a time-interleaved sampling system according to an exemplary embodiment of this application.
[0038] Figure 2 This is a flowchart illustrating a time-interleaved sampling method according to an exemplary embodiment of this application.
[0039] Figure 3 This is a flowchart illustrating a time-interleaved sampling method according to an exemplary embodiment of this application.
[0040] Figure 4 A block diagram of a decimal delay extraction system according to an embodiment of this application is shown.
[0041] Figure 5A flowchart illustrating a decimal delay extraction process according to an embodiment of this application is shown.
[0042] Figure 6 This is a structural block diagram of a time-interleaved sampling apparatus according to an exemplary embodiment.
[0043] Figure 7 This is a schematic diagram of a computer device provided according to an exemplary embodiment of this application. Detailed Implementation
[0044] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0045] It should be understood that the term "instruction" mentioned in the embodiments of this application can be a direct instruction, an indirect instruction, or an indication of a relationship. For example, A instructing B can mean that A directly instructs B, such as B being able to obtain information through A; it can also mean that A indirectly instructs B, such as A instructing C, so B can obtain information through C; or it can mean that there is a relationship between A and B.
[0046] In the description of the embodiments of this application, the term "correspondence" may indicate that there is a direct or indirect correspondence between two things, or that there is an association between two things, or that there is a relationship of instruction and being instructed, configuration and being configured, etc.
[0047] In the embodiments of this application, "predefined" can be achieved by pre-storing corresponding codes, tables or other means that can be used to indicate relevant information in the device (e.g., including terminal devices and network devices). This application does not limit the specific implementation method.
[0048] Figure 1 This is a schematic diagram illustrating the structure of a time-interleaved sampling system according to an exemplary embodiment of this application. Figure 1 As shown, the time-interleaved sampling system includes a time-interleaved sampling chip 101 and a data processing device 102.
[0049] Optionally, the time-interleaved sampling chip has multiple ADCs, that is, multiple sub-channel ADCs. For the multiple ADCs on the time-interleaved sampling chip, the sub-channel ADCs will sample alternately and combine the sampled digital signals to achieve high-frequency sampling of the signal through multiple low-frequency ADCs.
[0050] In order to achieve alternating sampling of multiple ADCs on a time-interleaved sampling chip, a clock link can be set up to construct the chip's clock signal into clock signals of each ADC with the same frequency but different phases, thereby controlling the ADCs of different sub-channels to perform sampling operations according to their respective clock signals.
[0051] For example, when there are four ADCs on the time-interleaved sampling chip, a clock link can be set on the time-interleaved sampling chip to construct the clock signal into four ADC clock signals with a phase difference of 90 degrees, that is, the phases are 0°, 90°, 180° and 270° respectively. At this time, within one clock cycle, the four ADCs sample at 1 / 4 clock cycle intervals, and the sampled digital signals are spliced in time order to obtain the time-interleaved sampling result required by the time-interleaved sampling chip.
[0052] However, in practical applications, the multi-channel ADCs in the ideal time-interleaved sampling chip described above may experience sampling time mismatch. That is, the actual ADCs do not sample at equal intervals; the sampling time of adjacent sub-channel ADCs may be separated by (1 / m + Δ) clock cycles, where m is the number of ADC channels. Therefore, in existing technical solutions, the industry common practice is to adjust the clock line in the analog domain or use variable delay devices for adjustment. However, this approach suffers from adjustment accuracy and instability issues with ultra-high-speed TI ADC analog devices, limiting its applicability.
[0053] Another approach is to directly compensate for the fractional time delay deviation of the signal in the digital domain corresponding to the digital signal acquired by the multi-channel ADC. By performing a phase shift operation on the acquired digital signal, the phase-shifted digital signals are combined to fit the sampling result under the ideal state.
[0054] According to the Nyquist sampling theorem, if the input signal frequency is less than half of the sub-channel sampling rate (Nyquist zone 1 signal), the ideal fractional interval corresponding to the digital signals of adjacent sub-channels is equal to the sampling interval 1 / m. Therefore, by adjusting the ideal fractional interval corresponding to the digital signals of adjacent sub-channels to 1 / m, the time-interleaved sampling result obtained by combining the digital signals of each sub-channel can be as close as possible to the result acquired by the time-interleaved sampling chip under ideal conditions.
[0055] However, for high-frequency signals, if the input signal frequency is higher than half of the sub-channel sampling rate (i.e., Nyquist 2 zone signal), signal aliasing will occur when the ADC alternates sampling. In this case, the ideal fractional interval corresponding to the digital signals of adjacent sub-channels will no longer be equal to 1 / m, and will exhibit a non-linear relationship. In this embodiment, the data processing device 102 performs FFT analysis on the acquired sub-channel signals and calculates the ideal fractional interval of the sub-channel under the current condition based on the analysis results. The digital signals sampled by each ideal sub-channel are then phase-shifted according to the ideal sub-channel signal interval. This ensures that the time-interleaved sampling result obtained by combining the digital signals of each sub-channel is as close as possible to the result acquired by the time-interleaved sampling chip under ideal conditions.
[0056] Figure 2 This is a flowchart illustrating a time-interleaving sampling method according to an exemplary embodiment of this application. The time-interleaving sampling method can be performed by, for example... Figure 1 The time-interleaving sampling system shown is executed. The data processing device in this time-interleaving sampling system can perform time delay compensation on the sub-channels of the time-interleaving sampling system through the following steps, thereby realizing the time-interleaving sampling process. The method shown in the embodiment of this application includes:
[0057] Step 201: Obtain the signals output by each sub-channel, and perform phase frequency analysis on each sub-channel signal to obtain the phase frequency characteristics corresponding to each sub-channel signal.
[0058] The phase-frequency characteristics include both phase characteristics and frequency characteristics.
[0059] In this embodiment of the application, the sub-channel signals output by the above-mentioned sub-channels are digital signals. When the data processing device acquires the sub-channel signals, it can perform discrete Fourier analysis on each sub-channel signal to obtain the phase characteristics and frequency characteristics corresponding to each sub-channel signal.
[0060] Step 202: Calculate the actual fractional interval corresponding to each sub-channel based on the phase frequency characteristics of each sub-channel signal.
[0061] After obtaining the phase frequency characteristics of each sub-channel, the actual fractional interval of each sub-channel can be calculated based on the phase characteristics of each sub-channel signal.
[0062] Taking the time-interleaved sampling system of this application embodiment, which includes four ADCs (i.e., ADC1, ADC2, ADC3 and ADC4), as an example, ADC1 can be used as the reference ADC, that is, the phase of ADC1 is used as the reference phase. The phase of ADC2 is compared with that of ADC1, and the phase difference between ADC2 and ADC1 is calculated. Based on the phase difference and frequency, the actual fractional interval between ADC2 and ADC1 can be calculated as the actual fractional interval between ADC2.
[0063] Similarly, by comparing the phase of ADC3 with that of ADC2, the phase difference between ADC3 and ADC2 is calculated. Based on the phase difference and frequency, the actual decimal interval between ADC3 and ADC2 can be calculated as the actual decimal interval corresponding to ADC3. Similarly, by comparing the phase of ADC4 with that of ADC3, the phase difference between ADC4 and ADC3 is calculated. Based on the phase difference and frequency, the actual decimal interval between ADC4 and ADC3 can be calculated as the actual decimal interval corresponding to ADC4.
[0064] Step 203: Based on the frequency characteristics of each sub-channel signal, obtain the ideal fractional interval corresponding to each sub-channel.
[0065] After obtaining the phase frequency characteristics of each sub-channel, the ideal fractional interval of each sub-channel can be calculated based on the frequency characteristics of each sub-channel signal.
[0066] Optionally, in this embodiment, since each sub-channel signal is a data signal acquired by a multi-channel ADC in a time-interleaved sampling chip to achieve the time-interleaved sampling function, and the clock signal used by the multi-channel ADC is a clock signal with the same frequency but different phases, the frequencies of each sub-channel signal are the same.
[0067] Optionally, in this embodiment of the application, when the data processing device obtains the frequency characteristics corresponding to each sub-channel signal, it can first compare the frequency corresponding to the sub-channel signal with the sampling frequency corresponding to the sub-channel to determine whether the frequency corresponding to the sub-channel signal is in the Nyquist 1 region. When the frequency corresponding to the sub-channel signal is in the Nyquist 1 region, 1 / m clock cycle can be directly used as the ideal fractional interval corresponding to each sub-channel signal.
[0068] When the data processing device determines that the frequency corresponding to the sub-channel signal is not in the Nyquist zone 1, the data processing device needs to further analyze and process the frequency of the sub-channel signal to obtain the ideal fractional interval corresponding to each sub-channel signal at that frequency.
[0069] Step 204: Extract the decimal delay deviation corresponding to each sub-channel based on the ideal decimal interval and the actual decimal interval corresponding to each sub-channel.
[0070] Once the ideal fractional interval and the actual fractional interval for each sub-channel are obtained, the difference between the ideal fractional interval and the actual fractional interval for each sub-channel can be used to obtain the fractional delay deviation for each sub-channel. This fractional delay deviation refers to the offset amount of the signal acquired by the sub-channel in the time domain.
[0071] Step 205: Based on the fractional delay deviation corresponding to each sub-channel, perform fractional delay deviation compensation on the analog-to-digital converter chip of each sub-channel to calibrate the time interleaving sampling results of the analog-to-digital converter chip of each sub-channel.
[0072] Once the fractional time delay deviations corresponding to each sub-channel are obtained, fractional time delay deviation compensation can be performed on the analog-to-digital converter (ADC) chips of each sub-channel. This involves offsetting the signals acquired by the ADC chips of each sub-channel according to their respective fractional time delay deviations. As a result, after the ADC chips of each sub-channel perform offsetting operations on the acquired digital signals, the offset digital signals are spliced together in time domain order to obtain the calibrated time-interleaved sampling results.
[0073] In summary, when controlling an ideal time-interleaved ADC to perform interleaved sampling, the signals of each sub-channel can be acquired first, and phase-frequency analysis can be performed on the sub-channel signals to obtain their phase and frequency characteristics. The phase difference between each sub-channel is then the actual fractional time delay deviation between them at the current moment. Next, the ideal fractional interval at each frequency is calculated using the frequency characteristics of the sub-channel signals. The ideal fractional interval is compared with each actual fractional interval to calculate the fractional time delay deviation. This deviation is then used to compensate for the fractional time delay deviation in the sub-channel ADC, allowing the compensated sub-channel ADC to perform time-interleaved sampling according to the ideal fractional interval. In this scheme, the corresponding ideal fractional interval is determined based on the frequency characteristics of the sub-channel signals. Different ideal time intervals can be used at low and high frequencies, ensuring that the ideal time-interleaved ADC can be compensated to the ideal time interval at different frequencies, thus increasing the applicable frequency range of the ideal time-interleaved ADC.
[0074] Figure 3 This is a flowchart illustrating a time-interleaving sampling method according to an exemplary embodiment of this application. The time-interleaving sampling method can be performed by, for example... Figure 1The time-interleaving sampling system shown is executed. The data processing device in this time-interleaving sampling system can perform time delay compensation on the sub-channels of the time-interleaving sampling system through the following steps, thereby realizing the time-interleaving sampling process. The method shown in the embodiment of this application includes:
[0075] Step 301: Obtain the signals output by each sub-channel, and perform phase frequency analysis on each sub-channel signal to obtain the phase frequency characteristics corresponding to each sub-channel signal.
[0076] In one possible implementation, the phase frequency analysis is a Fast Fourier Transform (FFT) analysis.
[0077] The Fast Fourier Transform (FFT) is an efficient algorithm for the Discrete Fourier Transform (DFT). The Fourier Transform is one of the most fundamental methods in time-domain and frequency-domain transform analysis. In the field of digital processing, the Discrete Fourier Transform (DFT) is the basis for many digital signal processing methods.
[0078] By processing the digital signals output by each sub-channel (i.e., sub-channel signals) using the FFT method, the frequency and phase characteristics corresponding to each sub-channel signal can be obtained.
[0079] Step 302: Calculate the actual fractional interval corresponding to each sub-channel based on the phase frequency characteristics corresponding to each sub-channel signal.
[0080] After obtaining the frequency characteristics and phase characteristics of each sub-channel signal, the actual fractional interval of each sub-channel can be calculated.
[0081] Step 303: Based on the frequency characteristics of each sub-channel signal, obtain the ideal fractional interval corresponding to each sub-channel.
[0082] After obtaining the frequency characteristics corresponding to each sub-channel signal, the frequency characteristics corresponding to each sub-channel signal can be compared with the target threshold to determine whether each sub-channel is in the Nyquist zone 1.
[0083] In this embodiment, the target threshold can be half of the sub-channel sampling rate. When the digital signal acquired by the sub-channel is greater than half of the sub-channel sampling rate, the sub-channel signal is not in the Nyquist zone 1; when the digital signal acquired by the sub-channel is less than or equal to half of the sub-channel sampling rate, the sub-channel signal is in the Nyquist zone 1.
[0084] In one possible implementation, the target ideal fractional interval is obtained when the frequency characteristics of the sub-channel signal are less than or equal to the target threshold.
[0085] In one possible implementation, the target ideal fractional interval is the ratio of the target time period to the number of sub-channels; the target time period is the time period of the analog-to-digital converter chip.
[0086] When the frequency characteristic of the sub-channel signal is detected to be less than or equal to the target threshold, it indicates that the digital signal acquired by the sub-channel (i.e., the sub-channel signal) is in the Nyquist zone 1. At this time, there is no signal aliasing problem. The ideal fractional interval of the digital signals acquired by adjacent sub-channels is equal to 1 / m of the clock period (i.e., the target time period), where m is the number of sub-channels.
[0087] In another possible implementation, when the frequency characteristics of each sub-channel signal are greater than the target threshold, the phase of the ideal signal of each sub-channel is constructed according to the ratio of the frequency characteristics of each sub-channel signal to the target sampling rate, so as to generate each ideal sub-channel signal.
[0088] Phase frequency analysis is performed on each ideal sub-channel signal to obtain the dominant frequency phase of each ideal sub-channel;
[0089] The ideal fractional interval is obtained based on the main frequency phase of each ideal sub-channel.
[0090] If the frequency characteristics of the subchannel signal are greater than the target threshold, it indicates that the digital signal acquired by the subchannel (i.e., the subchannel signal) is not in the Nyquist zone 1. At this time, there is a signal aliasing problem, and the subchannel signal needs to be further analyzed by data processing equipment.
[0091] At this point, for each sub-channel signal, the data processing device can construct the phase of the ideal signal based on the ratio of frequency characteristics to the target sampling rate, in order to generate each ideal sub-channel signal. That is, based on the frequency characteristics of the actually acquired signal and the target sampling rate, the phase is reconstructed to generate the ideal signal in the high-frequency state.
[0092] After generating the ideal signal in the high-frequency state (i.e. the ideal sub-channel signal), the data processing equipment performs phase frequency analysis on the regenerated ideal sub-channel signal to obtain the main frequency phase of each ideal sub-channel signal, that is, the phase value of the main frequency of the ideal sub-channel.
[0093] Once the main frequency phase of each ideal sub-channel signal is obtained, the main frequency phases of each ideal sub-channel signal are compared to obtain the ideal fractional interval corresponding to each sub-channel signal.
[0094] In one possible implementation, when generating each ideal sub-channel signal, the data processing device can obtain the frequency characteristics and the target ratio of the target sampling rate for each sub-channel signal;
[0095] The phase of the ideal signal of the sub-channel is constructed by multiplying the target ratio by the ideal sampling time; the ideal sampling time includes the ideal sampling time of the sub-channel signal in each time period; the sampling time interval between the ideal sampling times of each sub-channel in each time period is the ratio of the clock period to the number of sub-channels.
[0096] The ideal sub-channel signal is constructed based on the phase and amplitude of the ideal signal of the sub-channel.
[0097] The expression for the ideal sub-channel signal is as follows:
[0098]
[0099] In the above formula, Amp is the amplitude of the ideal signal, and f in f is the frequency of the sub-channel signal. s Where i is the sampling frequency, i is the sub-channel number (i.e., which ADC), n is the number of time cycles, and m is the number of sub-channels.
[0100] Using the above formula, the ideal sub-channel signals generated by different sub-channels at each time period can be constructed. At this time, the data processing device performs FFT analysis on the ideal sub-channel signals generated by each sub-channel to obtain the frequency and phase corresponding to each ideal sub-channel signal. The phase value of the main frequency of each ideal sub-channel signal is compared to obtain the ideal fractional interval of the ideal sub-channel signal.
[0101] By setting the signal interval of each sub-channel in the high-frequency state to the ideal fractional interval, the final fitted interleaved sampling signal can be as close as possible to the sampling result in the ideal state.
[0102] Step 304: For each sub-channel, the difference between the ideal decimal interval corresponding to the sub-channel and the actual decimal interval corresponding to the sub-channel is calculated to obtain the decimal delay deviation corresponding to the sub-channel.
[0103] Step 305: Based on the fractional delay deviation corresponding to each sub-channel, perform fractional delay deviation compensation on the analog-to-digital converter chip of each sub-channel to calibrate the time interleaving sampling results of the analog-to-digital converter chip of each sub-channel.
[0104] In one possible implementation, after obtaining the fractional time delay deviations corresponding to each sub-channel, the digital signals sampled by the analog-to-digital converter chips of each sub-channel can be processed by a data processing device to perform time delay processing and then spliced together to form the final time-interleaved sampling result, so as to fully realize the time-interleaved sampling process of the time-interleaved sampling chip.
[0105] Please refer to Figure 4 The diagram illustrates a block diagram of a fractional delay extraction system according to an embodiment of this application. Figure 4 As shown. In this system, the analog signal X(t) is input into DEMUX (i.e., the time-interleaved sampling chip of this application embodiment), and the analog signal is interleaved and sampled by multiple ADCs. The signals obtained by each ADC are subjected to FFT analysis to extract the phase and main frequency of the current signal. When the main frequency is not in the Nyquist 1 region, the ideal sub-channel signal is reconstructed, and then FFT is performed on the ideal sub-channel signal to obtain the ideal signal phase and main frequency, thereby extracting the ideal fractional interval of each sub-channel. It is compared with the corresponding actual fractional interval to finally obtain the fractional time delay offset value corresponding to each sub-channel.
[0106] Please refer to Figure 5 This document illustrates a flowchart of a fractional delay extraction process according to an embodiment of this application. First, an off-chip FFT analysis is performed on the digital signal of each sub-channel of the TIADC to extract the spectrum. The dominant frequency of the current signal can be extracted based on the position of the main peak in the spectrum. The phase of the current signal can be calculated based on the real and imaginary parts of the main peak. The fractional interval of the current signal is then calculated from the dominant frequency and phase. If the signal is a Nyquist-1 signal, the fractional interval of the ideal signal for all sub-channels is (1 / m, 2 / m, ..., (m-1) / m). If the signal is not a Nyquist-1 signal, the ideal signal is reconstructed based on the current dominant frequency. An FFT analysis is then performed again on the ideal signal of each sub-channel to extract the phase of the ideal signal. The fractional interval of the ideal signal is then calculated from the dominant frequency and phase of the ideal signal. The fractional delay deviation of each sub-channel is extracted by subtracting the fractional interval of the actual signal from the fractional interval of the ideal signal.
[0107] In summary, when controlling an ideal time-interleaved ADC to perform interleaved sampling, the signals of each sub-channel can be acquired first, and phase-frequency analysis can be performed on the sub-channel signals to obtain their phase and frequency characteristics. The phase difference between each sub-channel is then the actual fractional time delay deviation between them at the current moment. Next, the ideal fractional interval at each frequency is calculated using the frequency characteristics of the sub-channel signals. The ideal fractional interval is compared with each actual fractional interval to calculate the fractional time delay deviation. This deviation is then used to compensate for the fractional time delay deviation in the sub-channel ADC, allowing the compensated sub-channel ADC to perform time-interleaved sampling according to the ideal fractional interval. In this scheme, the corresponding ideal fractional interval is determined based on the frequency characteristics of the sub-channel signals. Different ideal time intervals can be used at low and high frequencies, ensuring that the ideal time-interleaved ADC can be compensated to the ideal time interval at different frequencies, thus increasing the applicable frequency range of the ideal time-interleaved ADC.
[0108] Figure 6 This is a structural block diagram of a time-interleaved sampling apparatus according to an exemplary embodiment.
[0109] The device includes:
[0110] The phase frequency analysis module 601 is used to acquire the signals output by each sub-channel and perform phase frequency analysis on each sub-channel signal to obtain the phase frequency characteristics corresponding to each sub-channel signal; the phase frequency characteristics include phase characteristics and frequency characteristics.
[0111] The actual interval acquisition module 602 is used to calculate the actual fractional interval corresponding to each sub-channel based on the phase characteristics corresponding to each sub-channel signal.
[0112] The ideal interval acquisition module 603 is used to acquire the ideal fractional interval corresponding to each sub-channel based on the frequency characteristics corresponding to each sub-channel signal.
[0113] The delay deviation extraction module 604 is used to extract the decimal delay deviation corresponding to each sub-channel based on the ideal decimal interval and the actual decimal interval corresponding to each sub-channel.
[0114] The time delay deviation compensation module 605 is used to compensate the decimal time delay deviation of the analog-to-digital converter chip of each sub-channel according to the decimal time delay deviation corresponding to each sub-channel, so as to calibrate the time interleaving sampling results of the analog-to-digital converter chip of each sub-channel.
[0115] In one possible implementation, the ideal interval acquisition module is further configured to:
[0116] When the frequency characteristics of the sub-channel signal are less than the target threshold, the target ideal fractional interval is obtained.
[0117] In one possible implementation, the target ideal fractional interval is the ratio of the target time period to the number of sub-channels; the target time period is the time period of the analog-to-digital converter chip.
[0118] In one possible implementation, the ideal interval acquisition module further includes:
[0119] An ideal signal reconstruction unit is used to construct the phase of the ideal signal of each sub-channel according to the ratio of the frequency characteristics of each sub-channel signal to the target sampling rate when the frequency characteristics of each sub-channel signal are greater than the target threshold, so as to generate each ideal sub-channel signal.
[0120] The main frequency phase acquisition unit is used to perform phase frequency analysis on each ideal sub-channel signal to obtain the main frequency phase of each ideal sub-channel.
[0121] An ideal interval acquisition unit is used to acquire the ideal fractional interval based on the main frequency phase of each ideal sub-channel.
[0122] In one possible implementation, the ideal signal reconstruction unit is further used for,
[0123] For each sub-channel signal, obtain the frequency characteristics and the target ratio of the target sampling rate;
[0124] The phase of the ideal signal of the sub-channel is constructed by multiplying the target ratio by the ideal sampling time; the ideal sampling time includes the ideal sampling time of the sub-channel signal in each time period; the sampling time interval between the ideal sampling times of each sub-channel in each time period is the ratio of the clock period to the number of sub-channels.
[0125] The ideal sub-channel signal is constructed based on the phase and amplitude of the ideal signal of the sub-channel.
[0126] In one possible implementation, the phase frequency analysis is a Fast Fourier Transform (FFT) analysis.
[0127] In one possible implementation, the time delay deviation extraction module is further configured to:
[0128] For each sub-channel, the difference between the ideal decimal interval corresponding to the sub-channel and the actual decimal interval corresponding to the sub-channel is used to obtain the decimal delay deviation corresponding to the sub-channel.
[0129] Please see Figure 7This is a schematic diagram of a computer device provided according to an exemplary embodiment of the present application. The computer device includes a memory and a processor. The memory is used to store a computer program. When the computer program is executed by the processor, it implements the above-described method.
[0130] The processor can be a central processing unit (CPU). It can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations thereof.
[0131] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods in the embodiments of this invention. The processor executes various functional applications and data processing by running the non-transitory software programs, instructions, and modules stored in the memory, thereby implementing the methods described in the above embodiments.
[0132] The memory may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor, etc. Furthermore, the memory may include high-speed random access memory and non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
[0133] In one exemplary embodiment, a computer-readable storage medium is also provided for storing at least one computer program, which is loaded and executed by a processor to implement all or part of the steps in the above-described method. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, or optical data storage device, etc.
[0134] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0135] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A time-interleaved sampling method, characterized in that, The method includes: The signals output by each sub-channel are acquired, and phase frequency analysis is performed on each sub-channel signal to obtain the phase frequency characteristics corresponding to each sub-channel signal; the phase frequency characteristics include phase characteristics and frequency characteristics. Based on the phase frequency characteristics corresponding to each sub-channel signal, calculate the actual fractional interval corresponding to each sub-channel. Based on the frequency characteristics of each sub-channel signal, the ideal fractional interval corresponding to each sub-channel is obtained. Based on the ideal decimal interval and the actual decimal interval corresponding to each sub-channel, extract the decimal delay deviation corresponding to each sub-channel. Based on the fractional delay deviation corresponding to each sub-channel, fractional delay deviation compensation is performed on the analog-to-digital converter chip of each sub-channel to calibrate the time interleaving sampling results of the analog-to-digital converter chip of each sub-channel. The step of obtaining the ideal fractional interval corresponding to each sub-channel based on the frequency characteristics corresponding to each sub-channel signal includes: When the frequency characteristics of each sub-channel signal are greater than the target threshold, the phase of the ideal signal of each sub-channel is constructed according to the ratio of the frequency characteristics of each sub-channel signal to the target sampling rate, so as to generate each ideal sub-channel signal. Phase frequency analysis is performed on each ideal sub-channel signal to obtain the dominant frequency phase of each ideal sub-channel; The ideal fractional interval is obtained based on the main frequency phase of each ideal sub-channel; The step of constructing the phase of the ideal signal for each sub-channel based on the ratio of the frequency characteristics corresponding to each sub-channel signal and the target sampling rate, in order to generate each ideal sub-channel signal, includes: For each sub-channel signal, obtain the frequency characteristics and the target ratio of the target sampling rate; The phase of the ideal signal of the sub-channel is constructed by multiplying the target ratio by the ideal sampling time; the ideal sampling time includes the ideal sampling time of the sub-channel signal in each time period; the sampling time interval between the ideal sampling times of each sub-channel in each time period is the ratio of the clock period to the number of sub-channels. The ideal sub-channel signal is constructed based on the phase and amplitude of the ideal signal of the sub-channel.
2. The method according to claim 1, characterized in that, The step of obtaining the ideal fractional interval based on the frequency characteristics corresponding to each sub-channel signal includes: When the frequency characteristics of the sub-channel signal are less than the target threshold, the target ideal fractional interval is obtained.
3. The method according to claim 2, characterized in that, The target ideal decimal interval is the ratio of the target time period to the number of sub-channels; the target time period is the time period of the analog-to-digital converter chip.
4. The method according to any one of claims 1 to 3, characterized in that, The phase frequency analysis is performed using Fast Fourier Transform (FFT).
5. The method according to any one of claims 1 to 3, characterized in that, The step of extracting the fractional delay deviation corresponding to each sub-channel based on the ideal fractional interval and the actual fractional interval corresponding to each sub-channel includes: For each sub-channel, the difference between the ideal decimal interval corresponding to the sub-channel and the actual decimal interval corresponding to the sub-channel is used to obtain the decimal delay deviation corresponding to the sub-channel.
6. A time-interleaved sampling device, characterized in that, The device includes: The phase frequency analysis module is used to acquire the signals output by each sub-channel and perform phase frequency analysis on each sub-channel signal to obtain the phase frequency characteristics corresponding to each sub-channel signal; the phase frequency characteristics include phase characteristics and frequency characteristics. The actual interval acquisition module is used to calculate the actual fractional interval corresponding to each sub-channel based on the phase frequency characteristics corresponding to each sub-channel signal. The ideal interval acquisition module is used to acquire the ideal fractional interval corresponding to each sub-channel based on the frequency characteristics corresponding to each sub-channel signal. The delay deviation extraction module is used to extract the decimal delay deviation corresponding to each sub-channel based on the ideal decimal interval and the actual decimal interval corresponding to each sub-channel. The time delay deviation compensation module is used to compensate the analog-to-digital converter chip of each sub-channel for the fractional time delay deviation corresponding to each sub-channel, so as to calibrate the time interleaving sampling results of the analog-to-digital converter chip of each sub-channel. The ideal interval acquisition module also includes: An ideal signal reconstruction unit is used to construct the phase of the ideal signal of each sub-channel according to the ratio of the frequency characteristics of each sub-channel signal to the target sampling rate when the frequency characteristics of each sub-channel signal are greater than the target threshold, so as to generate each ideal sub-channel signal. The main frequency phase acquisition unit is used to perform phase frequency analysis on each ideal sub-channel signal to obtain the main frequency phase of each ideal sub-channel. An ideal interval acquisition unit is used to acquire the ideal fractional interval based on the main frequency phase of each ideal sub-channel; The ideal signal reconstruction unit is also used for, For each sub-channel signal, obtain the frequency characteristics and the target ratio of the target sampling rate; The phase of the ideal signal of the sub-channel is constructed by multiplying the target ratio by the ideal sampling time; the ideal sampling time includes the ideal sampling time of the sub-channel signal in each time period; the sampling time interval between the ideal sampling times of each sub-channel in each time period is the ratio of the clock period to the number of sub-channels. The ideal sub-channel signal is constructed based on the phase and amplitude of the ideal signal of the sub-channel.
7. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing at least one instruction, at least one program, code set, or instruction set, the at least one instruction, at least one program, code set, or instruction set being loaded and executed by the processor to implement the time-interleaved sampling method as described in any one of claims 1 to 5.
8. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, which is loaded and executed by a processor to implement the time-interleaved sampling method as described in any one of claims 1 to 5.