Multiple-bit gray code generation circuit

Abstract

The multi-bit Golay code generation circuit of the present application includes: a zeroth Golay code generation circuit that generates a Golay code corresponding to the 0th bit of a multi-bit Golay code; and a plurality of Golay code generation circuits that generate Golay codes corresponding to each bit of a higher bit than the 0th bit of the multi-bit Golay code, the plurality of Golay code generation circuits each being composed of a plurality of flip-flop circuits, the output of a flip-flop circuit of a preceding stage being input to a flip-flop circuit of a next stage, the output of a flip-flop circuit of a final stage being inverted by a flip-flop circuit of a primary stage and held, and the output of any one of the plurality of flip-flop circuits being output as a Golay code corresponding to each bit.

Description

TECHNICAL FIELD

[0001] The present application relates to a multi-bit Gray code generation circuit that generates and outputs a multi-bit Gray code. BACKGROUND

[0002] Conventionally, various techniques for generating a multi-bit (bit) Gray code have been developed. As a technique associated with this, there is the invention disclosed in Japanese Patent Laid-Open No. 6-053818.

[0003] Japanese Patent Laid-Open No. 6-053818 relates to a multi-bit Gray code counter that counts a pulse signal and outputs a Gray code corresponding to the count value.

[0004] The multi-bit Gray code counter includes an N-bit Gray code adder / subtracter that has an adder / subtracter function and an M-bit Gray code counter. SUMMARY

[0005] In the multi-bit Gray code counter disclosed in the above-described Japanese Patent Laid-Open No. 6-053818, a plurality of logic circuits other than flip-flop (hereinafter, referred to as FF) circuits are connected between the FF circuits that constitute the Gray code counter. The driving frequency of a clock signal input to the FF circuits is determined by the delay time of the FF circuit of the previous stage, the delay time of the logic circuit, and the setup time of the FF circuit of the next stage.

[0006] That is, if a plurality of logic circuits exist between the FF circuits, the delay time becomes large, and it is not possible to make the driving frequency of the clock signal input to the FF circuits high, nor is it possible to make the frequency of the Gray code output from the Gray code counter high.

[0007] An object of one aspect of the present application is to realize a multi-bit Gray code generation circuit that can output a Gray code at a high frequency.

[0008] In order to solve the above-described problem, a multi-bit Gray code generation circuit according to one aspect of the present application includes a zeroth Gray code generation circuit that generates a Gray code corresponding to the 0th bit of a multi-bit Gray code, and a plurality of Gray code generation circuits that generate Gray codes corresponding to each bit of bits higher than the 0th bit of the multi-bit Gray code, the plurality of Gray code generation circuits being respectively constituted by a plurality of flip-flop circuits, the output of the flip-flop circuit of the previous stage being input to the flip-flop circuit of the next stage, the output of the flip-flop circuit of the final stage being inverted by the flip-flop circuit of the initial stage and held, and the output of any one of the plurality of flip-flop circuits being output as the Gray code corresponding to each bit.

[0009] According to one aspect of the present application, it is possible to provide a multi-bit Gray code generation circuit that can output a Gray code at a high frequency. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram showing a schematic configuration of a multi-bit Gray code generation circuit according to the first embodiment of the present application.

[0011] Figure 2 is a timing chart for explaining an outline of an operation of the multi-bit Gray code generation circuit according to the first embodiment of the present application.

[0012] Figure 3 is a diagram showing a circuit configuration of a clock delay circuit.

[0013] Figure 4 is a timing chart for explaining an operation of the clock delay circuit.

[0014] Figure 5 is a diagram showing a circuit configuration of a BitO Gray code generation circuit.

[0015] Figure 6 is a timing chart for explaining an operation of the BitO Gray code generation circuit.

[0016] Figure 7 is a diagram showing a circuit configuration of a Bitl Gray code generation circuit.

[0017] Figure 8 is a timing chart for explaining an operation of the Bitl Gray code generation circuit.

[0018] Figure 9 is a diagram showing a circuit configuration of a Bit2 Gray code generation circuit.

[0019] Figure 10 is a timing chart for explaining an operation of the Bit2 Gray code generation circuit.

[0020] Figure 11 is a diagram showing a circuit configuration of a Bit3 Gray code generation circuit.

[0021] Figure 12 is a timing chart for explaining an operation of the Bit3 Gray code generation circuit.

[0022] Figure 13 is a timing chart for explaining details of an operation of the multi-bit Gray code generation circuit according to the first embodiment of the present application.

[0023] Figure 14 is a block diagram showing a schematic configuration of a multi-bit Gray code generation circuit according to the second embodiment of the present application.

[0024] Figure 15 is a timing chart for explaining an operation when the SEL signal is "0" in the multi-bit Gray code generation circuit according to the second embodiment of the present application.

[0025] Figure 16 This is a timing chart for explaining the operation when the SEL signal is “1” in the multi-bit Gray code generation circuit according to the second embodiment of the present invention.

[0026] Figure 17 This is a block diagram showing a schematic configuration of a multi-bit Gray code generation circuit according to a third embodiment of the present invention.

[0027] Figure 18 This is a timing chart for explaining the operation when the SEL signal is “0” in the multi-bit Gray code generation circuit according to the third embodiment of the present invention.

[0028] Figure 19 This is a timing chart for explaining the operation when the SEL signal is “1” in the multi-bit Gray code generation circuit according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0029] [First embodiment]

[0030] Hereinafter, an embodiment of the present invention will be described in detail. In addition, for ease of description, the same reference numerals are given to the same components, and their names and functions are also the same. Therefore, their detailed description will not be repeated.

[0031] <Configuration and Operation of Gray Code Generation Circuit 100>

[0032] Figure 1 This is a block diagram schematically illustrating the configuration of a multi-bit Gray code generation circuit 100 according to the first embodiment of the present invention. Gray code generation circuit 100 includes a clock delay circuit 1, a Bit 0 Gray code generation circuit (also known as a zeroth Gray code generation circuit) 2, a Bit 1 Gray code generation circuit (also known as a first Gray code generation circuit) 3, a Bit 2 Gray code generation circuit (also known as a second Gray code generation circuit) 4, a Bit 3 Gray code generation circuit (also known as a third Gray code generation circuit) 5, and a Bit 4 Gray code generation circuit (also known as a fourth Gray code generation circuit) 6.

[0033] The clock delay circuit 1 starts outputting the clock signal CK0 several clocks after the reset signal XRST changes from a low level (hereinafter referred to as “0”) to a high level (hereinafter referred to as “1”).

[0034] Gray code generation circuits 2 for bit 0, 3 for bit 1, 4 for bit 2, 5 for bit 3, and 6 for bit 4 synchronize with clock signal CK0 output by clock delay circuit 1 and output the Gray code for each corresponding bit. Details of Gray code generation circuits 2 through 6 corresponding to each bit will be described later.

[0035] Figure 2 is a timing chart for explaining an outline of the operation of the multi-bit Gray code generation circuit 100 according to the first embodiment of the present application. At time Tl, the reset signal XRST becomes "1". At T2, which is several clocks later, the clock delay circuit 1 starts output of the clock signal CK0. Then, at T3, which is several clocks later, the Gray code generation circuits 2 to 6 corresponding to the respective bits start output of the Gray code D<4:0>.

[0036] <Configuration and operation of the clock delay circuit 1>

[0037] Figure 3 is a diagram showing the circuit configuration of the clock delay circuit 1. The clock delay circuit 1 includes FF circuits 11 to 13, a latch circuit 14, and an AND circuit 15. The same clock signal CK is connected to the FF circuits 11 to 13 and the latch circuit 14. In addition, the same reset signal XRST is connected to the FF circuits 11 to 13.

[0038] The FF circuits 11 to 13 are reset when the XRST signal is "0", and hold the value input to the input terminal D at the rising edge of the CK signal when the XRST signal is "1", and output to the output terminal Q.

[0039] Further, the FF circuits 11 to 13 operate at the rising edge of the clock signal, but can also operate at the falling edge of the clock signal. Therefore, since the FF circuits 11 to 13 can operate at the rising edge or the falling edge of the clock signal, it can also be described that the FF circuits 11 to 13 operate in synchronization with the clock signal.

[0040] The latch circuit 14 holds the value input to the terminal D at the rising edge of the CK signal and outputs to the terminal Q, and maintains this state during the period when the CK signal is "1". Also, when the CK signal is "0", the value input to the terminal D is output to (passed through) the terminal Q as it is.

[0041] Figure 4 is a timing chart for explaining the operation of the clock delay circuit 1. At time Tl, the reset signal XRST becomes "1". At T2, the output signal n0 of the FF circuit 11 changes from "0" to "1". At T3, the output signal nl of the FF circuit 12 changes from "0" to "1". At T4, the output signal n2 of the FF circuit 13 changes from "0" to "1".

[0042] At T5, the output signal n3 of the latch circuit 14 changes from "0" to "1". At T6, the AND circuit 15 starts output of the clock signal CK0.

[0043] <Configuration and operation of the BitO Gray code generation circuit 2>

[0044] Figure 5is a diagram showing the circuit configuration of the BitO Gray code generation circuit 2. The BitO Gray code generation circuit 2 includes an FF circuit 21. The clock signal CK0 output from the clock delay circuit 1 and the reset signal XRST are connected to the FF circuit 21.

[0045] The FF circuit 21 is reset when the XRST signal is "0", and holds the value of the terminal XD at the falling edge of the CKO signal when the XRST signal is "1", and outputs to the terminal Q. Since the XD terminal inverts the value output from the terminal Q and inputs, the XD terminal inverts the value output from the terminal Q and outputs every time the CKO signal falls. The value output to the output terminal Q of this FF circuit 21 becomes the Gray code DO of the 0th bit (BitO).

[0046] Further, the FF circuit 21 operates at the falling edge of the clock signal, but can also operate at the rising edge of the clock signal. Therefore, since the FF circuit 21 can operate at the rising edge or the falling edge of the clock signal, it can also be described that the FF circuit 21 operates in synchronization with the clock signal.

[0047] Figure 6 is a timing chart for explaining the operation of the BitO Gray code generation circuit 2. At time Tl, the output of the clock signal CKO from the clock delay circuit 1 is started, and the output signal DO of the FF circuit 21 becomes "0". At T2, the output signal DO of the FF circuit 21 changes from "0" to "1" at the falling edge of the CKO signal. At T3, the output signal DO of the FF circuit 21 is held at "1". At T4, the output signal DO of the FF circuit 21 changes from "1" to "0".

[0048] At T5, the output signal DO of the FF circuit 21 is held at "0". At T6, the output signal DO of the FF circuit 21 changes from "0" to "1". At T7, the output signal DO of the FF circuit 21 is held at "1". After that, the same operation is performed.

[0049] <Configuration and operation of Bitl Gray code generation circuit 3>

[0050] Figure 7 is a diagram showing the circuit configuration of the Bitl Gray code generation circuit 3. The Bitl Gray code generation circuit 3 includes FF circuits 31 and 32. The clock signal CKO output from the clock delay circuit 1 and the reset signal XRST are connected to the FF circuits 31 and 32.

[0051] The FF circuit 31 is reset when the XRST signal is "0", and holds the value of the terminal XD at the rising edge of the CK0 signal when the XRST signal is "1", and outputs to the terminal Q. Since the XD terminal inverts the value output from the output terminal Q of the FF circuit 32 and inputs, the XD terminal inverts the value output from the output terminal Q of the FF circuit 32 and outputs each time the CK0 signal rises.

[0052] The FF circuit 32 is reset when the XRST signal is "0", and holds the value of the terminal D at the rising edge of the CK0 signal when the XRST signal is "1", and outputs to the terminal Q. The value output to the output terminal Q of this FF circuit 32 becomes the Gray code Dl of the 1st bit (Bitl).

[0053] Further, the FF circuits 31 and 32 operate at the rising edge of the clock signal, but can also operate at the falling edge of the clock signal. Therefore, since the FF circuits 31 and 32 can operate at the rising edge or the falling edge of the clock signal, it can also be described that the FF circuits 31 and 32 operate in synchronization with the clock signal.

[0054] Figure 8 is a timing chart for explaining the operation of the Bitl Gray code generation circuit 3. At time Tl, the output of the clock signal CK0 from the clock delay circuit 1 is started, and the value of the output terminal Q of the FF circuit 31 (n0) changes from "0" to "1". At T2, the output signal n0 of the FF circuit 31 is held at "1". At T3, the value of the output terminal Q of the FF circuit 32 (Dl) changes from "0" to "1". At T4, the output signals n0 and Dl of the FF circuits 31 and 32 are held at "1".

[0055] At T5, the output signal n0 of the FF circuit 31 changes from "1" to "0". At T6, the output signal n0 of the FF circuit 31 is held at "0", and the output signal Dl of the FF circuit 32 is held at "1". At T7, the output signal Dl of the FF circuit 32 changes from "1" to "0". At T8, the output signals n0 and Dl of the FF circuits 31 and 32 are held at "0". After that, the same operation is performed.

[0056] <Bit2 Gray code generation circuit 4>

[0057] Figure 9 is a diagram showing the circuit configuration of the Bit2 Gray code generation circuit 4. The Bit2 Gray code generation circuit 4 includes FF circuits 41 to 44. The clock signal CK0 and the reset signal XRST output from the clock delay circuit 1 are connected to the FF circuits 41 to 44.

[0058] The FF circuit 41 is reset when the XRST signal is "0", and holds the value of the terminal XD at the rising edge of the CK0 signal when the XRST signal is "1", and outputs to the terminal Q. Since the XD terminal inverts the value output from the output terminal Q of the FF circuit 44 and inputs, the XD terminal inverts the value output from the output terminal Q of the FF circuit 44 and outputs each time the CK0 signal rises.

[0059] The FF circuits 42 to 44 are reset when the XRST signal is "0", and hold the value of the terminal D at the rising edge of the CK0 signal when the XRST signal is "1", and outputs to the terminal Q. The value output to the output terminal Q of the FF circuit 43 becomes the Gray code D2 of the 2nd bit (Bit2).

[0060] Further, the FF circuits 41 to 44 operate at the rising edge of the clock signal, but can also operate at the falling edge of the clock signal. Therefore, since the FF circuits 41 to 44 can operate at the rising edge or the falling edge of the clock signal, it can also be described that the FF circuits 41 to 44 operate in synchronization with the clock signal.

[0061] Figure 10 is a timing chart for explaining the operation of the Bit2 Gray code generation circuit 4. At time Tl, the output of the clock signal CK0 from the clock delay circuit 1 is started, and the value of the output terminal Q of the FF circuit 41 (n0) changes from "0" to "1". At T2, the output signal n0 of the FF circuit 41 is held at "1". At T3, the value of the output terminal Q of the FF circuit 42 (n1) changes from "0" to "1". At T4, the output signals n0 and n1 of the FF circuits 41 and 42 are held at "1".

[0062] At T5, the output signal D2 of the FF circuit 43 changes from "0" to "1". At T6, the output signals n0, n1 and D2 of the FF circuits 41 to 43 are held at "1". At T7, the output signal n2 of the FF circuit 44 changes from "0" to "1". At T8, the output signals n0, n1, D2 and n2 of the FF circuits 41 to 44 are held at "1".

[0063] At T9, the output signal n0 of the FF circuit 41 changes from "1" to "0". At TlO, the FF circuits 41 to 44 hold the same value. At Tl 1, the output signal n1 of the FF circuit 42 changes from "1" to "0". At T12, the FF circuits 41 to 44 hold the same value. At T13, the output signal D2 of the FF circuit 43 changes from "1" to "0". After that, the same operation is performed.

[0064] <Bit3 Gray code generation circuit 5>

[0065] Figure 11Fig. 2 is a diagram showing a circuit configuration of the Bit3 Gray code generation circuit 5. The Bit3 Gray code generation circuit 5 includes FF circuits 51 to 58. The clock signal CK0 and the reset signal XRST output from the clock delay circuit 1 are connected to the FF circuits 51 to 58.

[0066] The FF circuit 51 is reset when the XRST signal is "0", and holds the value of the terminal XD at the rising edge of the CK0 signal when the XRST signal is "1", and outputs to the terminal Q. Since the XD terminal inverts the value output from the output terminal Q of the FF circuit 58 and inputs, the XD terminal inverts the value output from the output terminal Q of the FF circuit 58 and outputs every time the CK0 signal rises.

[0067] The FF circuits 52 to 58 are reset when the XRST signal is "0", and hold the value of the terminal D at the rising edge of the CK0 signal when the XRST signal is "1", and outputs to the terminal Q. The value output to the output terminal Q of the FF circuit 55 becomes the Gray code D3 of the 3rd bit (Bit3).

[0068] Further, the FF circuits 51 to 58 operate at the rising edge of the clock signal, but can also operate at the falling edge of the clock signal. Therefore, since the FF circuits 51 to 58 can operate at the rising edge or the falling edge of the clock signal, it can also be described that the FF circuits 51 to 58 operate in synchronization with the clock signal.

[0069] Figure 12 Fig. 3 is a timing chart for explaining the operation of the Bit3 Gray code generation circuit 5. At time Tl, the output of the clock signal CK0 from the clock delay circuit 1 is started, and the value of the output terminal Q of the FF circuit 51 (n0) changes from "0" to "1". At T2, the output signal n0 of the FF circuit 51 is held at "1". At T3, the value of the output terminal Q of the FF circuit 52 (n1) changes from "0" to "1". At T4, the output signals n0 and n1 of the FF circuits 51 and 52 are held at "1".

[0070] At T5, the output signal n2 of the FF circuit 53 changes from "0" to "1". At T6, the output signals n0, n1, and n2 of the FF circuits 51 to 53 are held at "1". At T7, the output signal n3 of the FF circuit 54 changes from "0" to "1". At T8, the output signals n0, n1, n2, and n3 of the FF circuits 51 to 54 are held at "1".

[0071] At T9, the output signal D3 of the FF circuit 55 changes from "0" to "1". At T10, the FF circuits 51 to 58 maintain the same values. At T11, the output signal n4 of the FF circuit 56 changes from "0" to "1". At T12, the FF circuits 51 to 58 maintain the same values. At T13, the output signal n5 of the FF circuit 57 changes from "0" to "1".

[0072] At T14, the FF circuits 51 to 58 maintain the same values. At T15, the output signal n6 of the FF circuit 58 changes from "0" to "1". Repeating the same operation, at T16, the output signal D3 of the FF circuit 55 changes from "1" to "0".

[0073] Further, the configuration and operation of the Bit4 Gray code generation circuit 6 are not described in detail. However, for bits higher than the 3rd bit, those skilled in the art can easily make a generalization by referring to the configuration and operation of the BitO Gray code generation circuit 2 to the Bit3 Gray code generation circuit 5.

[0074] <Operation of the multi-bit Gray code generation circuit 100>

[0075] Figure 13 is a timing chart for explaining the operation of the multi-bit Gray code generation circuit 100 in detail. At time Tl, the output of the clock signal CK0 from the clock delay circuit 1 is started, but the output signal D0 of the BitO Gray code generation circuit 2 changes to "0". At this time, the multi-bit Gray code is expressed in decimal as "0".

[0076] At time T2, the output signal D0 of the BitO Gray code generation circuit 2 changes to "1", and the output signals of the other Gray code generation circuits 3 to 6 do not change. At this time, the multi-bit Gray code is expressed in decimal as "1".

[0077] At time T3, the output signal Dl of the Bitl Gray code generation circuit 3 changes to "1", and the output signals of the other Gray code generation circuits 2, 4 to 6 do not change. At this time, the multi-bit Gray code is expressed in decimal as "3".

[0078] At time T4, the output signal D0 of the BitO Gray code generation circuit 2 changes to "0", and the output signals of the other Gray code generation circuits 3 to 6 do not change. At this time, the multi-bit Gray code is expressed in decimal as "2".

[0079] At time T5, the output signal D2 of the Bit2 Gray code generation circuit 4 changes to "1", and the output signals of the other Gray code generation circuits 2, 3, 5, 6 do not change. At this time, the multi-bit Gray code is expressed in decimal as "6".

[0080] At time T6, the output signal D0 of the BitO Gray code generation circuit 2 becomes "1", and the output signals of the other Gray code generation circuits 3 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "7".

[0081] At time T7, the output signal Dl of the Bitl Gray code generation circuit 3 becomes "0", and the output signals of the other Gray code generation circuits 2, 4 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "5".

[0082] At time T8, the output signal D0 of the BitO Gray code generation circuit 2 becomes "0", and the output signals of the other Gray code generation circuits 3 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "4".

[0083] At time T9, the output signal D3 of the Bit3 Gray code generation circuit 5 becomes "1", and the output signals of the other Gray code generation circuits 2 to 4 and 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "12".

[0084] At time T10, the output signal D0 of the BitO Gray code generation circuit 2 becomes "1", and the output signals of the other Gray code generation circuits 3 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "13".

[0085] At time Tl l, the output signal Dl of the Bitl Gray code generation circuit 3 becomes "1", and the output signals of the other Gray code generation circuits 2, 4 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "15".

[0086] At time T12, the output signal D0 of the BitO Gray code generation circuit 2 becomes "0", and the output signals of the other Gray code generation circuits 3 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "14".

[0087] At time T13, the output signal D2 of the Bit2 Gray code generation circuit 4 becomes "0", and the output signals of the other Gray code generation circuits 2, 3, 5, 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "10".

[0088] At time T14, the output signal D0 of the BitO Gray code generation circuit 2 becomes "1", and the output signals of the other Gray code generation circuits 3 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "11".

[0089] At time T15, the output signal Dl of the Bitl Gray code generation circuit 3 becomes "0", and the output signals of the other Gray code generation circuits 2, 4 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "9".

[0090] At time T16, the output signal D0 of the BitO Gray code generation circuit 2 becomes "0", and the output signals of the other Gray code generation circuits 3 to 6 do not change. At this time, the multi-bit Gray code is expressed in decimal as "8".

[0091] At time T17, the output signal D4 of the Bit4 Gray code generation circuit 6 becomes "1", and the output signals of the other Gray code generation circuits 2 to 5 do not change. At this time, the multi-bit Gray code is expressed in decimal as "24". After that, the same operation is performed.

[0092] As explained above, in the multi-bit Gray code generation circuit 100 according to the present embodiment, the circuit configuration of the Bitl Gray code generation circuit 3 to the Bit3 Gray code generation circuit 5 has the following configuration. That is, it has a so-called multiple FF circuit ring connection in which the output of the FF circuit of the preceding stage is input to the FF circuit of the next stage and the output of the FF circuit of the final stage is inverted by the FF circuit of the initial stage and is held. Further, the output of any one of the multiple FF circuits is set as the Gray code corresponding to each bit.

[0093] By being configured as described above, there is no logic circuit between the FF circuits, the delay time is small, and the driving frequency of the clock signal input to the FF circuit can be made high. Therefore, the frequency of the Gray code output from the multi-bit Gray code generation circuit 100 can be made high.

[0094] Further, since the BitO Gray code generation circuit 2 and the other Gray code generation circuits 3 to 6 operate in a manner that the clock signals are shifted by the amount of a half period, the entire circuit can operate with a half period of the clock signal. Therefore, the frequency of the Gray code output from the multi-bit Gray code generation circuit 100 can be further made high.

[0095] Further, since the clock delay circuit 1 starts the output of the clock signal after a predetermined number of clocks after the reset release based on the reset signal XRST, the output of the multi-bit Gray code can be started at an arbitrary timing.

[0096] [Second Embodiment]

[0097] Hereinafter, other embodiments of the present application will be explained. Further, in order to facilitate the explanation, the same reference numerals are attached to the components having the same functions as those explained in the above embodiment, and the explanation will not be repeated.

[0098] <Configuration and Operation of Gray Code Generation Circuit 100a>

[0099] Figure 14 is a block diagram showing the schematic configuration of the multi-bit Gray code generation circuit 100a according to the second embodiment of the present application. As in the above embodiment, the multi-bit Gray code generation circuit 100a is configured by a clock delay circuit 1, a BitO Gray code generation circuit 2, a Bitl Gray code generation circuit 3, a Bit2 Gray code generation circuit 4, and a Bit3 Gray code generation circuit 5. Figure 1The multi-bit Gray code generation circuit 100 according to the first embodiment shown in FIG. 1 differs from the multi-bit Gray code generation circuit 100 shown in FIG. 2 only in that the buffers 61 to 63, the inverters (inverting circuits) 64 and 65, and the selectors (selecting circuits) 66 and 67 are added.

[0100] The buffers 61 to 63 output the values of the output signals D0 to D2 from the BitO Gray code generation circuit 2 to the Bit2 Gray code generation circuit 4 as SD0 to SD2 without change. The buffers 61 to 63 can also be omitted.

[0101] The inverter 64 inverts the value of the output signal D3 from the Bit3 Gray code generation circuit 5 and outputs the inverted value. When the SEL signal is "0", the selector 66 selects the value of the output signal D3 from the Bit3 Gray code generation circuit 5 as SD3. When the SEL signal is "1", the selector 66 selects the inverted value of D3 by the inverter 64 as SD3.

[0102] The inverter 65 inverts the value of the output signal D4 from the Bit4 Gray code generation circuit 6 and outputs the inverted value. When the SEL signal is "0", the selector 67 selects the value of the output signal D4 from the Bit4 Gray code generation circuit 6 as SD4. When the SEL signal is "1", the selector 67 selects the inverted value of D4 by the inverter 65 as SD4.

[0103] Figure 15 is a timing chart for explaining the operation when the SEL signal is "0" in the multi-bit Gray code generation circuit 100a according to the second embodiment of the present application. This timing chart is the same as the timing chart shown in FIG. 3. Therefore, detailed explanation will not be repeated. Figure 13

[0104] Figure 16 is a timing chart for explaining the operation when the SEL signal is "1" in the multi-bit Gray code generation circuit 100a according to the second embodiment of the present application. At time Tl, the output of the clock signal CK0 from the clock delay circuit 1 is started, but the output signals D0 to D2 from the BitO Gray code generation circuit 2 to the Bit2 Gray code generation circuit 4 are "0", and SD0 to SD3 become "0". Further, the output signals D3 and D4 from the Bit3 Gray code generation circuit 5 and the Bit4 Gray code generation circuit 6 are "0", and SD3 to SD4 become "1". At this time, the multi-bit Gray code is "24" in decimal notation.

[0105] At time T2, the output signal D0 from the BitO Gray code generation circuit 2 becomes "1", and the output signals from the other Gray code generation circuits 3 to 6 are not changed. At this time, the multi-bit Gray code is "25" in decimal notation.

[0106] ​At time T3, the output signal Dl of the Bitl Gray code generation circuit 3 becomes "1", and the output signals of the other Gray code generation circuits 2, 4 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "27".

[0107] At time T4, the output signal D0 of the BitO Gray code generation circuit 2 becomes "0", and the output signals of the other Gray code generation circuits 3 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "26".

[0108] At time T5, the output signal D2 of the Bit2 Gray code generation circuit 4 becomes "1", and the output signals of the other Gray code generation circuits 2, 3, 5, 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "30".

[0109] At time T6, the output signal D0 of the BitO Gray code generation circuit 2 becomes "1", and the output signals of the other Gray code generation circuits 3 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "31".

[0110] At time T7, the output signal Dl of the Bitl Gray code generation circuit 3 becomes "0", and the output signals of the other Gray code generation circuits 2, 4 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "29".

[0111] At time T8, the output signal D0 of the BitO Gray code generation circuit 2 becomes "0", and the output signals of the other Gray code generation circuits 3 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "28".

[0112] At time T9, the output signal D3 of the Bit3 Gray code generation circuit 5 becomes "1", and SD3 becomes "0". The output signals of the other Gray code generation circuits 2 to 4 and 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "20".

[0113] At time T10, the output signal D0 of the BitO Gray code generation circuit 2 becomes "1", and the output signals of the other Gray code generation circuits 3 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "21".

[0114] At time Tl l, the output signal Dl of the Bitl Gray code generation circuit 3 becomes "1", and the output signals of the other Gray code generation circuits 2, 4 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "23".

[0115] At time T12, the output signal D0 of the BitO Gray code generation circuit 2 becomes "0", and the output signals of the other Gray code generation circuits 3 to 6 remain unchanged. At this time, the multi-bit Gray code is expressed in decimal as "22".

[0116] At time T13, the output signal D2 of the Bit2 Gray code generation circuit 4 becomes "0", and the output signals of the other Gray code generation circuits 2, 3, 5, 6 do not change. At this time, the multi-bit Gray code is expressed in decimal as "18".

[0117] At time T14, the output signal DO of the BitO Gray code generation circuit 2 becomes "1", and the output signals of the other Gray code generation circuits 3 to 6 do not change. At this time, the multi-bit Gray code is expressed in decimal as "19".

[0118] At time T15, the output signal Dl of the Bitl Gray code generation circuit 3 becomes "0", and the output signals of the other Gray code generation circuits 2, 4 to 6 do not change. At this time, the multi-bit Gray code is expressed in decimal as "17".

[0119] At time T16, the output signal DO of the BitO Gray code generation circuit 2 becomes "0", and the output signals of the other Gray code generation circuits 3 to 6 do not change. At this time, the multi-bit Gray code is expressed in decimal as "16".

[0120] At time T17, the output signal D4 of the Bit4 Gray code generation circuit 6 becomes "1", and SD4 becomes "0". The output signals of the other Gray code generation circuits 2 to 5 do not change. At this time, the multi-bit Gray code is expressed in decimal as "0". After that, the same operation is performed.

[0121] As explained above, in the multi-bit Gray code generation circuit 100a according to the present embodiment, the selectors 66 and 67 select the values of the output signals D3 and D4 from the Bit3 Gray code generation circuit 5 and the Bit4 Gray code generation circuit 6 when the SEL signal is "0", and output them as SD3 and SD4. In addition, when the SEL signal is "1", the selectors 66 and 67 select the values of D3 and D4 inverted by the inverters 64 and 65 and output them as SD3 and SD4.

[0122] Therefore, by changing the SEL signal from "0" to "1", it is possible to express the initial code of the Gray code in decimal and change it from "0" to "24", and it is possible to provide a multi-bit Gray code generation circuit with high versatility.

[0123] 〔Third Embodiment〕

[0124] Hereinafter, other embodiments of the present application will be explained. Also, in order to facilitate explanation, components having the same function as the components explained in the above embodiments are labeled with the same reference numerals, and will not be explained again.

[0125] <Configuration and Operation of Gray Code Generation Circuit 100b>

[0126] Figure 17is a block diagram showing a schematic configuration of a multi-bit Gray code generation circuit 100b according to a third embodiment of the present application. As shown in FIG. 7, the multi-bit Gray code generation circuit 100b includes a BitO Gray code generation circuit 2, a Bitl Gray code generation circuit 3, a Bit2 Gray code generation circuit 4, a Bit3 Gray code generation circuit 5, FF circuits 71 to 73, and selectors (selection circuits) 74 to 78. Figure 1 The multi-bit Gray code generation circuit 100b according to the third embodiment differs from the multi-bit Gray code generation circuit 100 according to the first embodiment shown in FIG. 1 only in that the FF circuits 71 to 73 and the selectors 74 to 78 are added.

[0127] The FF circuits 71 to 73 are reset when the XRST signal is "0", and hold the value of the terminal D at the falling edge of the CKO signal when the XRST signal is "1", and output the value to the terminal Q.

[0128] When the SEL signal is "0", the selector 74 selects the output signal DO from the BitO Gray code generation circuit 2 as the GB_DO output. In addition, when the SEL signal is "1", the selector 74 selects the clock signal CKO as the GB_DO output.

[0129] When the SEL signal is "0", the selector 75 selects the output signal Dl from the Bitl Gray code generation circuit 3 as the GB_Dl output. In addition, when the SEL signal is "1", the selector 75 selects the output signal DO from the BitO Gray code generation circuit 2 as the GB_Dl output.

[0130] When the XRST signal is "1", the FF circuit 71 holds the value of the output signal Dl from the Bitl Gray code generation circuit 3 at the falling edge of the CKO signal, and outputs the value to the selector 76. When the SEL signal is "0", the selector 76 selects the output signal D2 from the Bit2 Gray code generation circuit 4 as the GB_D2 output. In addition, when the SEL signal is "1", the selector 76 selects the output signal from the FF circuit 71 as the GB_D2 output.

[0131] When the XRST signal is "1", the FF circuit 72 holds the value of the output signal n2 of the Bit2 Gray code generation circuit 4 at the falling edge of the CKO signal, and outputs the value to the selector 77. When the SEL signal is "0", the selector 77 selects the output signal D3 from the Bit3 Gray code generation circuit 5 as the GB_D3 output. In addition, when the SEL signal is "1", the selector 77 selects the output signal from the FF circuit 72 as the GB_D3 output.

[0132] When the XRST signal is "1", the FF circuit 73 holds the value of the output signal n6 of the Bit3 Gray code generation circuit 5 at the falling edge of the CK0 signal, and outputs the value to the selector 78. When the SEL signal is "0", the selector 78 selects the output signal D4 from the Bit4 Gray code generation circuit 6 as the GB_D4 output. In addition, when the SEL signal is "1", the selector 78 selects the output signal from the FF circuit 73 as the GB_D4 output.

[0133] Hereinafter, the output signals GB_D0 to GB_D4 of the selectors 74 to 78 are referred to as binary codes.

[0134] Figure 18 is a timing chart for explaining the operation when the SEL signal is "0" in the multi-bit Gray code generation circuit 100b according to the third embodiment of the present application. This timing chart is the same as the timing chart shown in Figure 13 . Therefore, detailed explanation will not be repeated.

[0135] Figure 19 is a timing chart for explaining the operation when the SEL signal is "1" in the multi-bit Gray code generation circuit 100b according to the third embodiment of the present application. At time Tl, the output signals GB_D0 to GB_D4 of the selectors 74 to 78 all become "0". At this time, the binary code is expressed as "0" in decimal.

[0136] At time T2, the output of the clock signal CK0 from the clock delay circuit 1 is started, and the selector 74 selects the clock signal CK0 as the GB_D0 output. At this time, the binary code is expressed as "1" in decimal. Thereafter, the selector 74 outputs the same time-series waveform as the clock signal CK0 to GB_D0.

[0137] At time T3, the output signal D0 of the BitO Gray code generation circuit 2 becomes "1", and the selector 75 outputs "1" to GB_Dl. At this time, the binary code is expressed as "2" in decimal.

[0138] At time T4, the output signal Dl of the Bitl Gray code generation circuit 3 becomes "1", and the output of the output terminal Q of the FF circuit 71 is held as "0". At this time, the binary code is expressed as "3" in decimal.

[0139] At time T5, the output signal D0 of the BitO Gray code generation circuit 2 becomes "0", and the selector 75 outputs "0" to GB_Dl. In addition, the FF circuit 71 holds the value "1" of the output signal Dl of the Bitl Gray code generation circuit 3, and outputs the value to the selector 76. The selector 76 selects the value "1" held by the FF circuit 71 as the GB_D2 output. At this time, the binary code is expressed as "4" in decimal.

[0140] At time T6, the values of the outputs GB_D1 to GB_D4 of the selectors 75 to 78 are unchanged. At this time, the binary code is expressed as "5" in decimal.

[0141] At time T7, the output signal D0 of the BitO Gray code generation circuit 2 becomes "1", and the selector 75 outputs "1" to GB_D1. At this time, the binary code is expressed as "6" in decimal.

[0142] At time T8, the values of the outputs GB_D1 to GB_D4 of the selectors 75 to 78 are unchanged. At this time, the binary code is expressed as "7" in decimal.

[0143] At time T9, the FF circuit 71 holds the value "0" of the output signal D1 of the Bitl Gray code generation circuit 3, and outputs the value to the selector 76. The selector 76 selects the value "0" held by the FF circuit 71 as the GB_D2 output. In addition, the FF circuit 72 holds the value "1" of the output signal n2 of the Bit2 Gray code generation circuit 4, and outputs the value to the selector 77. The selector 77 selects the value "1" held by the FF circuit 72 as the GB_D3 output. At this time, the binary code is expressed as "8" in decimal.

[0144] At time T10, the values of the outputs GB_D1 to GB_D4 of the selectors 75 to 78 are unchanged. At this time, the binary code is expressed as "9" in decimal.

[0145] At time T11, the output signal D0 of the BitO Gray code generation circuit 2 becomes "1", and the selector 75 outputs "1" to GB_D1. At this time, the binary code is expressed as "10" in decimal.

[0146] At time T12, the values of the outputs GB_D1 to GB_D4 of the selectors 75 to 78 are unchanged. At this time, the binary code is expressed as "11" in decimal.

[0147] At time T13, the output signal D0 of the BitO Gray code generation circuit 2 becomes "0", and the selector 75 outputs "0" to GB_D1. In addition, the FF circuit 71 holds the value "1" of the output signal D1 of the Bitl Gray code generation circuit 3, and outputs the value to the selector 76. The selector 76 selects the value "1" held by the FF circuit 71 as the GB_D2 output. At this time, the binary code is expressed as "12" in decimal.

[0148] At time T14, the values of the outputs GB_D1 to GB_D4 of the selectors 75 to 78 are unchanged. At this time, the binary code is expressed as "13" in decimal.

[0149] At time T15, the output signal D0 of the BitO Gray code generation circuit 2 becomes "1", and the selector 75 outputs "1" to GB_D1. At this time, the binary code is expressed as "14" in decimal.

[0150] At time T16, the values of the outputs GB_D1 to GB_D4 of the selectors 75 to 78 are not changed. At this time, the binary code is expressed as "15" in decimal.

[0151] At time T17, the FF circuit 71 holds the value "0" of the output signal D1 of the Bitl Gray code generation circuit 3 and outputs the value to the selector 76. The selector 76 selects the value "0" held by the FF circuit 71 as the GB_D2 output. In addition, the FF circuit 72 holds the value "0" of the output signal n2 of the Bit2 Gray code generation circuit 4 and outputs the value to the selector 77. The selector 77 selects the value "0" held by the FF circuit 72 as the GB_D3 output. In addition, the FF circuit 73 holds the value "1" of the output signal n6 of the Bit3 Gray code generation circuit 5 and outputs the value to the selector 78. The selector 78 selects the value "1" held by the FF circuit 73 as the GB_D4 output. At this time, the binary code is expressed as "16" in decimal.

[0152] As described above, according to the multi-bit Gray code generation circuit 100b of the present embodiment, the selector 74 selects the clock signal CK0 and outputs it when the SEL signal is "1". When the SEL signal is "0", the selector 75 selects and outputs the output signal D0 from the BitO Gray code generation circuit 2. In addition, the selectors 76 to 78 select and output the output signals from the FF circuit 73. With this configuration, the multi-bit Gray code generation circuit 100b can convert a 5-bit Gray code into a 5-bit binary code.

[0153] <Summary>

[0154] The multi-bit Gray code generation circuit according to Mode 1 of the present application includes a zeroth Gray code generation circuit that generates a Gray code corresponding to a 0th bit of a multi-bit Gray code, and a plurality of Gray code generation circuits that generate Gray codes corresponding to respective bits higher than the 0th bit of the multi-bit Gray code, the plurality of Gray code generation circuits each being configured by a plurality of flip-flop circuits, an output of a preceding-stage flip-flop circuit being input to a next-stage flip-flop circuit, an output of a final-stage flip-flop circuit being inverted by a primary flip-flop circuit and held, and an output of any one of the plurality of flip-flop circuits being output as the Gray code corresponding to the respective bit.

[0155] According to the above configuration, there is no logic circuit between the flip-flop circuits, the delay time is small, and the driving frequency of the clock signal input to the flip-flop circuits can be made high. Therefore, the frequency of the Gray code output from the multi-bit Gray code generation circuit can be made high.

[0156] The multi-bit Gray code generation circuit according to Mode 2 of the present application is configured such that, in Mode 1 described above, the zeroth Gray code generation circuit operates with a half period of the clock signal offset from the plurality of Gray code generation circuits.

[0157] According to the above configuration, the frequency of the Gray code output from the multi-bit Gray code generation circuit can be further made high.

[0158] The multi-bit Gray code generation circuit according to Mode 3 of the present application is configured such that, in Mode 1 or 2 described above, the zeroth Gray code generation circuit includes a first flip-flop circuit that holds a value obtained by inverting an output in synchronization with the clock signal and outputs the output as the 0th bit of the Gray code.

[0159] According to the above configuration, the driving frequency of the clock signal input to the flip-flop circuits can be made high.

[0160] The multi-bit Gray code generation circuit according to Mode 4 of the present application is configured such that, in any one of Modes 1 to 3 described above, the plurality of Gray code generation circuits include a first Gray code generation circuit having: a second flip-flop circuit that holds and outputs a value obtained by inverting an input in synchronization with the clock signal; and a third flip-flop circuit that holds a value of an output of the second flip-flop circuit in synchronization with the clock signal and outputs to the second flip-flop circuit, and outputs an output of the third flip-flop circuit as the 1st bit of the Gray code.

[0161] According to the above configuration, there is no logic circuit between the flip-flop circuits, the delay time is small, and the driving frequency of the clock signal input to the flip-flop circuits can be made high.

[0162] The multi-bit Gray code generation circuit according to Mode 5 of the present application is configured such that, in Mode 4 described above, the plurality of Gray code generation circuits further include a second Gray code generation circuit having: a fourth flip-flop circuit that holds and outputs a value obtained by inverting an input in synchronization with the clock signal; a fifth flip-flop circuit that holds and outputs a value of an output of the fourth flip-flop circuit in synchronization with the clock signal; a sixth flip-flop circuit that holds and outputs a value of an output of the fifth flip-flop circuit in synchronization with the clock signal, and outputs an output of the sixth flip-flop circuit as the 2nd bit of the Gray code; and a seventh flip-flop circuit that holds a value of an output of the sixth flip-flop circuit in synchronization with the clock signal and outputs to the fourth flip-flop circuit.

[0163] According to the above configuration, there is no logic circuit between the flip-flop circuits, the delay time is small, and the driving frequency of the clock signal input to the flip-flop circuit can be made high.

[0164] The multi-bit Gray code generation circuit according to Mode 6 of the present application, in Aspect 5 above, further includes a third Gray code generation circuit having an eighth flip-flop circuit that holds and outputs a value obtained by inverting an input in synchronization with a clock signal, a ninth flip-flop circuit that holds and outputs a value of an output of the eighth flip-flop circuit in synchronization with the clock signal, a tenth flip-flop circuit that holds and outputs a value of an output of the ninth flip-flop circuit in synchronization with the clock signal, an eleventh flip-flop circuit that holds and outputs a value of an output of the tenth flip-flop circuit in synchronization with the clock signal, a twelfth flip-flop circuit that holds and outputs a value of an output of the eleventh flip-flop circuit in synchronization with the clock signal and outputs an output of the twelfth flip-flop circuit as the third bit of the Gray code, a thirteenth flip-flop circuit that holds and outputs a value of an output of the twelfth flip-flop circuit in synchronization with the clock signal, a fourteenth flip-flop circuit that holds and outputs a value of an output of the thirteenth flip-flop circuit in synchronization with the clock signal, and a fifteenth flip-flop circuit that holds a value of an output of the fourteenth flip-flop circuit in synchronization with the clock signal and outputs to the eighth flip-flop circuit.

[0165] According to the above configuration, there is no logic circuit between the flip-flop circuits, the delay time is small, and the driving frequency of the clock signal input to the flip-flop circuit can be made high.

[0166] The multi-bit Gray code generation circuit according to Mode 7 of the present application, in Aspect 6 above, further includes a fourth Gray code generation circuit that generates the fourth bit of the Gray code, a first selection circuit that selectively outputs a value of an output from the third Gray code generation circuit and a value obtained by inverting the output from the third Gray code generation circuit, and a second selection circuit that selectively outputs a value of an output from the fourth Gray code generation circuit and a value obtained by inverting the output from the fourth Gray code generation circuit.

[0167] According to the above configuration, a multi-bit Gray code generation circuit that can change the start code of the Gray code and is highly versatile can be provided.

[0168] In the multi-bit Gray code generation circuit according to the aspect 8 of the present application, the multi-bit Gray code generation circuit further includes: a fourth Gray code generation circuit that generates a fourth bit of the Gray code; a sixteenth flip-flop circuit that holds and outputs a value of the output of the first Gray code generation circuit in synchronization with the clock signal; a seventeenth flip-flop circuit that holds and outputs a value of the output of the seventh flip-flop circuit of the second Gray code generation circuit in synchronization with the clock signal; an eighteenth flip-flop circuit that holds and outputs a value of the output of the fifteenth flip-flop circuit of the third Gray code generation circuit in synchronization with the clock signal; a third selection circuit that selectively outputs the output from the zeroth Gray code generation circuit and the clock signal; a fourth selection circuit that selectively outputs the output from the first Gray code generation circuit and the output from the zeroth Gray code generation circuit; a fifth selection circuit that selectively outputs the output from the second Gray code generation circuit and the output from the sixteenth flip-flop circuit; a sixth selection circuit that selectively outputs the output from the third Gray code generation circuit and the output from the seventeenth flip-flop circuit; and a seventh selection circuit that selectively outputs the output from the fourth Gray code generation circuit and the output from the eighteenth flip-flop circuit.

[0169] According to the above configuration, the multi-bit Gray code generation circuit can convert the Gray code into the binary code.

[0170] In the multi-bit Gray code generation circuit according to the aspect 9 of the present application, the multi-bit Gray code generation circuit further includes a clock delay circuit that starts the output of the clock signal after a lapse of a predetermined number of clocks from the reset release.

[0171] According to the above configuration, the multi-bit Gray code generation circuit can start the output of the multi-bit Gray code at an arbitrary timing.

[0172] The present application is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and embodiments obtained by appropriately combining the technical means disclosed in the respective embodiments are also included in the technical scope of the present application. Moreover, new technical features can be formed by combining the technical means disclosed in the respective embodiments.

Claims

1. A multiple-bit gray code generation circuit, characterized by: comprises: a zeroth Gray code generation circuit that generates a Gray code corresponding to a 0th bit of a multi-bit Gray code; and a plurality of Gray code generation circuits that generate Gray codes corresponding to respective bits higher than the 0th bit of the multi-bit Gray code, the plurality of Gray code generation circuits are each configured of a plurality of flip-flop circuits, an output of a flip-flop circuit of a preceding stage is input to a flip-flop circuit of a next stage, an output of a flip-flop circuit of a final stage is inverted by a flip-flop circuit of a primary stage and held, an output of any one of the plurality of flip-flop circuits is output as a Gray code corresponding to the respective bit, a clock signal is commonly supplied to the zeroth Gray code generation circuit and the plurality of Gray code generation circuits, the zeroth Gray code generation circuit outputs a signal at each falling edge of the clock signal, and the plurality of Gray code generation circuits output a signal at each rising edge of the clock signal, so that the zeroth Gray code generation circuit and the plurality of Gray code generation circuits operate in a manner offset by an amount of a half period of the clock signal.

2. The multi-bit Gray code generation circuit according to claim 1, wherein the zeroth Gray code generation circuit includes a first flip-flop circuit that holds a value inverted from an output in synchronization with a clock signal and outputs the inverted value as a 0th bit of a Gray code.

3. The multi-bit Gray code generation circuit according to claim 1, wherein the plurality of Gray code generation circuits include a first Gray code generation circuit, the first Gray code generation circuit has: a second flip-flop circuit that holds and outputs a value inverted from an input in synchronization with a clock signal; and a third flip-flop circuit that holds a value of an output of the second flip-flop circuit in synchronization with the clock signal and outputs to the second flip-flop circuit, and outputs an output of the third flip-flop circuit as a 1st bit of a Gray code.

4. The multi-bit Gray code generation circuit according to claim 3, wherein the plurality of Gray code generation circuits further include a second Gray code generation circuit, the second Gray code generation circuit has: a fourth flip-flop circuit that holds and outputs a value inverted from an input in synchronization with a clock signal; a fifth flip-flop circuit that holds and outputs a value of an output of the fourth flip-flop circuit in synchronization with the clock signal; a sixth flip-flop circuit that holds and outputs a value of an output of the fifth flip-flop circuit in synchronization with the clock signal, and outputs an output of the sixth flip-flop circuit as a 2nd bit of a Gray code; and a seventh flip-flop circuit that holds a value of an output of the sixth flip-flop circuit in synchronization with the clock signal and outputs to the fourth flip-flop circuit.

5. The multi-bit Gray code generation circuit according to claim 4, wherein the plurality of Gray code generation circuits further include a third Gray code generation circuit, the third Gray code generation circuit has: an eighth flip-flop circuit that holds and outputs a value inverted from an input in synchronization with a clock signal; a ninth flip-flop circuit that holds and outputs a value of an output of the eighth flip-flop circuit in synchronization with the clock signal; ​ ​ a tenth flip-flop circuit which holds and outputs a value of an output of the ninth flip-flop circuit in synchronization with the clock signal; an eleventh flip-flop circuit which holds and outputs a value of an output of the tenth flip-flop circuit in synchronization with the clock signal; a twelfth flip-flop circuit which holds and outputs a value of an output of the eleventh flip-flop circuit in synchronization with the clock signal, and outputs an output of the twelfth flip-flop circuit as a third bit of the Gray code; a thirteenth flip-flop circuit which holds and outputs a value of an output of the twelfth flip-flop circuit in synchronization with the clock signal; a fourteenth flip-flop circuit which holds and outputs a value of an output of the thirteenth flip-flop circuit in synchronization with the clock signal; and a fifteenth flip-flop circuit which holds a value of an output of the fourteenth flip-flop circuit in synchronization with the clock signal and outputs to the eighth flip-flop circuit.

6. The multi-bit Gray code generation circuit according to claim 5, wherein the multi-bit Gray code generation circuit further comprises: a fourth Gray code generation circuit which generates a fourth bit of the Gray code; a first selection circuit which selectively outputs a value of an output from the third Gray code generation circuit and a value of an output from the third Gray code generation circuit inverted; a second selection circuit which selectively outputs a value of an output from the fourth Gray code generation circuit and a value of an output from the fourth Gray code generation circuit inverted.

7. The multi-bit Gray code generation circuit according to claim 5, wherein the multi-bit Gray code generation circuit further comprises: a fourth Gray code generation circuit which generates a fourth bit of the Gray code; a sixteenth flip-flop circuit which holds and outputs a value of an output of the first Gray code generation circuit in synchronization with the clock signal; a seventeenth flip-flop circuit which holds and outputs a value of an output of the seventh flip-flop circuit of the second Gray code generation circuit in synchronization with the clock signal; an eighteenth flip-flop circuit which holds and outputs a value of an output of the fifteenth flip-flop circuit of the third Gray code generation circuit in synchronization with the clock signal; a third selection circuit which selectively outputs an output from the zeroth Gray code generation circuit and the clock signal; a fourth selection circuit which selectively outputs an output from the first Gray code generation circuit and an output from the zeroth Gray code generation circuit; a fifth selection circuit which selectively outputs an output from the second Gray code generation circuit and an output from the sixteenth flip-flop circuit; a sixth selection circuit which selectively outputs an output from the third Gray code generation circuit and an output from the seventeenth flip-flop circuit; a seventh selection circuit which selectively outputs an output from the fourth Gray code generation circuit and an output from the eighteenth flip-flop circuit.

8. The multi-bit Gray code generation circuit according to claim 1, wherein the multi-bit Gray code generation circuit further comprises a clock delay circuit which starts output of the clock signal after a prescribed number of clocks elapses from a reset release. ​

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