Method for generating random instruction test program based on data path constraint solving

Abstract

The present invention discloses a method for generating a random instruction test program based on data path constraint solving, comprising the following steps: S1. Circularly read the random instruction sequence file based on constraint solving, reading one line each time. If it is empty, jump to S7; S2. According to the content read in S1, parse the instruction format to obtain the instruction name and the type of each operand in the instruction format; S3. Randomly read the data path constraint solving result file corresponding to the instruction parsed in S2 to obtain a set of verification tuple data based on data path constraints; S4. Pre-store the verification tuple data obtained in S3 into the local memory space according to the alignment requirements; S5. According to the current random instruction read from the random instruction sequence file in S1; S6. Jump to S1 to continue reading the instruction sequence for parsing; S7. Generate result verification code. The present invention can improve the effectiveness of random instruction testing.

Description

Technical Field

[0001] The present invention relates to a method for generating a random instruction test program based on data path constraint solving, which is used for the functional correctness verification of a processor and the stable and reliable test of a computer system, and belongs to the field of computing technology. Background Art

[0002] Random instruction testing is an important method to test the execution components of a processor. It is necessary to conduct sufficient test verification on the instruction combinations during the R & D stage of the processor. To ensure the effectiveness of the test, it is necessary to effectively set the instruction operands and check the results.

[0003] There is a common problem in writing random instruction test programs, that is, it is impossible to simultaneously perform random, targeted, and effective setting of instruction operands while checking the results. This will lead to many random instruction tests being implemented based on specific restrictive conditions, which will greatly reduce the effectiveness of random testing. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for generating a random instruction test program based on data path constraint solving to solve the problem of difficult effective setting and verification of operands when generating random combinations of computing instructions.

[0005] To achieve the above purpose, the present invention provides a method for generating a random instruction test program based on data path constraint solving, including the following steps:

[0006] S1. Circularly read the random instruction sequence file based on constraint solving, read one line each time. If it is empty, jump to S7;

[0007] S2. According to the content read in S1, parse the instruction format, obtain the instruction name and the storage method of each operand in the instruction format. If the operand is stored in a register, it is necessary to further parse whether the type of the register is a scalar register or a vector register;

[0008] S3. Randomly read the data path constraint solving result file corresponding to the instruction parsed in step S2 to obtain a set of verification tuple data based on data path constraints;

[0009] S4. Pre-store the verification tuple data obtained in S3 into the local memory space according to the alignment requirements. That is, on the basis of the previous local memory address, if the currently processed instruction contains a vector register, the local memory address is offset backward to ensure that the starting address of the local memory is 64B aligned. Specifically, if the input operand being processed in this instruction format comes from a vector register, the data is stored in the local memory space, and then the local memory address is offset by 64B;

[0010] If the input operand being processed in this instruction format comes from a scalar register, store the data in the local memory space, and then offset the local memory address by 8B;

[0011] If the input operand being processed in this instruction format is an immediate value, do not store it in the local memory;

[0012] For the result operand, store the result operand at the local memory address addr_check dedicated to storing the result operand;

[0013] S5. According to the current random instruction read from the random instruction sequence file in S1, distinguish and process it in combination with the type mode of the operands in the instruction format. The process is as follows:

[0014] S51. If the input operand being processed currently comes from a vector register, use a vector load instruction to load the data into the register used by the current instruction;

[0015] If the input operand being processed currently comes from a scalar register, use a scalar load instruction to load the data into the corresponding register;

[0016] S52. Adopt the processing principle in S51 to process and generate a memory access load instruction, and then store the result operand of the current instruction in the specified local memory space;

[0017] S6. Jump to S1 to continue reading the instruction sequence for parsing;

[0018] S7. Generate result verification code:

[0019] According to the processing processes of S4 and S5, store the calculation result of the processor instruction and the result data of the instruction verification tuple data in different non - overlapping positions in the local memory space respectively;

[0020] Then, adopt the method of directly comparing the calculation result with the data in the corresponding local memory space of the verification data to check whether they are consistent: if they are consistent, the result is correct; if not, report an error.

[0021] Due to the application of the above - mentioned technical solution, the present invention has the following advantages compared with the prior art:

[0022] The random instruction test program generation method based on data - path constraint solving of the present invention, based on the constrained - random instruction combination sequence, performs random constraint settings on the operands, can ensure the validity of the instruction operands in the random instruction sequence, and can solve the result verification problem, greatly reducing the limitations on random instruction testing and improving the effectiveness of random instruction testing. Description of the Drawings

[0023] Appendix Figure 1This is the flowchart of the method for generating a random instruction test program of the present invention. Specific embodiments

[0024] Embodiment: The present invention provides a method for generating a random instruction test program based on data path constraint solving, including the following steps:

[0025] S1. Loop to read the random instruction sequence file based on constraint solving, read one line each time. If it is empty, jump to S7;

[0026] S2. According to the content read in S1, parse the instruction format, obtain the instruction name and the storage method of each operand in the instruction format. If the operand is stored in a register, it is necessary to further parse whether the type of the register is a scalar register or a vector register;

[0027] S3. Randomly read the data path constraint solving result file corresponding to the instruction parsed in S2, and obtain a set of verification tuple data based on data path constraints;

[0028] S4. Pre-store the verification tuple data obtained in S3 into the local memory space according to the alignment requirement, that is, on the basis of the previous local memory address, if the current processed instruction contains a vector register, offset the local memory address backward to ensure that the starting address of the local memory is 64B aligned. Specifically: if the input operand being processed in this instruction format comes from a vector register, store the data into the local memory space, and then offset the local memory address by 64B;

[0029] If the input operand being processed in this instruction format comes from a scalar register, store the data into the local memory space, and then offset the local memory address by 8B;

[0030] If the input operand being processed in this instruction format is an immediate number, do not store it into the local memory;

[0031] Process the result operand, and store the result operand in the local memory address addr_check dedicated to storing the result operand;

[0032] S5. According to the current random instruction read from the random instruction sequence file in S1, distinguish and process it in combination with the type method of the operand in the instruction format. The process is as follows:

[0033] S51. If the input operand being processed comes from a vector register, use a vector load instruction to load the data into the register used by the current instruction, generating an instruction such as vldw$32,0($x);

[0034] If the input operand being currently processed comes from a scalar register, a scalar load instruction is used to load the data into the corresponding register, generating an instruction such as ldl$1,0($x);

[0035] S52. Adopt the processing principle in S51 to process and generate memory access load instructions: vector registers generate instructions such as vstw$32,0($x), and scalar registers generate instructions such as ldl$1,0($x);

[0036] Then store the result operand of the current instruction into the specified local memory space;

[0037] S6. Jump to S1 to continue reading the instruction sequence for parsing;

[0038] S7. Generate result verification code:

[0039] According to the processing procedures of S4 and S5, store the calculation result of the processor instruction and the result data of the instruction verification tuple data in different non - overlapping positions in the local memory space respectively;

[0040] Then adopt the method of directly comparing the calculation result with the data in the corresponding local memory space of the verification data to check whether they are consistent: if they are consistent, the result is correct; if not, an error is reported.

[0041] A further explanation of the above - mentioned embodiments is as follows:

[0042] Based on the verification tuple data based on data - path constraints and the random instruction sequence based on pipeline resource constraints generated from the papers "Microprocessor Instruction Verification Data Constraint Generation Technology Based on SMT Solver" and the patent "Result Self - Verification Instruction Sequence Filling Method Based on Pipeline Constraints" published by the inventor before, this invention parses the occupancy of register resources in the instruction sequence, combines the existing verification tuple data, expands the instruction sequence, and realizes targeted mixed constraints on the resources of the instruction execution unit and effective setting of operands to improve the test quality.

[0043] This invention provides a method for generating a random instruction test program with self - verification function by combining verification tuple data and constraint - solving instruction sequences, solves the pseudo - randomness of random instruction generation, eliminates the general limitations of traditional random instruction testing, and can randomly combine non - memory - access computing instructions;

[0044] In addition, the verification tuple data provides valid data for each computing instruction, and the instruction sequence based on constraint solving adds valid combinations to random instructions. Based on the data validity and the validity of instruction combinations, the two are combined to implement a more meaningful random instruction test program, while solving the result verification problem and providing the possibility for on-site reproduction during the test verification process.

[0045] The specific process is as follows:

[0046] 1) Read the random instruction sequence file based on constraint solving in a loop, reading one line each time; if it is empty, jump to 8);

[0047] 2) According to the content read, parse the instruction format, obtain the instruction name and the type of each operand in the instruction format. If it is a register, it is necessary to parse whether the type of the register is a scalar register or a vector register;

[0048] 3) Randomly read the data path constraint solving result file corresponding to this instruction to obtain a set of verification tuple data based on data path constraints;

[0049] 4) Pre-store the verification tuple data into the local memory space (LDM) according to the alignment requirements:

[0050] Process based on the previous local memory address: If the currently processed instruction contains vector registers, offset the local memory address backward to ensure that the starting address of the local memory is 64B aligned;

[0051] (1) If the input operand being processed in this instruction format is from a vector register, store the data into the LDM, and then offset the local memory address by 64B;

[0052] (2) If it is from a scalar register, after storing the data into the LDM, then offset the local memory address by 8B;

[0053] (3) If it is an immediate number, do not store it into the local memory;

[0054] (4) Process the result operand, store the result operand in the local memory address addr_check dedicated to storing the result operand, and the increment principle of addr_check follows the processing methods of (2) and (3);

[0055] 5) According to the current random instruction obtained from the random instruction sequence file in 1), including the register numbers used, etc., distinguish and process it in combination with the type method of the operands in the instruction format. The process is as follows:

[0056] (1) If the input operand being currently processed is from a vector register, a vector load instruction is used to load the data into the register used by the current instruction, generating an instruction such as vldw$32,0($x); if it is from a scalar register, a scalar load instruction is used to load the data into the corresponding register, generating an instruction like ldl$1,0($x).

[0057] (2) Then, following the processing principle in subsection (1) of this section, after generating the memory access load instruction, the result operand of the current instruction is stored in the specified LDM memory.

[0058] For vector registers, an instruction such as vstw$32,0($x) is generated;

[0059] For scalar registers, an instruction such as ldl$1,0($x) is generated.

[0060] (6) Combining the processing methods in subsections (4) and (5), an example of the generated instruction fragment is as follows:

[0061] For example, the given fragment: vaddw$32,0x2d,$33

[0062]

[0063] (7) Jump back to (1) to continue fetching the instruction sequence for parsing.

[0064] (8) Generate result verification code: According to the processing in subsections (4) and (5), the calculation result of the processor instruction and the result data of the instruction verification tuple data are stored in different non - overlapping positions in the LDM respectively; then, a direct comparison is made between the calculation result and the data in the corresponding local storage space of the verification data to check for consistency: if they are consistent, the result is correct; if not, an error is reported.

[0065] When using the above - mentioned method for generating a random instruction test program based on data - path constraint solving, with its instruction combination sequence based on constrained randomness and random constraint settings for operands, it can ensure the validity of the instruction operands in the random instruction sequence, and at the same time solve the result verification problem, greatly reducing the limitations on random instruction testing and enhancing the effectiveness of random instruction testing.

[0066] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable those familiar with this technology to understand the content of the present invention and implement it accordingly, and should not be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for generating a random instruction test program based on data path constraint solving, characterized in that, it includes the following steps: S1. Read the random instruction sequence file based on constraint solving in a loop, read one line each time, and jump to S7 if it is empty; S2. According to the content read in S1, parse the instruction format, obtain the instruction name and the storage method of each operand in the instruction format. If the operand is stored in a register, it is necessary to further parse whether the type of the register is a scalar register or a vector register; S3. Randomly read the data path constraint solving result file corresponding to the instruction parsed in step S2, and obtain a set of verification tuple data based on data path constraints; S4. Pre-store the verification tuple data obtained in S3 into the local memory space according to the alignment requirements, that is, on the basis of the previous local memory address, if the current processed instruction contains a vector register, the local memory address is offset backward to ensure that the start address of the local memory is 64B aligned. Specifically: if the input operand being processed in this instruction format comes from a vector register, the data is stored in the local memory space, and then the local memory address is offset by 64B; if the input operand being processed in this instruction format comes from a scalar register, the data is stored in the local memory space, and then the local memory address is offset by 8B; if the input operand being processed in this instruction format is an immediate number, it is not stored in the local memory; Process the result operand, and store the result operand in the local memory address addr_check dedicated to storing the result operand; S5. According to the current random instruction read from the random instruction sequence file in S1, make a distinction and processing in combination with the type method of the operand in the instruction format. The process is as follows: S51. If the input operand being processed comes from a vector register, use a vector load instruction to load the data into the register used by the current instruction; If the input operand being processed comes from a scalar register, use a scalar load instruction to load the data into the corresponding register; S52. Adopt the processing principle in S51 to process and generate a memory access load instruction, and then store the result operand of the current instruction into the specified local memory space; S6. Jump to S1 to continue reading the instruction sequence for parsing; S7. Generate result verification code: According to the processing processes of S4 and S5, store the calculation result of the processor instruction and the result data of the instruction verification tuple data in different positions in the local memory space without overlapping; Then adopt the method of directly comparing the calculation result with the data in the corresponding local memory space of the verification data to check whether they are consistent: if they are consistent, the result is correct; if they are inconsistent, an error is reported.

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