Infrared thermopile array and method of making the same

Abstract

The application provides an infrared thermoelectric array and a preparation method thereof. The method comprises the following steps: providing a substrate with infrared thermocouples arranged in an array on the front surface; forming a patterned dielectric layer and a release groove etching window on the back surface of the substrate, wherein the dielectric layer comprises an outer dielectric layer and an inner dielectric layer; forming a photoresist layer on the outer dielectric layer; etching the substrate to a first preset depth by deep reactive ion etching through the release groove etching window; removing the inner dielectric layer; and etching the substrate exposed on the inner part of the outer dielectric layer by deep reactive ion etching to form a plurality of bosses arranged in an array. The infrared thermoelectric array prepared by the method has reduced thermal conductivity and reduced risk of film rupture. In addition, the bosses can quickly conduct heat, so that the temperature of the cold junction area is consistent with the ambient temperature. When the bosses are etched, only the side etching of the remaining substrate needs to be considered, which greatly reduces the influence of side etching on the bosses, thereby greatly reducing the size of the bosses and improving the array integration.

Description

Technical Field

[0001] This invention relates to the field of micromechanical sensor technology, and in particular to an infrared thermopile array and its fabrication method. Background Technology

[0002] The development of infrared technology dates back over 200 years to the discovery of infrared radiation by British astronomer W. Herschel in 1800. It is crucial in military fields such as infrared imaging, infrared guidance, and infrared early warning. Its working principle is based on the Seebeck effect: when two different materials, A and B, are connected at one end as the hot end, a temperature difference ΔT is generated between the hot and cold ends when this hot end is heated. Depending on the Seebeck coefficients of the two materials, a voltage output Uout occurs at the cold end. The relationship between the output signal and the temperature difference is expressed as: Uout = (αA - αB) * ΔT, where αA and αB are the Seebeck coefficients of the two materials, respectively.

[0003] Infrared thermopile detectors, as the earliest thermal infrared detectors, initially utilized vacuum deposition methods, resulting in large device sizes that were difficult to mass-produce. With the introduction of MEMS technology, the earliest silicon-based infrared thermopile detectors with micro-mechanical fabrication of closed-film structures emerged. Due to their low cost, suitability for mass production, large output signal, higher sensitivity, small size, and ease of packaging, they quickly became a research hotspot.

[0004] like Figure 1 The diagram shows a typical infrared thermopile sensor. This sensor includes a silicon substrate 01 with a groove 011. A thermocouple 02 is positioned across the groove 01 on the surface of the silicon substrate 01, with one end of the thermocouple 02 on the silicon substrate designated as a cold junction region 03. A thin film material for sensing and absorbing ambient heat is also positioned on the end of the thermocouple 02 suspended above the groove 011, with the corresponding area of ​​this thin film material designated as a hot junction region 04. During the use of the thermopile sensor, the hot junction region 04 absorbs the temperature of the environment being measured, creating a temperature difference between the hot junction region 04 and the cold junction region 03. This temperature difference further generates a thermoelectric electromotive force (EMF) across the thermocouple. By analyzing the relationship between the EMF and the temperature difference, the temperature difference between the ambient temperature and the cold junction region can be calculated. Furthermore, given the temperature of the cold junction region, the ambient temperature can be calculated based on the corresponding temperature difference.

[0005] Currently, the infrared thermopile array is generally released using a front-side wet etching method to form the aforementioned groove 011. However, the wet etching method is complex to operate, costly, and prone to causing film rupture in the infrared thermopile structure. Furthermore, the depth of the etching cavity is limited by the wet etching process, making it difficult to achieve a deep etching depth, which is not conducive to the integration of the infrared thermopile array. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an infrared thermopile array and its preparation method, which solves the problems of the prior art using the front wet etching method to release the infrared thermopile array, such as complex operation, high cost, easy film breakage, and unfavorable integration of the infrared thermopile array.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating an infrared thermopile array, the method comprising:

[0008] A substrate is provided, and infrared thermocouples arranged in an array are formed on the front side of the substrate;

[0009] A dielectric layer is formed on the back side of the substrate, and the dielectric layer is patterned to form a patterned dielectric layer. The patterned dielectric layer is divided into an outer dielectric layer and an inner dielectric layer. A release groove etching window is formed between the outer dielectric layer, the inner dielectric layer and the adjacent inner dielectric layer. The release groove etching windows are arranged in an array, and each release groove etching window corresponds to the hot junction region of the corresponding infrared thermocouple.

[0010] A photoresist layer is formed on the outer dielectric layer using a photolithography process;

[0011] The substrate is etched using a deep reactive ion etching process through the release groove etching window to a first preset depth;

[0012] Remove the internal dielectric layer;

[0013] The substrate exposed inside the outer dielectric layer is etched using a deep reactive ion etching process until the infrared thermocouple is exposed on the front side of the substrate, so as to form an array of protrusions inside the outer dielectric layer. Release grooves are formed between adjacent protrusions and between the protrusions and the outer substrate. The protrusions serve as the cold junction region of the infrared thermocouple.

[0014] Optionally, the substrate is a silicon substrate, and the dielectric layer is a silicon oxide dielectric layer.

[0015] Optionally, the silicon oxide dielectric layer is formed using a thermal oxidation process.

[0016] Optionally, the temperature of the thermal oxidation process is between 1180℃ and 1200℃, and the thickness of the silicon oxide dielectric layer is between 0.7μm and 0.9μm.

[0017] Optionally, the thickness of the silicon substrate is between 400 μm and 700 μm.

[0018] Optionally, the thickness of the boss is between 10μm and 100μm, and the width of the boss is between 40μm and 50μm.

[0019] Optionally, the internal dielectric layer can be removed using a dry etching process or a wet etching process.

[0020] Optionally, the support structure of the infrared thermocouple is a sandwich structure of silicon nitride-silicon oxide-silicon nitride.

[0021] The present invention also provides an infrared thermopile array, which is prepared by any one of the above-described methods for preparing an infrared thermopile array.

[0022] As described above, the infrared thermopile array and its fabrication method of the present invention, wherein the infrared thermopile array prepared by this method has a release groove that penetrates the substrate, that is, the depth of the release groove is the same as the thickness of the substrate, increasing the volume of the release groove and greatly reducing the thermal conductivity of the infrared thermopile, thereby improving the performance of the infrared thermopile; in addition, the release groove is formed by deep reactive ion etching process, eliminating the need for steps such as rinsing with etching solution and spin drying, reducing the risk of film breakage in the suspended infrared thermopile; furthermore, the boss, as the cold junction of the infrared thermopile, when the infrared thermopile absorbs infrared radiation, because... The raised area has a raised section (which is essentially substrate material). The heat absorbed in this area is rapidly transferred to the substrate through the raised section, keeping the temperature of the cold junction region consistent with the ambient temperature. At the same time, when etching to form the raised section, only the side etching of the remaining substrate needs to be considered, which greatly reduces the impact of side etching on the raised section, thereby significantly reducing the size of the raised section (i.e., the cold junction region). Correspondingly, the size of the infrared thermopile array can be significantly reduced, improving the array integration. Finally, the back dry etching process of this embodiment is used to release the infrared thermopile, which is simple to operate and easy to implement. Attached Figure Description

[0023] Figure 1 The diagram shows the structure of a pixel in an infrared thermopile array sensor in the prior art.

[0024] Figure 2 The diagram shown is a process flow chart of the method for fabricating the infrared thermopile array of the present invention.

[0025] Figures 3 to 12 The diagram shows the structural schematics of each step in the fabrication method of the infrared thermopile array of the present invention.

[0026] Component designation explanation

[0027] 01 Silicon substrate

[0028] 011 Groove

[0029] 02 Thermocouple

[0030] 03 Cold Junction Zone

[0031] 04 Hot Junction Region

[0032] 10 Substrates

[0033] 11 Infrared thermocouples

[0034] 12 Dielectric Layer

[0035] 13 Graphical Media Layer

[0036] 14. Outer dielectric layer

[0037] 15 Internal dielectric layer

[0038] 16. Release groove etching window

[0039] 17 Photoresist layer

[0040] 18 Shallow grooves

[0041] 19. convex platform

[0042] 20 Hot Junction Region

[0043] 21 Cold junction region

[0044] Steps S1 to S6 Detailed Implementation

[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] Please see Figures 2 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] like Figure 1As shown, in current methods for fabricating infrared thermopile arrays, when releasing the composite film structure (infrared thermopile dielectric film) to form the groove 011, a wet etching method is generally used from the front side of the composite film structure. First, small etching holes are formed from the front side, and then the wet etching solution etches the substrate through these holes, completing the release of the composite film structure and forming a suspended composite film structure. Finally, the etching solution needs to be removed through rinsing and spin-drying. Because the composite film structure is a suspended thin film, it is easily broken during the removal of the etching solution, causing film breakage. Furthermore, during front-side wet etching, due to the anisotropic release characteristics of MEMS, the size of the etching cavity gradually decreases with etching time, and eventually the etching depth no longer changes. Therefore, the etching cavity depth is relatively small; for example, for silicon substrates, the etching depth is generally around 100 μm, resulting in poor thermal conductivity and affecting device performance. Moreover, the front-side wet etching method is relatively complex and costly.

[0048] Based on the above problems, this embodiment provides a method for fabricating an infrared thermopile array to solve the aforementioned problems. Moreover, the advantages of the fabrication method in this embodiment are particularly evident in the fabrication of the infrared thermopile array structure.

[0049] like Figure 2 As shown, the preparation method includes the following steps:

[0050] like Figures 2 to 4 As shown, step S1 is performed first, providing a substrate 10, and an array of infrared thermocouples 11 are formed on the front side of the substrate 10. Wherein, Figure 3 for Figure 4 Top view, Figure 4 For along Figure 3 A cross-sectional view along the AA direction.

[0051] It should be noted that, since the key step in this embodiment is the release process of the infrared thermocouple, the structure and fabrication process of the infrared thermocouple 11 adopt existing conventional processes and structures. For example, the infrared thermocouple includes a thermopile, a support structure, etc. Figure 1 The structure above the groove 011 is a pixel C in this application (e.g. Figure 3 The diagram shows the structure of the infrared thermocouple 11, but it is not limited to this structure; other conventional structures are also possible and will not be described in detail here. As an example, the support structure of the infrared thermocouple 11 is a sandwich structure of silicon nitride-silicon oxide-silicon nitride. Furthermore, the array distribution of the infrared thermocouples 11 and the number of arrays are set according to specific circumstances, for example... Figure 3 The diagram shows an array of five rows by five columns, but it is not limited to this.

[0052] The material of the substrate 10 can be any material suitable for the structure of an infrared thermopile device. As an example, in this embodiment, the material of the substrate 10 is preferably silicon. Preferably, when the substrate 10 is a silicon substrate, the thickness of the substrate 10 is selected to be between 400μm and 700μm, for example, it can be 400μm, 500μm, 600μm or 700μm.

[0053] like Figure 2 , Figure 5 and Figure 6 As shown, then step S2 is performed to form a dielectric layer 12 (such as...) on the back side of the substrate 10. Figure 5 As shown), the dielectric layer 12 is patterned to form a patterned dielectric layer 13. The patterned dielectric layer 13 is divided into an outer dielectric layer 14 and an inner dielectric layer 15. The outer dielectric layer 14 and the inner dielectric layer 15 form a release groove etching window 16 between them and the adjacent inner dielectric layer 15. The release groove etching windows 16 are arranged in an array, and each release groove etching window 16 corresponds to the hot junction region of the corresponding infrared thermocouple 11.

[0054] The dielectric layer 12 serves as a mask layer for subsequent deep reactive ion etching (DRIE) processes. The material of the dielectric layer 12 can be any suitable material for use as a mask, such as silicon oxide or silicon nitride. As an example, when the substrate 10 is selected as a silicon substrate in this embodiment, the dielectric layer 12 is preferably a silicon oxide dielectric layer. The silicon oxide dielectric layer can be formed using any suitable existing method, such as deposition or thermal oxidation. Thermal oxidation is preferred. The thermal oxidation process is preferably performed at a temperature between 1180°C and 1200°C, and the thickness of the silicon oxide dielectric layer is preferably between 0.7 μm and 0.9 μm.

[0055] It should be noted that the patterned dielectric layer 13 is divided into an outer dielectric layer 14 and an inner dielectric layer 15. The substrate under the mask of the outer dielectric layer 14 will eventually form the supporting frame around the infrared thermopile array structure, and the substrate under the mask of the inner dielectric layer 15 will eventually form the cold junction region of the infrared thermopile array structure. This can be specifically demonstrated in the following steps.

[0056] like Figure 2 and Figure 7 As shown, step S3 is then performed, in which a photoresist layer 17 is formed on the outer dielectric layer 14 using a photolithography process.

[0057] The photoresist layer 17 subsequently serves as an etching mask layer for removing the inner dielectric layer 15. As an example, a photoresist layer is first coated on the back side of the substrate 10, and then photolithography is used to remove the photoresist layer other than that on the outer dielectric layer 14, forming the photoresist layer 17 covering the outer dielectric layer 14.

[0058] like Figure 2 and Figure 8 As shown, step S4 is then performed, in which the substrate 10 is etched using a deep reactive ion etching process through the release groove etching window 16 to a first preset depth D.

[0059] As can be seen from the subsequent process steps, the first preset depth D is directly related to the thickness of the subsequently formed boss. According to the shape preservation characteristics of etching, the subsequently formed boss is formed through the first preset depth D. Therefore, when the specific etching process and etching parameters are determined, the first preset depth D can be set according to the thickness of the subsequently formed boss.

[0060] like Figure 2 and Figure 9 As shown, step S5 is then performed to remove the internal dielectric layer 15.

[0061] In this step, the photoresist layer 17 formed on the outer dielectric layer 14 serves as an etching mask layer for the inner dielectric layer 15, thereby retaining the outer dielectric layer 14 after the inner dielectric layer 15 is removed. The method for removing the inner dielectric layer 15 is not limited here; for example, existing applicable dry etching or wet etching processes can be used.

[0062] like Figure 2 , Figures 10 to 12 As shown, in step S6, a deep reactive ion etching process is used to etch the exposed substrate 10 inside the outer dielectric layer 14 until the infrared thermocouple 11 is exposed on the front side of the substrate 10. This forms an array of protrusions 19 inside the outer dielectric layer 14. Release grooves 22 are formed between adjacent protrusions 19 and between the protrusions 19 and the outer substrate 10. The protrusions 19 serve as the cold junction region 21 of the infrared thermocouple 11. The area corresponding to the release groove 22 serves as the hot junction region 20 of the infrared thermocouple 11. Figure 12 for Figure 11 The top view is provided to facilitate understanding of the positional relationship between the boss 19 and the infrared thermocouple 11. Figure 12 Equivalent to Figure 11 A perspective view based on a top view. Figure 11 For along Figure 12 A cross-sectional view along the AA direction.

[0063] like Figure 11 As shown, as an example, when the thickness of the substrate 10 is selected to be between 400μm and 700μm, the thickness H2 of the boss is between 10μm and 100μm, and the width W of the boss is between 40μm and 50μm.

[0064] In the fabrication method of this embodiment, the release groove penetrates the substrate, meaning the depth of the release groove is the same as the thickness of the substrate. This increases the volume of the release groove, significantly reducing the thermal conductivity of the infrared thermopile and thus improving its performance. Furthermore, the release groove is formed using deep reactive ion etching, eliminating the need for rinsing with etching solution and spin-drying, reducing the risk of film breakage in the suspended infrared thermopile structure. Moreover, the protrusion serves as the cold junction of the infrared thermopile. When the infrared thermopile absorbs infrared radiation, the heat absorbed in the protrusion area (which is essentially substrate material) is rapidly transferred to the substrate, ensuring the temperature of the cold junction area remains consistent with the ambient temperature. Simultaneously, when etching to form the protrusion, only the side etching of the remaining substrate needs to be considered, greatly reducing the impact of side etching on the protrusion and thus significantly reducing its size (i.e., the cold junction area). Correspondingly, this significantly reduces the size of the infrared thermopile array and improves array integration. Finally, the release of the infrared thermopile is achieved using the back-side dry etching process of this embodiment, which is simple to operate and easy to implement.

[0065] This embodiment also provides an infrared thermopile array, which is prepared using the above-described method for preparing an infrared thermopile array.

[0066] In summary, this invention provides an infrared thermopile array and its fabrication method. The infrared thermopile array fabricated using this method has a release groove that penetrates the substrate, meaning the depth of the release groove is the same as the substrate thickness. This increases the volume of the release groove, significantly reducing the thermal conductivity of the infrared thermopile and thus improving its performance. Furthermore, the release groove is formed using deep reactive ion etching, eliminating the need for rinsing with etching solution and spin-drying, reducing the risk of film breakage in the suspended infrared thermopile structure. Moreover, the protrusions act as cold junctions for the infrared thermopile, allowing the infrared thermopile to absorb infrared radiation. During etching, because the raised area contains raised sections (essentially substrate material), the heat absorbed in this area is rapidly transferred to the substrate through the raised sections, keeping the temperature of the cold junction region consistent with the ambient temperature. Simultaneously, when etching to form the raised section, only the side etching of the remaining substrate needs to be considered, greatly reducing the impact of side etching on the raised section and thus significantly reducing the size of the raised section (i.e., the cold junction region). Correspondingly, the size of the infrared thermopile array can be significantly reduced, improving the array integration density. Finally, the back-side dry etching process of this embodiment is used to release the infrared thermopile, which is simple to operate and easy to implement. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of fabricating an infrared thermopile array, characterized by, The preparation method includes: A substrate is provided, and infrared thermocouples arranged in an array are formed on the front side of the substrate; A dielectric layer is formed on the back side of the substrate, and the dielectric layer is patterned to form a patterned dielectric layer. The patterned dielectric layer is divided into an outer dielectric layer and an inner dielectric layer. A release groove etching window is formed between the outer dielectric layer, the inner dielectric layer and the adjacent inner dielectric layer. The release groove etching windows are arranged in an array, and each release groove etching window corresponds to the hot junction region of the corresponding infrared thermocouple. A photoresist layer is formed on the outer dielectric layer using a photolithography process; The substrate is etched using a deep reactive ion etching process through the release groove etching window to a first preset depth; Remove the internal dielectric layer; The substrate exposed inside the outer dielectric layer is etched using a deep reactive ion etching process until the infrared thermocouple is exposed on the front side of the substrate, so as to form an array of protrusions inside the outer dielectric layer. Release grooves are formed between adjacent protrusions and between the protrusions and the outer substrate. The protrusions serve as the cold junction region of the infrared thermocouple.

2. The method for fabricating an infrared thermopile array according to claim 1, characterized in that: The substrate is a silicon substrate, and the dielectric layer is a silicon oxide dielectric layer.

3. The method for fabricating an infrared thermopile array according to claim 2, characterized in that: The silicon oxide dielectric layer is formed using a thermal oxidation process.

4. The method for fabricating an infrared thermopile array according to claim 3, characterized in that: The temperature of the thermal oxidation process is between 1180℃ and 1200℃, and the thickness of the silicon oxide dielectric layer is between 0.7μm and 0.9μm.

5. The method for fabricating an infrared thermopile array according to claim 2, characterized in that: The thickness of the silicon substrate is between 400 μm and 700 μm.

6. The method for fabricating an infrared thermopile array according to claim 5, characterized in that: The thickness of the boss is between 10μm and 100μm, and the width of the boss is between 40μm and 50μm.

7. The method for fabricating an infrared thermopile array according to claim 1, characterized in that: The internal dielectric layer is removed using a dry etching process or a wet etching process.

8. The method for fabricating an infrared thermopile array according to claim 1, characterized in that: The support structure of the infrared thermocouple is a sandwich structure of silicon nitride-silicon oxide-silicon nitride.

9. An infrared thermopile array, characterized in that: It is prepared using the method described in any one of claims 1 to 8 for the preparation of an infrared thermopile array.

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