Method of locating failure locations in semiconductor structures and three-dimensional memory

Abstract

The application relates to a positioning method of a failure position in a semiconductor structure and a three-dimensional memory, and the positioning method comprises the following steps: positioning a first failure position on the back surface of a semiconductor structure; removing a first metal layer on the front surface of the semiconductor structure; forming a second metal layer on a target area on the front surface, the target area being arranged in a staggered mode with the front projection of the first failure position on the back surface; and positioning a second failure position on the front surface through the second metal layer. The positioning method of the application can accurately position the failure position and shorten the time for positioning defects.

Description

Technical Field

[0001] This invention relates primarily to the field of semiconductor manufacturing, and more specifically to a method for locating failure sites in a semiconductor structure and a three-dimensional memory. Background Technology

[0002] In the R&D and mass production of 3D NAND flash memory products, process anomalies, unstable manufacturing equipment, and improper operation by personnel can lead to product defects, thus affecting product yield and production capacity. To help the production line return to normal and improve yield and capacity, it is crucial to identify the causes of product failures promptly. Therefore, accurate location and efficient detection of failure points are paramount. Electroluminescence microscopy (EMMI), based on the electroluminescence effect, is an accurate, rapid, and widely used tool for failure location and analysis. It can detect failures caused by junction leakage, gate oxide leakage, breakdown, electrostatic discharge, and hot carrier effects. Generally, the failure location is first located using EMMI, followed by mechanical or chemical delamination layer by layer for observation. Finally, a thin-layer sample is prepared using fibrinogen (FIB), and the defect is identified and observed using transmission electron microscopy (TEM). Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a method for locating the failure location in a semiconductor structure and a corresponding three-dimensional memory for locating the failure location. The method can accurately locate the failure location in the semiconductor structure and shorten the failure analysis time.

[0004] The present invention provides a method for locating a failure location in a semiconductor structure to solve the above-mentioned technical problems. The method includes: locating a first failure location on the back side of the semiconductor structure; removing a first metal layer, wherein the first metal layer is located on the front side of the semiconductor structure; forming a second metal layer in a target area on the front side, wherein the orthographic projection of the target area on the back side of the semiconductor structure is offset from the orthographic projection of the first failure location on the back side; and locating a second failure location on the front side through the second metal layer.

[0005] In one embodiment of the present invention, the semiconductor structure includes a memory array and a logic circuit, the memory array being located on the front side of the semiconductor structure, the first metal layer being formed above the memory array, and the logic circuit being located on the back side of the semiconductor structure.

[0006] In one embodiment of the present invention, a dynamic point-grabbing method using optical emission microscopy is used to locate the first failure location and / or the second failure location.

[0007] In one embodiment of the present invention, the target area includes a first target area and a second target area that do not contact each other, and the second metal layer includes a grounded metal layer and a positive voltage metal layer that do not contact each other. The grounded metal layer covers the first target area, and the positive voltage metal layer covers the second target area. When the second failure location is located using the dynamic point-grabbing method of optical emission microscopy, the grounded metal layer is used for grounding, and the positive voltage metal layer is used for positive voltage connection.

[0008] In one embodiment of the present invention, the step of removing the first metal layer includes: removing the first metal layer using a chemical reagent.

[0009] In one embodiment of the present invention, the chemical reagent includes hydrochloric acid and / or nitric acid.

[0010] In one embodiment of the present invention, the second metal layer is formed using a focused ion beam method.

[0011] In one embodiment of the present invention, the material of the second metal layer includes tungsten.

[0012] In one embodiment of the present invention, the semiconductor structure further includes a through-silicon contact structure extending through the memory array, and the step of removing the first metal layer includes exposing the through-silicon contact structure on the front side.

[0013] In one embodiment of the present invention, after the step of locating the second failure location on the front side by means of the second metal layer, the method further includes: preparing a thin-film sample containing a target structure using a focused ion beam, the target structure including the through-silicon contact structure; and locating the target structure including the second failure location in the thin-film sample using a transmission electron microscope.

[0014] In one embodiment of the present invention, the semiconductor structure includes 3D NAND.

[0015] To solve the above-mentioned technical problems, the present invention also proposes a three-dimensional memory, including a front side, a back side, and a failure location. The target area of ​​the front side has a metal layer, and the orthographic projection of the target area on the back side is offset from the orthographic projection of the failure location on the back side. The metal layer is used to locate the failure location from the front side.

[0016] In one embodiment of the present invention, a storage array and logic circuitry are included, the storage array being located on the front side of the three-dimensional memory and the logic circuitry being located on the back side of the three-dimensional memory.

[0017] In one embodiment of the present invention, the target area includes a first target area and a second target area that do not contact each other, and the metal layer includes a grounded metal layer and a positive pressure metal layer that do not contact each other. The grounded metal layer covers the first target area, and the positive pressure metal layer covers the second target area. When locating the failure position from the front, the grounded metal layer is used for grounding, and the positive pressure metal layer is used for positive pressure.

[0018] In one embodiment of the present invention, the material of the metal layer includes tungsten.

[0019] In one embodiment of the invention, a through-silicon contact structure is further included, which extends through the memory array, and the failure location is located in the through-silicon contact structure.

[0020] In one embodiment of the present invention, the logic circuit includes a CMOS circuit.

[0021] The present invention provides a method for locating failure locations in a semiconductor structure. By locating a first failure location on the back side of the semiconductor structure, removing a first metal layer on the front side of the semiconductor structure, and then locating a second failure location from the front side using a second metal layer formed in the target area on the front side of the semiconductor structure, the location range is further narrowed through two locating steps. This method can accurately locate failure locations in the semiconductor structure and can use a two-probe method for DC testing. The method is simple to operate, quick to locate, and shortens the failure analysis time. Attached Figure Description

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0023] Figure 1 This is an exemplary flowchart of a method for locating the failure location in a semiconductor structure according to an embodiment of the present invention;

[0024] Figure 2A and Figure 2B This is a top view of a semiconductor structure, which is a method for locating the failure location in a semiconductor structure according to an embodiment of the present invention.

[0025] Figure 3 This is a top view of a semiconductor structure, which is a method for locating the failure location in a semiconductor structure according to an embodiment of the present invention.

[0026] Figure 4 This is a top view of a semiconductor structure, which is a method for locating the failure location in a semiconductor structure according to an embodiment of the present invention.

[0027] Figure 5 This is a cross-sectional view of the target structure in a method for locating the failure location in a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0028] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the invention is not limited to the specific embodiments disclosed below.

[0030] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0031] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0032] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more steps may be removed from these processes.

[0033] Dynamic EMMI technology is used to capture points from the front of 3D NAND products. However, the thick and densely packed metal pads (Al Pads) on the front of 3D NAND products reflect and absorb photons emitted from defect locations, significantly reducing the effective energy and transmission efficiency of the photons. Therefore, it is difficult to capture hot spots from the front of the product. Even if hot spots are captured, they are usually large or diffuse, resulting in significantly low accuracy in locating the failure location. Inverting the 3D NAND product and using backlighting for dynamic point capture allows photons emitted from the defect location to exit through the back silicon substrate. However, the photons' penetration ability is limited, and the thicker back silicon substrate causes some dissipation, making it difficult to further improve the back-side positioning accuracy.

[0034] When preparing thin-layer samples for the located failure area, if a cross-section sample is used directly, the defect may be missed during the sample preparation process due to the orientation of the failure location; if a plane view sample is used, it is difficult to prepare a sample for transmission electron microscopy (TEM / STEM) observation due to the large coverage area.

[0035] To address the above problems, the following embodiments of the present invention provide a method for locating failure locations in a semiconductor structure. This method can accurately locate failure locations in a semiconductor structure and shorten the failure analysis time.

[0036] Figure 1 This is an exemplary flowchart of a method for locating the failure site in a semiconductor structure according to an embodiment of the present invention. (See reference) Figure 1 As shown, the positioning method of this embodiment includes the following steps:

[0037] Step S110: Locate the first failure location on the back side of the semiconductor structure.

[0038] Step S120: Remove the first metal layer, which is located on the front side of the semiconductor structure.

[0039] Step S130: A second metal layer is formed in the target area on the front side, wherein the orthographic projection of the target area on the back side of the semiconductor structure is offset from the orthographic projection of the first failure location on the back side.

[0040] Step S140: Locate the second failure location on the front side using the second metal layer.

[0041] The above steps are described in detail below through specific embodiments.

[0042] In step S110, the present invention uses optical emission microscopy (EMMI) technology to locate the failure location on the back side of the semiconductor structure. EMMI can capture photons emitted during electron-hole recombination in a semiconductor component. Photons emitted at failure locations caused by faults (e.g., junction leakage, gate oxide leakage, breakdown, electrostatic discharge, hot carrier effects) differ from photons emitted at the same location in other normal semiconductor structures, thus allowing the failure location to be determined based on the anomalous photons.

[0043] In one embodiment of the present invention, the semiconductor structure in step S110 includes 3D NAND.

[0044] In some embodiments, the semiconductor structure includes a memory array and logic circuitry, wherein the memory array is located on the front side of the semiconductor structure, the first metal layer in step S120 is formed above the memory array, and the logic circuitry is located on the back side of the semiconductor structure. Exemplarily, the memory array includes a substrate and a stacked structure formed on the substrate by alternating gate layers and dielectric layers, with a channel structure formed through the stacked structure; the logic circuitry includes CMOS circuitry. The semiconductor structure is formed by bonding the memory array and the CMOS circuitry together. Therefore, one side of the formed semiconductor structure is the memory array, and the other side is the CMOS circuitry. In this invention, the side with the memory array is referred to as the front side of the semiconductor structure, and the side with the CMOS circuitry is referred to as the back side of the semiconductor structure.

[0045] In some embodiments of the present invention, the substrate in the semiconductor structure includes a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or another substrate. The semiconductor material of the substrate may include or may be a material selected from at least one of silicon, silicon-germanium, germanium, nickel arsenide, or other semiconductor materials. The semiconductor material may be doped or undoped, such as being doped with p-type or n-type dopants. Furthermore, the substrate is not limited to any particular size, shape, or material. For example, the substrate may be a rounded / circular substrate having a diameter of 200 mm, 300 mm, or other diameters (such as 450 mm). Depending on the requirements, the substrate may also be any polygonal, square, rectangular, curved, or other non-circular workpiece, such as a polygonal substrate.

[0046] According to step S110, the specific operation process for locating the first failure location includes: first, fixing the semiconductor structure on the sample stage of the optical emission microscope; then, using a probe to provide current to the semiconductor structure; next, adjusting the focal length of the optical emission microscope to make the image of the back side of the semiconductor structure in the display clear; finally, performing dynamic point-grabbing to determine the area where the first failure location is located. It should be noted that during dynamic point-grabbing on the back side of the semiconductor structure, although photons emitted at the first failure location can exit from the substrate on the back side, the large substrate thickness causes a certain degree of photon dissipation, making it difficult to accurately locate the first failure location. Therefore, subsequent steps are required to further determine the accurate location of the first failure location.

[0047] It should be noted that the first failure location refers to the failure location located on the back side of the semiconductor structure in step S110, and the first failure location may include multiple failure locations. This invention does not limit the number, size, or specific location of the first failure locations.

[0048] In step S120, the first metal layer on the front side of the semiconductor structure is removed.

[0049] Figure 2A and Figure 2B This is a top view of a semiconductor structure used in a method for locating failure sites in a semiconductor structure according to an embodiment of the present invention. (Reference) Figure 2A and Figure 2B As shown, in this embodiment, the front side 210 of the semiconductor structure is covered with a first metal layer 220. (See reference...) Figure 2B As shown, in some embodiments, the semiconductor structure further includes a through-silicon contact (TSC) 240 that extends through the memory array. The first metal layer 220 may be a metal pad that electrically connects the through-silicon contact 240 in the semiconductor structure to the outside. The through-silicon contact 240 may be distributed in groups, such as... Figure 2B As shown in rectangle 230, six through-silicon contact structures 240 are uniformly distributed within the rectangle 230, each through-silicon contact structure 240 having a circular cross-section. In step S120, after the first metal layer 220 is removed, the through-silicon contact structures 240 in the semiconductor structure are exposed, as are the through-silicon contact structures 240 contained in the failure location 260 determined according to step S110. Figure 2B This is for illustrative purposes only and is not intended to limit the specific shape, distribution, and number of the through-silicon contact structure 240.

[0050] This invention does not limit the method for removing the first metal layer. In some embodiments, chemical reagents are used to remove the first metal layer 220. In some embodiments of this invention, the material of the first metal layer 220 is metallic aluminum (Al), and the corresponding chemical reagents include hydrochloric acid and / or nitric acid. It is understood that when the material of the first metal layer 220 changes, the aforementioned chemical reagents also change accordingly to remove the first metal layer 220.

[0051] Figure 2B The diagram shows a first failure location 260 as an example, which is determined according to step S110. Due to the reasons mentioned above, the first failure location 260 is not precise.

[0052] In some embodiments of the present invention, the first metal layer in step S120 is a metal pad located on the front side of the semiconductor structure. By removing these metal pads, the photons emitted at the first failure location can be easily collected and detected, thereby helping to accurately locate the first failure location.

[0053] In step S130, a second metal layer is formed on the target area on the front side 210 of the semiconductor structure, and the orthographic projection of the target area on the back side of the semiconductor structure is offset from the orthographic projection of the first failure location on the back side.

[0054] Figure 3 and Figure 4 This is a top view of a semiconductor structure, which is a method for locating the failure location in a semiconductor structure according to an embodiment of the present invention. Figure 3 The diagram shows a partial structure of a semiconductor structure including a target region. In this embodiment, a focused ion beam (FIB) machine is used to form a second metal layer 250 in the target region. The target region refers to the area where the second metal layer 250 is located, and its size and shape are the same as the second metal layer 250. This target region does not include the first failure location 260 determined in step S110; that is, the orthographic projection of the target region on the back side of the semiconductor structure is offset from the orthographic projection of the first failure location 260 on the back side, and the two do not intersect or overlap. Therefore, the second metal layer 250 does not cover the first failure location 260, effectively narrowing the location range. Thus, when current is supplied to the semiconductor structure through the second metal layer 250, the second metal layer 250 will not reflect or absorb photons emitted from the first failure location 260, helping to improve the accuracy of locating the first failure location.

[0055] In some embodiments of the present invention, the material of the second metal layer 250 includes tungsten (W), and the thickness of the second metal layer 250 is 100 nm. The function of the second metal layer 250 is to electrically connect the semiconductor structure to the outside. In one embodiment, the second metal layer 250 is as follows: Figure 3 The rectangle shown measures 20 micrometers by 15 micrometers.

[0056] In some embodiments of the present invention, reference is made to Figure 4 As shown, the target area includes a first target area and a second target area, which are not in contact with each other. Correspondingly, the second metal layer includes a non-contact ground metal layer 360 and a positive voltage metal layer 370, wherein the ground metal layer 360 covers the first target area, and the positive voltage metal layer 370 covers the second target area. When locating the second failure location using the photoluminescence microscopy dynamic point-grabbing method, the ground metal layer 360 is used for grounding, and the positive voltage metal layer 370 is used for positive voltage connection. In these embodiments, according to the photoluminescence microscopy dynamic point-grabbing method, a first target area and a second target area need to be determined on the front side of the semiconductor structure, and a ground metal layer 360 and a positive voltage metal layer 370 are formed respectively to facilitate dynamic point-grabbing. The ground metal layer 360 corresponds to the grounding end during dynamic point-grabbing, and the positive voltage metal layer 370 corresponds to the positive voltage end during dynamic point-grabbing. Figure 4 As shown, partial semiconductor structures 310 and 320, including a ground metal layer 360 and a positive voltage metal layer 370, are shown respectively. They can belong to two regions in the same semiconductor structure.

[0057] The present invention does not limit the size or shape of the first target region and the second target region.

[0058] A grounding metal layer 360 can be formed on the first target region using a focused ion beam apparatus, and a positive voltage metal layer 370 can be formed on the second target region. The grounding metal layer 360 can be located at the original location of the Vss metal pad (VssPad) for grounding; the positive voltage metal layer 370 can be located at the original location of the Vmon metal pad (VmonitorPad) for positive voltage connection. The semiconductor structure can be integrated into the EMMI dynamic point circuit structure via the grounding metal layer 360 and the positive voltage metal layer 370.

[0059] In step S140, a second failure location is located on the front side of the semiconductor structure through the second metal layer.

[0060] refer to Figure 4As shown, in one embodiment of the present invention, before performing step S140, the following steps are further included: grounding the grounded metal layer 360 covering the first target area using probe 330; and applying positive voltage to the positive voltage-connected metal layer 370 covering the second target area using probe 340. The grounded metal layer 360 and the positive voltage-connected metal layer 370 can be electrically connected via wire 350.

[0061] According to step S140, after the grounding metal layer 360 is grounded and the positive voltage metal layer 370 is positively voltagered, the two-probe method of EMMI technology can be used to dynamically locate points on the front side of the semiconductor structure, that is, to perform secondary positioning of the first failure location 260 to obtain the second failure location 380. The second failure location 380 can be the same as or different from the first failure location 260. In some cases, the area occupied by the second failure location 380 is smaller than the area occupied by the first failure location 260, indicating that a more accurate failure location can be obtained after secondary positioning, and the positioning accuracy is higher.

[0062] Some methods for dynamically pinpointing the front or back of semiconductor products require setting multiple probes simultaneously on a single semiconductor product to cover a large area. This necessitates applying alternating current and coding to control the testing equipment for multi-point detection, ultimately determining the failure location within the probe's coverage area – a complex process. Compared to multi-probe multi-point detection methods, the method of this invention is simpler to operate. It first locates a first failure location on the back of the semiconductor structure, obtaining a larger positioning range. Then, a second metal layer is formed in the target area outside the positioning range on the front of the semiconductor structure. By applying direct current through the second metal layer to the semiconductor structure, a more precise second failure location can be located. This eliminates the need for complex current control and programming, allowing for precise failure location using direct current.

[0063] In one embodiment of the present invention, the specific operation process for secondary location of the failure position includes: locating a first failure position on the back side of the semiconductor structure; flipping and fixing the semiconductor structure; using probes to connect the ground metal layer 360 and the positive voltage metal layer 370 respectively, and providing DC current to the semiconductor structure through the probes; and locating a second failure position 380 on the front side of the semiconductor structure. Compared with determining the first failure position 260 from the back side, determining the second failure position 380 from the front side avoids the dissipation of photons by the substrate, thus accurately locating the failed structure. According to the location method of the present invention, it can also save 60-70% of the time for subsequent FIB / TEM (Transmission Electron Microscope, TEM) defect confirmation steps, thereby significantly shortening the analysis cycle and improving the sample analysis success rate, enabling timely identification of the root cause of the failure, and improving yield and quality.

[0064] In some embodiments of the present invention, the following steps are included before performing the above steps: first, cleaning the semiconductor structure using alcohol and / or acetone; then, cleaning the semiconductor structure using an ultrasonic cleaner; and finally, drying the semiconductor structure. The above cleaning method can remove stains and attached particles from the semiconductor structure, avoiding their impact on dynamic gripping points.

[0065] When dynamically pinpointing the front side of a semiconductor structure, the removal of the first metal layer covering the front side improves the effective energy and transmission efficiency of photons, allowing for precise location of the first failure point. Furthermore, by re-locating the first failure point, the second failure point can be accurately located, enhancing the effectiveness and reliability of the location results and shortening the failure analysis time.

[0066] In some embodiments of the present invention, after step S140 is performed, the following steps are further included:

[0067] Step S141: Prepare a thin-film sample containing the target structure using a focused ion beam, the target structure including a through-silicon contact structure (TSC);

[0068] Step S142: Use transmission electron microscopy (TEM) to locate the target structure, including the second failure location, in the thin-layer sample.

[0069] Among them, the through-silicon contact structure in the target structure is as follows: Figure 2B The through-silicon contact structure 240 shown is used in step S120 to remove the first metal layer, exposing the through-silicon contact structure to the front side of the semiconductor structure, making it easier to collect and detect photons emitted from defects.

[0070] Figure 5 This is a cross-sectional view of the target structure in a method for locating the failure location in a semiconductor structure according to an embodiment of the present invention. For example... Figure 5 As shown, the target structure includes a first portion 410 and a second portion 420. The first portion 410 can be a stacked structure in a memory array, and the second portion 420 is a capping layer above the stacked structure. The through-silicon contact structure includes a through-array contact 411 penetrating the first portion 410 and a through-silicon contact 421 penetrating the second portion 420. The through-silicon contact 421 and the through-array contact 411 can be integral. In some embodiments, the through-silicon contact 421 and the through-array contact 411 are cylinders with a circular cross-section, wherein the diameter of the through-silicon contact 421 is larger than the diameter of the through-array contact 411. The semiconductor structure can be electrically connected to other components through the through-silicon contact 421 and the through-array contact 411. Figure 5In the illustrated embodiment, a failure point 430 is present in the through-silicon contact 421. The positioning method according to the present invention can accurately locate the position of the failure point 430, thereby revealing the location of the target structure with the failure point. This helps developers find the root cause of the failure and improve product yield and quality. The positioning method according to the present invention is rapid, sensitive, and has high image resolution.

[0071] The above embodiments of the present invention provide a method for locating the failure location in a semiconductor structure. This method can quickly and accurately locate the failure location in the semiconductor structure, thus shortening the failure analysis time.

[0072] This invention also proposes a three-dimensional memory, which can use the positioning method described above to locate the failure location in the three-dimensional memory. The three-dimensional memory includes a front side, a back side, and the failure location. The target area on the front side has a metal layer, and the orthographic projection of the target area on the back side is offset from the orthographic projection of the failure location on the back side. The metal layer is used to locate the failure location from the front side.

[0073] It can be adopted Figure 3 A top view schematic diagram of a three-dimensional memory as an embodiment of the present invention. (See reference) Figure 3 As shown, the front of the three-dimensional memory is shown from a top view, and a metal layer 250 is present in the target area on the front of the three-dimensional memory. Figure 3 Failure location 260 is also shown. It should be noted that failure location 260 is used to indicate the location of the failed part in the three-dimensional memory. It is the projected position of the failed part on the front or back side, and is not used to limit the failed part to the surface position of the front side of the three-dimensional memory. The specific failed part can be located inside the three-dimensional memory.

[0074] like Figure 3 As shown, the target area where the metal layer 250 is located does not cover the failure location 260, meaning that the two are offset from each other on the back side.

[0075] In some embodiments, the three-dimensional memory includes a memory array and logic circuitry, with the memory array located on the front side of the three-dimensional memory and the logic circuitry located on the back side. According to these embodiments, the three-dimensional memory is formed by superimposing and bonding the memory array and the logic circuitry together. In these embodiments, the projection positions of the target region and the failure location on the front side and the back side of the three-dimensional memory are the same.

[0076] In some embodiments, the logic circuitry includes CMOS circuitry. The three-dimensional memory has a three-dimensional structure in which a memory array is superimposed on top of the CMOS circuitry. Specifically, the memory array includes a substrate and a stacked structure formed on the substrate by alternating gate layers and dielectric layers, with a channel structure formed throughout the stacked structure.

[0077] In some embodiments, the target area includes a first target area and a second target area that are not in contact with each other. The metal layer includes a grounded metal layer and a positive voltage metal layer that are not in contact with each other. The grounded metal layer covers the first target area, and the positive voltage metal layer covers the second target area. When locating the failure location from the front, the grounded metal layer is used for grounding, and the positive voltage metal layer is used for receiving positive voltage. For a description of this part of the structure, please refer to the preceding description of the location method and... Figure 4 .

[0078] In some embodiments, the material of the metal layer includes tungsten.

[0079] In some embodiments, the three-dimensional memory further includes a through-silicon contact structure that runs through the memory array, with the failure location located within the through-silicon contact structure.

[0080] The three-dimensional memory of the present invention has a metal layer on the target area on its front side for locating the failure location, which provides effective structural support for the failure location of the three-dimensional memory, thereby improving the efficiency of failure location.

[0081] The basic concepts have been described above. Obviously, for those skilled in the art, the above disclosure is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0082] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0083] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

Claims

1. A method for locating the failure site in a semiconductor structure, characterized in that, include: Locate the first failure location on the back side of the semiconductor structure; Removing a first metal layer, wherein the first metal layer is located on the front side of the semiconductor structure, wherein the semiconductor structure includes a memory array and logic circuitry, the memory array is located on the front side of the semiconductor structure, the first metal layer is formed above the memory array, the logic circuitry is located on the back side of the semiconductor structure, and the semiconductor structure further includes a through-silicon contact structure penetrating the memory array, the step of removing the first metal layer includes: exposing the through-silicon contact structure on the front side; A second metal layer is formed in the target area on the front side, wherein the orthographic projection of the target area on the back side of the semiconductor structure is offset from the orthographic projection of the first failure location on the back side; and The second failure location is located on the front side through the second metal layer.

2. The positioning method as described in claim 1, characterized in that, The first failure location and / or the second failure location are located using a dynamic point-grabbing method with optical emission microscopy.

3. The positioning method as described in claim 2, characterized in that, The target area includes a first target area and a second target area that do not contact each other. The second metal layer includes a grounded metal layer and a positive voltage metal layer that do not contact each other. The grounded metal layer covers the first target area, and the positive voltage metal layer covers the second target area. When the second failure location is located using the dynamic point-grabbing method of optical emission microscopy, the grounded metal layer is used for grounding, and the positive voltage metal layer is used for positive voltage connection.

4. The positioning method as described in claim 1, characterized in that, The step of removing the first metal layer includes: removing the first metal layer using a chemical reagent.

5. The positioning method as described in claim 4, characterized in that, The chemical reagents include hydrochloric acid and / or nitric acid.

6. The positioning method as described in claim 1, characterized in that, The second metal layer is formed using a focused ion beam method.

7. The positioning method as described in claim 1, characterized in that, The material of the second metal layer includes tungsten.

8. The positioning method as described in claim 1, characterized in that, The semiconductor structure includes 3D NAND.

9. The positioning method as described in claim 1, characterized in that, Following the step of locating the second failure location on the front side using the second metal layer, the method further includes: Thin-layer samples containing a target structure, including the through-silicon contact structure, were prepared using a focused ion beam; and The target structure, including the second failure location, was located in the thin-layer sample using a transmission electron microscope.

10. A three-dimensional memory, characterized in that, include: The front, back, and failure location are defined as follows: the target area on the front has a metal layer; the orthographic projection of the target area on the back is offset from the orthographic projection of the failure location on the back; and the metal layer is used to locate the failure location from the front. A storage array and logic circuitry, wherein the storage array is located on the front side of the three-dimensional memory and the logic circuitry is located on the back side of the three-dimensional memory; The failure location is located within the through-silicon contact structure that extends through the memory array.

11. The three-dimensional memory as claimed in claim 10, characterized in that, The target area includes a first target area and a second target area that do not contact each other. The metal layer includes a grounded metal layer and a positive pressure metal layer that do not contact each other. The grounded metal layer covers the first target area, and the positive pressure metal layer covers the second target area. When locating the failure position from the front, the grounded metal layer is used for grounding, and the positive pressure metal layer is used for positive pressure.

12. The three-dimensional memory as claimed in claim 10, characterized in that, The material of the metal layer includes tungsten.

13. The three-dimensional memory as claimed in claim 10, characterized in that, The logic circuit includes CMOS circuitry.

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