Display substrate, manufacturing method thereof, and display device

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device, wherein the display substrate includes a substrate and a plurality of sub-pixels arranged in an array on the substrate; the plurality of sub-pixels include a plurality of display sub-pixels located in a display area of a display panel, and a plurality of virtual sub-pixels at least partially adjacent to the plurality of display sub-pixels; the virtual sub-pixels include: a first potential signal line pattern; a virtual sub-pixel driving circuit, the virtual sub-pixel driving circuit including a virtual driving transistor, and a first conductive connection portion coupled to the gate of the virtual driving transistor; a second conductive connection portion, the second conductive connection portion being coupled to the first conductive connection portion and the first potential signal line pattern, respectively.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] With the continuous development of display technology, the application of flexible organic light-emitting diode (OLED) display panels is becoming more and more extensive. In order to occupy a certain proportion in future market competition, companies are paying more and more attention to improving the yield rate and display quality of display panels.

[0003] In a flexible OLED display panel, each sub-pixel corresponds to its own sub-pixel driving circuit. The sub-pixel driving circuit generally includes a driving transistor. The driving transistor can be turned on under the control of its gate to provide a driving signal to its corresponding sub-pixel. Therefore, the gate potential of the driving transistor plays a very important role in the operation of the entire sub-pixel driving circuit and is an important factor affecting the yield and display quality of the display panel. Summary of the Invention

[0004] The present disclosure aims to provide a display substrate, a method for manufacturing the same, and a display device.

[0005] A first aspect of the present disclosure provides a display substrate, comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate; the plurality of sub-pixels include a plurality of display sub-pixels located in a display area of a display panel, and a plurality of dummy sub-pixels at least partially adjacent to the plurality of display sub-pixels;

[0006] The display sub-pixel includes: a display sub-pixel driving circuit, the display sub-pixel driving circuit including a driving transistor, a first transistor, and a second transistor; the gate of the driving transistor is coupled to the second electrode of the first transistor and the second electrode of the second transistor respectively;

[0007] The virtual sub-pixel includes:

[0008] a first potential signal line pattern;

[0009] a dummy sub-pixel driving circuit, the dummy sub-pixel driving circuit comprising a dummy driving transistor and a first conductive connection portion coupled to a gate of the dummy driving transistor; and

[0010] A second conductive connection portion is coupled to the first conductive connection portion and the first potential signal line pattern respectively.

[0011] Optionally, the first conductive connection portion extends along a first direction;

[0012] The first potential signal line pattern includes a first power signal line pattern, and the first power signal line pattern includes a first portion extending along the first direction;

[0013] The second conductive connection portion extends along a second direction intersecting the first direction, and the second conductive connection portion is respectively coupled to the first conductive connection portion and the first portion of the first power signal line pattern.

[0014] Optionally, the first potential signal line pattern includes a first power signal line pattern, the first power signal line pattern includes a first portion and a second portion coupled to each other, the first portion extends along the first direction, the second portion extends along a second direction, and the second direction intersects the first direction;

[0015] The first conductive connection portion extends along the first direction;

[0016] The second conductive connection portion extends along the first direction, and is respectively coupled to the first conductive connection portion and the second portion of the first power signal line pattern.

[0017] Optionally, the second parts included in at least two of the virtual sub-pixels are coupled along the second direction.

[0018] Optionally, the first portion and the second portion included in at least one target virtual sub-pixel are formed into an integrated structure;

[0019] The target virtual sub-pixel is a virtual sub-pixel located at the outermost side of the display area along the first direction.

[0020] Optionally, the first potential signal line pattern includes a first power signal line pattern, and the first conductive connection portion, the second conductive connection portion and the first power signal line pattern form an integrated structure.

[0021] Optionally, the virtual sub-pixel further includes:

[0022] a first gate line pattern and a first light-emitting control signal line pattern, both extending along the second direction, the first gate line pattern and the first light-emitting control signal line pattern being arranged along the first direction, an orthographic projection of the gate electrode of the dummy drive transistor on the substrate being located between the orthographic projection of the first gate line pattern on the substrate and the orthographic projection of the first light-emitting control signal line pattern on the substrate;

[0023] The orthographic projection of the first gate line pattern on the substrate is located between the orthographic projection of the second conductive connection portion on the substrate and the orthographic projection of the first light-emitting control signal line pattern on the substrate.

[0024] Optionally, the display sub-pixel includes:

[0025] a second gate line pattern and a second light emitting control signal line pattern both extending along a second direction;

[0026] The first gate line pattern included in at least one of the virtual sub-pixels along the second direction, and the second gate line pattern included in the display sub-pixels located in the same row as the virtual sub-pixel along the second direction and adjacent to the at least one virtual sub-pixel form an integrated structure;

[0027] The first light-emitting control signal line pattern included in at least one of the virtual sub-pixels along the second direction, and the second light-emitting control signal line pattern included in the display sub-pixel located in the same row as the virtual sub-pixel along the second direction and adjacent to the at least one virtual sub-pixel form an integrated structure.

[0028] Optionally, the first potential signal line pattern includes a first power signal line pattern; and the virtual sub-pixel driving circuit further includes:

[0029] a first storage capacitor, wherein the gate of the dummy driving transistor is reused as a first plate of the first storage capacitor, a second plate of the first storage capacitor is located on a side of the first plate facing away from the substrate, an orthographic projection of the second plate on the substrate and an orthographic projection of a first portion of the first power signal line pattern extending in a first direction on the substrate having an overlapping area, and the second plate is coupled to the first portion in the overlapping area;

[0030] The display sub-pixel further includes:

[0031] a second power signal line pattern, wherein the second power signal line pattern includes a third portion extending along the first direction;

[0032] The display sub-pixel driving circuit further includes a second storage capacitor, the gate of the driving transistor is multiplexed as a third plate of the second storage capacitor, a fourth plate of the second storage capacitor is located on a side of the third plate facing away from the substrate, an orthographic projection of the fourth plate on the substrate and an orthographic projection of a third portion of the second power signal line pattern on the substrate have an overlapping area, and the fourth plate is coupled to the third portion in the overlapping area;

[0033] The second electrode plates included in the dummy sub-pixels located in the same row along the second direction and the fourth electrode plates included in the display sub-pixels located in the row form an integrated structure.

[0034] Optionally, the display sub-pixel includes:

[0035] a second power signal line pattern, wherein the second power signal line pattern includes a third portion extending along the first direction;

[0036] The first portion of the first power signal line pattern included in each of the dummy sub-pixels located in the same column along the first direction and the third portion of the second power signal line pattern included in each of the display sub-pixels located in the column form an integrated structure.

[0037] Optionally, the virtual sub-pixel further includes: a first data line pattern extending along the first direction;

[0038] The display sub-pixel includes a second data line pattern extending along a first direction;

[0039] The first data line patterns included in the dummy sub-pixels located in the same column along the first direction and the second data line patterns included in the display sub-pixels located in the column form an integrated structure.

[0040] Optionally, the virtual sub-pixel includes an active layer pattern, and the active layer pattern includes:

[0041] a first active sub-pattern and a second active sub-pattern arranged opposite to each other, wherein the first active sub-pattern and the second active sub-pattern both extend along a first direction;

[0042] a third active sub-pattern disposed between the first active sub-pattern and the second active sub-pattern, wherein two ends of the third active sub-pattern are coupled to the first active sub-pattern and the second active sub-pattern, and an orthographic projection of at least a portion of the third active sub-pattern on the substrate overlaps with an orthographic projection of the gate of the dummy driving transistor on the substrate;

[0043] An orthographic projection of a portion of the first conductive connection portion away from the gate of the dummy driving transistor on the substrate does not overlap with an orthographic projection of the active layer pattern on the substrate.

[0044] Optionally, the virtual sub-pixel further includes a first data line pattern extending along the first direction, and an orthographic projection of the second active sub-pattern on the substrate is located between the orthographic projection of the first data line pattern on the substrate and the orthographic projection of the first active sub-pattern on the substrate;

[0045] An orthographic projection of the first data line pattern on the substrate does not overlap with an orthographic projection of the active layer pattern on the substrate.

[0046] Optionally, the first potential signal line pattern includes a first power signal line pattern; and the virtual sub-pixel further includes:

[0047] a first data line pattern, a first gate line pattern, a first light-emitting control signal line pattern, a first reset signal line pattern, and a first initialization signal line pattern; at least a portion of the first power signal line pattern and the first data line pattern all extend along a first direction, and the first gate line pattern, the first light-emitting control signal line pattern, the first reset signal line pattern, and the first initialization signal line pattern all extend along a second direction;

[0048] The dummy sub-pixel driving circuit further includes: a second dummy transistor, a fifth dummy transistor and a sixth dummy transistor;

[0049] The gate of the dummy driving transistor is coupled to the first power signal line pattern, the first electrode of the dummy driving transistor is coupled to the second electrode of the fifth dummy transistor, and the second electrode of the dummy driving transistor is coupled to the first electrode of the sixth dummy transistor;

[0050] The gate of the second dummy transistor is coupled to the first reset signal line pattern, the first electrode of the second dummy transistor is coupled to the first initialization signal line pattern, and the second electrode of the second dummy transistor is floating;

[0051] A gate electrode of the fifth dummy transistor is coupled to the first light emitting control signal line pattern, and a first electrode of the fifth dummy transistor is coupled to the first power signal line pattern;

[0052] A gate of the sixth dummy transistor is coupled to the first light emitting control signal line pattern.

[0053] Optionally, the display sub-pixel driving circuit also includes a third conductive connection portion extending along the first direction, the first end of the third conductive connection portion is coupled to the gate of the driving transistor, and the second end of the third conductive connection portion is coupled to the second electrode of the first transistor and the second electrode of the second transistor respectively.

[0054] Optionally, the second electrode of the first transistor is coupled to the second electrode of the second transistor to form a common connection end, and the orthographic projection of the second end of the third conductive connection portion on the substrate overlaps with the orthographic projection of the common connection end on the substrate, and the second end of the third conductive connection portion is coupled to the common connection end at the overlapping point.

[0055] Optionally, the display subpixel includes: a second power signal line pattern, a second data line pattern, a second gate line pattern, a second light emission control signal line pattern, a second reset signal line pattern, a third reset signal line pattern, a second initialization signal line pattern, and a third initialization signal line pattern; at least a portion of the second power signal line pattern and the second data line pattern extend along a first direction; the second gate line pattern, the second light emission control signal line pattern, the second reset signal line pattern, the third reset signal line pattern, the second initialization signal line pattern, and the third initialization signal line pattern all extend along a second direction, and the second direction intersects the first direction;

[0056] The display sub-pixel driving circuit further includes: a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;

[0057] The first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled to the first electrode of the first transistor;

[0058] The gate of the first transistor is coupled to the second gate line pattern;

[0059] The gate of the second transistor is coupled to the second reset signal line pattern, and the first electrode of the second transistor is coupled to the second initialization signal line pattern;

[0060] A gate electrode of the fourth transistor is coupled to the second gate line pattern, a first electrode of the fourth transistor is coupled to the second data line pattern, and a second electrode of the fourth transistor is coupled to the first electrode of the driving transistor;

[0061] The gate of the fifth transistor is coupled to the second light emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the second power supply signal line pattern;

[0062] The gate of the sixth transistor is coupled to the second light emitting control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the light emitting element in the display sub-pixel;

[0063] A second electrode of the seventh transistor is coupled to the light emitting element in the display sub-pixel, a gate of the seventh transistor is coupled to the third reset signal line pattern, and a first electrode of the seventh transistor is coupled to the third initialization signal line pattern.

[0064] Optionally, the first conductive connecting portion and the second conductive connecting portion are an integral structure.

[0065] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate.

[0066] Based on the above technical solution of the display substrate, a third aspect of the present disclosure provides a method for manufacturing a display substrate, the method comprising:

[0067] A plurality of sub-pixels arranged in an array are fabricated on a substrate; the plurality of sub-pixels include a plurality of display sub-pixels located in a display area of a display panel, and a plurality of dummy sub-pixels at least partially adjacent to the plurality of display sub-pixels;

[0068] The display sub-pixel includes: a display sub-pixel driving circuit, the display sub-pixel driving circuit including a driving transistor, a first transistor, and a second transistor; the gate of the driving transistor is coupled to the second electrode of the first transistor and the second electrode of the second transistor respectively;

[0069] The virtual sub-pixel includes:

[0070] a first potential signal line pattern;

[0071] a dummy sub-pixel driving circuit, the dummy sub-pixel driving circuit comprising a dummy driving transistor and a first conductive connection portion coupled to a gate of the dummy driving transistor;

[0072] A second conductive connection portion is coupled to the first conductive connection portion and the first potential signal line pattern respectively.

[0073] Optionally, the first potential signal line pattern includes a first power signal line pattern; and the steps of manufacturing the first conductive connecting portion, the second conductive connecting portion, and the first potential signal line pattern specifically include:

[0074] The first conductive connection portion, the second conductive connection portion and the first power signal line pattern are formed as an integrated structure through a single patterning process. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0076] Figure 1 A schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0077] Figure 2 for Figure 1 a first enlarged schematic diagram of part C;

[0078] Figure 3 for Figure 1 a second enlarged schematic diagram of portion C;

[0079] Figure 4 A first structural diagram of a virtual sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0080] Figure 5 A first schematic layout diagram of a virtual sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0081] Figure 6 A second structural diagram of a virtual sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0082] Figure 7 A second schematic layout diagram of a virtual sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0083] Figure 8 for Figure 7 Schematic diagram of active layer layout;

[0084] Figure 9 for Figure 7 Schematic diagram of the layout of the first gate metal layer;

[0085] Figure 10 for Figure 7 Schematic diagram of the layout of the second gate metal layer;

[0086] Figure 11 for Figure 7 Schematic diagram of the layout of the source and drain metal layer;

[0087] Figure 12 A third schematic layout diagram of a virtual sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0088] Figure 13a for Figure 2 An enlarged schematic diagram of part B;

[0089] Figure 13b for Figure 13a Schematic diagram of the cross section along the A1A2 direction;

[0090] Figure 13c for Figure 13a Schematic diagram of the cross section along the B1B2 direction;

[0091] Figure 13d for Figure 2 A magnified schematic diagram of part C;

[0092] Figure 14 A first structural diagram of a display sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0093] Figure 15A first layout diagram of a display sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0094] Figure 16 Figure 15 Schematic diagram of active layer layout;

[0095] Figure 17 for Figure 15 Schematic diagram of the layout of the first gate metal layer;

[0096] Figure 18 for Figure 15 Schematic diagram of the layout of the second gate metal layer;

[0097] Figure 19 for Figure 15 Schematic diagram of the source and drain metal layer layout. DETAILED DESCRIPTION

[0098] In order to further illustrate the display substrate and its manufacturing method, and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0099] The display substrate provided by the present disclosure includes a display area and a non-display area located around the display area. The display area includes a central portion and an edge portion. The edge portion is a portion of the display area close to the boundary of the display area. Taking a rectangular display area with rounded corners as an example, the edge portion includes portions located on the upper, lower, left, and right sides of the display area, as well as portions located at the four rounded corners of the display area.

[0100] In the display substrate, during the actual layout of the display area, in order to ensure the uniformity of the display substrate process, virtual sub-pixels will be set at the edge of the display area, around the normal display sub-pixels. These virtual sub-pixels will not undergo vapor deposition of organic light-emitting materials, that is, they will not emit light. Their function is to maintain etching uniformity with the circuit etching of the normal display pixels during the etching process, and to prevent changes in the line width and line spacing of the local circuits due to uneven etching of the edge display sub-pixels.

[0101] However, when actually laying out the virtual sub-pixels and display sub-pixels, due to the limited layout space at the edge of the display area, it is impossible to layout virtual sub-pixels with the same structure as the display sub-pixels. Therefore, when laying out the virtual sub-pixels, the structure of the corresponding virtual sub-pixel driving circuit is simplified compared to the structure of the normal display sub-pixel driving circuit. However, the virtual sub-pixels provided in the display substrate are not independent, and the signal writing to them is consistent with the design of the normal display sub-pixels. However, the simplified virtual sub-pixel driving circuit structure in the virtual sub-pixels may not ensure the stability of the virtual sub-pixels during the driving process, resulting in floating nodes in the virtual sub-pixel driving circuit, which may lead to poor stability of the display substrate during operation and poor display quality.

[0102] The following describes the layout structure of the display sub-pixels and dummy sub-pixels by taking a display sub-pixel driving circuit including 7T1C (ie, 7 thin film transistors and 1 capacitor) as an example.

[0103] like Figure 1 、 Figure 2 、 Figure 4 、 Figure 5 and Figure 13d As shown, the virtual sub-pixel 80 includes: a first data line pattern 808, a first gate line pattern 802, a first light-emitting control signal line pattern 803, a first reset signal line pattern 805 and a first initialization signal line pattern 804; at least a portion of the first power signal line pattern 801 (such as the first portion 8011) and the first data line pattern 808 extend along a first direction (such as the Y direction), and the first gate line pattern 802, the first light-emitting control signal line pattern 803, the first reset signal line pattern 805 and the first initialization signal line pattern 804 extend along a second direction (such as the X direction).

[0104] The virtual sub-pixel driving circuit in the virtual sub-pixel 80 includes: a virtual driving transistor (i.e., a third dummy transistor T3'), a second dummy transistor T2', a fifth dummy transistor T5', a sixth dummy transistor T6', a seventh dummy transistor T7', and a first storage capacitor Cst'. It should be noted that the "virtual" in the virtual driving transistor and dummy transistor can be understood as dummy, i.e., not driving the light-emitting layer to emit light.

[0105] The second dummy transistor T2' has a dual-gate structure, a gate 202g' of the second dummy transistor T2' is coupled to the first reset signal line pattern 805, a source S2' of the second dummy transistor T2' is coupled to the first initialization signal line pattern 804, and a drain D2' of the second dummy transistor T2' is floating.

[0106] The gate 205g' of the fifth dummy transistor T5' is coupled to the first light emitting control signal line pattern 803, the source S5' of the fifth dummy transistor T5' is coupled to the first power signal line pattern 801, and the drain D5' of the fifth dummy transistor T5' is coupled to the source S3' of the third dummy transistor T3'.

[0107] The gate 206g' of the sixth dummy transistor T6' is coupled to the first light emitting control signal line pattern 803, the source S6' of the sixth dummy transistor T6' is coupled to the drain D3' of the third dummy transistor T3', and the drain D6' of the sixth dummy transistor T6' is coupled to the anode of the light emitting element EL.

[0108] The gate 207g' of the seventh dummy transistor T7' is coupled to the first reset signal line pattern 805' in the next dummy sub-pixel 80 adjacent along the first direction, the drain D7' of the seventh dummy transistor T7' is coupled to the anode of the light-emitting element EL, and the source S7' of the seventh dummy transistor T7' is coupled to the first initialization signal line pattern 804' in the next dummy sub-pixel 80 adjacent along the first direction; the cathode of the light-emitting element EL is coupled to the negative power signal line VSS.

[0109] The first plate Cst1 ′ of the first storage capacitor Cst′ is reused as the gate 203 g ′ of the third dummy transistor T3 ′ and coupled thereto. The second plate Cst2 ′ of the first storage capacitor Cst′ is coupled to the first power signal line pattern 801 .

[0110] It is worth noting that Figure 4 As shown, since the dummy sub-pixel driving circuit does not include the first dummy transistor T1' and the fourth dummy transistor T4', the data signal provided by the first data line pattern 808 cannot be sequentially written to the N1 node through the fourth dummy transistor T4', the third dummy transistor T3', and the first dummy transistor T1', causing the N1 node to be in a floating state. It should be noted that the gate of the dummy driving transistor is coupled to the N1 node.

[0111] Because coupling occurs between node N1 and the first power signal line pattern 801 in the virtual sub-pixel driving circuit via the first storage capacitor Cst' and other parasitic capacitors in the virtual sub-pixel driving circuit, changes in the voltage at node N1 cause changes in the voltage on the first power signal line pattern 801. The voltage changes on the first power signal line pattern 801 affect power changes on the second power signal line pattern 901 in the display sub-pixel 90. The voltage VDD on the second power signal line pattern 901 affects the current flowing through the light-emitting element of the display sub-pixel 90, thereby affecting the normal light emission of the light-emitting element in the display sub-pixel 90, resulting in uneven brightness in some areas of the display substrate.

[0112] In more detail, the current I flowing through the light-emitting element of the display sub-pixel 90 satisfies the following relationship: I = 1 / 2 × K (Vdata - VDD) 2, where K is a constant and Vdata is the data voltage. Therefore, when VDD changes, it will cause the current I to change, thereby affecting the luminous efficiency of the light-emitting element.

[0113] Based on the above analysis, it can be seen that the voltage of the N1 node in the virtual sub-pixel driver circuit plays a very important role in the operation of the entire display sub-pixel driver circuit and is a key factor affecting the operating performance of the display sub-pixel driver circuit. Therefore, improving the yield of display products and enhancing the competitiveness of display products through the design and improvement of the N1 node has become the current focus.

[0114] See also Figure 1 、 Figure 2 、 Figure 6 and Figure 7 As shown, an embodiment of the present disclosure provides a display substrate 1, comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate; the plurality of sub-pixels include a plurality of display sub-pixels 90 located in a display area of a display panel, and a plurality of dummy sub-pixels 80 at least partially adjacent to the plurality of display sub-pixels;

[0115] The display sub-pixel 90 includes: a display sub-pixel driving circuit, wherein the display sub-pixel driving circuit includes a driving transistor (i.e., a third transistor T3), a first transistor T1, and a second transistor T2; the gate of the driving transistor is coupled to the second electrode (i.e., the drain D1) of the first transistor T1 and the second electrode (i.e., the drain D2) of the second transistor T2, respectively;

[0116] The virtual sub-pixel 80 includes: a first potential signal line pattern, a virtual sub-pixel driving circuit and a second conductive connection portion 8062; the virtual sub-pixel driving circuit includes a virtual driving transistor, and a first conductive connection portion 8061 coupled to the gate of the virtual driving transistor; the second conductive connection portion 8062 is respectively coupled to the first conductive connection portion 8061 and the first potential signal line pattern.

[0117] Specifically, the plurality of virtual sub-pixels 80 included in the display substrate 1 may be distributed along the boundaries of the plurality of display sub-pixels 90, and at a certain boundary, a plurality of virtual sub-pixels 80 may be distributed along both the first direction and the second direction. Figure 2 At the A boundary in FIG, three virtual sub-pixels 80 are distributed along the first direction, and two virtual sub-pixels 80 are distributed along the second direction.

[0118] like Figure 7 As shown, the virtual sub-pixel driving circuit includes the virtual driving transistor and the first conductive connection part 8061, one end of the first conductive connection part 8061 is coupled to the gate of the virtual driving transistor, and the potential on the first conductive connection part 8061 is the potential of the N1 node.

[0119] The virtual sub-pixel 80 also includes the first potential signal line pattern and the second conductive connection portion 8062. In the same virtual sub-pixel 80, one end of the second conductive connection portion 8062 is coupled to the other end of the first conductive connection portion 8061, and the other end of the second conductive connection portion 8062 is coupled to the first potential signal line pattern, thereby achieving the goal of maintaining the N1 node at the same potential as the first potential signal line pattern.

[0120] It should be noted that the above-mentioned “coupling” includes direct electrical connection and indirect electrical connection through a conductive layer.

[0121] Exemplarily, the first conductive connection portion 8061 and the second conductive connection portion 8062 may be formed as an integral structure. Note that the integral structure includes: the first conductive connection portion 8061 and the second conductive connection portion 8062 being simultaneously formed in contact with each other using the same material through a single patterning process; or the first conductive connection portion 8061 and the second conductive connection portion 8062 being in direct contact with each other.

[0122] Exemplarily, the first conductive connection portion 8061 extends along a first direction, the second conductive connection portion 8062 extends along a second direction, and the width of the first conductive connection portion 8061 in a direction perpendicular to the first direction is smaller than the width of the second conductive connection portion 8062 in a direction perpendicular to the second direction. When the first potential signal line pattern includes the first power signal line pattern 801, this approach can further reduce the resistance of the first power signal line pattern 801.

[0123] Illustratively, the first conductive connection portion 8061 extends along a first direction, the second conductive connection portion 8062 extends along a second direction, and the width of the first conductive connection portion 8061 perpendicular to the first direction is equal to the width of the second conductive connection portion 8062 perpendicular to the second direction.

[0124] Exemplarily, the orthographic projection of the first conductive connection portion 8061 on the substrate has a first overlapping area with the orthographic projection of the first gate line pattern 802 on the substrate, and the width of the portion of the first conductive connection portion 8061 located in the first overlapping area perpendicular to the first direction is smaller than the width of the remaining portion of the first conductive connection portion 8061 perpendicular to the first direction.

[0125] Exemplarily, the orthographic projection of the second conductive connection portion 8062 on the substrate has a second overlapping area with the orthographic projection of the first gate line pattern 802 on the substrate, and the width of the portion of the second conductive connection portion 8062 located in the second overlapping area perpendicular to the second direction is smaller than the width of the remaining portion of the second conductive connection portion 8062 perpendicular to the second direction.

[0126] Exemplarily, the orthographic projection of the first power signal line pattern 801 on the substrate has a third overlapping area with the orthographic projection of the first gate line pattern 802 on the substrate, and the width of the portion of the first power signal line pattern 801 located in the third overlapping area, in a direction perpendicular to the first direction, is smaller than the width of the remaining portion of the first power signal line pattern 801 in a direction perpendicular to the first direction.

[0127] The above configuration can better reduce the overlapping area between the first gate line pattern 802 and the first conductive connection portion 8061 , the second conductive connection portion 8062 and / or the first power signal line pattern 801 , thereby better reducing the load of the first gate line pattern 802 .

[0128] Illustratively, the first conductive connection portion 8061 and the second conductive connection portion 8062 are provided in different layers.

[0129] Exemplarily, the first conductive connection portion 8061 and the first power signal line pattern 801 are provided in the same layer, and the first conductive connection portion 8061 and the second conductive connection portion 8062 are provided in different layers.

[0130] Exemplarily, the first potential signal line pattern includes a first initialization signal line pattern, one end of the second conductive connection portion 8062 is coupled to the other end of the first conductive connection portion 8061, and the other end of the second conductive connection portion 8062 is coupled to the first initialization signal line pattern, thereby achieving the goal of maintaining the N1 node at the same potential as the first initialization signal line pattern.

[0131] Exemplarily, the first potential signal line pattern includes a first power signal line pattern 801. In the same virtual sub-pixel 80, one end of the second conductive connection portion 8062 is coupled to the other end of the first conductive connection portion 8061, and the other end of the second conductive connection portion 8062 is coupled to the first power signal line pattern 801, thereby achieving the goal of maintaining the N1 node at the same potential as the first power signal line pattern 801.

[0132] According to the specific structure of the above-mentioned display substrate, in the display substrate 1 provided by the embodiment of the present disclosure, by providing the second conductive connection portion 8062, the first conductive connection portion 8061 is coupled to the first potential signal line pattern, so that the N1 node in the virtual sub-pixel driving circuit always maintains the same stable potential as the first potential signal line pattern, thereby avoiding the phenomenon of local uneven display brightness in the display substrate 1 due to the floating connection of the N1 node.

[0133] The specific structures of the first conductive connection portion 8061, the first potential signal line pattern, and the second conductive connection portion 8062 vary. In some embodiments, the first potential signal line pattern includes a first power signal line pattern 801, wherein the first conductive connection portion 8061 extends along a first direction; the first power signal line pattern 801 includes a first portion 8011 extending along the first direction; the second conductive connection portion 8062 extends along a second direction that intersects the first direction, and the second conductive connection portion 8062 is coupled to the first conductive connection portion 8061 and the first portion 8011 of the first power signal line pattern 801, respectively.

[0134] Specifically, the first conductive connection portion 8061 may be extended along the first direction, the first portion 8011 of the first power signal line pattern 801 may be extended along the first direction, and the first conductive connection portion 8061 and the first power signal line pattern 801 may be arranged along the second direction.

[0135] At the same time, a second conductive connection portion 8062 can be set to extend along the second direction, and the orthographic projection of the second conductive connection portion 8062 on the substrate is located between the orthographic projection of the first conductive connection portion 8061 on the substrate and the orthographic projection of the first part 8011 of the first power signal line pattern 801 on the substrate. The end of the second conductive connection portion 8062 close to the first conductive connection portion 8061 is coupled to the first conductive connection portion 8061, and the end of the second conductive connection portion 8062 close to the first part 8011 is coupled to the first power signal line pattern 801.

[0136] like Figure 12 As shown, in some other embodiments, the first potential signal line graphic includes a first power signal line graphic 801, the first power signal line graphic 801 includes a first part 8011 and a second part 8012 coupled to each other, the first part 8011 extends along the first direction, the second part 8012 extends along the second direction, and the second direction intersects with the first direction; the first conductive connection portion 8061 extends along the first direction; the second conductive connection portion 8062 extends along the first direction, and the second conductive connection portion 8062 is coupled to the first conductive connection portion 8061 and the second part 8012 of the first power signal line graphic 801, respectively.

[0137] Specifically, the first power signal line pattern 801 may include a first portion 8011 and a second portion 8012 coupled to each other. The first power signal line pattern 801 of this structure has a larger area and can effectively reduce the voltage drop generated on the first power signal line pattern 801.

[0138] At the same time, the second part 8012 of the power signal line pattern can be set to extend along the second direction, and the first conductive connection part 8061 and the second conductive connection part 8062 both extend along the first direction. The orthographic projection of the second conductive connection part 8062 on the substrate is located between the orthographic projection of the first conductive connection part 8061 on the substrate and the orthographic projection of the second part 8012 of the first power signal line pattern 801 on the substrate. The end of the second conductive connection part 8062 close to the first conductive connection part 8061 is coupled to the first conductive connection part 8061, and the end of the second conductive connection part 8062 close to the second part 8012 is coupled to the second part 8012.

[0139] It should be noted that, in the above embodiment, the first direction may be the Y direction, and the second direction may be the X direction.

[0140] When the first power signal line pattern 801, the first conductive connection part 8061 and the second conductive connection part 8062 adopt the specific structure provided in the above embodiment, the layout space occupied by the second conductive connection part 8062 can be minimized to the maximum extent, thereby better reducing the overall layout space occupied by the virtual sub-pixel 80, which is more conducive to improving the resolution of the display substrate.

[0141] like Figure 13a As shown, in some embodiments, the second portions 8012 included in at least two of the virtual sub-pixels 80 are coupled along the second direction.

[0142] Specifically, the multiple sub-pixels included in the display substrate are distributed in an array and can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels. The multiple rows of sub-pixels are sequentially arranged along the first direction, and each row of sub-pixels includes multiple sub-pixels sequentially arranged along the second direction. The multiple sub-pixels include dummy sub-pixels 80 located at the edge and display sub-pixels 90 located at the center. The multiple columns of sub-pixels are sequentially arranged along the second direction, and each column of sub-pixels includes multiple sub-pixels sequentially arranged along the first direction. The multiple sub-pixels also include dummy sub-pixels 80 located at the edge and display sub-pixels 90 located at the center.

[0143] Exemplarily, the second parts 8012 included in the virtual sub-pixels 80 located in the same row along the second direction are coupled in sequence.

[0144] The above-mentioned second parts 8012 included in at least two virtual sub-pixels 80 along the second direction are coupled, so that the first power line pattern of at least part of the virtual sub-pixels 80 included in the display substrate can be formed into a mesh structure with a larger area, which is more conducive to reducing the voltage drop of the first power signal line pattern 801, thereby better improving the display quality of the display substrate.

[0145] It should be noted that the virtual sub-pixels 80 coupled together along the second direction are all located on the same side of the display substrate. For example, on the left or right side of the display substrate, the second parts 8012 included in the virtual sub-pixels 80 located in the same row along the second direction are coupled in sequence.

[0146] like Figure 3 As shown, in some embodiments, the first portion 8011 and the second portion 8012 included in at least one target virtual sub-pixel 80' are formed into an integrated structure; the target virtual sub-pixel 80' is the virtual sub-pixel 80 located at the outermost side of the display area along the first direction.

[0147] Specifically, if Figure 13aAs shown, when the first part 8011 and the second part 8012 included in a plurality of target virtual sub-pixels 80' located in the same row are formed into an integrated structure, the length of the first data line graphic 808 included in the target virtual sub-pixel 80' along the first direction can be shortened to avoid a short circuit between the first data line graphic 808 and the second part 8012.

[0148] Exemplarily, the first portion 8011 and the second portion 8012 included in each target virtual sub-pixel 80 ′ are formed into an integrated structure.

[0149] Exemplarily, the first portion 8011 and the second portion 8012 included in the target virtual sub-pixels 80 ′ located in the same row along the second direction are formed into an integrated structure.

[0150] In addition, it is worth noting that the target dummy sub-pixel 80 ′ may not include the first initialization signal line pattern 804 , the first reset signal line pattern 805 and the second dummy transistor T2 ′.

[0151] like Figure 7 and Figure 12 As shown, in some embodiments, the first potential signal line pattern includes a first power signal line pattern 801 , and the first conductive connection portion 8061 , the second conductive connection portion 8062 and the first power signal line pattern 801 form an integrated structure.

[0152] The first conductive connection part 8061, the second conductive connection part 8062 and the first power signal line pattern 801 are formed into an integrated structure, so that the first conductive connection part 8061, the second conductive connection part 8062 and the first power signal line pattern 801 can be formed simultaneously in one composition process, thereby better simplifying the production process of the display substrate and reducing the production cost of the display substrate.

[0153] It should be noted that the first conductive connection portion 8061 , the second conductive connection portion 8062 and the first power signal line pattern 801 can all be made of the first source-drain metal layer in the display substrate.

[0154] like Figure 7 and Figure 12 As shown, in some embodiments, the virtual sub-pixel 80 further includes:

[0155] a first gate line pattern 802 and a first light-emitting control signal line pattern 803, both extending along the second direction, wherein the first gate line pattern 802 and the first light-emitting control signal line pattern 803 are arranged along the first direction, and an orthographic projection of the gate of the dummy drive transistor on the substrate is located between the orthographic projection of the first gate line pattern 802 on the substrate and the orthographic projection of the first light-emitting control signal line pattern 803 on the substrate;

[0156] The orthographic projection of the first gate line pattern 802 on the substrate is located between the orthographic projection of the second conductive connection portion 8062 on the substrate and the orthographic projection of the first light-emitting control signal line pattern 803 on the substrate.

[0157] Specifically, the specific layout position of the second conductive connection portion 8062 is varied. For example, the orthographic projection of the first gate line pattern 802 on the substrate can be set between the orthographic projection of the second conductive connection portion 8062 on the substrate and the orthographic projection of the first light-emitting control signal line pattern 803 on the substrate; in this way, the second conductive connection portion 8062 can be located on the side of the first gate line pattern 802 away from the first light-emitting control signal line pattern 803 and the virtual drive transistor, so that the second conductive connection portion 8062 has a larger layout space, which can better avoid the second conductive connection portion 8062 from short-circuiting with other conductive structures other than the first conductive connection portion 8061 and the first power signal line pattern 801, thereby better improving the stability of the display substrate.

[0158] like Figure 13a and Figure 15 As shown, in some embodiments, the display sub-pixel 90 includes:

[0159] A second gate line pattern 902 and a second light emitting control signal line pattern 903 both extending along the second direction;

[0160] The first gate line pattern 802 included in at least one of the virtual sub-pixels 80 along the second direction, and the second gate line pattern 902 included in the display sub-pixel 90 located in the same row as the virtual sub-pixel and adjacent to the at least one virtual sub-pixel 80 along the second direction form an integrated structure;

[0161] The first light-emitting control signal line pattern 803 included in at least one of the virtual sub-pixels 80 along the second direction, and the second light-emitting control signal line pattern 903 included in the display sub-pixel 90 located in the same row as the virtual sub-pixel along the second direction and adjacent to the at least one virtual sub-pixel form an integrated structure.

[0162] Specifically, the display sub-pixel 90 includes the second gate line pattern 902 and the second light emitting control signal line pattern 903, the second gate line pattern 902 and the second light emitting control signal line pattern 903 are arranged opposite to each other along the first direction, and at least a portion of the second gate line pattern 902 extends along the second direction.

[0163] When laying out the virtual sub-pixels 80 and the display sub-pixels 90, illustratively, the first gate line pattern 802 included in each of the virtual sub-pixels 80 located in the same row along the second direction, and the second gate line pattern 902 included in each of the display sub-pixels 90 located in the row can be laid out on the same straight line; similarly, the first light-emitting control signal line pattern 803 included in each of the virtual sub-pixels 80 located in the same row along the second direction, and the second light-emitting control signal line pattern 903 included in each of the display sub-pixels 90 located in the row can be laid out on the same straight line.

[0164] Exemplarily, the first gate line patterns 802 included in each of the virtual sub-pixels 80 located in the same row along the second direction, and the second gate line patterns 902 included in each of the display sub-pixels 90 located in the row are sequentially coupled to form an integrated structure;

[0165] The first light-emitting control signal line pattern 803 included in each of the virtual sub-pixels 80 located in the same row along the second direction, and the second light-emitting control signal line pattern 903 included in each of the display sub-pixels 90 located in the row are coupled in sequence to form an integrated structure.

[0166] Furthermore, the first gate line pattern 802, the first light-emitting control signal line pattern 803, the second gate line pattern 902 and the second light-emitting control signal line pattern 903 can also be set in the same layer and the same material. In this way, all of the first gate line patterns 802, all of the first light-emitting control signal line patterns 803 and all of the second gate line patterns 902, all of the second light-emitting control signal line patterns 903 in the display substrate can be formed simultaneously through a single patterning process, thereby better simplifying the production process of the display substrate and reducing the production cost of the display substrate.

[0167] like Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in some embodiments, the first potential signal line pattern includes a first power signal line pattern 801; the virtual sub-pixel driving circuit further includes:

[0168] a first storage capacitor Cst', wherein the gate of the virtual driving transistor is reused as a first plate Cst1' of the first storage capacitor Cst', a second plate Cst2' of the first storage capacitor Cst' is located on a side of the first plate Cst1' facing away from the substrate, an orthographic projection of the second plate Cst2' on the substrate and an orthographic projection of a first portion 8011 of the first power signal line pattern 801 extending along the first direction on the substrate having an overlapping area, and the second plate is coupled to the first portion 8011 in the overlapping area;

[0169] The display sub-pixel 90 further includes:

[0170] a second power signal line pattern 901, wherein the second power signal line pattern 901 includes a third portion extending along the first direction;

[0171] The display sub-pixel driving circuit further includes a driving transistor and a second storage capacitor Cst. The gate of the driving transistor is multiplexed as a third plate Cst1 of the second storage capacitor Cst. A fourth plate Cst2 of the second storage capacitor Cst is located on a side of the third plate Cst1 facing away from the substrate. An orthographic projection of the fourth plate Cst2 on the substrate overlaps with an orthographic projection of a third portion of the second power signal line pattern 901 on the substrate. In the overlapping area, the fourth plate Cst2 is coupled to the third portion.

[0172] The second electrode plate Cst2 included in each of the dummy sub-pixels 80 located in the same row along the second direction and the fourth electrode plate Cst2 included in each of the display sub-pixels 90 located in the row form an integrated structure.

[0173] Specifically, the virtual sub-pixel driving circuit also includes a first storage capacitor, and the display sub-pixel driving circuit also includes a second storage capacitor. The second plate of the first storage capacitor and the fourth plate of the second storage capacitor can be set in the same layer and the same material, so that the second plates of all the first storage capacitors and the fourth plates of the second storage capacitors included in the display substrate can be formed simultaneously in the same patterning process, thereby better simplifying the production process of the display substrate and reducing the production cost of the display substrate.

[0174] The above-mentioned arrangement forms an integrated structure of the second electrode plate included in each of the virtual sub-pixels 80 located in the same row along the second direction, and the fourth electrode plate included in each of the display sub-pixels 90 located in the row, which can minimize the layout space occupied by the second electrode plate and the fourth electrode plate, and is more conducive to the high-resolution development trend of the display substrate.

[0175] like Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in some embodiments, the display sub-pixel 90 includes: a second power signal line pattern 901, the second power signal line pattern 901 includes a third portion extending along the first direction;

[0176] The first portion 8011 of the first power signal line pattern 801 included in each of the virtual sub-pixels 80 located in the same column along the first direction and the third portion of the second power signal line pattern 901 included in each of the display sub-pixels 90 located in the column form an integrated structure.

[0177] This arrangement minimizes the layout space occupied by the first power signal line pattern 801 and the second power signal line pattern 901, further facilitating the development of high-resolution display substrates. Furthermore, all first power signal line patterns 801 included in the virtual sub-pixel 80 and all second power signal line patterns 901 included in the display sub-pixel 90 can be simultaneously formed through a single patterning process, thereby further simplifying the display substrate manufacturing process and reducing the display substrate manufacturing cost.

[0178] like Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown, in some embodiments, the virtual sub-pixel 80 further includes:

[0179] A first gate line pattern 802, a first light-emitting control signal line pattern 803, a first initialization signal line pattern 804, and a first reset signal line pattern 805, all extending along the second direction; the first gate line pattern 802, the first light-emitting control signal line pattern 803, the first initialization signal line pattern 804, and the first reset signal line pattern 805 are arranged in sequence along the first direction;

[0180] The display sub-pixel 90 further includes: a second initialization signal line pattern 9041, a third initialization signal line pattern 9042, a second reset signal line pattern 9051, and a third reset signal line pattern 9052, all extending along the second direction;

[0181] The first initialization signal line pattern 804 included in each of the dummy sub-pixels 80 located in the same row along the second direction and the second initialization signal line pattern 9041 included in each of the display sub-pixels 90 located in the row are sequentially coupled to form an integrated structure;

[0182] The first reset signal line pattern 805 included in each of the virtual sub-pixels 80 located in the same row along the second direction and the second reset signal line pattern 9051 included in each of the display sub-pixels 90 located in the row are coupled in sequence to form an integrated structure.

[0183] Specifically, in one of the display sub-pixels 90 , the second initialization signal line pattern 9041 , the second reset signal line pattern 9051 , the third initialization signal line pattern 9042 , and the third reset signal line pattern 9052 may be sequentially arranged along the first direction.

[0184] The above-mentioned arrangement comprises the first initialization signal line pattern 804 included in each of the virtual sub-pixels 80 located in the same row along the second direction, and the second initialization signal line pattern 9041 included in each of the display sub-pixels 90 located in the row, which are coupled in sequence and form an integrated structure; and the first reset signal line pattern 805 included in each of the virtual sub-pixels 80 located in the same row along the second direction, and the second reset signal line pattern 9051 included in each of the display sub-pixels 90 located in the row, which are coupled in sequence and form an integrated structure; not only effectively reduces the layout space occupied by each virtual sub-pixel 80 and display sub-pixel 90, but also can simultaneously form the first initialization signal line pattern 804 and the second initialization signal line pattern 9041 through a single patterning process; and can simultaneously form the first reset signal line pattern 805 and the second reset signal line pattern 9051 through a single patterning process.

[0185] It is worth noting that in the display sub-pixel 90, the second initialization signal line pattern 9041 and the third initialization signal line pattern 9042 are set on the same layer and made of the same material, and can be formed simultaneously in the same composition process; the second reset signal line pattern 9051 and the third reset signal line pattern 9052 are set on the same layer and made of the same material, and can be formed simultaneously in the same composition process.

[0186] like Figure 13a and Figure 15 As shown, in some embodiments, the virtual sub-pixel 80 further includes: a first data line graphic 808 extending along a first direction; the display sub-pixel 90 includes a second data line graphic 908 extending along the first direction; the first data line graphic 808 included in each of the virtual sub-pixels 80 located in the same column along the first direction, and the second data line graphic 908 included in each of the display sub-pixels 90 located in the column form an integrated structure.

[0187] Specifically, the above arrangement forms an integrated structure with the first data line patterns 808 included in each of the virtual sub-pixels 80 located in the same column along the first direction, and the second data line patterns 908 included in each of the display sub-pixels 90 located in the same column. This minimizes the layout space occupied by the first data line patterns 808 and the second data line patterns 908, further facilitating the development of high-resolution display substrates. Furthermore, all of the first data line patterns 808 included in the virtual sub-pixels 80 and all of the second data line patterns 908 included in the display sub-pixels 90 can be simultaneously formed through a single patterning process, thereby further simplifying the display substrate manufacturing process and reducing the display substrate manufacturing cost.

[0188] like Figure 8 As shown, in some embodiments, the virtual sub-pixel 80 includes an active layer pattern, and the active layer pattern includes:

[0189] A first active sub-pattern 8071 and a second active sub-pattern 8072 are arranged opposite to each other, and both the first active sub-pattern 8071 and the second active sub-pattern 8072 extend along a first direction;

[0190] a third active sub-pattern 8073 disposed between the first active sub-pattern 8071 and the second active sub-pattern 8072, wherein two ends of the third active sub-pattern 8073 are coupled to the first active sub-pattern 8071 and the second active sub-pattern 8072, and an orthographic projection of at least a portion of the third active sub-pattern 8073 on the substrate overlaps with an orthographic projection of the gate of the dummy driving transistor on the substrate;

[0191] like Figure 7 As shown, the orthographic projection of the portion of the first conductive connection portion 8061 away from the gate of the dummy driving transistor on the substrate does not overlap with the orthographic projection of the active layer pattern on the substrate.

[0192] Specifically, the specific structure of the active layer pattern included in the virtual sub-pixel 80 is varied. Exemplarily, the active layer pattern is set to include: the first active sub-pattern 8071, the second active sub-pattern 8072 and the third active sub-pattern 8073; this arrangement makes the orthographic projection of the first conductive connection portion 8061 on the substrate located between the orthographic projection of the first active sub-pattern 8071 on the substrate and the orthographic projection of the second active sub-pattern 8072 on the substrate; the orthographic projection of the end of the first conductive connection portion 8061 coupled to the virtual driving transistor on the substrate overlaps with the orthographic projection of the third active sub-pattern 8073 on the substrate; the orthographic projection of the portion of the first conductive connection portion 8061 away from the gate of the virtual driving transistor on the substrate does not overlap with the orthographic projection of the active layer pattern on the substrate.

[0193] The above configuration simplifies the structure of the active layer pattern included in the virtual sub-pixel 80, effectively reduces the layout space occupied by the active layer pattern, and thus better reduces the layout difficulty of the virtual sub-pixel 80 in the edge area.

[0194] like Figure 7 and Figure 8 As shown, in some embodiments, the virtual sub-pixel 80 further includes a first data line pattern 808 extending along the first direction, and the orthographic projection of the second active sub-pattern 8072 on the substrate is located between the orthographic projection of the first data line pattern 808 on the substrate and the orthographic projection of the first active sub-pattern 8071 on the substrate;

[0195] An orthographic projection of the first data line pattern 808 on the substrate does not overlap with an orthographic projection of the active layer pattern on the substrate.

[0196] Specifically, in the virtual sub-pixel 80, the orthographic projection of the portion of the first power signal line pattern 801 extending along the first direction on the substrate can cover at least part of the orthographic projection of the second active sub-pattern 8072 on the substrate, the first data line pattern 808 is spaced apart from the first power signal line pattern 801, and the orthographic projection of the first data line pattern 808 on the substrate does not overlap with the orthographic projection of the active layer pattern on the substrate, and will not provide a data signal to the virtual sub-pixel driving circuit.

[0197] Since the virtual sub-pixel driving circuit included in the virtual sub-pixel 80 is not a complete circuit structure, that is, the virtual sub-pixel driving circuit cannot achieve normal driving function, the above-mentioned setting method makes the first data line graphic 808 not provide data signals for the virtual sub-pixel 80, thereby avoiding the problem that the virtual sub-pixel driving circuit operates abnormally due to receiving the data signal, thereby affecting the stability of the display substrate.

[0198] like Figure 14 and Figure 15 As shown, in some embodiments, the display sub-pixel driving circuit also includes a third conductive connection portion 8063 extending along the first direction, the first end of the third conductive connection portion 8063 is coupled to the gate of the driving transistor (i.e., the gate 203g of the third transistor T3), and the second end of the third conductive connection portion 8063 is coupled to the second electrode of the first transistor T1 and the second electrode of the second transistor T2, respectively.

[0199] like Figure 14 and Figure 15 As shown, in some embodiments, the second electrode of the first transistor T1 is coupled to the second electrode of the second transistor T2 to form a common connection terminal (located at Figure 15 The orthographic projection of the second end of the third conductive connection portion 8063 on the substrate overlaps with the orthographic projection of the common connection end on the substrate, and the second end of the third conductive connection portion 8063 is coupled to the common connection end at the overlapping position.

[0200] like Figures 14 and 15 As shown, in some embodiments, the display sub-pixel 90 includes: a second power signal line pattern 901, a second data line pattern 908, a second gate line pattern 902, a second light-emitting control signal line pattern 903, a second reset signal line pattern 9051, a third reset signal line pattern 9052, a second initialization signal line pattern 9041, and a third initialization signal line pattern 9042; at least a portion of the second power signal line pattern 901 and the second data line pattern 908 extend along a first direction; the second gate line pattern 902, the second light-emitting control signal line pattern 903, the second reset signal line pattern 9051, the third reset signal line pattern 9052, the second initialization signal line pattern 9041, and the third initialization signal line pattern 9042 all extend along a second direction, and the second direction intersects with the first direction;

[0201] The display sub-pixel 90 further includes a display sub-pixel driving circuit, which includes: a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0202] The gate of the driving transistor is coupled to the second electrode of the first transistor, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled to the first electrode of the first transistor;

[0203] The gate of the first transistor is coupled to the second gate line pattern 902;

[0204] The gate of the second transistor is coupled to the second reset signal line pattern 9051, the first electrode of the second transistor is coupled to the second initialization signal line pattern 9041, and the second electrode of the second transistor is coupled to the gate of the driving transistor;

[0205] A gate electrode of the fourth transistor is coupled to the second gate line pattern 902 , a first electrode of the fourth transistor is coupled to the second data line pattern 908 , and a second electrode of the fourth transistor is coupled to the first electrode of the driving transistor;

[0206] The gate of the fifth transistor is coupled to the second light emitting control signal line pattern 903, and the first electrode of the fifth transistor is coupled to the second power supply signal line pattern 901;

[0207] The gate of the sixth transistor is coupled to the second light emitting control signal line pattern 903 , the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the light emitting element in the display sub-pixel 90 ;

[0208] The second electrode of the seventh transistor is coupled to the light-emitting element in the display sub-pixel 90 , the gate of the seventh transistor is coupled to the third reset signal line pattern 9052 , and the first electrode of the seventh transistor is coupled to the third initialization signal line pattern 9042 .

[0209] Specifically, if Figure 14 and Figure 15 As shown, taking a display sub-pixel driving circuit as an example, each transistor included in the display sub-pixel driving circuit is a P-type transistor, wherein the first transistor T1 is a dual-gate structure, the gate 201g of the first transistor T1 is coupled to the second gate line pattern 902, the source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3 (i.e., the driving transistor), and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.

[0210] The second transistor T2 has a dual-gate structure, a gate 202g of the second transistor T2 is coupled to the second reset signal line pattern 9051, a source S2 of the second transistor T2 is coupled to the second initialization signal line pattern 9041, and a drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0211] A gate 204g of the fourth transistor T4 is coupled to the second gate line pattern 902, a source S4 of the fourth transistor T4 is coupled to the second data line pattern 908, and a drain D4 of the fourth transistor T4 is coupled to the source S3 of the third transistor T3.

[0212] The gate 205g of the fifth transistor T5 is coupled to the second light emitting control signal line pattern 903, the source S5 of the fifth transistor T5 is coupled to the second power signal line pattern 901, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0213] The gate 206g of the sixth transistor T6 is coupled to the second light emitting control signal line pattern 903, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode of the light emitting element EL.

[0214] A gate 207 g of the seventh transistor T7 is coupled to the third reset signal line pattern 9052 , a drain D7 of the seventh transistor T7 is coupled to the anode of the light emitting element EL, and a source S7 of the seventh transistor T7 is coupled to the third initialization signal line pattern 9042 .

[0215] The third plate Cst1 of the second storage capacitor Cst is multiplexed as the gate 203 g of the third transistor T3 , and the fourth plate Cst2 of the second storage capacitor Cst is coupled to the second power signal line pattern 901 .

[0216] When the display sub-pixel driving circuit of the above structure is in operation, each operation cycle includes a first reset period P1, a writing compensation period P2, a second reset period P3 and a light emitting period P4.

[0217] During the first reset period P1, the second reset signal input by the second reset signal line graph 9051 is at a valid level, the second transistor T2 is turned on, and the initialization signal transmitted by the second initialization signal line graph 9041 is input to the gate 203g of the third transistor T3, so that the gate-source voltage Vgs maintained on the third transistor T3 in the previous frame is cleared, thereby resetting the gate 203g of the third transistor T3.

[0218] During the write compensation period P2, the second reset signal is at an inactive level, the second transistor T2 is turned off, the gate scan signal input by the second gate line pattern 902 is at an active level, the first transistor T1 and the fourth transistor T4 are controlled to be turned on, the second data line pattern 908 writes the data signal, and is transmitted to the source S3 of the third transistor T3 through the fourth transistor T4. At the same time, the first transistor T1 and the fourth transistor T4 are turned on, so that the third transistor T3 forms a diode structure. Therefore, the threshold voltage of the third transistor T3 is compensated by the cooperation of the first transistor T1, the third transistor T3 and the fourth transistor T4. When the compensation time is long enough, the gate 203g potential of the third transistor T3 can be controlled to eventually reach Vdata+Vth, where Vdata represents the data signal voltage value and Vth represents the threshold voltage of the third transistor T3.

[0219] In the second reset period P3, the gate scan signal is at an inactive level, the first transistor T1 and the fourth transistor T4 are both turned off, the third reset signal input by the third reset signal line pattern 9052 is at an active level, controlling the seventh transistor T7 to be turned on, and the initialization signal transmitted by the third initialization signal line pattern 9042 is input to the anode of the light-emitting element EL, controlling the light-emitting element EL not to emit light.

[0220] During the light-emitting period P4, the light-emitting control signal written in the second light-emitting control signal line pattern 903 is at an effective level, controlling the fifth transistor T5 and the sixth transistor T6 to be turned on, so that the power signal transmitted by the second power signal line pattern 901 is input to the source S3 of the third transistor T3. At the same time, since the gate 203g of the third transistor T3 is maintained at Vdata+Vth, the third transistor T3 is turned on, and the gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, where VDD is the voltage value corresponding to the power signal. The leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element EL, driving the corresponding light-emitting element EL to emit light.

[0221] like Figure 13a 、 Figure 13c 、 Figures 16-19 As shown, when manufacturing the above-mentioned display sub-pixel driving circuit, the layout of each film layer corresponding to the display sub-pixel driving circuit is as follows:

[0222] An active film layer, a first gate insulating layer GI1, a first gate metal layer, a second gate insulating layer GI2, a second gate metal layer, an interlayer insulating layer ILD, and a first source-drain metal layer are stacked in sequence in a direction away from the substrate 40; and an inorganic insulating layer, a planar layer, an anode and other film layers are also arranged on the source-drain metal layer.

[0223] It should be noted that in the embodiments of the present disclosure, the inorganic layer can be made of inorganic materials such as silicon nitride and silicon oxide; the organic layer, such as the planar layer and the pixel defining layer, can be made of organic materials such as polyimide, which is not limited in the present disclosure.

[0224] like Figure 16 As shown, the active film layer is used to form the channel region (e.g., 101pg to 107pg), source formation region (e.g., 101ps to 107ps), and drain formation region (e.g., 101pd to 107pd) of each transistor in the display sub-pixel driving circuit. Due to doping, the active film layer corresponding to the source formation region and the drain formation region has better conductivity than the active film layer corresponding to the channel region. The active film layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0225] In addition, it is worth noting that the active film layers corresponding to the source formation region and the drain formation region can directly serve as the corresponding source or drain, or, a source in contact with the source formation region can be made of metal material, and a drain in contact with the drain formation region can be made of metal material.

[0226] like Figure 17 As shown, the first gate metal layer is used to form the gate of each transistor in the display sub-pixel driving circuit (such as: 201g~207g), and the display substrate includes a second gate line pattern 902, a second light-emitting control signal line pattern 903, a second reset signal line pattern 9051 and a third reset signal line pattern 9052 and other structures. The gate 203g of the third transistor T3 in each display sub-pixel driving circuit is reused as the third plate Cst1 of the second storage capacitor Cst in the display sub-pixel driving circuit.

[0227] like Figure 18 As shown, the second gate metal layer is used to form the fourth plate Cst2 of the second storage capacitor Cst, and the second initialization signal line pattern 9041 and the third initialization signal line pattern 9042 included in the display substrate.

[0228] like Figure 14 、 Figure 15 and 19 As shown, the first source-drain metal layer is used to form the source (such as: S1~S7) and drain (such as: D1~D7) of each transistor in the display sub-pixel driving circuit, as well as the second data line pattern 908, the second power signal line pattern 901 and some conductive connection parts included in the display substrate.

[0229] For more details, please refer to Figures 14 to 17The gate 201g of the first transistor T1 covers the first channel region 101pg, the source S1 of the first transistor T1 is located in the first source formation region 101ps, and the drain D1 of the first transistor T1 is located in the first drain formation region 101pd.

[0230] The gate 202g of the second transistor T2 covers the second channel region 102pg, the source S2 of the second transistor T2 is located in the second source formation region 102ps, and the drain D2 of the second transistor T2 is located in the second drain formation region 102pd.

[0231] The gate 203g of the third transistor T3 covers the third channel region 103pg, the source S3 of the third transistor T3 is located in the third source formation region 103ps, and the drain D3 of the third transistor T3 is located in the third drain formation region 103pd.

[0232] The gate 204g of the fourth transistor T4 covers the fourth channel region 104pg, the source S4 of the fourth transistor T4 is located in the fourth source formation region 104ps, and the drain D4 of the fourth transistor T4 is located in the fourth drain formation region 104pd.

[0233] The gate 205g of the fifth transistor T5 covers the fifth channel region 105pg, the source S5 of the fifth transistor T5 is located in the fifth source formation region 105ps, and the drain D5 of the fifth transistor T5 is located in the fifth drain formation region 105pd.

[0234] The gate 206g of the sixth transistor T6 covers the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located in the sixth source formation region 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain formation region 106pd.

[0235] The gate 207g of the seventh transistor T7 covers the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located in the seventh source formation region 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain formation region 107pd.

[0236] The gate 203g of the third transistor T3 is multiplexed as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD.

[0237] In addition, in the display substrate provided by the present disclosure, the multiple display sub-pixels 90 included can be distributed in an array, and the multiple display sub-pixels 90 can be divided into multiple rows of display sub-pixels 90 and multiple columns of display sub-pixels 90. Each row of display sub-pixels 90 includes multiple display sub-pixels 90 arranged along the second direction, and each column of display sub-pixels 90 includes multiple display sub-pixels 90 arranged along the first direction, and the first direction intersects with the second direction.

[0238] In order to simplify the layout space of sub-pixels, the third reset signal line graphic 9052 included in a row of display sub-pixels 90 can be multiplexed as the second reset signal line graphic 9051 included in the adjacent next row of display sub-pixels 90; similarly, the third initialization signal line graphic 9042 corresponding to a row of display sub-pixels 90 can be multiplexed as the second initialization signal line graphic 9041 corresponding to the adjacent next row of display sub-pixels 90.

[0239] like Figure 15 As shown, in some embodiments, taking the sub-pixel driving circuit included in a display sub-pixel 90 as an example, in a first direction (e.g., the Y direction), the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1, and the gate 202g of the second transistor T2 are all located on the first side of the gate of the driving transistor (i.e., the gate 203g of the third transistor T3), and the gate of the seventh transistor T7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 are all located on the second side of the gate of the driving transistor. Exemplarily, the first side and the second side of the gate of the driving transistor are two opposite sides along the first direction. Furthermore, the first side of the gate of the driving transistor can be the upper side of the gate of the driving transistor, and the second side of the gate of the driving transistor can be the lower side of the gate of the driving transistor T1. The lower side, for example, the side of the display substrate used for bonding the IC is the lower side of the display substrate. The lower side of the gate of the driving transistor is the side of the gate of the driving transistor closer to the IC. The upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor farther away from the IC.

[0240] In some embodiments, as Figure 15 As shown, in the second direction (e.g., the X direction), the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, and the gate 201g of the first transistor T1 and the gate 206g of the sixth transistor T6 are both located on the fourth side of the gate of the driving transistor. Exemplarily, the third side and the fourth side of the gate of the driving transistor are two opposite sides along the second direction; further, the third side of the gate of the driving transistor can be the right side of the gate of the driving transistor, and the fourth side of the gate of the driving transistor can be the left side of the gate of the driving transistor. For example, in the same sub-pixel, the second data line pattern 908 is located to the right of the second power signal line pattern 901, and the second power signal line pattern 901 is located to the right of the second data line pattern 908.

[0241] like Figure 6 and Figure 7 As shown, in some embodiments, the first potential signal line pattern includes a first power signal line pattern 801; the virtual sub-pixel 80 further includes:

[0242] a first data line pattern 808, a first gate line pattern 802, a first light-emitting control signal line pattern 803, a first reset signal line pattern 805, and a first initialization signal line pattern 804; at least a portion of the first power signal line pattern 801 and the first data line pattern 808 all extend along a first direction, and the first gate line pattern 802, the first light-emitting control signal line pattern 803, the first reset signal line pattern 805, and the first initialization signal line pattern 804 all extend along a second direction;

[0243] The dummy sub-pixel driving circuit further includes: a second dummy transistor, a fifth dummy transistor and a sixth dummy transistor;

[0244] The gate of the dummy driving transistor is coupled to the first power signal line pattern 801 , the first electrode of the dummy driving transistor is coupled to the second electrode of the fifth dummy transistor, and the second electrode of the dummy driving transistor is coupled to the first electrode of the sixth dummy transistor;

[0245] The gate of the second dummy transistor is coupled to the first reset signal line pattern 805 , the first electrode of the second dummy transistor is coupled to the first initialization signal line pattern 804 , and the second electrode of the second dummy transistor is floating;

[0246] The gate of the fifth dummy transistor is coupled to the first light emitting control signal line pattern 803 , and the first electrode of the fifth dummy transistor is coupled to the first power signal line pattern 801 ;

[0247] A gate of the sixth dummy transistor is coupled to the first light emitting control signal line pattern 803 .

[0248] Specifically, taking a virtual sub-pixel driving circuit as an example, each virtual transistor included in the virtual sub-pixel driving circuit is a P-type transistor, the second virtual transistor T2' is a dual-gate structure, the gate 202g' of the second virtual transistor T2' is coupled to the first reset signal line pattern 805, the source S2' of the second virtual transistor T2' is coupled to the first initialization signal line pattern 804, and the drain D2' of the second virtual transistor T2' is floating.

[0249] The gate 205g' of the fifth dummy transistor T5' is coupled to the first light emitting control signal line pattern 803, the source S5' of the fifth dummy transistor T5' is coupled to the first power signal line pattern 801, and the drain D5' of the fifth dummy transistor T5' is coupled to the source S3' of the third dummy transistor T3'.

[0250] The gate 206 g ′ of the sixth dummy transistor T6 ′ is coupled to the first light emitting control signal line pattern 803 .

[0251] Furthermore, the source S6 ′ of the sixth dummy transistor T6 ′ may be coupled to the drain D3 ′ of the third dummy transistor T3 ′, and the drain D6 ′ of the sixth dummy transistor T6 ′ may be coupled to the anode of the light emitting element EL.

[0252] Exemplarily, the virtual sub-pixel driving circuit also includes a seventh virtual transistor T7', the gate 207g' of the seventh virtual transistor T7' is coupled to the first reset signal line pattern 805' in the next virtual sub-pixel 80 adjacent along the first direction, the drain D7' of the seventh virtual transistor T7' is coupled to the anode of the light-emitting element EL, and the source S7' of the seventh virtual transistor T7' is coupled to the first initialization signal line pattern 804'.

[0253] The first plate Cst1 ′ of the first storage capacitor Cst′ is reused as the gate 203 g ′ of the third dummy transistor T3 ′ and coupled thereto. The second plate Cst2 ′ of the first storage capacitor Cst′ is coupled to the first power signal line pattern 801 .

[0254] In a normal display sub-pixel 90, the N1 node can be coupled to the active pattern (Poly pattern) corresponding to the drain D1 of the first transistor T1 through a hole, and the data signal can be written to the N1 node through the fourth transistor T4, the third transistor T3 and the first transistor T1 in sequence. During the light-emitting stage of the display sub-pixel 90, the leakage current will pass through the fifth transistor T5, the third transistor T3 and the sixth transistor T6 in sequence to reach the light-emitting element EL, causing the light-emitting element EL to emit light.

[0255] In the dummy sub-pixel 80, since the normal first dummy transistor T1' is not formed, the N1 node in the dummy sub-pixel 80 cannot properly receive the data signal, and thus the dummy sub-pixel driving circuit corresponding to the dummy sub-pixel 80 cannot function properly. In the present application, by providing the second conductive connection portion 8062 to couple the N1 node to the corresponding first power signal line pattern 801, the N1 node is prevented from being in a floating state and adversely affecting the power signal in the display substrate. This effectively improves the stability of the power signal in the display substrate and ensures the good operating performance of the display sub-pixel driving circuit.

[0256] It should be noted that the specific structure of the virtual sub-pixel driving circuit may be determined according to the actual layout. For example, the virtual sub-pixel driving circuit does not lack virtual transistors, or the lack of virtual transistors is not limited to the following: Figure 6 The first dummy transistor T1' and the fourth dummy transistor T4' in FIG.

[0257] In addition, according to actual layout requirements, the specific structures included in the virtual sub-pixel driving circuits located at different positions may be different. For example, some virtual sub-pixel driving circuits are provided to include a complete transistor structure (such as the first virtual transistor T1' to the seventh virtual transistor T7'), and other virtual sub-pixel driving circuits are provided to include partial virtual transistors.

[0258] like Figure 7 、 Figure 13a and Figure 13b As shown, when manufacturing the above-mentioned virtual sub-pixel driving circuit, the layout of each film layer corresponding to the virtual sub-pixel driving circuit is as follows:

[0259] An active film layer, a first gate insulating layer GI1 , a first gate metal layer, a second gate insulating layer GI2 , a second gate metal layer, an interlayer insulating layer ILD, and a first source / drain metal layer are sequentially stacked in a direction away from the substrate 40 .

[0260] like Figure 8 As shown, the active film layer is used to form the channel region (e.g., 102pg'-107pg'), source formation region (e.g., 102ps'-107ps'), and drain formation region (e.g., 102pd'-107pd') of each virtual transistor in the virtual sub-pixel driving circuit. Due to doping, the active film layer corresponding to the source formation region and the drain formation region has better conductivity than the active film layer corresponding to the channel region. The active film layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0261] In addition, it is worth noting that the active film layers corresponding to the source formation region and the drain formation region can directly serve as the corresponding source or drain, or, a source in contact with the source formation region can be made of metal material, and a drain in contact with the drain formation region can be made of metal material.

[0262] like Figure 9 As shown, the first gate metal layer is used to form the gate of each virtual transistor in the virtual sub-pixel driving circuit (such as: 202g'~207g'), and the display substrate includes a first gate line pattern 802, a first light-emitting control signal line pattern 803, a first reset signal line pattern 805 and other structures. The gate 203g' of the third virtual transistor T3' in each virtual sub-pixel driving circuit is reused as the first plate Cst1' of the first storage capacitor Cst' in the virtual sub-pixel driving circuit.

[0263] like Figure 10 As shown, the second gate metal layer is used to form the second plate Cst2 ′ of the first storage capacitor Cst′ and the first initialization signal line pattern 804 included in the display substrate.

[0264] like Figure 6 、 Figure 7 and 11 As shown, the first source-drain metal layer is used to form the source (such as: S2'~S7') and drain (such as: D2'~D7') of each virtual transistor in the virtual sub-pixel driving circuit, as well as the first data line pattern 808, the first power signal line pattern 801, the first conductive connection part 8061 and the second conductive connection part 8062 included in the display substrate.

[0265] For more details, please refer to Figures 6 to 9 The gate 202g' of the second dummy transistor T2' covers the second channel region 102pg', the source S2' of the second dummy transistor T2' is located in the second source formation region 102ps', and the drain D2' of the second dummy transistor T2' is located in the second drain formation region 102pd'.

[0266] The gate 203g' of the third dummy transistor T3' covers the third channel region 103pg', the source S3' of the third dummy transistor T3' is located in the third source formation region 103ps', and the drain D3' of the third dummy transistor T3' is located in the third drain formation region 103pd'.

[0267] The gate 205g' of the fifth dummy transistor T5' covers the fifth channel region 105pg', the source S5' of the fifth dummy transistor T5' is located in the fifth source formation region 105ps', and the drain D5' of the fifth dummy transistor T5' is located in the fifth drain formation region 105pd'.

[0268] The gate 206g' of the sixth dummy transistor T6' covers the sixth channel region 106pg', the source S6' of the sixth dummy transistor T6' is located in the sixth source formation region 106ps', and the drain D6' of the sixth dummy transistor T6' is located in the sixth drain formation region 106pd'.

[0269] The gate 207g' of the seventh dummy transistor T7' covers the seventh channel region 107pg', the source S7' of the seventh dummy transistor T7' is located in the seventh source formation region 107ps', and the drain D7' of the seventh dummy transistor T7' is located in the seventh drain formation region 107pd'.

[0270] The gate 203 g ′ of the third dummy transistor T3 ′ is reused as the first plate Cst1 ′ of the first storage capacitor Cst′. The second plate Cst2 ′ of the first storage capacitor Cst′ is coupled to the first power signal line pattern 801 .

[0271] In addition, in the display substrate provided by the present disclosure, the multiple virtual sub-pixels 80 included can be distributed in an array, and the multiple virtual sub-pixels 80 can be divided into multiple rows of virtual sub-pixels 80 and multiple columns of virtual sub-pixels 80. Each row of virtual sub-pixels 80 includes multiple virtual sub-pixels 80 arranged along the second direction, and each column of virtual sub-pixels 80 includes multiple virtual sub-pixels 80 arranged along the first direction, and the first direction intersects with the second direction.

[0272] To simplify the layout space of sub-pixels, the gate 207g' of the seventh dummy transistor T7' in a row of dummy sub-pixels 80 may be coupled to the second reset signal line pattern 9051 of the next display sub-pixel 90 adjacent along the first direction.

[0273] like Figure 7 As shown, in some embodiments, taking the sub-pixel driving circuit included in a virtual sub-pixel 80 as an example, in a first direction (e.g., the Y direction), the gate 202g' of the second dummy transistor T2' is located on the first side of the gate of the dummy driving transistor (i.e., the gate 203g' of the third dummy transistor T3'), and the gate 207g' of the seventh dummy transistor T7', the gate 206g' of the sixth dummy transistor T6', and the gate 205g' of the fifth dummy transistor T5' are all located on the second side of the gate of the dummy driving transistor. Exemplarily, the first side and the second side of the gate of the dummy driving transistor are opposite sides along the first direction. Furthermore, the first side of the gate of the dummy driving transistor can be the upper side of the gate of the dummy driving transistor, and the second side of the gate of the dummy driving transistor can be the lower side of the gate of the dummy driving transistor T1. The lower side, for example, the side of the dummy substrate used for bonding the IC is the lower side of the dummy substrate. The lower side of the gate of the dummy driving transistor is the side of the gate of the dummy driving transistor closer to the IC. The upper side is an opposite side to the lower side, for example, a side of the gate of the dummy driving transistor that is farther away from the IC.

[0274] In some embodiments, as Figure 7 As shown, in the second direction (e.g., the X direction), the gate 205g' of the fifth dummy transistor T5' is located on the third side of the gate of the dummy drive transistor, and the gate 206g' of the sixth dummy transistor T6' is located on the fourth side of the gate of the dummy drive transistor. Exemplarily, the third side and the fourth side of the gate of the dummy drive transistor are two opposite sides along the second direction; further, the third side of the gate of the dummy drive transistor can be the right side of the gate of the dummy drive transistor, and the fourth side of the gate of the dummy drive transistor can be the left side of the gate of the dummy drive transistor. For example, in the same sub-pixel, the first data line pattern 808 is located on the right side of the first power signal line pattern 801, and the first power signal line pattern 801 is located on the right side of the first data line pattern 808.

[0275] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0276] Because the display substrate 1 provided in the above embodiment is provided with the second conductive connection portion 8062, coupling the first conductive connection portion 8061 to the first power signal line pattern 801, the N1 node in the virtual sub-pixel driving circuit always maintains the same stable potential as the first power signal line pattern 801, thereby avoiding the phenomenon of uneven local display brightness on the display substrate 1 caused by the floating connection of the N1 node. Therefore, the display device provided in the embodiment of the present disclosure also has the above-mentioned beneficial effects when including the above-mentioned display substrate, and no further details are given here.

[0277] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, or a tablet computer.

[0278] The present disclosure also provides a method for manufacturing a display substrate, the method comprising:

[0279] A plurality of sub-pixels arranged in an array are fabricated on a substrate; the plurality of sub-pixels include a plurality of display sub-pixels 90 located in a display area of a display panel, and a plurality of dummy sub-pixels 80 at least partially adjacent to the plurality of display sub-pixels;

[0280] The display sub-pixel 90 includes: a display sub-pixel driving circuit, wherein the display sub-pixel driving circuit includes a driving transistor (i.e., a third transistor T3), a first transistor T1, and a second transistor T2; the gate of the driving transistor is coupled to the second electrode (i.e., the drain D1) of the first transistor T1 and the second electrode (i.e., the drain D2) of the second transistor T2, respectively;

[0281] The virtual sub-pixel 80 includes:

[0282] a first potential signal line pattern;

[0283] a dummy sub-pixel driving circuit, the dummy sub-pixel driving circuit comprising a dummy driving transistor and a first conductive connection portion 8061 coupled to a gate of the dummy driving transistor;

[0284] The second conductive connection portion 8062 is coupled to the first conductive connection portion 8061 and the first potential signal line pattern respectively.

[0285] In the display substrate 1 manufactured using the manufacturing method provided by the embodiment of the present disclosure, the first conductive connection portion 8061 is coupled to the first potential signal line pattern by setting the second conductive connection portion 8062, so that the N1 node in the virtual sub-pixel driving circuit always maintains the same stable potential as the first potential signal line pattern, thereby avoiding the phenomenon of local uneven display brightness in the display substrate 1 due to the floating connection of the N1 node.

[0286] In some embodiments, the first potential signal line pattern includes a first power signal line pattern 801; and the steps of manufacturing the first conductive connecting portion 8061, the second conductive connecting portion 8062, and the first potential signal line pattern specifically include:

[0287] Through a single patterning process, the first conductive connection portion 8061 , the second conductive connection portion 8062 and the first power signal line pattern 801 are formed as an integrated structure.

[0288] The first conductive connection portion 8061 , the second conductive connection portion 8062 and the first power signal line pattern 801 can be formed simultaneously in one patterning process, thereby better simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.

[0289] It should be noted that in the drawings of the present disclosure, the small squares with cross lines represent the approximate locations of the vias.

[0290] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0291] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0292] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0293] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0294] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate; the plurality of sub-pixels comprising a plurality of display sub-pixels located in a display area of a display panel and a plurality of dummy sub-pixels at least partially adjacent to the plurality of display sub-pixels; The display sub-pixel comprises: A display sub-pixel driving circuit, wherein the display sub-pixel driving circuit includes a driving transistor, a first transistor, and a second transistor; The gate of the driving transistor is coupled to the second electrode of the first transistor and the second electrode of the second transistor respectively; The virtual sub-pixel includes: a first potential signal line pattern; a dummy sub-pixel driving circuit, the dummy sub-pixel driving circuit comprising a dummy driving transistor and a first conductive connection portion coupled to a gate of the dummy driving transistor; and A second conductive connection portion is coupled to the first conductive connection portion and the first potential signal line pattern respectively.

2. The display substrate according to claim 1, wherein The first conductive connection portion extends along a first direction; The first potential signal line pattern includes a first power signal line pattern, and the first power signal line pattern includes a first portion extending along the first direction; The second conductive connection portion extends along a second direction intersecting the first direction, and the second conductive connection portion is respectively coupled to the first conductive connection portion and the first portion of the first power signal line pattern.

3. The display substrate according to claim 1, wherein The first potential signal line pattern includes a first power signal line pattern, the first power signal line pattern includes a first portion and a second portion coupled to each other, the first portion extending along a first direction, the second portion extending along a second direction, and the second direction intersecting the first direction; The first conductive connection portion extends along the first direction; The second conductive connection portion extends along the first direction, and is respectively coupled to the first conductive connection portion and the second portion of the first power signal line pattern.

4. The display substrate according to claim 3, wherein: The second portions included in at least two of the virtual sub-pixels are coupled along the second direction.

5. The display substrate according to claim 3, wherein: The first portion and the second portion included in at least one target virtual sub-pixel are formed into an integrated structure; The target virtual sub-pixel is a virtual sub-pixel located at the outermost side of the display area along the first direction. The display substrate according to claim 1 , wherein: The first potential signal line pattern includes a first power signal line pattern, and the first conductive connection portion, the second conductive connection portion, and the first power signal line pattern are formed into an integrated structure.

7. The display substrate according to claim 1, wherein: The virtual sub-pixel further includes: a first gate line pattern and a first light-emitting control signal line pattern, both extending along the second direction, the first gate line pattern and the first light-emitting control signal line pattern being arranged along the first direction, an orthographic projection of the gate electrode of the dummy drive transistor on the substrate being located between the orthographic projection of the first gate line pattern on the substrate and the orthographic projection of the first light-emitting control signal line pattern on the substrate; The orthographic projection of the first gate line pattern on the substrate is located between the orthographic projection of the second conductive connection portion on the substrate and the orthographic projection of the first light-emitting control signal line pattern on the substrate.

8. The display substrate according to claim 7, wherein: The display sub-pixel comprises: a second gate line pattern and a second light emitting control signal line pattern both extending along a second direction; The first gate line pattern included in at least one of the virtual sub-pixels along the second direction, and the second gate line pattern included in the display sub-pixels located in the same row as the virtual sub-pixel along the second direction and adjacent to the at least one virtual sub-pixel form an integrated structure; The first light-emitting control signal line pattern included in at least one of the virtual sub-pixels along the second direction, and the second light-emitting control signal line pattern included in the display sub-pixel located in the same row as the virtual sub-pixel along the second direction and adjacent to the at least one virtual sub-pixel form an integrated structure.

9. The display substrate according to claim 1, wherein: The first potential signal line pattern includes a first power signal line pattern; the virtual sub-pixel driving circuit further includes: a first storage capacitor, wherein the gate of the dummy driving transistor is reused as a first plate of the first storage capacitor, a second plate of the first storage capacitor is located on a side of the first plate facing away from the substrate, an orthographic projection of the second plate on the substrate and an orthographic projection of a first portion of the first power signal line pattern extending in a first direction on the substrate having an overlapping area, and the second plate is coupled to the first portion in the overlapping area; The display sub-pixel further includes: a second power signal line pattern, wherein the second power signal line pattern includes a third portion extending along the first direction; The display sub-pixel driving circuit further includes a second storage capacitor, the gate of the driving transistor is multiplexed as a third plate of the second storage capacitor, a fourth plate of the second storage capacitor is located on a side of the third plate facing away from the substrate, an orthographic projection of the fourth plate on the substrate and an orthographic projection of a third portion of the second power signal line pattern on the substrate have an overlapping area, and the fourth plate is coupled to the third portion in the overlapping area; The second electrode plates included in the dummy sub-pixels located in the same row along the second direction and the fourth electrode plates included in the display sub-pixels located in the row form an integrated structure.

10. The display substrate according to claim 1, wherein The display sub-pixel comprises: a second power signal line pattern, wherein the second power signal line pattern includes a third portion extending along the first direction; The first portion of the first power signal line pattern included in each of the dummy sub-pixels located in the same column along the first direction and the third portion of the second power signal line pattern included in each of the display sub-pixels located in the column form an integrated structure.

11. The display substrate according to claim 1, wherein: The virtual sub-pixel further includes: a first data line pattern extending along a first direction; The display sub-pixel includes a second data line pattern extending along a first direction; The first data line pattern included in each of the virtual sub-pixels located in the same column along the first direction and the second data line pattern included in each of the display sub-pixels located in the column form an integrated structure.

12. The display substrate according to claim 1, wherein The virtual sub-pixel includes an active layer pattern, and the active layer pattern includes: a first active sub-pattern and a second active sub-pattern arranged opposite to each other, wherein the first active sub-pattern and the second active sub-pattern both extend along a first direction; a third active sub-pattern disposed between the first active sub-pattern and the second active sub-pattern, wherein two ends of the third active sub-pattern are coupled to the first active sub-pattern and the second active sub-pattern, and an orthographic projection of at least a portion of the third active sub-pattern on the substrate overlaps with an orthographic projection of the gate of the dummy driving transistor on the substrate; An orthographic projection of a portion of the first conductive connection portion away from the gate of the dummy driving transistor on the substrate does not overlap with an orthographic projection of the active layer pattern on the substrate.

13. The display substrate according to claim 12, wherein: The virtual sub-pixel further includes a first data line pattern extending along the first direction, and an orthographic projection of the second active sub-pattern on the substrate is located between the orthographic projection of the first data line pattern on the substrate and the orthographic projection of the first active sub-pattern on the substrate; An orthographic projection of the first data line pattern on the substrate does not overlap with an orthographic projection of the active layer pattern on the substrate.

14. The display substrate according to claim 1, wherein The first potential signal line pattern includes a first power signal line pattern; the virtual sub-pixel further includes: a first data line pattern, a first gate line pattern, a first light-emitting control signal line pattern, a first reset signal line pattern, and a first initialization signal line pattern; at least a portion of the first power signal line pattern and the first data line pattern all extend along a first direction, and the first gate line pattern, the first light-emitting control signal line pattern, the first reset signal line pattern, and the first initialization signal line pattern all extend along a second direction; The dummy sub-pixel driving circuit further includes: a second dummy transistor, a fifth dummy transistor and a sixth dummy transistor; The gate of the dummy driving transistor is coupled to the first power signal line pattern, the first electrode of the dummy driving transistor is coupled to the second electrode of the fifth dummy transistor, and the second electrode of the dummy driving transistor is coupled to the first electrode of the sixth dummy transistor; The gate of the second dummy transistor is coupled to the first reset signal line pattern, the first electrode of the second dummy transistor is coupled to the first initialization signal line pattern, and the second electrode of the second dummy transistor is floating; A gate electrode of the fifth dummy transistor is coupled to the first light emitting control signal line pattern, and a first electrode of the fifth dummy transistor is coupled to the first power signal line pattern; A gate of the sixth dummy transistor is coupled to the first light emitting control signal line pattern.

15. The display substrate according to claim 1, wherein The display sub-pixel driving circuit also includes a third conductive connection portion extending along the first direction, a first end of the third conductive connection portion is coupled to the gate of the driving transistor, and a second end of the third conductive connection portion is coupled to the second electrode of the first transistor and the second electrode of the second transistor respectively.

16. The display substrate according to claim 15, wherein: The second electrode of the first transistor is coupled to the second electrode of the second transistor to form a common connection end, and the positive projection of the second end of the third conductive connection portion on the substrate overlaps with the positive projection of the common connection end on the substrate, and the second end of the third conductive connection portion is coupled to the common connection end at the overlapping point.

17. The display substrate according to claim 1, wherein: The display subpixel includes: a second power signal line pattern, a second data line pattern, a second gate line pattern, a second light emission control signal line pattern, a second reset signal line pattern, a third reset signal line pattern, a second initialization signal line pattern, and a third initialization signal line pattern; at least a portion of the second power signal line pattern and the second data line pattern extend along a first direction; the second gate line pattern, the second light emission control signal line pattern, the second reset signal line pattern, the third reset signal line pattern, the second initialization signal line pattern, and the third initialization signal line pattern all extend along a second direction, and the second direction intersects the first direction; The display sub-pixel driving circuit further includes: a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; The first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled to the first electrode of the first transistor; The gate of the first transistor is coupled to the second gate line pattern; The gate of the second transistor is coupled to the second reset signal line pattern, and the first electrode of the second transistor is coupled to the second initialization signal line pattern; A gate electrode of the fourth transistor is coupled to the second gate line pattern, a first electrode of the fourth transistor is coupled to the second data line pattern, and a second electrode of the fourth transistor is coupled to the first electrode of the driving transistor; The gate of the fifth transistor is coupled to the second light emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the second power supply signal line pattern; The gate of the sixth transistor is coupled to the second light emitting control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the light emitting element in the display sub-pixel; A second electrode of the seventh transistor is coupled to the light emitting element in the display sub-pixel, a gate of the seventh transistor is coupled to the third reset signal line pattern, and a first electrode of the seventh transistor is coupled to the third initialization signal line pattern.

18. The display substrate according to claim 1, wherein The first conductive connecting portion and the second conductive connecting portion are an integral structure.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. A method for manufacturing a display substrate, the method comprising: Fabricating a plurality of sub-pixels arranged in an array on a substrate; The plurality of sub-pixels include a plurality of display sub-pixels located in a display area of the display panel, and a plurality of dummy sub-pixels at least partially adjacent to the plurality of display sub-pixels; The display sub-pixel includes: a display sub-pixel driving circuit, the display sub-pixel driving circuit including a driving transistor, a first transistor, and a second transistor; the gate of the driving transistor is coupled to the second electrode of the first transistor and the second electrode of the second transistor respectively; The virtual sub-pixel includes: a first potential signal line pattern; a dummy sub-pixel driving circuit, the dummy sub-pixel driving circuit comprising a dummy driving transistor and a first conductive connection portion coupled to a gate of the dummy driving transistor; A second conductive connection portion is coupled to the first conductive connection portion and the first potential signal line pattern respectively.

21. The method for manufacturing a display substrate according to claim 20, wherein: The first potential signal line pattern includes a first power signal line pattern; and the steps of manufacturing the first conductive connecting portion, the second conductive connecting portion, and the first potential signal line pattern specifically include: The first conductive connection portion, the second conductive connection portion and the first power signal line pattern are formed as an integrated structure through a single patterning process.

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