Display panel and display device

Abstract

The present application discloses a display panel and a display device, wherein the display panel includes a substrate having a first display area and a second display area. Since the pixel circuit driving the light-emitting element in the second display area is only located in the first display area and not in the second display area, the light transmittance of the second display area is ensured to be good. Accordingly, the display panel disclosed in the present application has a good display effect.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The under-screen camera technology is a new technology proposed to increase the screen-to-body ratio of display devices.

[0003] In the related art, a display panel with an under-screen camera generally includes a first display area for normal display and a second display area for setting the camera. The second display area generally includes: a plurality of light-emitting elements and a plurality of pixel circuits, each pixel circuit is connected to a light-emitting element and is used to drive the light-emitting element to emit light, and the interconnected pixel circuits and light-emitting elements overlap in a direction perpendicular to the display panel.

[0004] Since a pixel circuit is also disposed in the second display area in the related art, the light transmittance of the second display area is poor, and accordingly, the display effect of the display panel is poor. Summary of the invention

[0005] The present disclosure provides a display panel and a display device, which can solve the problem of poor display effect of the display panel in the related art. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, the display panel comprising:

[0007] A base substrate having a first display area and a second display area, wherein the first display area at least partially surrounds the second display area;

[0008] A plurality of first pixel circuits, a plurality of second pixel circuits and a plurality of first light-emitting elements are located in the first display area, and the plurality of second pixel circuits are distributed between the plurality of first pixel circuits at intervals;

[0009] A plurality of second light emitting elements, located in the second display area;

[0010] Among them, at least one first pixel circuit among the multiple first pixel circuits is connected to at least one first light-emitting element among the multiple first light-emitting elements, and the orthographic projection of the at least one first pixel circuit on the substrate substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting element on the substrate substrate; at least one second pixel circuit among the multiple second pixel circuits is connected to at least one second light-emitting element among the multiple second light-emitting elements through a conductive line.

[0011] Optionally, the density of the plurality of second light-emitting elements is the same as that of the plurality of first light-emitting elements.

[0012] Optionally, the resolution of the first display area is the same as the resolution of the second display area; or, the resolution of the first display area is different from the resolution of the second display area.

[0013] Optionally, each of the first pixel circuits is connected to one of the first light-emitting elements;

[0014] Furthermore, an orthographic projection of each of the first pixel circuits on the base substrate at least partially overlaps with an orthographic projection of the connected first light-emitting element on the base substrate.

[0015] Optionally, the plurality of first pixel circuits include a plurality of columns of first pixel circuits extending along the first direction, and the plurality of second pixel circuits include a plurality of columns of second pixel circuits extending along the first direction;

[0016] Wherein, the plurality of columns of second pixel circuits are distributed at intervals between the plurality of columns of first pixel circuits.

[0017] Optionally, any two adjacent columns of the second pixel circuits are spaced by the same number of columns or different number of columns of the first pixel circuits.

[0018] Optionally, the plurality of first pixel circuits include a plurality of rows of first pixel circuits extending along a second direction, and the plurality of second pixel circuits include a plurality of rows of second pixel circuits extending along the second direction, wherein the second direction intersects the first direction, and the plurality of rows of second pixel circuits are spaced apart between the plurality of rows of first pixel circuits.

[0019] Optionally, the first direction is perpendicular to the second direction.

[0020] Optionally, the first display area includes: a first sub-display area and a second sub-display area arranged in sequence along a first direction; the first sub-display area includes: two symmetrical target sub-display areas;

[0021] Wherein, one of the target sub-display areas, the second display area and another of the target sub-display areas are arranged in sequence along the second direction.

[0022] Optionally, the second display area includes two third sub-display areas symmetrically arranged along the second direction; the display panel includes: a first conductive line, a second conductive line and a third conductive line;

[0023] Each of the third sub-display areas includes k light-emitting element groups, each of the light-emitting element groups includes a plurality of adjacent columns of the second light-emitting elements, and the first light-emitting element group to the kth light-emitting element group are sequentially arranged in a direction close to another third sub-display area, and k is an integer greater than 0;

[0024] Each of the target sub-display areas includes k pixel circuit groups corresponding one-to-one to the k light-emitting element groups, each of the pixel circuit groups includes multiple adjacent columns of the second pixel circuits, and the first pixel circuit group to the kth pixel circuit group are arranged in sequence along a direction away from the adjacent third sub-display area; and each of the second light-emitting elements in each of the light-emitting element groups is connected to each of the second pixel circuits in a corresponding one of the pixel circuit groups through the first conductive line, the second conductive line and / or the third conductive line.

[0025] Optionally, k is 4.

[0026] Optionally, each of the second light-emitting elements in the first light-emitting element group is connected to each of the second pixel circuits in the first pixel circuit group through the first conductive line;

[0027] Each of the second light-emitting elements in the second light-emitting element group is connected to each of the second pixel circuits in the second pixel circuit group through the second conductive line;

[0028] Each of the second light-emitting elements in the third light-emitting element group is connected to each of the second pixel circuits in the third pixel circuit group through the third conductive line;

[0029] Each of the second light-emitting elements in the fourth light-emitting element group is connected to each of the second pixel circuits in the fourth pixel circuit group through the first conductive line, the second conductive line and the third conductive line.

[0030] Optionally, the first conductive line connected to each of the second light-emitting elements in the first light-emitting element group, the second conductive line connected to each of the second light-emitting elements in the second light-emitting element group, and each of the third conductive lines connected to each of the second light-emitting elements in the third light-emitting element group include: a first conductive line segment, a second conductive line segment, and a third conductive line segment;

[0031] One end of the first conductive line segment is connected to the corresponding second light-emitting element, and the other end of the first conductive line segment is connected to one end of the second conductive line segment;

[0032] The other end of the second conductive line segment is connected to one end of the third conductive line segment;

[0033] The other end of the third conductive line segment is connected to the corresponding second pixel circuit;

[0034] The first conductive line segment and the third conductive line segment extend along the first direction, the second conductive line segment extends along the second direction, and an orthographic projection of the second conductive line segment on the base substrate at least partially overlaps with an orthographic projection of a second light-emitting element connected thereto on the base substrate.

[0035] Optionally, the second conductive line segment included in the first conductive line at least partially overlaps with the second conductive line segment included in the third conductive line, the second conductive line segment included in the first conductive line does not overlap with the second conductive line segment included in the second conductive line, and the second conductive line segment included in the third conductive line does not overlap with the second conductive line segment included in the second conductive line.

[0036] Optionally, the fourth light-emitting element group includes: two first sub-light-emitting element groups, two second sub-light-emitting element groups and two third sub-light-emitting element groups symmetrically arranged along the axis of the third sub-display area, each sub-light-emitting element group includes a plurality of adjacent rows of the second light-emitting elements, and the first sub-light-emitting element group, the second sub-light-emitting element group and the third sub-light-emitting element group located on the same side are arranged in sequence in a direction away from the axis, and the axis extends along the second direction;

[0037] The fourth pixel circuit group includes: two first sub-pixel circuit groups corresponding to the two first sub-light emitting element groups, two second sub-pixel circuit groups corresponding to the two second sub-light emitting element groups, and two third sub-pixel circuit groups corresponding to the two third sub-light emitting element groups.

[0038] Among them, each of the second light-emitting elements in each of the first sub-light-emitting element groups is connected to each of the second pixel circuits in the corresponding first sub-pixel circuit group through the first conductive line; each of the second light-emitting elements in each of the second sub-light-emitting element groups is connected to each of the second pixel circuits in the corresponding second sub-pixel circuit group through the second conductive line; each of the second light-emitting elements in each of the third sub-light-emitting element groups is connected to each of the second pixel circuits in the corresponding third sub-pixel circuit group through the third conductive line.

[0039] Optionally, the first conductive line connected to each of the second light-emitting elements in each of the first sub-light-emitting element groups, the second conductive line connected to each of the second light-emitting elements in each of the second sub-light-emitting element groups, and the third conductive line connected to each of the second light-emitting elements in each of the third sub-light-emitting element groups include: a fourth conductive line segment, a fifth conductive line segment, a sixth conductive line segment, and a seventh conductive line segment;

[0040] One end of the fourth conductive line segment is connected to the corresponding second light-emitting element, and the other end of the fourth conductive line segment is connected to one end of the fifth conductive line segment;

[0041] The other end of the fifth conductive line segment is connected to one end of the sixth conductive line segment;

[0042] The other end of the sixth conductive line segment is connected to one end of the seventh conductive line segment;

[0043] The other end of the seventh conductive line segment is connected to the corresponding second pixel circuit;

[0044] The fifth conductive line segment and the seventh conductive line segment extend along the first direction, and the sixth conductive line segment extends along the second direction; the fourth conductive line segment is located between a row where the second light-emitting element connected thereto is located and an adjacent row;

[0045] The fifth conductive line segment included in the first conductive line is located in the area where the second to fourth light-emitting element groups are located, the fifth conductive line segment included in the second conductive line is located in the area where the third and fourth light-emitting element groups are located, and the fifth conductive line segment included in the third conductive line is located in the area where the fourth light-emitting element group is located; the sixth conductive line segment on the side away from the second sub-display area along the axis is located on the side of the second display area away from the second sub-display area, and the sixth conductive line segment on the side close to the second sub-display area along the axis is located in the second display area close to the second sub-display area.

[0046] Optionally, the first to third light emitting element groups respectively include 12 columns of the second light emitting elements; the fourth light emitting element group includes 8 columns of the second light emitting elements;

[0047] The first to third pixel circuit groups respectively include 12 columns of the second pixel circuits; and the fourth pixel circuit group includes 8 columns of the second pixel circuits.

[0048] Optionally, the display panel further comprises: a plurality of metal layers;

[0049] The data line connected to each of the second pixel circuits is arranged in the same layer as any of the metal layers;

[0050] The plurality of metal layers include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer.

[0051] Optionally, along the direction away from the adjacent third sub-display area, in the second pixel circuits from the first column to the i-th column in each of the target sub-display area, the data lines connected to the second pixel circuits located in odd columns are on the same layer as the first gate metal layer; the data lines connected to the second pixel circuits located in even columns are on the same layer as the second gate metal layer; the data lines connected to the second pixel circuits from the i-th column to the n-th column are on the same layer as the first source and drain metal layer, where i is an integer greater than 1 and less than n, and n is equal to the total number of columns in each of the target sub-display area.

[0052] Optionally, the data line connected to each of the second pixel circuits includes: a first data line segment, a second data line segment and a third data line segment;

[0053] One end of the first data line segment is connected to the corresponding metal layer, and the other end is connected to one end of the second data line segment, the other end of the second data line segment is connected to one end of the third data line segment, and the other end of the third data line segment is connected to the second pixel circuit;

[0054] The second data line segment extends along the first direction, and the second data line segment included in the data line on the same layer as the first gate metal layer, the second data line segment included in the data line on the same layer as the second gate metal layer, and the second data line segment included in the data line on the same layer as the first source and drain metal layer do not overlap with each other.

[0055] Optionally, the second source-drain metal layer covers the first gate metal layer, the second gate metal layer and the first source-drain metal layer.

[0056] Optionally, in the same column of the second pixel circuits, the data line connected to the second pixel circuit located in the first sub-display area is different from the data line connected to the second pixel circuit located in the second sub-display area.

[0057] Optionally, the display panel further includes at least one column of dummy second pixel circuits, and the at least one column of dummy second pixel circuits is located in the target sub-display area close to the second display area.

[0058] Optionally, among the multiple first pixel circuits and the multiple second pixel circuits, the width of any pixel circuit is smaller than the width of any first light-emitting element.

[0059] Optionally, the width of each pixel circuit differs from the width of the first light-emitting element by 4 micrometers.

[0060] Optionally, each of the second pixel circuits and each of the second light-emitting elements has a transition portion, and the conductive wires are respectively connected to the transition portion of the at least one second pixel circuit and the transition portion of the at least one second light-emitting element.

[0061] Optionally, the conductive wire is a transparent conductive wire.

[0062] Optionally, the material of the transparent conductive wire is indium tin oxide.

[0063] Optionally, the second display area is a light-transmitting display area.

[0064] On the other hand, a display device is provided, the display device comprising: an integrated circuit, and a display panel as described in the above aspect;

[0065] The integrated circuit is connected to a first pixel circuit and a second pixel circuit in the display panel, and is used to drive the first pixel circuit and the second pixel circuit to operate;

[0066] Optionally, the display device further includes: a photosensor, and the photosensor is located in the second display area of ​​the display panel.

[0067] Optionally, the second display area is rectangular, and the orthographic projection area of ​​the photosensor on the base substrate is less than or equal to the area of ​​the inscribed circle of the second display area.

[0068] The beneficial effects brought by the technical solution provided by the present disclosure may at least include:

[0069] In summary, the embodiments of the present disclosure provide a display panel and a display device, wherein the display panel includes a substrate having a first display area and a second display area. Since the pixel circuit driving the light-emitting element in the second display area is only located in the first display area and not in the second display area, the light transmittance of the second display area is ensured to be good. Accordingly, the display panel disclosed in the present application has a good display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0071] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0072] Figure 2is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0073] Figure 3 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0074] Figure 4 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0075] Figure 5 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0076] Figure 6 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0077] Figure 7 It is a layout of a pixel circuit before and after compression provided by an embodiment of the present disclosure;

[0078] Figure 8 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0079] Fig. 9 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0080] Fig.10 is a structural layout of a pixel circuit provided by an embodiment of the present disclosure;

[0081] Fig.11 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0082] Fig.12 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0083] Fig.13 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0084] Fig.14 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0085] Fig.15 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0086] Fig.16 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0087] Fig.17 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0088] Fig.18is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0089] Fig.19 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0090] Fig. 20 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0091] Fig.21 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0092] Fig. 22 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0093] Fig.23 is a schematic diagram of a conductive wire structure provided by an embodiment of the present disclosure;

[0094] Fig.24 is a schematic diagram of a conductive wire structure provided by an embodiment of the present disclosure;

[0095] Fig.25 is a schematic diagram of a conductive wire structure provided by an embodiment of the present disclosure;

[0096] Fig.26 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0097] Fig. 27 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0098] Fig.28 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0099] Fig.29 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure;

[0100] Fig.30 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0101] Fig.31 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0102] Fig.32 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0103] Fig.33 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0104] Fig.34is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0105] Fig.35 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0106] Fig.36 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0107] Fig.37 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0108] Fig.38 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0109] Fig.39 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0110] Fig.40 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0111] Fig.41 is a schematic diagram of a data line structure provided by an embodiment of the present disclosure;

[0112] Fig.42 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0113] Fig.43 is a structural schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0114] Fig.44 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0115] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0116] With the development of display technology, the existing notch screen or water drop screen design is gradually unable to meet the user's demand for a high screen-to-body ratio of display panels, and a series of display panels with a light-transmitting display area have emerged. In this type of display panel, hardware such as light sensors (such as cameras) can be set in the light-transmitting display area. Since there is no need to punch holes, a true full screen becomes possible while ensuring the practicality of the display panel.

[0117] An embodiment of the present disclosure provides a display panel that, while ensuring reliable driving of the light-emitting elements in the light-transmitting display area and ensuring good transmittance of the light-transmitting display area, does not reduce the number of pixels in the non-light-transmitting display area, thereby ensuring good display effect in the non-light-transmitting display area.

[0118] Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 1 As shown, the display panel may include:

[0119] The base substrate 01 may have a first display area A1 and a second display area A2, and the first display area A1 may at least partially surround the second display area A2. For example, Figure 1 The second display area A2 is shown to be located at the top center of the base substrate 01 , and accordingly, the four sides of the rectangular first display area A1 may all surround the second display area A2 , that is, the second display area A2 may be surrounded by the first display area A1 .

[0120] In some embodiments, the second display area A2 may not be located at Figure 1 The substrate 01 is not located at the top middle position, but at other positions. Figure 1 , the second display area A2 can be located at the upper left corner or the upper right corner of the base substrate 01.

[0121] Recombination Figure 2 As can be seen from the other display panel shown, the display panel may also include: a plurality of first pixel circuits 10, a plurality of second pixel circuits 20 and a plurality of first light-emitting elements 30 located in the first display area A1, and a plurality of second light-emitting elements 40 located in the second display area A2, and the plurality of second pixel circuits 20 may be distributed at intervals between the plurality of first pixel circuits 10.

[0122] Among them, at least one first pixel circuit 10 among the plurality of first pixel circuits 10 may be connected to at least one first light-emitting element 30 among the plurality of first light-emitting elements 30, and the orthographic projection of at least one first pixel circuit 10 on the substrate 01 may at least partially overlap with the orthographic projection of at least one first light-emitting element 30 on the substrate 01. The at least one first pixel circuit 10 may be used to provide a driving signal for the connected first light-emitting element 30 to drive the first light-emitting element 30 to emit light.

[0123] At least one second pixel circuit 20 among the plurality of second pixel circuits 20 can be connected to at least one second light-emitting element 40 among the plurality of second light-emitting elements 40 through a conductive line L1, and the at least one second pixel circuit 20 can be used to provide a driving signal to the connected second light-emitting element 40 to drive the second light-emitting element 40 to emit light. And because the second light-emitting element 40 and the second pixel circuit 20 are located in different areas, Figure 2 As shown, there is no overlapping part between the orthographic projection of at least one second pixel circuit 20 on the base substrate 01 and the orthographic projection of at least one second light-emitting element 40 on the base substrate 01 .

[0124] Optionally, in the embodiment of the present disclosure, the first display area A1 can be set as a non-light-transmitting display area, and the second display area A2 can be set as a light-transmitting display area. That is, the first display area A1 recorded in the embodiment of the present disclosure is not light-transmitting, and the second display area A2 is light-transmitting. In this way, there is no need to perform hole-digging processing on the display panel, and the required hardware structures such as the photosensitive sensor can be directly set in the second display area A2, laying a solid foundation for the realization of a true full screen. In addition, since the second display area A2 only includes light-emitting elements but not pixel circuits, it can also ensure that the transmittance of the second display area A2 is good.

[0125] In summary, the embodiment of the present disclosure provides a display panel, which includes a substrate having a first display area and a second display area. Since the pixel circuit driving the light-emitting element in the second display area is only located in the first display area and not in the second display area, the light transmittance of the second display area is ensured to be good. Accordingly, the display panel recorded in the embodiment of the present disclosure has a good display effect.

[0126] Figure 3 by Figure 2 Taking the display panel shown in FIG. 1 as an example, another structural schematic diagram of a display panel is shown. Figure 3 It can be further seen that the first display area A1 includes not only a plurality of pixels but also a plurality of columns of second pixel circuits 20 , and the second display area A2 includes only a plurality of second light emitting elements 40 .

[0127] Wherein, a pixel refers to a structure including a pixel circuit and a light-emitting element. Taking the first pixel circuit 10 and the first light-emitting element 30 as an example, refer to Figure 3 It can be seen that each pixel shown includes: a red sub-pixel R, two green sub-pixels G1 and G2, and a blue sub-pixel B, and the red sub-pixel R and the blue sub-pixel B are located in the same column, and the two green sub-pixels G1 and G2 are located in the same column. Of course, in some embodiments, the pixel may also include sub-pixels of other colors and other numbers, and the arrangement of each sub-pixel is not limited to Figure 3For example, each pixel may include only one red sub-pixel R, one blue sub-pixel B, and one green sub-pixel G.

[0128] Optionally, in the embodiment of the present disclosure, the electrical connection relationship between the plurality of first pixel circuits 10 and the plurality of first light-emitting elements 30 may correspond to each other one by one. That is, each first pixel circuit 10 may be connected to one first light-emitting element 30, and the first light-emitting elements 30 connected to each first pixel circuit 10 are different. Figure 2 In the display panel shown, the orthographic projection of each first pixel circuit 10 on the base substrate 01 at least partially overlaps with the orthographic projection of the connected first light-emitting element 30 on the base substrate 01 .

[0129] Similar to the electrical connection relationship between the first pixel circuit 10 and the first light emitting element 30, the electrical connection relationship between the plurality of second pixel circuits 20 and the plurality of second light emitting elements 40 may also correspond one to one. Moreover, the orthographic projection of each second pixel circuit 20 on the base substrate 01 does not overlap with the orthographic projection of the connected second light emitting element 40 on the base substrate 01.

[0130] Optionally, the density of the plurality of second light-emitting elements 40 located in the second display area A2 may be the same as that of the plurality of first light-emitting elements 30 located in the first display area A1. That is, the number of light-emitting elements per inch in the first display area A1 and the second display area A2 is the same. That is, the first display area A1 (i.e., the main display area) does not have two partitions with different pixel densities. Furthermore, compared with the related art, when displaying a picture, the first display area A1 does not have a light-dark dividing line, and the display effect of the display panel is better.

[0131] by Figure 2 Take the display panel shown as an example, Figure 4 The structure of a display panel is shown. Figure 4 It can be seen that the resolution of the first display area A1 can be greater than that of the second display area A2. That is, the area of ​​the first display area A1 is larger than that of the second display area A2, and the number of light-emitting elements included in the first display area A1 is larger than that of the second display area A2.

[0132] In some embodiments, the resolution of the first display area A1 may be less than or equal to the resolution of the second display area A2. For example, the area of ​​the first display area A1 may be the same as the area of ​​the second display area A2, and the number of light-emitting elements included in the first display area A1 and the number of light-emitting elements included in the second display area A2 may also be the same. Alternatively, the area of ​​the first display area A1 may be smaller than the area of ​​the second display area A2, and the number of light-emitting elements included in the first display area A1 is less than that of the light-emitting elements included in the second display area A2.

[0133] Optional, Figure 5 Shows Figure 4 The partial enlarged schematic diagram of the display panel is shown. Figure 4 and Figure 5 It can be seen that the size of the first light-emitting element 30 can be larger than that of the second light-emitting element 40, that is, the anode of the light-emitting element in the second display area A2 is smaller than the anode of the light-emitting element in the first display area A1. In this way, the light transmittance of the second display area A2 can be ensured to be greater than that of the first display area A1. Furthermore, the shape and size of the anode of the second light-emitting element 40 can be further optimized to ensure better light transmittance. For example, in combination Figure 3 In the display panel shown, the anode of the second light emitting element 40 is elliptical.

[0134] Optionally, in order to further ensure that the transmittance of the second display area A2 is good, the conductive line L1 recorded in the embodiment of the present disclosure may be a transparent conductive line. For example, the conductive line L1 may be made of a transparent material such as indium tin oxide (ITO) or indium gallium zinc oxide (IGZO). Assuming that the conductive line L1 is made of an ITO material, the conductive line L1 may also be referred to as an ITO trace. The following embodiments are all described by taking the conductive line L1 as an ITO trace as an example.

[0135] Optionally, in the embodiment of the present disclosure, since the base substrate 01 has a light-transmissive display area, namely, the second display area A2, Figure 6 As shown, the light sensor 50 structure (eg, camera) in the display module included in the display device can be directly arranged in the second display area A2, that is, no additional hole is needed on the display panel. In this way, a solid foundation is laid for the realization of a full-screen display panel.

[0136] Optionally, the second display area A2 may be rectangular, and the area of ​​the positive projection of the light sensor 50 on the substrate 01 may be smaller than or equal to the area of ​​the inscribed circle of the second display area A2. That is, the size of the area where the light sensor 50 is located may be smaller than or equal to the size of the inscribed circle of the second display area A2. Figure 6 In the display panel shown, the size of the area where the light sensor 50 is located is equal to the size of the inscribed circle Y0 of the second display area A2, that is, the shape of the area where the light sensor 50 is located can be circular, and accordingly, the area where the light sensor 50 is located can also be called a light-transmitting hole. Of course, in some embodiments, the second display area A2 can also be other shapes besides a rectangle, such as a circle or an ellipse.

[0137] In the related art, the pixel circuit (including the first pixel circuit 10 and the second pixel circuit 20) and the first light-emitting element 30 have the same size (pitch). For example, the general width is about 30 micrometers (μm) to 32μm, and the length is about 60μm to 65μm. In the embodiment of the present disclosure, in order to provide sufficient space for the arrangement of the second pixel circuit 20 without reducing the number of pixels in the first display area A1, each pixel circuit can be compressed along the second direction X2 (such as the gate line extension direction, which can also be called the horizontal direction) so that the width of the pixel circuit in the second direction is smaller than the width of the first light-emitting element 30; or, the first light-emitting element 30 can be extended along the second direction so that the width of the first light-emitting element 30 in the second direction is larger than the width of the first light-emitting element 30. In this way, under the premise that the size of the substrate 01 is the same, there can be more areas in the first display area A1, and accordingly, the second pixel circuit 20 specifically used to drive the second light-emitting element 40 located in the second display area A2 can be arranged in the more areas.

[0138] For example, the width of each pixel circuit may differ from the width of the first light emitting element 30 by about 4 μm. Taking the compressed pixel circuit and the width difference of 4 μm as an example, Figure 7 The structure layout of the pixel circuit before and after compression (ie, the related art and the embodiment of the present disclosure) is shown. Figure 7 It can be seen that the pixel circuit may include a driving structure and a transition portion B1 for connecting to the anode of the light-emitting element, and the size of the transition portion B1 may represent the size of the pixel circuit. Before compression, the size of the pixel circuit and the light-emitting element are both 1-100 μm wide and 2-200 μm high. After compression, the size of the light-emitting element remains unchanged, the height of the pixel circuit remains unchanged, but the width is narrowed by 1-20 μm, so that every few columns of compressed pixel circuits will have one or more columns of compressed pixel circuits, and the entire screen adopts this design to achieve full-screen compression. Among them, these extra columns can be selected to connect the second light-emitting element 40 in the second display area A2 to control the second light-emitting element 40 to emit light. In some embodiments, it is preferred that the extra column pixel circuit near the periphery of the second display area A2 is used as the second pixel circuit 20 to connect the second light-emitting element 40. In this way, normal display can be ensured without changing the resolution of the display panel. That is, the existing space of the display panel is fully utilized to achieve normal display.

[0139] It should be noted that, combined with Figure 3 The width of the pixel circuit may refer to the length of the positive projection of the layout of the pixel circuit on the substrate 01 along the second direction X2. The width of the first light emitting element 30 refers to the length of the positive projection of the anode of the first light emitting element 30 on the substrate 01 along the second direction X2.

[0140] In addition, combined Figure 3 and Figure 8 As shown in the accompanying drawings, each first light-emitting element described in the embodiment of the present disclosure belongs to a sub-pixel in a pixel. For example, it may be a red sub-pixel R, a green sub-pixel G1, G2 or a blue sub-pixel B. When determining the size of the anode of the first light-emitting element, the width D10 of the pixel in the first direction X1 or the second direction X2 can generally be measured with one pixel as a period, and then for the width D01 of each first light-emitting element, the total pixel width D10 can be divided by the number of sub-pixels included in the pixel (for example, Figure 8 Similarly, since each first light-emitting element is connected to a corresponding pixel circuit, the width of each pixel circuit in the first direction X1 or the second direction X2 can still be measured using each pixel circuit connected to a pixel as a period, and then for the width D0 of each pixel circuit, the total width can be divided by the number of sub-pixels included in the pixel.

[0141] Optional, combined Figure 7 As shown in the pixel circuit, the pixel circuit recorded in the embodiment of the present disclosure may be a 7T1C structure, that is, it includes 7 transistors and 1 capacitor. Fig. 9 shows a schematic diagram of the structure of a 7T1C pixel circuit, Fig.10 The structural layout of the 7T1C pixel circuit is shown.

[0142] Among them, combined Fig. 9 and Fig.10 As can be seen from the pixel circuit shown, the 7T1C pixel circuit 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7 and a storage capacitor C1. The pixel circuit can be connected to a gate signal terminal Gate, a data signal terminal Data, reset signal terminals RST1 and RST2, a light-emitting control signal terminal EM, a power supply terminal VDD, initial power supply terminals Vinit1 and Vinit2, and a light-emitting element, and the light-emitting element can also be connected to a power supply terminal VSS. The pixel circuit can be used to drive the connected light-emitting element to emit light in response to the signals provided by the connected signal terminals.

[0143] In addition, transistors can be divided into N-type and P-type transistors according to their characteristics. The embodiments of the present disclosure are described by taking the case where all transistors are P-type transistors. Based on the description and teaching of the implementation method disclosed in the present disclosure, ordinary technicians in this field can easily think of using N-type transistors for at least some of the transistors in the pixel circuit structure of the embodiment of the present disclosure, that is, using N-type transistors or a combination of N-type transistors and P-type transistors, without making any creative work. Therefore, these implementation methods are also within the protection scope of the embodiments of the present disclosure.

[0144] In order to further reflect that after compressing the pixel circuit, there are more columns of pixel circuits, Fig.11 A schematic structural diagram of a first display area A1 is shown. Fig.12 Shows Figure 4 Schematic diagram of part of the structure (including only the pixel circuit), Fig.13 Shows Figure 4 Schematic diagram of part of the structure (including only the light-emitting element).

[0145] refer to Figures 11 to 13 It can be seen that the width of the pixel circuit is smaller than the width of the light-emitting element. In this way, the pixel circuits in the 2nd and 9th columns from left to right are not connected to any first light-emitting element 30, and belong to the extra-column pixel circuits, which can be used as the second pixel circuit 20 for connecting the second light-emitting element 40 in the second display area A2. In addition, each first light-emitting element 30 can include RG1BG2, a total of 4 types of anodes, and a transition part B2 for connecting to the first pixel circuit 10. The transition part B1 of the first pixel circuit 10 and the transition part B2 of the first light-emitting element 30 can be connected through the source-drain metal layer SD2. Alternatively, if the first pixel circuit 10 and the first light-emitting element 30 are already overlapped together, there is no need to set the SD2 line connection.

[0146] It should be noted that at least one second pixel circuit 20 and at least one second light-emitting element 40 may also both have a transition part, and at least one second pixel circuit 20 and at least one second light-emitting element 40 are connected through the conductive line L1. In fact, the conductive line L1 can be respectively connected to the transition part of at least one second pixel circuit 20 and the transition part of at least one second light-emitting element 40.

[0147] Therefore, in order to ensure that there is sufficient space for the conductive line L1, the axis of the transition part of each second pixel circuit 20 located in the same row can be aligned with the axis of the transition part of any second light-emitting element 40, and the axis can extend along the second direction X2. That is, in the same row in the row direction, the transition part of the second pixel circuit 20 and the transition part of the second light-emitting element 40 are located on the same line. Similarly, combined with the above Figures 11 to 13In the same row, the transfer portion B1 of the first pixel circuit 10 and the transfer portion B2 of the first light emitting element 30 may also be located on the same line, so that the wiring arrangement is neat.

[0148] Optional, Fig.14 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present disclosure. Fig.14 As shown, the first display area A1 may include: a first sub-display area A11 and a second sub-display area A12 arranged in sequence along the first direction X1. The first sub-display area A11 may include: two symmetrical target sub-display areas A110. That is, the layouts of the two target sub-display areas A110 are the same. The second display area A2 may include two third sub-display areas A21 arranged symmetrically along the second direction X2. That is, the layouts of the two third sub-display areas A21 are the same. Among them, one target sub-display area A110, the second display area A2 and another target sub-display area A110 may be arranged in sequence along the second direction X2.

[0149] based on Fig.14 As shown in the display panel, the layout of the left and right halves of the display panel is the same. Therefore, the following embodiments only show the structure of the left half of the display panel, that is, a target sub-display area A110 and an adjacent third sub-display area A21 located in the left half. The right half is the same and will not be described in detail.

[0150] Furthermore, the multiple column pixel circuits recorded in the embodiment of the present disclosure, that is, multiple second pixel circuits 20 can be dispersedly arranged in the first display area A1, and the arrangement position can be flexibly adjusted according to the needs, as long as it can be effectively connected to the second light-emitting element 40 and drive the second light-emitting element 40 to emit light reliably. For example, the embodiment of the present disclosure takes the multiple second pixel circuits 20 dispersedly arranged in the column direction, row direction and diagonal direction as an example, and the arrangement position of the second pixel circuit 20 is schematically described as follows:

[0151] As an optional implementation, the second pixel circuit 20 extends along the column direction. Fig.15 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present disclosure. Fig.14 and Fig.15 It can be seen that the plurality of first pixel circuits 10 may include a plurality of columns of first pixel circuits 10 extending along the first direction X1 , and the plurality of second pixel circuits 20 may include a plurality of columns of second pixel circuits 20 extending along the first direction X1 .

[0152] Among them, multiple columns of second pixel circuits 20 can be spaced between multiple columns of first pixel circuits 10. For example, there is one column of second pixel circuits 20 for each adjacent multiple columns of first pixel circuits 10. In other words, multiple adjacent columns of first pixel circuits 10 can be spaced between each two adjacent columns of second pixel circuits 20.

[0153] Optionally, any two adjacent columns of second pixel circuits 20 may be spaced apart by the same number of first pixel circuits 10, thus ensuring arrangement uniformity. For example, any two adjacent columns of second pixel circuits 20 may be spaced apart by eight adjacent columns of first pixel circuits 10. Alternatively, any two adjacent columns of second pixel circuits 20 may be spaced apart by different numbers of first pixel circuits 10.

[0154] Example, combined Fig.16 In the display panel shown, starting from the left boundary line between the third sub-display area A21 and the target sub-display area A110, the 2nd column of pixel circuits, the 12th column of pixel circuits and the 20th column of pixel circuits to the left can all be second pixel circuits 20. It should be noted that the extra columns of second pixel circuits 20 below the second display area A2 can be used as dummy columns and are not connected to any light-emitting elements.

[0155] As another optional implementation, the second pixel circuit 20 does not extend along the column direction. Fig.17 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present disclosure. Fig.17 As shown, the plurality of first pixel circuits 10 may include a plurality of rows of first pixel circuits 10 extending along the second direction X2, and the plurality of second pixel circuits 20 may include a plurality of rows of second pixel circuits 20 extending along the second direction X2.

[0156] Optionally, the first direction X1 and the second direction X2 may intersect. For example, when the first direction X1 and the second direction X2 are not perpendicular, the plurality of second pixel circuits 20 may be arranged along a diagonal direction. When the first direction X1 and the second direction X2 are perpendicular, the plurality of second pixel circuits 20 may be arranged along a row direction.

[0157] Wherein, a plurality of rows of second pixel circuits 20 are distributed between a plurality of rows of first pixel circuits 10 at intervals. For example, Fig.17 The multiple second pixel circuits 20 shown extend in the row direction, that is, there is a row of second pixel circuits 20 for each adjacent multiple rows of first pixel circuits 10. In other words, multiple adjacent rows of first pixel circuits 10 may be spaced between each two adjacent rows of second pixel circuits 20. The following embodiments are all described by taking the multiple second pixel circuits 20 arranged in sequence in the column direction as an example.

[0158] It should be noted that the extra pixel circuit, that is, the second pixel circuit 20 and the second light emitting element 40 can be connected via a conductive line L1, and the number of stacked layers of the conductive line L1 can be flexibly adjusted according to the radius of the light-transmitting hole. Fig.18 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present disclosure. Fig.18As shown, the display panel may include: a first conductive line L11 (ie, ITO1), a second conductive line L12 (ie, ITO2) and a third conductive line L13 (ie, ITO3).

[0159] Each third sub-display area A21 may include k light-emitting element groups. Each light-emitting element group may include multiple adjacent columns of second light-emitting elements 40, and the first to k-th light-emitting element groups may be arranged in sequence in a direction close to another third sub-display area. Accordingly, each target sub-display area A110 includes k pixel circuit groups corresponding to the k light-emitting element groups Z0. Each pixel circuit group may include multiple adjacent columns of second pixel circuits 20, and the first to k-th pixel circuit groups may be arranged in sequence in a direction away from the adjacent third sub-display area.

[0160] Wherein, k can be an integer greater than 0. For example, the embodiment of the present disclosure is described by taking k as 4 as an example. Optionally, the first light-emitting element group Z01 to the third light-emitting element group Z03 can include 12 columns of second light-emitting elements 40 respectively. The fourth light-emitting element group Z04 can include 8 columns of second light-emitting elements 40. Correspondingly, the first pixel circuit group Z11 to the third pixel circuit group Z13 can include 12 columns of second pixel circuits 20 respectively. The fourth pixel circuit group Z14 can include 8 columns of second pixel circuits 20.

[0161] That is, Fig.18 In the display panel shown, in the third sub-display area A21, the second light-emitting element 40 in the 1st column to the second light-emitting element 40 in the 13th column (i.e., R1 to R13) belong to the first light-emitting element group Z01; the second light-emitting element 40 in the 14th column to the second light-emitting element 40 in the 26th column (i.e., R14 to R26) belong to the second light-emitting element group Z02; the second light-emitting element 40 in the 27th column to the second light-emitting element 40 in the 39th column (i.e., R27 to R39) belong to the third light-emitting element group Z03; the second light-emitting element 40 in the 40th column to the second light-emitting element 40 in the 48th column (i.e., R40 to R48) belong to the fourth light-emitting element group Z04.

[0162] Correspondingly, in the target sub-display area A110, the second pixel circuit 20 in the 1st column to the second pixel circuit 20 in the 13th column (i.e., P1 to P13) belong to the 1st pixel circuit group Z11; the second pixel circuit 20 in the 14th column to the second pixel circuit 20 in the 26th column (i.e., P14 to P26) belong to the 2nd pixel circuit group Z12; the second pixel circuit 20 in the 27th column to the second pixel circuit 20 in the 39th column (i.e., P27 to P39) belong to the 3rd pixel circuit group Z13; the second pixel circuit 20 in the 40th column to the second pixel circuit 20 in the 48th column (i.e., P40 to P48) belong to the 4th pixel circuit group Z14. Fig.18Only the first pixel circuit 10 and the first light emitting element 30 are not shown.

[0163] Optionally, in the embodiment of the present disclosure, each second light emitting element 40 in each light emitting element group and each second pixel circuit 20 in a corresponding pixel circuit group may be connected through a first conductive line L11, a second conductive line L12 and / or a third conductive line L13.

[0164] For example, Fig.19 As shown, each second light emitting element 40 in the first light emitting element group Z01 and each second pixel circuit 20 in the first pixel circuit group Z11 can be connected to each other through a first conductive line L11 ( Fig.19 ITO1 represents the first conductive line L11).

[0165] like Fig. 20 As shown, each second light emitting element 40 in the second light emitting element group Z02 and each second pixel circuit 202 in the second pixel circuit group Z12 can be connected to each other through the second conductive line L12 ( Fig. 20 ITO2 represents the second conductive line L12).

[0166] like Fig.21 As shown, each second light emitting element 40 in the third light emitting element group Z03 and each second pixel circuit 20 in the third pixel circuit group Z13 can be connected to each other through a third conductive line L13 ( Fig.21 The third conductive line L13 is represented by ITO3 for connection.

[0167] like Fig. 22 As shown, each second light-emitting element 40 in the fourth light-emitting element group Z04 can be connected to each second pixel circuit 20 in the fourth pixel circuit group Z14 through a first conductive line L11 (ie, ITO1), a second conductive line L12 (ie, ITO2) and a third conductive line L13 (ie, ITO3).

[0168] For example, refer to Fig. 22, the fourth light-emitting element group Z04 may include: two first sub-light-emitting element groups Z041, two second sub-light-emitting element groups Z042 and two third sub-light-emitting element groups Z043 arranged symmetrically along the axis xx of the third sub-display area A21. Each sub-light-emitting element group may include multiple adjacent rows of second light-emitting elements 40, and the number of rows of second light-emitting elements 40 included in each sub-light-emitting element group may be the same or different. In addition, the first sub-light-emitting element group Z041, the second sub-light-emitting element group Z042 and the third sub-light-emitting element group Z043 located on the same side may be arranged in sequence in a direction away from the axis xx, and the axis xx extends along the second direction X2. The fourth pixel circuit group Z14 may include two first sub-pixel circuit groups Z141 corresponding to the two first sub-light-emitting element groups Z041, two second sub-pixel circuit groups Z142 corresponding to the two second sub-light-emitting element groups Z042, ​​and two third sub-pixel circuit groups Z143 corresponding to the two third sub-light-emitting element groups Z043. The arrangement of the first sub-pixel circuit group Z141 , the second sub-pixel circuit group Z142 and the third sub-pixel circuit group Z143 located on the same side is the same as that of the sub-light emitting element group.

[0169] Among them, each second light-emitting element 40 in each first sub-light-emitting element group Z041 can be connected to each second pixel circuit 20 in the corresponding first sub-pixel circuit group Z141 through a first conductive line L11 (i.e., ITO1). Each second light-emitting element 40 in each second sub-light-emitting element group Z042 can be connected to each second pixel circuit 20 in the corresponding second sub-pixel circuit group Z142 through a second conductive line L12 (i.e., ITO2). Each second light-emitting element 40 in each third sub-light-emitting element group Z043 can be connected to each second pixel circuit 20 in the corresponding third sub-pixel circuit group Z143 through a third conductive line L13 (i.e., ITO3).

[0170] Fig.23 It is a schematic diagram of a conductive wire structure provided in an embodiment of the present disclosure. Fig.24 yes Figures 19 to 21 The layout of the structure shown. Combined with Figures 19 to 21 It can be seen that the first conductive line L11 connected to each second light-emitting element 40 in the first light-emitting element group Z01, the second conductive line L12 connected to each second light-emitting element 40 in the second light-emitting element group Z02, and each third conductive line L13 connected to each second light-emitting element 40 in the third light-emitting element group Z03 may include: a first conductive line segment La, a second conductive line segment Lb and a third conductive line segment Lc.

[0171] Among them, one end of the first conductive line segment La can be connected to the corresponding second light-emitting element 40, and the other end of the first conductive line segment La is connected to one end of the second conductive line segment Lb. The other end of the second conductive line segment Lb can be connected to one end of the third conductive line segment Lc. The other end of the third conductive line segment Lc can be connected to the corresponding second pixel circuit 20. In addition, the first conductive line segment La and the third conductive line segment Lc can extend along the first direction X1, the second conductive line segment Lb can extend along the second direction X2, and the orthographic projection of the second conductive line segment Lb on the base substrate 01 at least partially overlaps with the orthographic projection of the second light-emitting element 40 on the base substrate 01 (refer to the following Fig.24 That is, the first conductive line L11, the second conductive line L12 and the third conductive line L13 can all be led out from the connected second light emitting element 40 and extend laterally in their own directions to the position of the second pixel circuit 20 to be connected to the second pixel circuit 20.

[0172] Optionally, in order to avoid mutual interference of signals, the second conductive line segment Lb included in the first conductive line L11 and the second conductive line segment Lb included in the third conductive line L13 may at least partially overlap. The second conductive line segment Lb included in the first conductive line L11 and the second conductive line segment Lb included in the second conductive line L12 may not overlap, and the second conductive line segment Lb included in the third conductive line L13 and the second conductive line segment Lb included in the second conductive line L12 may not overlap. The overlapping parts may be switched through vias.

[0173] It should be noted that Fig.24 The first conductive line L11 connected to each second light emitting element 40 in the first light emitting element group Z01, that is, the structure layout of the ITO1 wiring in the display panel is only schematically shown. For the second conductive line L12 (that is, the ITO2 wiring) connected to each second light emitting element 40 in the second light emitting element group Z02, and the third conductive line L13 (that is, the ITO3 wiring) connected to each second light emitting element 40 in the third light emitting element group Z03, the structure layout in the display panel can be directly referred to. Fig.24 The schematic diagram of the display panel is shown and will not be described in detail here.

[0174] Optional, Fig.25 Schematic diagram of a conductive wire structure provided by an embodiment of the present disclosure. Fig.25As shown, the first conductive line L11 connected to each second light-emitting element 40 in each first sub-light-emitting element group Z041, the second conductive line L12 connected to each second light-emitting element 40 in each second sub-light-emitting element group Z042, ​​and the third conductive line L13 connected to each second light-emitting element 40 in each third sub-light-emitting element group Z043 may include: a fourth conductive line segment Ld, a fifth conductive line segment Le, a sixth conductive line segment Lf, and a seventh conductive line segment Lg.

[0175] Among them, one end of the fourth conductive line segment Ld can be connected to the corresponding second light-emitting element 40, and the other end of the fourth conductive line segment Ld is connected to one end of the fifth conductive line segment Le. The other end of the fifth conductive line segment Le can be connected to one end of the sixth conductive line segment Lf. The other end of the sixth conductive line segment Lf can be connected to one end of the seventh conductive line segment Lg. The other end of the seventh conductive line segment Lg can be connected to the corresponding second pixel circuit 20. In addition, the fifth conductive line segment Le and the seventh conductive line segment Lg can extend along the first direction X1, and the sixth conductive line segment Lf can extend along the second direction X2. The fourth conductive line segment Ld can be located between the row where the second light-emitting element 40 connected is located and the adjacent row.

[0176] Fig.26 is a schematic diagram of another display panel structure provided by an embodiment of the present disclosure, Fig. 27 This is a schematic diagram of another display panel structure provided by an embodiment of the present disclosure. Fig.28 yes Fig. 27 A simplified schematic diagram of the display panel is shown. Figure 26 to Figure 28 It can be seen that the fifth conductive line segment Le included in the first conductive line L11 (i.e., ITO1 shown in the figure) can be located in the area where the second light-emitting element group Z02 to the fourth light-emitting element group Z04 are located. The fifth conductive line segment Le included in the second conductive line L12 (i.e., ITO2 shown in the figure) can be located in the area where the third light-emitting element group Z03 and the fourth light-emitting element group Z04 are located. The fifth conductive line segment Le included in the third conductive line L13 (i.e., ITO3 shown in the figure) can be located in the area where the fourth light-emitting element group Z04 is located. The sixth conductive line segment Lf on the side away from the second sub-display area A12 along the axis can be located on the side of the second display area A2 away from the second sub-display area A12, and the sixth conductive line segment Lf on the side close to the second sub-display area A12 along the axis can be located in the second display area A2 close to the second sub-display area A12.

[0177] That is, the fifth conductive line segment Le included in the first conductive line L11 can be led out from the connected second light-emitting element 40, and extend from the area where the second light-emitting elements 40 in columns R14 to R48 are located (i.e., the area where Z02 to Z04 are located) along the column direction to the side of the third sub-display area A21 close to the non-display area or close to the second sub-display area A12, and then extend transversely along the row direction to the area where the corresponding second pixel circuit 20 is located, so as to be connected to the second pixel circuit 20. The fifth conductive line segment Le included in the second conductive line L12 can be led out from the connected second light-emitting element 40, and extend from the area where the second light-emitting elements 40 in columns R27 to R48 are located (i.e., the area where Z03 and Z04 are located) along the column direction to the side of the third sub-display area A21 close to the non-display area or close to the second sub-display area A12, and then extend transversely along the row direction to the area where the corresponding second pixel circuit 20 is located, so as to be connected to the second pixel circuit 20. The fifth conductive line segment Le included in the third conductive line L13 can be led out from the connected second light emitting element 40, and extend from the area where the second light emitting element 40 is located in the R40 to R48 columns (i.e., the area where Z04 is located) along the column direction to the side of the third sub-display area A21 close to the non-display area or close to the second sub-display area A12, and then extend transversely along the row direction to the area where the corresponding second pixel circuit 20 is located, so as to be connected to the second pixel circuit 20. In addition, the sixth conductive line segments Lf included in each conductive line located on the same side and extending along the row direction can partially overlap, or do not overlap.

[0178] refer to Fig.26 and Fig. 27 It can be seen that the display panel may further include at least one column of dummy second pixel circuits 20, and the at least one column of dummy second pixel circuits 20 may be located in the target sub-display area A110. The column of dummy second pixel circuits 20 may also be called a transition column, and the column of dummy second pixel circuits 20 is not connected to any light-emitting element.

[0179] By setting the transition column, it is possible to avoid the problem that the distance between the first column of second light-emitting elements 40 and the second pixel circuit 20 connected thereto is smaller than the distance between the last column of second light-emitting elements 40 and the second pixel circuit 20 connected thereto, resulting in a large start-up time difference between the first column of second light-emitting elements 40 and the last column of second light-emitting elements 40, thereby further ensuring a better display effect.

[0180] In addition, compared Fig.26 and Fig. 27It can be seen that in the first light-emitting element group 01, the first conductive line L11 (i.e., ITO1 shown in the figure) connected to each second light-emitting element 40 located in adjacent rows can be located on the same side facing upward, or can be symmetrically arranged on different sides. In the second light-emitting element group 01, the second conductive line L12 (i.e., ITO2 shown in the figure) connected to each second light-emitting element 40 located in adjacent rows can be located on the same side facing upward, or can be symmetrically arranged on different sides. In the third light-emitting element group 01, the third conductive line L13 (i.e., ITO1 shown in the figure) connected to each second light-emitting element 40 located in adjacent rows can be located on the same side facing upward, or can be symmetrically arranged on different sides. Of course, the above signal lines can also all be located on the same side facing downward, which will not be repeated in the drawings.

[0181] Fig.29 A cross-sectional view of a display panel is shown. Among them, ITO1 represents the first conductive line L11, ITO2 represents the second conductive line L12, and ITO3 represents the third conductive line L13. Anode refers to the anode of the light-emitting element, PLN refers to the planar layer, Fig.29 The display panel shown includes five planar layers PLN1 to PLN5, SD1 refers to a first source-drain metal layer, and SD2 refers to a second source-drain metal layer.

[0182] Optionally, the display panel may further include: a first gate metal layer GATE1, a second gate metal layer GATE2, a first source and drain metal layer SD1, and a second source and drain metal layer SD2. The data line DATA connected to each second pixel circuit 20 may be provided in the same layer as any metal layer.

[0183] For example, refer to Fig.30 In the display panel shown, along the direction away from the adjacent third sub-display area A21, in the second pixel circuits 20 in the first to i-th columns in each target sub-display area A110, the data lines DATA connected to the second pixel circuits 20 located in the odd columns can be in the same layer as the first gate metal layer GATE1. The data lines DATA connected to the second pixel circuits 20 located in the even columns can be in the same layer as the second gate metal layer GATE2. The data lines DATA connected to the second pixel circuits 20 in the i-th to n-th columns can be in the same layer as the first source and drain metal layer SD1. Among them, i can be an integer greater than 1 and less than n, and n can be equal to the total number of columns in each target sub-display area A110. That is, the data lines DATA connected to the second pixel circuits 20 in the first i columns can be alternately arranged in the same layer as GATE1 and GATE2. The data lines DATA connected to the second pixel circuits 20 in the i-th to n-th columns can all be arranged in the same layer as SD1.

[0184] Optionally, assuming that the third sub-display area A21 includes 48 columns of second light-emitting elements 40, i can be 24, that is, every 24 columns of second light-emitting elements 40 can be a group. Correspondingly, that is, in the 1st to 24th columns, the data lines DATA connected to the odd columns can be in the same layer as the first gate metal layer GATE1, in the 1st to 24th columns, the data lines DATA connected to the even columns can be in the same layer as the second gate metal layer GATE2, and the data lines DATA connected to the 24th to 48th columns are all in the same layer as the first source and drain metal layer SD1.

[0185] Optional, Fig.31 and Fig.32 The structure layout of the data line DATA connected to the second pixel circuit 20 in the odd-numbered columns and the first gate metal layer GATE1 at different positions is shown. Fig.33 and Fig.34 The structure layout of the data line DATA connected to the second pixel circuit 20 in the even-numbered columns and the second gate metal layer GATE2 at the same layer at different positions is shown. Fig.35 and Fig.36 The structure layout of the data lines DATA connected to the second pixel circuits 20 in the i-th column to the n-th column and in the same layer as SD1 is shown at different positions. Fig.37 and Fig.38 The overall layout of the display panel at different positions, the same layer as the first gate metal layer GATE1, the same layer as the second gate metal layer GATE2, and the same layer as SD1, is shown. Fig.39 and Fig.40 The structure layout including the conductive line L1 and the data line DATA is shown.

[0186] Fig.41 It can be seen from the above data line related figures that the data line DATA connected to each second pixel circuit 20 may include a first data line segment D11, a second data line segment D12 and a third data line segment D13.

[0187] Among them, one end of the first data line segment D11 can be connected to the corresponding metal layer, and the other end can be connected to one end of the second data line segment D12. The other end of the second data line segment D12 can be connected to one end of the third data line segment D13, and the other end of the third data line segment D13 can be connected to the second pixel circuit 20.

[0188] Furthermore, the second data line segment D12 may extend along the first direction X1, and the second data line segment D12 included in the data line DATA in the same layer as the first gate metal layer GATE1, the second data line segment D12 included in the data line DATA in the same layer as the second gate metal layer GATE2, and the second data line segment D12 included in the data line DATA in the same layer as the first source-drain metal layer SD1 may not overlap each other. That is, each data line DATA may be led out from the boundary between the third sub-display area A21 and the second sub-display area A12 by the metal layer transfer, and extend from the display area to the non-display area in the third sub-display area A21 in the column direction, and then extend along the row direction to the second pixel circuit 20 in the corresponding column, and be connected to the second pixel circuit 20.

[0189] In addition, combined with Fig.42 In the display panel shown, in the same column of second pixel circuits 20, the data line DATA connected to the second pixel circuits 20 located in the first sub-display area A11 may be different from the data line DATA connected to the second pixel circuits 20 located in the second sub-display area A12. For example, the data line DATA connected to a column of second pixel circuits 20 is disconnected at the boundary between the first sub-display area A11 and the second sub-display area A12. In this way, the problem of mutual interference between the signals provided by the data lines can be avoided, ensuring effective and reliable driving of the second light-emitting element 40.

[0190] Furthermore, reference Fig.43 In the display panel shown, the second source-drain metal layer SD2 can cover the first gate metal layer GATE1, the second gate metal layer GATE2 and the first source-drain metal layer SD1. In this way, the signal shielding of the connection point between the driving transistor and the light-emitting element can be achieved, thereby reducing signal crosstalk.

[0191] It can have a certain shielding effect on the influence of the parasitic capacitance on the conductive line L1, ensuring a better display effect.

[0192] In summary, the embodiment of the present disclosure provides a display panel, which includes a substrate having a first display area and a second display area. Since the pixel circuit driving the light-emitting element in the second display area is only located in the first display area and not in the second display area, the light transmittance of the second display area is ensured to be good. Accordingly, the display panel recorded in the embodiment of the present disclosure has a good display effect.

[0193] Fig.44 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. Fig.44 As shown, the display device may include: an integrated circuit 100, and a display panel 200 as shown in any of the above figures.

[0194] The integrated circuit 100 can be connected to the first pixel circuit and the second pixel circuit in the display panel 200, and used to drive the first pixel circuit and the second pixel circuit to work. For example, the driving circuit 100 can be connected to each signal terminal connected to the pixel circuit, and used to provide signals to each signal terminal.

[0195] It should be noted that Fig.44 The position of the integrated circuit 100 is only schematically shown, and the integrated circuit 100 may be located on the right side of the display panel 200, or on both the left side and the right side of the display panel 200. Alternatively, it may be located on the upper side and / or the lower side of the display panel 200.

[0196] Optionally, the display device can be: an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television set, a monitor, or any other product or component with a display function.

[0197] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the display substrate and the display device described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0198] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel comprises: A base substrate having a first display area and a second display area, wherein the first display area at least partially surrounds the second display area; A plurality of first pixel circuits, a plurality of second pixel circuits and a plurality of first light-emitting elements are located in the first display area, and the plurality of second pixel circuits are distributed between the plurality of first pixel circuits at intervals; A plurality of second light emitting elements, located in the second display area; Among them, at least one first pixel circuit among the multiple first pixel circuits is connected to at least one first light-emitting element among the multiple first light-emitting elements, and the orthographic projection of the at least one first pixel circuit on the substrate substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting element on the substrate substrate; at least one second pixel circuit among the multiple second pixel circuits is connected to at least one second light-emitting element among the multiple second light-emitting elements through a conductive line.

2. The display panel according to claim 1, characterized in that: The plurality of second light emitting elements and the plurality of first light emitting elements have the same density.

3. The display panel according to claim 1, characterized in that: The resolution of the first display area is the same as that of the second display area; or the resolution of the first display area is different from that of the second display area.

4. The display panel according to any one of claims 1 to 3, characterized in that: Each of the first pixel circuits is connected to one of the first light-emitting elements; Furthermore, an orthographic projection of each of the first pixel circuits on the base substrate at least partially overlaps with an orthographic projection of the connected first light-emitting element on the base substrate.

5. The display panel according to any one of claims 1 to 3, characterized in that: The plurality of first pixel circuits include a plurality of columns of first pixel circuits extending along a first direction, and the plurality of second pixel circuits include a plurality of columns of second pixel circuits extending along the first direction; Wherein, the plurality of columns of second pixel circuits are distributed at intervals between the plurality of columns of first pixel circuits.

6. The display panel according to claim 5, characterized in that: Any two adjacent columns of the second pixel circuits are spaced by the first pixel circuits of the same number or different number.

7. The display panel according to any one of claims 1 to 3, characterized in that: The plurality of first pixel circuits include a plurality of rows of first pixel circuits extending along a second direction, and the plurality of second pixel circuits include a plurality of rows of second pixel circuits extending along the second direction, wherein the second direction intersects the first direction; Wherein, the multiple rows of second pixel circuits are distributed at intervals between the multiple rows of first pixel circuits.

8. The display panel according to claim 7, characterized in that: The first direction is perpendicular to the second direction.

9. The display panel according to any one of claims 1 to 3, characterized in that: The first display area includes: a first sub-display area and a second sub-display area arranged in sequence along a first direction; the first sub-display area includes: two symmetrical target sub-display areas; Wherein, one of the target sub-display areas, the second display area and another of the target sub-display areas are arranged in sequence along the second direction.

10. The display panel according to claim 9, characterized in that: The second display area includes two third sub-display areas symmetrically arranged along the second direction; the display panel includes: a first conductive line, a second conductive line and a third conductive line; Each of the third sub-display areas includes k light-emitting element groups, each of the light-emitting element groups includes a plurality of adjacent columns of the second light-emitting elements, and the first to kth light-emitting element groups are sequentially arranged in a direction close to another third sub-display area, and k is an integer greater than 0; Each of the target sub-display areas includes k pixel circuit groups corresponding one-to-one to the k light-emitting element groups, each of the pixel circuit groups includes multiple adjacent columns of the second pixel circuits, and the first pixel circuit group to the kth pixel circuit group are arranged in sequence along a direction away from the adjacent third sub-display area; and each of the second light-emitting elements in each of the light-emitting element groups is connected to each of the second pixel circuits in a corresponding one of the pixel circuit groups through the first conductive line, the second conductive line and / or the third conductive line.

11. The display panel according to claim 10, characterized in that: k is 4.

12. The display panel according to claim 11, characterized in that: Each of the second light-emitting elements in the first light-emitting element group is connected to each of the second pixel circuits in the first pixel circuit group through the first conductive line; Each of the second light-emitting elements in the second light-emitting element group is connected to each of the second pixel circuits in the second pixel circuit group through the second conductive line; Each of the second light-emitting elements in the third light-emitting element group is connected to each of the second pixel circuits in the third pixel circuit group through the third conductive line; Each of the second light-emitting elements in the fourth light-emitting element group is connected to each of the second pixel circuits in the fourth pixel circuit group through the first conductive line, the second conductive line and the third conductive line.

13. The display panel according to claim 12, characterized in that: The first conductive line connected to each of the second light-emitting elements in the first light-emitting element group, the second conductive line connected to each of the second light-emitting elements in the second light-emitting element group, and each of the third conductive lines connected to each of the second light-emitting elements in the third light-emitting element group include: a first conductive line segment, a second conductive line segment, and a third conductive line segment; One end of the first conductive line segment is connected to the corresponding second light-emitting element, and the other end of the first conductive line segment is connected to one end of the second conductive line segment; The other end of the second conductive line segment is connected to one end of the third conductive line segment; The other end of the third conductive line segment is connected to the corresponding second pixel circuit; The first conductive line segment and the third conductive line segment extend along the first direction, the second conductive line segment extends along the second direction, and an orthographic projection of the second conductive line segment on the base substrate at least partially overlaps with an orthographic projection of a second light-emitting element connected thereto on the base substrate.

14. The display panel according to claim 13, characterized in that: The second conductive line segment included in the first conductive line at least partially overlaps with the second conductive line segment included in the third conductive line, the second conductive line segment included in the first conductive line does not overlap with the second conductive line segment included in the second conductive line, and the second conductive line segment included in the third conductive line does not overlap with the second conductive line segment included in the second conductive line.

15. The display panel according to claim 12, characterized in that: The fourth light-emitting element group includes: two first sub-light-emitting element groups, two second sub-light-emitting element groups and two third sub-light-emitting element groups symmetrically arranged along the axis of the third sub-display area, each sub-light-emitting element group includes a plurality of adjacent rows of the second light-emitting elements, and the first sub-light-emitting element group, the second sub-light-emitting element group and the third sub-light-emitting element group located on the same side are arranged in sequence in a direction away from the axis, and the axis extends along the second direction; The fourth pixel circuit group includes: two first sub-pixel circuit groups corresponding to the two first sub-light emitting element groups, two second sub-pixel circuit groups corresponding to the two second sub-light emitting element groups, and two third sub-pixel circuit groups corresponding to the two third sub-light emitting element groups. Among them, each of the second light-emitting elements in each of the first sub-light-emitting element groups is connected to each of the second pixel circuits in the corresponding first sub-pixel circuit group through the first conductive line; each of the second light-emitting elements in each of the second sub-light-emitting element groups is connected to each of the second pixel circuits in the corresponding second sub-pixel circuit group through the second conductive line; each of the second light-emitting elements in each of the third sub-light-emitting element groups is connected to each of the second pixel circuits in the corresponding third sub-pixel circuit group through the third conductive line.

16. The display panel according to claim 15, characterized in that: The first conductive line connected to each of the second light-emitting elements in each of the first light-emitting element groups, the second conductive line connected to each of the second light-emitting elements in each of the second light-emitting element groups, and the third conductive line connected to each of the second light-emitting elements in each of the third light-emitting element groups include: a fourth conductive line segment, a fifth conductive line segment, a sixth conductive line segment, and a seventh conductive line segment; One end of the fourth conductive line segment is connected to the corresponding second light-emitting element, and the other end of the fourth conductive line segment is connected to one end of the fifth conductive line segment; The other end of the fifth conductive line segment is connected to one end of the sixth conductive line segment; The other end of the sixth conductive line segment is connected to one end of the seventh conductive line segment; The other end of the seventh conductive line segment is connected to the corresponding second pixel circuit; The fifth conductive line segment and the seventh conductive line segment extend along the first direction, and the sixth conductive line segment extends along the second direction; the fourth conductive line segment is located between a row where the second light-emitting element connected thereto is located and an adjacent row; The fifth conductive line segment included in the first conductive line is located in the area where the second to fourth light-emitting element groups are located, the fifth conductive line segment included in the second conductive line is located in the area where the third and fourth light-emitting element groups are located, and the fifth conductive line segment included in the third conductive line is located in the area where the fourth light-emitting element group is located; the sixth conductive line segment on the side away from the second sub-display area along the axis is located on the side of the second display area away from the second sub-display area, and the sixth conductive line segment on the side close to the second sub-display area along the axis is located in the second display area close to the second sub-display area.

17. The display panel according to claim 11, characterized in that: The first to third light emitting element groups respectively include 12 columns of the second light emitting elements; the fourth light emitting element group includes 8 columns of the second light emitting elements; The first to third pixel circuit groups respectively include 12 columns of the second pixel circuits; and the fourth pixel circuit group includes 8 columns of the second pixel circuits.

18. The display panel according to claim 10, characterized in that: The display panel further includes: a plurality of metal layers; The data line connected to each of the second pixel circuits is arranged in the same layer as any of the metal layers; The plurality of metal layers include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer.

19. The display panel according to claim 18, characterized in that: Along the direction away from the adjacent third sub-display area, among the second pixel circuits in the first to i-th columns in each of the target sub-display areas, the data lines connected to the second pixel circuits in odd-numbered columns are in the same layer as the first gate metal layer; The data lines connected to the second pixel circuits located in even columns are on the same layer as the second gate metal layer; the data lines connected to the second pixel circuits in the i-th to n-th columns are on the same layer as the first source and drain metal layer, where i is an integer greater than 1 and less than n, and n is equal to the total number of columns in each of the target sub-display areas.

20. The display panel according to claim 19, characterized in that: The data lines connected to each of the second pixel circuits include: a first data line segment, a second data line segment and a third data line segment; One end of the first data line segment is connected to the corresponding metal layer, and the other end is connected to one end of the second data line segment, the other end of the second data line segment is connected to one end of the third data line segment, and the other end of the third data line segment is connected to the second pixel circuit; The second data line segment extends along the first direction, and the second data line segment included in the data line on the same layer as the first gate metal layer, the second data line segment included in the data line on the same layer as the second gate metal layer, and the second data line segment included in the data line on the same layer as the first source and drain metal layer do not overlap with each other.

21. The display panel according to claim 19, characterized in that: The second source-drain metal layer covers the first gate metal layer, the second gate metal layer and the first source-drain metal layer.

22. The display panel according to claim 10, characterized in that: In the same column of the second pixel circuits, the data line connected to the second pixel circuit located in the first sub-display area is different from the data line connected to the second pixel circuit located in the second sub-display area.

23. The display panel according to claim 10, characterized in that: The display panel further includes at least one column of dummy second pixel circuits, and the at least one column of dummy second pixel circuits is located in the target sub-display area close to the second display area.

24. The display panel according to any one of claims 1 to 3, characterized in that: Among the plurality of first pixel circuits and the plurality of second pixel circuits, a width of any pixel circuit is smaller than a width of any first light emitting element.

25. The display panel according to claim 24, characterized in that: The width of each pixel circuit differs from the width of the first light emitting element by 4 micrometers.

26. The display panel according to any one of claims 1 to 3, characterized in that: Each of the second pixel circuits and each of the second light emitting elements has a switching portion, and the conductive lines are respectively connected to the switching portion of the at least one second pixel circuit and the switching portion of the at least one second light emitting element.

27. The display panel according to any one of claims 1 to 3, characterized in that: The conductive wire is a transparent conductive wire.

28. The display panel according to claim 27, characterized in that: The material of the transparent conductive line is indium tin oxide.

29. The display panel according to any one of claims 1 to 3, characterized in that: The second display area is a light-transmitting display area.

30. A display device, characterized in that: The display device comprises: an integrated circuit, and a display panel as claimed in any one of claims 1 to 29; The integrated circuit is connected to the first pixel circuit and the second pixel circuit in the display panel, and is used to drive the first pixel circuit and the second pixel circuit to operate.

31. The display device according to claim 30, characterized in that: The display device further includes a photosensitive sensor, and the photosensitive sensor is located in the second display area of ​​the display panel.

32. The display device according to claim 31, characterized in that The second display area is rectangular, and the orthographic projection area of ​​the photosensor on the base substrate is smaller than or equal to the area of ​​the inscribed circle of the second display area.

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