Deformable display device

Abstract

A deformed display device includes: a display area, the display area includes a plurality of pixel array areas in which a plurality of pixel array groups are arranged and a plurality of circuit areas in which a plurality of driving circuits are arranged, wherein the pixel array groups and the driving circuits form a pixel block; and a virtual area arranged on one side of the display area, the virtual area includes a plurality of virtual pixel array areas in which a plurality of virtual pixel array groups are arranged and a plurality of virtual circuit areas in which a plurality of virtual circuits are arranged, wherein the virtual pixel array groups and the virtual circuits do not form a pixel block.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefits of Korean Patent Application No. 10-2020-0169569 filed in Korea on December 7, 2020, and is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to a deformed display device using a gate-in-panel (GIP) circuit. Background Art

[0004] Recently, as the information age has matured, there has been an increasing interest in information display that processes and displays massive amounts of information. As a result, various flat panel display devices have been developed and are receiving attention.

[0005] Specific examples of flat panel display devices include liquid crystal display (LCD) devices, plasma display panel (PDP) devices, field emission display (FED) devices, electroluminescent display (ELD) devices, and organic light emitting diode display (OLED) devices. Flat panel displays show excellent performance of thin thickness, light weight, and low power consumption, and have rapidly replaced cathode ray tubes (CRTs).

[0006] In recent years, in the process of developing technologies for realizing these display devices, in addition to technologies for displaying images, technologies for realizing designs desired by consumers are also required for the display devices.

[0007] One of these technologies is the diversification of the shape of the display area. The display area is the area where pixels basically emit light to display an image, and it may require various shapes other than a rectangular shape.

[0008] Here, the display device requiring diversified display area shapes can be applied to various fields such as televisions, car displays, wearable devices, etc., as well as mobile devices such as smartphones or tablet PCs.

[0009] Therefore, a technology of deforming a display device has been studied to meet the needs of consumers by diversifying the shape of a display area of ​​a display device for various purposes and ensuring flexibility in product design.

[0010] In particular, recently, in the process of diversifying the shape of a display area, research on a deformable display device having a narrow bezel has been actively conducted. Summary of the invention

[0011] Accordingly, embodiments of the present disclosure are directed to a deformable display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0012] One aspect of the present disclosure is to provide a deformed display device that can achieve a narrow bezel by reducing the width of the bezel in the display device using a GIP circuit.

[0013] Another aspect of the present disclosure is to provide a deformable display device having improved uniformity of driving characteristics.

[0014] Another aspect of the present disclosure is to provide a deformed display device that prevents display quality degradation in a dummy area by maintaining regularity of alternating arrangement of pixel array groups and driving circuits for driving the groups in the dummy area.

[0015] Other features and aspects will be described in the following description, and these other features and aspects will be partially obvious from the description, or can be learned by practicing the inventive concept provided herein. Other features and aspects of the inventive concept can be realized and obtained through the structures specifically pointed out in the written description, or the structures that can be derived therefrom, and the claims and drawings thereof.

[0016] In order to achieve these and other aspects of the present inventive concept, as specifically implemented and broadly described herein, a deformed display device includes: a display area, the display area including a plurality of pixel array areas in which a plurality of pixel array groups are arranged and a plurality of circuit areas in which a plurality of driving circuits are arranged, wherein the pixel array groups and the driving circuits form a pixel block; and a virtual area arranged on one side of the display area, the virtual area including a plurality of virtual pixel array areas in which a plurality of virtual pixel array groups are arranged and a plurality of virtual circuit areas in which a plurality of virtual circuits are arranged, wherein the virtual pixel array groups and the virtual circuits do not form a pixel block.

[0017] In another embodiment, a deformed display device includes a display area, the display area includes a plurality of pixel array areas in which a plurality of pixel array groups are arranged and a plurality of circuit areas in which a plurality of driving circuits are arranged, wherein a first number of pixel array groups and a first number of driving circuits form a pixel block; and a virtual area disposed on one side of the display area, the virtual area includes a plurality of virtual pixel array areas in which a plurality of virtual pixel array groups are arranged and a plurality of virtual circuit areas in which a plurality of virtual circuits are arranged, wherein a second number of virtual pixel array groups and a second number of virtual circuits are arranged at one end of a row of the display area, the second number being less than the first number. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed inventive concept. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain various principles of the present disclosure. In the drawings:

[0019] Figure 1 is a schematic diagram of a deformed display device according to an embodiment of the present disclosure;

[0020] Figure 2 is a view showing a structural example of pixels and a common control circuit block in a pixel array group according to an embodiment of the present disclosure;

[0021] Figure 3 is a schematic diagram showing a configuration of a pixel block according to an embodiment of the present disclosure;

[0022] Figure 4 is a schematic diagram showing an arrangement example of a gate signal generating circuit and an emission signal generating circuit of a scan driving circuit of a display device according to a modification of an embodiment of the present disclosure;

[0023] Figure 5 is a schematic diagram showing a virtual pixel array group according to an embodiment of the present disclosure;

[0024] Figure 6 is a schematic diagram of a signal line formed along a circuit area provided with a driving circuit and a dummy circuit area provided with a dummy circuit according to an embodiment of the present disclosure;

[0025] Figure 7 It is shown Figure 6 A schematic diagram of a conceptual configuration of a gate signal generating circuit in a driving circuit of;

[0026] Fig. 8A is a schematic diagram of a thin film transistor in a circuit region, and Figure 8B is a schematic diagram of a thin film transistor in a virtual circuit region;

[0027] Fig. 9 is a schematic diagram of a circuit area provided with a driving circuit and a dummy circuit area provided with a dummy circuit according to another embodiment of the present disclosure; and

[0028] Fig.10 is a schematic diagram of a signal line formed along a circuit region provided with a driving circuit and a dummy circuit region provided with a dummy circuit according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.

[0030] Figure 1is a schematic diagram of a deformed display device according to an embodiment of the present disclosure.

[0031] exist Figure 1 In the embodiment of the present disclosure, the display device 10 may include a display panel 100 including a plurality of Figure 2 A plurality of pixels P and a panel driving circuit for driving the display panel 100.

[0032] Here, the panel driving circuit for driving the display panel 100 may include a data driving circuit 200 , a scan driving circuit 500 , a timing control circuit 300 , and a power supply circuit 400 .

[0033] The display panel 100 may be a liquid crystal display panel or an organic light emitting diode display panel. However, the present disclosure is not limited thereto, and the display panel 100 may be another type of display panel capable of controlling the light transmittance of a thin film transistor.

[0034] The display panel 100 may include a display area AA (or active area) and a non-display area NA (or inactive area) surrounding the display area AA, wherein in the display area AA, a substrate is provided. Figure 2 pixels P to display the image.

[0035] Set in display area AA Figure 2 The pixels P may be arranged in a matrix form, and each pixel P may include Figure 2 The plurality of sub-pixels SP1, SP2 and SP3 that emit light of different colors. For example, Figure 2 Each pixel P may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B arranged adjacent to each other along a row line direction (ie, a horizontal direction in the context of the figure).

[0036] here, Figure 2 A plurality of pixels P arranged along the row direction in the Figure 2 Each pixel array group PAG will be described in more detail later. Figure 2 Pixel array group PAG.

[0037] Meanwhile, in the deformed display device 10 according to an embodiment of the present disclosure, the display area AA may have a deformed shape (or a free form) different from a typical rectangular shape.

[0038] That is, the display area AA may be formed in a deformed shape such as a circle, an ellipse, a polygon, etc. Therefore, the boundary between the display area AA and the non-display area NA may also have various shapes such as a circular arc, an elliptical arc, a curve, an oblique line, etc., instead of a straight line shape.

[0039] The display area AA may include an upper side, a lower side, a left side, and a right side. In addition, at least one of the four sides of the display area AA may not have a straight line shape. In addition, a portion of at least one of the four sides of the display area AA may have a curvature or a curved shape.

[0040] In addition, in the display panel 100, various signal lines for transmitting driving signals may be formed on the substrate to drive the display panel 100. Figure 2 The pixel P (or Figure 2 sub-pixels SP1, SP2 and SP3).

[0041] Figure 2 The plurality of data lines DL are used to transmit data signals (or data voltages Vda) as image signals, and the plurality of data lines DL may extend in a column line direction (vertical line or first direction), and each data line DL may be connected to a corresponding column line. Figure 2 Sub-pixels SP1, SP2 and SP3.

[0042] In addition, a plurality of gate lines for transmitting gate signals may extend in the row line direction (horizontal direction or second direction), and each gate line may be connected to a gate line of a corresponding row line. Figure 2 Sub-pixels SP1, SP2 and SP3.

[0043] The transmission lines for transmitting the transmission signal may extend along the column lines and parallel to the data lines DL, and each transmission line may be connected to the corresponding column line. Figure 2 Sub-pixels SP1, SP2 and SP3.

[0044] The timing control circuit 300 can control the driving timing of the data driving circuit 200 and the scan driving circuit 500. The timing control circuit 300 can process the digital data signal Da input from the external system according to the optical characteristics of the display panel 100, and provide the processed digital data signal Da to the data driving circuit 200.

[0045] Further, the timing control circuit 300 can generate a data control signal DCS for controlling the driving timing of the data driving circuit 200 and a scan control signal SCS for controlling the driving timing of the scan driving circuit 500 based on timing signals (for example, a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and a data enable signal input from an external system).

[0046] The power supply circuit 400 may generate and provide various voltages for driving components of the deformed display device 10. The power supply circuit 400 may generate and output a first logic voltage VGL and a second logic voltage VGH (or a low logic voltage and a high logic voltage) for driving the scan driving circuit 500, and a first power supply voltage VSS and a second power supply voltage VDD (or a low potential driving voltage and a high potential driving voltage) for driving the display panel 100.

[0047] The data driving circuit 200 can drive Figure 2 The data driving circuit 200 may convert the digital data signal Da into an analog data signal (ie, a data voltage Vda) based on the data control signal DCS, and may provide the data voltage Vda to the data line DL. Figure 2 The corresponding data line DL.

[0048] The data driving circuit 200 may be configured in the form of an integrated circuit (IC). In addition, the data driving circuit 200 may include at least one driving IC. In the embodiment of the present disclosure, a case where a plurality of driving ICs are provided is taken as an example.

[0049] Meanwhile, each driving IC may be mounted on the flexible circuit film 210 and connected to the display panel 100. As another example, each driving IC may be directly mounted on the substrate of the display panel 100 in the form of a chip on glass (COG).

[0050] In the flexible circuit film 210 , wiring may be provided outside the driving IC to transmit a control signal SCS for driving the scan driving circuit 500 , voltages VGL and VGH, and voltages VSS and VDD for driving the display panel 100 to the display panel 100 .

[0051] The scan driving circuit 500 can be driven by outputting corresponding scan signals to the gate lines and the emission lines. The scan driving circuit 500 can generate scan signals based on the scan control signal SCS and provide the scan signals to the corresponding signal lines. For example, the scan driving circuit 500 can generate gate signals and emission signals and provide these signals to the corresponding signal lines.

[0052] The scan driving circuit 500 may output gate signals to the gate lines in a line sequential manner, and output emission signals to the emission lines in a line sequential manner.

[0053] The scan driving circuit 500 may be directly formed on a substrate of the display panel 100 in a gate-in-panel (GIP) type.

[0054] The display device 10 according to the modification of the embodiment of the present disclosure is characterized in that the scan driving circuit 500 is not formed in the non-display area NA but is dispersedly formed in the display area AA.

[0055] like Figure 1 As shown in FIG. 1 , the display area AA may include a plurality of pixel array areas PA and a plurality of circuit areas SA. The pixel array area PA is arranged Figure 2 The circuit area SA is an area respectively provided between adjacent pixel array areas PA and constituting the scan driving circuit 500.

[0056] Arranged in a matrix Figure 2 A plurality of pixels P may be arranged in each pixel array area PA. In addition, the pixel array area PA may substantially display an image. The pixel array areas PA may be parallel to each other and extend in the column line direction, and may be spaced apart from each other in the row line direction, with the circuit area SA interposed therebetween.

[0057] In addition, each circuit area SA may be disposed between adjacent pixel array areas PA.

[0058] In addition, some circuits constituting the scan driving circuit 500 may be formed in the circuit area SA. The circuit areas SA may be parallel to each other and extend along the column lines, and may be spaced apart from each other along the row line direction with the pixel array area PA interposed therebetween.

[0059] In the modified display device 10 according to the embodiment of the present disclosure, the circuit area SA is dispersedly arranged in the display area AA, so that the pixel array area PA as the actual image display area is configured to have a segmented shape. That is, the pixel area PA is segmented and separated by the circuit area SA.

[0060] Accordingly, since the scan driving circuit 500 for generating the scan signal is formed in the display area AA without forming the scan driving circuit 500 in the non-display area NA, the width of the non-display area NA can be reduced. Therefore, a narrow frame that reduces the width of the non-display area NA can be effectively implemented in the display device 10.

[0061] By forming driving circuits (which are unit circuits for generating scan signals) in the plurality of circuit areas SA, respectively, deviation of scan signals generated according to positions based on the row line direction of the display area AA can be reduced.

[0062] Therefore, the uniformity of the driving characteristics in the entire display area AA is improved, thereby improving the display quality. For example, a plurality of circuit areas SA are arranged spaced apart from each other in the row line direction, and a driving circuit is formed in each circuit area SA, so that the deviation of the scanning signal generated along the row line direction of the display area AA can be reduced.

[0063] In the modified display device 10 according to the embodiment of the present disclosure, since the display area AA is configured in a free form, the lengths are not the same and differ according to the position with respect to the row line direction and / or the column line direction.

[0064] That is, the horizontal resolution and / or the vertical resolution may differ depending on the location.

[0065] Reference Figure 1 To explain this in detail, the length of the display area AA in the row line direction may be different as a whole, and the length of the display area AA in the column line direction may be different as a whole, and may be different.

[0066] As described above, since the display area AA has a deformed shape, the lengths of all row lines may be different and may differ according to positions. Therefore, the number of pixel array areas PA and circuit areas SA disposed on the row lines may differ according to positions.

[0067] For example, at least four pixel array areas PA and at least four circuit areas SA may be arranged on a row line disposed on a relatively upper side. On the other hand, only one to three pixel array areas PA may be located on a row line disposed on a relatively lower side, and only one to three circuit areas SA may also be located on a row line disposed on a relatively lower side.

[0068] Therefore, reference Figure 4 , the number of pixel array areas PA and circuit areas SA arranged on the first row line (row line [1]) may be different from the number of pixel array areas PA and circuit areas SA arranged on the nth row line (row line [n]) (n is a natural number).

[0069] therefore, Figure 3 The number of pixel array groups PAG is related to Figure 3 The driving circuits GC and EC may be different depending on the position of the row lines.

[0070] here, Figure 3 The pixel array group PAG and Figure 3 The driving circuits GC and EC are used to form Figure 3 The smallest unit of pixel block PB. Figure 1 As shown in Figure 3 The pixel array group PAG and Figure 3 The driving circuits GC and EC do not depend on the position of the row line and constitute the minimum unit, so that an unrealized Figure 3 A virtual area DA of the pixel block PB.

[0071] In the present disclosure, the virtual area DA is defined as an area in which the pixel block PB is not implemented. In addition, since the virtual area DA is set in the display area AA, an image is also displayed in the virtual area DA. Therefore, the term 'virtual' should not be interpreted as not driving or applying a signal.

[0072] The display device 10 according to the embodiment of the present disclosure can prevent the display quality from being affected by the fact that the display quality is not realized. Figure 3 The virtual area DA of the pixel block PB is reduced.

[0073] This will refer to Figure 2 and Figure 3 Describe in more detail.

[0074] Figure 2 is a view showing a structural example of pixels and a common control circuit block in a pixel array group according to an embodiment of the present disclosure, and Figure 3 is a schematic diagram showing a configuration of a pixel block according to an embodiment of the present disclosure.

[0075] also, Figure 4 1 is a schematic diagram showing an arrangement example of a gate signal generating circuit and an emission signal generating circuit of a scan driving circuit of a display device according to a modification of an embodiment of the present disclosure.

[0076] also, Figure 5 is a schematic diagram illustrating a virtual pixel array group according to an embodiment of the present disclosure.

[0077] like Figure 2 As shown in , the pixel array group PAG according to an embodiment of the present disclosure may be configured to include: a plurality of pixels P arranged along a row line direction and a common control circuit block C disposed between adjacent pixels P.

[0078] Here, for the sake of convenience of explanation, the pixel array group PAG is described as including two pixels P adjacent to each other along a row line and one common control circuit block C disposed therebetween, as an example.

[0079] Each pixel P may include a plurality of sub-pixels SP1, SP2 and SP3, which are adjacent to each other along a row direction and emit light of different colors. For example, the pixel P may include a red first sub-pixel SP1, a green second sub-pixel SP2 and a blue third sub-pixel SP3.

[0080] Furthermore, a common control circuit block C disposed between the pixels P is commonly connected to the first subpixel SP1 , the second subpixel SP2 , and the third subpixel SP3 of the pixel P to commonly control the storage capacitors of the subpixels SP1 , SP2 , and SP3 .

[0081] Here, an internal compensation structure may be applied to compensate for the threshold voltage of the driving transistor DT of the sub-pixels SP1, SP2, and SP3, and in this regard, for each of the sub-pixels SP1, SP2, and SP3, a 7T1C structure is taken as an example.

[0082] Each sub-pixel SP1, SP2 and SP3 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6 of a switching transistor, a driving transistor DT, and a storage capacitor Cst as a driving element. In addition, each sub-pixel SP1, SP2 and SP3 may include a light emitting diode OD, which is a light emitting element driven by the driving element.

[0083] Here, the transistors T1 to T6 and DT of the sub-pixels SP1, SP2, and SP3 may be P-type transistors. Alternatively, the transistors T1 to T6 and DT of the sub-pixels SP1, SP2, and SP3 may be N-type transistors.

[0084] In addition, the transistors T1 to T6 and DT of the sub-pixels SP1, SP2 and SP3 may be mixed as P-type transistors and N-type transistors. For example, the driving transistor DT may be an N-type transistor, and the switching transistors T1 to T6 may be P-type transistors. Alternatively, the driving transistor DT may be a P-type transistor, and the switching transistors T1 to T6 may be N-type transistors.

[0085] The first transistor T1 may have a gate electrode connected to a gate line of an nth row line (as a corresponding row line), a source electrode connected to a corresponding data line DL, and a drain electrode connected to a first node N1 (ie, a drain electrode of the second transistor T2 and a source electrode of the driving transistor DT).

[0086] The first transistor T1 may be turned on to correspond to the gate signal Vg[n] of the corresponding n-th row line. Thus, the data signal Vda provided through the data line DL may be applied to the first node N1.

[0087] The second transistor T2 may have a gate electrode connected to the emission line of the corresponding n-th row line, a source electrode receiving the high potential driving voltage VDD of the second power supply voltage, and a drain electrode connected to the first node N1.

[0088] The second transistor T2 may be turned on to correspond to the emission signal Vem[n] of the corresponding n-th row line. Therefore, the high potential driving voltage VDD may be applied to the first node N1.

[0089] The third transistor T3 may have a gate electrode connected to the gate line of the corresponding nth row line, a source electrode connected to the drain electrode of the driving transistor DT and the source electrode of the fifth transistor (i.e., the third node N3), and a drain electrode connected to the gate electrode of the driving transistor DT and the first electrode of the storage capacitor Cst (i.e., the second node N2).

[0090] The third transistor T3 may be turned on to correspond to the gate signal Vg[n] of the corresponding n-th row line. Therefore, the driving transistor DT may be in a diode connection state.

[0091] The fourth transistor T4 may have a gate electrode connected to the gate line of the previous (n-1)th row line, a source electrode receiving the initialization voltage Vini, and a drain electrode connected to the second node N2.

[0092] The fourth transistor T4 may be turned on to correspond to the gate signal Vg[n-1] of the (n-1)th row line. Therefore, the second node N2 (ie, the gate electrode of the driving transistor DT) may be initialized using the initialization voltage Vini.

[0093] The fifth transistor T5 may have a gate electrode connected to the emission line of the corresponding nth row line, a source electrode connected to the third node N3, and a drain electrode connected to the light emitting diode OD and the drain electrode of the sixth transistor T6 (ie, the fourth node N4).

[0094] The fifth transistor T5 may be turned on to correspond to the emission signal Vem[n] of the corresponding n-th row line. Therefore, the fifth transistor T5 applies the emission driving current generated by the driving transistor DT to the light emitting diode OD, so that the light emitting diode OD may emit light.

[0095] The sixth transistor T6 may have a gate electrode connected to the gate line of the corresponding n-th row line, a source electrode receiving the initialization voltage Vini, and a drain electrode connected to the fourth node N4.

[0096] The sixth transistor T6 may be turned on to correspond to the gate signal Vg[n] of the corresponding n-th row line. Therefore, the fourth node N4 (ie, the light emitting diode OD) may be initialized using the initialization voltage Vini.

[0097] The storage capacitor Cst may include a first electrode connected to the second node N2 and a second electrode connected to the common control node Nc. The common control node Nc may be connected to a voltage output terminal of the common control circuit block C.

[0098] The common control circuit block C may be commonly connected to a common control node Nc of the sub-pixels SP1, SP2, and SP3 of the pixel P. The sub-pixels SP1, SP2, and SP3 of the pixel P may be controlled by commonly receiving a voltage output from an output terminal of the common control circuit block C.

[0099] The common control circuit block C may include a plurality of switch transistors. For example, the common control circuit block C may include a first common control transistor Tc1, a second common control transistor Tc2, and a third common control transistor Tc3.

[0100] Here, the first common control transistor Tc1, the second common control transistor Tc2 and the third common control transistor Tc3 are P-type transistors. As another example, the transistors Tc1, Tc2 and Tc3 of the common control circuit block C may be N-type transistors.

[0101] The first common control transistor Tc1 and the second common control transistor Tc2 may be connected in parallel. Therefore, the first common control transistor Tc1 may have a gate electrode connected to the gate line of the previous (n-1)th row line, a source electrode receiving a reference voltage Vref, and a drain electrode connected to the output terminal of the common control circuit block C (i.e., the common control node Nc of the sub-pixels SP1, SP2, and SP3).

[0102] The second common control transistor Tc2 may have a gate electrode connected to the gate line of the corresponding nth row line, a source electrode receiving a reference voltage Vref, and a drain electrode connected to the output end of the common control circuit block C (ie, the common control node Nc of the sub-pixels SP1, SP2, and SP3).

[0103] At this time, the first common control transistor Tc1 may be turned on according to the gate signal Vg[n-1] of the (n-1)th row line. Therefore, the first common control transistor Tc1 may output the reference voltage Vref.

[0104] The second common control transistor Tc2 may be turned on according to the gate signal Vg[n] of the n-th row line. Therefore, the second common control transistor Tc2 may output the reference voltage Vref.

[0105] As such, during the horizontal period of the previous row line and the horizontal period of the current row line, the common control circuit block C may operate to output the reference voltage Vref.

[0106] The third common control transistor Tc3 may have a gate electrode connected to the emission line of the corresponding nth row line, a source electrode receiving a high potential driving voltage VDD, and a drain electrode connected to the output end of the common control circuit block C (i.e., the common control node Nc of sub-pixels SP1, SP2, SP3).

[0107] In this case, the third common control transistor Tc3 may be turned on according to the emission signal Vem[n] of the n-th row line. Therefore, the common control transistor Tc3 may output the high potential driving voltage VDD.

[0108] According to the embodiments of the present disclosure Figure 1 The modified display device 10 can compensate for the deviation of the threshold voltage Vth of the driving transistor DT, and can also compensate for the deviation of the high potential driving voltage VDD.

[0109] Can be based on Figure 1 The line transmitting the high potential driving voltage VDD in the display panel 100 is used to drop the voltage, and there may be a deviation of the high potential driving voltage VDD depending on the position.

[0110] In the embodiment of the present disclosure, by commonly controlling the voltage charged to the storage capacitor Cst using the common control circuit block C, it is possible to remove the component of the high potential driving voltage VDD when generating the emission driving current.

[0111] Therefore, emission deviation due to deviation of the high potential driving voltage VDD can be prevented, and thus display quality can be ensured.

[0112] In addition, in order to compensate for the deviation of the high potential driving voltage VDD, a common control circuit block C is provided on a pixel P basis, thereby performing common control, and thus the number of control circuits can be reduced compared to the case where a control circuit is provided based on sub-pixels SP1, SP2 and SP3.

[0113] Furthermore, the threshold voltage Vth can be directly detected from the data signal Vda, and an electrical short circuit between the high potential driving voltage VDD and the reference voltage Vref can be prevented during the driving process. Therefore, the detection performance of the threshold voltage Vth can be improved.

[0114] Here, reference Figure 3 In the pixel array group PAG of each pixel array area PA, a plurality of pixels P arranged along a row line direction are provided, and a common control circuit block C is arranged between adjacent pixels P, so that the common control circuit block C can be commonly connected to all pixels P arranged on both sides thereof, that is, all first sub-pixels SP1, second sub-pixels SP2 and third sub-pixels SP3 of each of the two pixels P.

[0115] In addition, the driving circuits GC and EC of the circuit area SA may be formed between adjacent pixel array groups PAG.

[0116] In the arrangement of each row line, the pixel array groups PAG of the pixel array area PA and the driving circuits GC and EC of the circuit area SA may be arranged alternately. In each pixel array group PAG of the pixel array area PA, two pixels P may be arranged adjacent to each other with a common control circuit block C between them.

[0117] Therefore, similar to the common control circuit block C, the circuit area SA may be disposed between two adjacent pixels P. Therefore, similar to the common control circuit block C, the driving circuits GC and EC of the circuit area SA may be disposed between two adjacent pixels P.

[0118] Here, the common control circuit block C may be formed to have substantially the same width as the circuit area SA.

[0119] According to an embodiment of the present disclosure, an area that can be allocated as an area for a common control circuit block C can be used as the circuit area SA, thereby eliminating the need to allocate a common control circuit block C in the display area AA. Figure 1 The scan driving circuit 500 provides an additional area.

[0120] A transmission line TL for transmitting a signal may be disposed between adjacent circuit areas SA. When the driving circuits GC and EC are provided in adjacent circuit areas SA, respectively, or are not additionally provided, a signal may be transmitted through the transmission line TL disposed between adjacent circuit areas SA.

[0121] Here, considering the number of thin film transistors and the voltage charged to the storage capacitor Cst in the pixel array group PAG, the pixel array area PA and the circuit area SA may be determined as a minimum unit, which is referred to as a pixel block PB.

[0122] refer to Figure 3 , four pixel array areas PA and four circuit areas SA can form a minimum unit of a pixel block PB. For example, in a display device according to an embodiment of the present disclosure, a pixel array group PAG of four pixel array areas PA and driving circuits GC and EC of four circuit areas SA form a pixel block PB.

[0123] However, the present disclosure is not limited thereto, and the number of pixel array groups PAG and the number of signal generating circuits GC and EC may vary according to the characteristics of the display device.

[0124] At the same time, as described above, according to the embodiments of the present disclosure Figure 1 The display device 10 may have different lengths along the row line direction. Therefore, the number of pixel array areas PA and circuit areas SA arranged in each row line may be different according to the position.

[0125] According to the position of the row line, there may be a virtual area DA where the pixel array group PAG of the pixel array area PA and the driving circuits GC and EC of the circuit area SA do not form a pixel block PB. In the virtual area DA where the pixel block PB is not formed, the driving circuits GC and EC cannot work normally, so the driving circuits GC and EC are not needed.

[0126] Looking more closely, Figure 4 As shown, the pixel array areas PA and the circuit areas SA may be alternately arranged in each row of the display area AA. The circuit area SA may be disposed between adjacent pixel array areas PA.

[0127] The driving circuit GC and EC including the gate signal generating circuit GC and the emission signal generating circuit EC are arranged in the circuit area SA between the pixel array areas PA. At this time, the first, second, third and fourth pixel array areas PA and the first, second, third and fourth circuit areas SA form a pixel block PB. Each of the first, second, third and fourth circuit areas SA can be arranged between adjacent pixel array areas PA.

[0128] refer to Figure 4 , the first, second, third and fourth pixel array groups PAG and the first, second, third and fourth driving circuits GC and EC form a pixel block PB. The first, second, third and fourth pixel array groups PAG and the first, second, third and fourth driving circuits GC and EC are alternated with each other. The first, second and third driving circuits GC and EC are respectively arranged between the first, second, third and fourth pixel array groups PAG of the pixel block PB, and the fourth driving circuits GC and EC are arranged between the pixel array groups PAG of adjacent pixel blocks PB.

[0129] In the embodiments according to the present disclosure Figure 1 In the modified display device 10, since the display area AA is configured in a free form, the dummy area DA in which the pixel block PB is not formed is formed based on the row line.

[0130] The virtual area DA may include a virtual pixel array area DPA. In addition, a plurality of virtual pixel array groups DPAG may be arranged along a row line direction in the virtual pixel array area DPA. Figure 4 In the embodiment, a virtual pixel array group DPAG is arranged along a row line direction in the virtual pixel array area DPA, but the present invention is not limited thereto.

[0131] The virtual pixel array group DPAG may include a plurality of virtual pixels DP arranged along a row line direction. A virtual common control circuit block DCC may be disposed between adjacent virtual pixels DP. In addition, the virtual pixels DP may be disposed on both sides of the virtual common control circuit block DCC.

[0132] The virtual pixel DP may include a plurality of virtual sub-pixels (not shown) arranged in a matrix and emitting light of different colors. For example, each virtual pixel DP may include a red virtual sub-pixel, a green virtual sub-pixel, and a blue virtual sub-pixel arranged adjacent to each other along each row line direction.

[0133] The virtual common control circuit block DCC commonly controls virtual sub-pixels of virtual pixels DP adjacent thereto.

[0134] At this time, the virtual pixel array group DPAG receives signals from the gate signal generating circuit GC and the light emission signal generating circuit EC of the pixel block PB adjacent thereto.

[0135] Therefore, an additional gate signal generating circuit GC and an additional emission signal generating circuit EC may not be provided on one side of the dummy pixel array group DPAG. This means that no other driving circuit for applying a scan signal to the dummy pixel array group DPAG is required in the dummy area DA.

[0136] Since other driving circuits for applying scan signals to the dummy pixel array group DPAG are not provided in the dummy area DA, a circuit area for other driving circuits is not required in the dummy area DA. However, the present disclosure is not limited thereto.

[0137] For example, according to the embodiments of the present disclosure Figure 1 The modified display device 10 is characterized in that a dummy circuit area DSA is further provided in the dummy area DA.

[0138] According to the embodiments of the present disclosure Figure 1 The modified display device 10 may further include: a dummy circuit DC of the dummy circuit area DSA arranged at one side of the dummy pixel array group DPAG in the dummy area DA.

[0139] Therefore, in the embodiment according to the present disclosure Figure 1 In the modified display device 10, even in the dummy area DA, the regularity of the alternating arrangement of the dummy pixel array groups DPAG of the dummy pixel array area DPA and the dummy circuits DC of the dummy circuit area DSA for driving them can be maintained.

[0140] Therefore, it is possible to prevent the display quality from being degraded due to the virtual area DA.

[0141] Specifically, according to the deformed shape of the display device, in the virtual area DA where the pixel block PB (four pixel array groups PAG and four driving circuits GC and EC) that does not form the minimum unit is not formed, only the virtual pixel array group DPAG can be arranged without a circuit area SA in which a signal generating circuit for the virtual pixel array group DPAG for driving the virtual pixel array area DPA is set.

[0142] However, in this case, since the regularity of the alternating arrangement of the pixel array group PAG and the driving circuits GC and EC in the display area AA is destroyed, one side or both sides of the virtual pixel array group DPAG of the virtual pixel array area DPA in the virtual area DA (where the driving circuits GC and EC should be set) in the display area AA may be identified as stains.

[0143] On the other hand, according to an embodiment of the present disclosure Figure 1 The modified display device 10 may further include a virtual circuit area DSA on one side of the virtual pixel array area DPA in the virtual area DA. For example, the virtual circuit DC of the virtual circuit area DSA may be further arranged on one side of the virtual pixel array group DPAG of the virtual pixel array area DPA in the virtual area DA.

[0144] Therefore, even in the dummy area DA of the display area AA, the dummy pixel array area DPA and the dummy circuit area DSA may be alternately arranged because the pixel array area PA and the circuit area SA are alternately arranged.

[0145] like Figure 4 As shown in , the pixel array groups PAG of the pixel array area PA and the driving circuits (gate signal generating circuits GC and emission signal generating circuits EC) of the circuit area SA can be arranged alternately. In addition, in the virtual area DA, the virtual pixel array groups DPAG of the virtual pixel array area DPA and the virtual circuits DC of the virtual circuit area DSA can be arranged alternately.

[0146] Therefore, even in the dummy area DA, although four dummy pixel array groups DPAG and four dummy pixels DC are not provided like the pixel block PB, the dummy pixel array groups DPAG and the dummy circuits DC are alternately arranged so that the regularity of the arrangement can be maintained.

[0147] refer to Figure 5 , according to the embodiments of the present disclosure Figure 1 The modified display device 10 may have a regularity in which the pixel array groups PAG and the driving circuits GC and EC are alternately arranged, and also have a regularity in which the dummy pixel array groups DPAG and the dummy circuits DC are alternately arranged in the dummy area DA.

[0148] A plurality of pixels P arranged along a row line direction are provided in each pixel array group PAG, and a common control circuit block C is disposed between adjacent pixels P, so that the pixels P are disposed on both sides of the common control circuit block C, respectively.

[0149] The driving circuits GC and EC of the circuit area SA are disposed between adjacent pixel array groups PAG, so that there is a regularity in which the pixel array groups PAG and the driving circuits GC and EC are alternately arranged.

[0150] In addition, even in the dummy area DA which does not form the pixel block PB which is the minimum unit for driving the display device, the dummy pixel array groups DPAG and the dummy circuits DC (dummy driving circuits) are alternately arranged so that regularity can be maintained.

[0151] The dummy pixel array group DPAG may include a plurality of dummy pixels DP arranged along a row line direction, and the dummy common control circuit block DCC may be disposed between adjacent dummy pixels DP. In addition, the dummy pixels DP are respectively disposed on both sides of the dummy common control circuit block DCC.

[0152] Therefore, in the display device according to the embodiment of the present disclosure, the virtual pixel array group DPAG and the virtual circuit DC can be alternately arranged in the virtual area DA of the display area AA, so that the regularity of the alternating arrangement of the pixel array group PAG and the driving circuits GC and EC can be maintained. Therefore, since stains can be prevented from being recognized on one or both sides of the virtual pixel array group DPAG in the virtual area DA of the display area AA, the display quality can be prevented from being reduced due to the virtual area DA.

[0153] Figure 6 is a schematic diagram of a signal line formed along a circuit area provided with a driving circuit and a dummy circuit area provided with a dummy circuit according to an embodiment of the present disclosure, and Figure 7 It is shown Figure 6 Schematic diagram of a conceptual configuration of a gate signal generating circuit in a driving circuit.

[0154] Fig. 8A is a schematic diagram of a thin film transistor in a circuit region, and Figure 8B is a schematic diagram of a thin film transistor in a virtual circuit area.

[0155] Fig. 9 is a schematic diagram of a circuit area provided with a driving circuit and a dummy circuit area provided with a dummy circuit according to another embodiment of the present disclosure.

[0156] like Figure 6 As shown in the figure, a clock signal line CL for transmitting gate clock signals GCLK and GCLKb and a first power line, that is, a first voltage line PL1 for transmitting logic voltages VGL and VGH, can be formed in the circuit area SA arranged in the display area AA along the column line direction extending from the circuit area SA.

[0157] The clock signal lines CL for transmitting the first gate clock signal GCLK and the second gate clock signal GCLKb, respectively, may be disposed in different circuit areas SA. For example, the clock signal line CL for transmitting the first gate clock signal GCLK may be disposed in the circuit area SA in which the first circuit portion Dg1 of the stage STGg is formed, and the clock signal line CL for transmitting the second gate clock signal GCLKb may be disposed in the circuit area SA in which the second circuit portion Dg2 of the stage STGg is formed.

[0158] The first voltage line PL1 for transmitting the first logic voltage VGL and the second logic voltage VGH, respectively, may be disposed in different circuit areas SA. For example, the first voltage line PL1 for transmitting the first logic voltage VGL may be disposed in the circuit area SA in which the first circuit portion Dg1 of the stage STGg is formed, and the first voltage line PL1 for transmitting the second logic voltage VGH may be disposed in the circuit area SA in which the second circuit portion Dg2 of the stage STGg is formed.

[0159] The gate signal generating circuit GC may include a plurality of stages STGg independently connected to each other to sequentially generate gate signals Vg corresponding to a plurality of row lines. In addition, each stage STGg may include a plurality of transistors and at least one capacitor, and output a gate signal Vg as a scan signal.

[0160] That is, each stage STGg may include a Q transistor and a Qb transistor, and a control circuit for controlling the switching operation of the Q transistor and the Qb transistor, wherein the Q transistor and the Qb transistor are connected in series with an output node (or output end), and the output node (or output end) is connected to a corresponding gate line GL inserted therebetween.

[0161] The Q transistor can output a gate signal Vg of a conduction level to the gate line GL, and the Qb transistor can output a gate signal Vg of a cutoff level to the gate line GL. For example, when the switching transistor of the sub-pixel connected to the gate line GL is a P-type, the Q transistor can output a low-level gate signal, and the Qb transistor can output a high-level gate signal.

[0162] In addition, each stage STGg may receive an output of a gate signal Vg of a previous stage STGg and use it as a start signal. Here, the stage STGg[1] of the first row line may receive a separate start signal GVST.

[0163] In addition, the stage STGg can receive a first gate clock signal GCLK and a second gate clock signal GCLKb of different phases as clock signals, and first and second logic voltages, which are logic voltages of opposite phases).

[0164] During the horizontal period of the corresponding row line, the stage STGg can output the corresponding gate clock signal as the gate signal Vg through the Q transistor. For example, the first stage STGg[1] can output the first gate clock signal GCLK as the gate signal Vg[1] through the corresponding Q transistor, and the second stage STGg[2] can output the second gate clock signal GCLKb as the gate signal Vg[2] through the corresponding Q transistor.

[0165] In addition, the stage STGg can output the first logic voltage VGL or the second logic voltage VGH as a voltage of the cut-off level through the Qb transistor as the gate signal Vg after the horizontal period. For example, when the switching transistor of the sub-pixel connected to the gate line GL is a P-type, the second logic voltage VGH (which is a high logic voltage) can be output as the gate signal Vg.

[0166] In this case, a dummy circuit DC including a plurality of stages may be provided in a dummy circuit area DSA located in the dummy area DA. The dummy circuit DC provided in the dummy circuit area has the same configuration as the gate signal generating circuit GC provided in the circuit area SA, but substantially no signal is applied thereto and / or output therefrom.

[0167] The dummy circuit DC set in the dummy circuit area DSA does not apply a signal to the dummy pixel DP of the dummy pixel array group DPAG in the dummy area DA, so that the signal line can be configured separately, or the signal line may not be connected to the stage so that no signal is applied and / or output.

[0168] The gate signal generating circuit GC disposed in the circuit area SA may include a circuit connected to the gate line Figure 2 Multiple levels of STGg, and Figure 2 Each stage STGg may include a plurality of thin film transistors.

[0169] like Fig. 8A As shown in FIG. 1 , the thin film transistor provided in the circuit area SA may include a buffer layer 303 deposited on a substrate 301, an oxide semiconductor (active layer) 305 deposited on the buffer layer 303, a gate insulating layer 307 deposited on the oxide semiconductor 305, and a gate electrode 309 deposited on the gate insulating layer 307. In addition, an insulating layer 311 may be formed on the gate electrode 309 to cover the oxide semiconductor 305, the gate insulating layer 307, and the gate electrode 309.

[0170] A first contact hole 315 may be provided in the insulating layer 311. A source electrode 317a and a drain electrode 317b disposed on the insulating layer 311 may be electrically connected to the oxide semiconductor 305 through the first contact hole 315.

[0171] A passivation layer 313 may be disposed on the source electrode 317 a and the drain electrode 317 b , and a metal layer 319 disposed on the passivation layer 313 may be electrically connected to the drain electrode 317 b through a second contact hole 316 provided in the passivation layer 313 .

[0172] Metal layer 319 can be electrically connected to various types of power supplies. Alternatively, metal layer 319 can be electrically connected to Figure 2 An output terminal to which the scan signal is outputted by the stage STGg.

[0173] like Figure 8B As shown in the figure, the thin film transistor of the virtual circuit DC set in the virtual circuit area DSA may include a buffer layer 303, an oxide semiconductor 305, a gate insulating layer 307, a gate electrode 309, an insulating layer 311, a source electrode 317a and a drain electrode 317b, a passivation layer 313, and a metal layer 319, similar to the thin film transistor of the gate signal generating circuit GC.

[0174] However, unlike the insulating layer 311 provided in the thin film transistor of the gate signal generating circuit GC, the insulating layer 311 provided in the thin film transistor of the dummy circuit DC is different in that the first contact hole 315 is not provided therein.

[0175] Therefore, the source electrode 317a and the drain electrode 317b of the thin film transistor set in the dummy circuit DC are not electrically connected to the oxide semiconductor 305, so that substantially no signal is applied to the dummy circuit DC set in the dummy circuit area DSA, and / or substantially no signal is output from the dummy circuit DC.

[0176] Here, although it has been described as an example that the insulating layer 311 does not include the first contact hole 315 exposing the oxide semiconductor 305 , the second contact hole 316 provided in the passivation layer 313 and exposing the drain electrode 317 b may be omitted.

[0177] As such, the dummy circuit DC of the dummy circuit area DSA may be disposed on one side or both sides of the dummy pixel array group DPAG disposed in the dummy pixel array region DPA of the dummy area DA.

[0178] The dummy circuit DC of the dummy circuit area DSA has the same configuration as the gate signal generating circuit GC provided in the circuit area SA, but no signal is applied thereto and / or output therefrom.

[0179] In the embodiments according to the present disclosure Figure 1In the modified display device 10, even in the virtual area DA, the virtual pixel array group DPAG and the virtual circuit DC can be alternately arranged. Therefore, even in the virtual area DA of the display area AA, the regularity of the alternating arrangement of the pixel array group PAG and the driving circuits GC and EC can be maintained using the virtual pixel array group DPAG and the virtual circuit DC, thereby preventing the display quality from being reduced due to the virtual area DA.

[0180] In addition, although not shown in the drawings, Figure 4 The emission signal generating circuit EC may also be disposed in the circuit area SA, and a clock signal line CL transmitting an emission clock signal (not shown) may be disposed along a column line direction extending in the circuit area SA.

[0181] At this time, the virtual circuit DC has the same Figure 4 The virtual circuit DC may be arranged in a virtual circuit area DSA located in the virtual area DA, but without applying a signal to and / or outputting a signal from the transmission signal generating circuit EC of the same configuration as the transmission signal generating circuit EC of the virtual circuit DC. That is, a signal cannot be applied to the clock signal line CL arranged in the virtual circuit DC.

[0182] Here, if Fig. 9 As shown in , an auxiliary common control circuit block AC may be further provided in a virtual circuit area DSA located in the virtual area DA. The auxiliary common control circuit block AC may have the same configuration as the virtual common control circuit block DCC provided in the virtual pixel array group DPAG, but may not substantially have signals applied thereto and / or output therefrom.

[0183] That is, the auxiliary common control circuit block AC disposed in the dummy circuit area DSA does not output and apply the control signal for controlling the dummy pixels DP of the dummy pixel array group DPAG disposed in the dummy area DA. Figure 2 The signal of the storage capacitor Cst.

[0184] To this end, the auxiliary common control circuit block AC may be configured such that Figure 2 The common control node Nc may not be connected to the virtual sub-pixel of the virtual pixel DP. Figure 2 The drain electrodes of the first common control transistor Tc1, the second common control transistor Tc2 and the third common control transistor Tc3.

[0185] Thereby, even in the dummy area DA, the regularity that the dummy pixel array groups DPAG and the auxiliary common control circuit blocks AC are alternately arranged can be maintained.

[0186] Fig.10is a schematic diagram of a signal line formed along a circuit region provided with a driving circuit and a dummy circuit region provided with a dummy circuit according to another embodiment of the present disclosure.

[0187] like Fig.10 As shown in FIG. 1 , a clock signal line CL for transmitting gate clock signals GCLK and GCLKb and a first voltage line PL1 for transmitting logic voltages VGL and VGH may be formed in the circuit area SA disposed in the display area AA along a column line direction extending from the circuit area SA.

[0188] The clock signal lines CL for transmitting the first gate clock signal GCLK and the second gate clock signal GCLKb, respectively, may be arranged in different circuit areas SA. For example, the clock signal line CL for transmitting the first gate clock signal GCLK may be arranged in the circuit area SA in which the first circuit portion Dg1 of the stage STGg is formed, and the clock signal line CL for transmitting the second gate clock signal GCLKb may be arranged in the circuit area SA in which the second circuit portion Dg2 of the stage STGg is formed.

[0189] Similarly, the first voltage line PL1 for transmitting the first logic voltage VGL and the second logic voltage VGH, respectively, may be disposed in different circuit areas SA. For example, the first voltage line PL1 for transmitting the first logic voltage VGL may be disposed in the circuit area SA in which the first circuit portion Dg1 of the stage STGg is formed, and the first voltage line PL1 for transmitting the second logic voltage VGH may be disposed in the circuit area SA in which the second circuit portion Dg2 of the stage STGg is formed.

[0190] In addition, second power lines (ie, the second-first voltage line PL2 - 1 and the second-second voltage line PL2 - 2 ) for transmitting the low potential driving voltage VSS are disposed in the dummy circuit area DSA located in the dummy area DA.

[0191] At this time, the low potential driving voltage VSS is supplied to the first circuit portion Dg1 through the second-first voltage line PL2-1, and the low potential driving voltage VSS is supplied to the second circuit portion Dg2 through the second-second voltage line PL2-2.

[0192] In this way, by setting the second-first voltage line PL2-1 and the second-second voltage line PL2-2 for transmitting the low-potential driving voltage VSS in the virtual circuit area DSA located in the virtual area DA, the regularity of the alternating arrangement of the pixel array group PAG and the driving circuit can be maintained even in the virtual area DA, thereby preventing the display quality from being reduced due to the virtual area DA.

[0193] In addition, there is no need to form a wide power line in the non-display area NA to form the second-first voltage line PL2-1 and the second-second voltage line PL2-2 outside the display area AA, and the second-first voltage line PL2-1 and the second-second voltage line PL2-2 formed in the display area AA can replace the wide power line of the non-display area NA.

[0194] Therefore, the width of the non-display area NA can be reduced, thereby effectively realizing a narrow frame. In addition, even if the display device has a large area, a narrow frame can be effectively realized while equalizing the low potential driving voltage VSS in the display area AA.

[0195] As described above, in the deformed display device according to the embodiment of the present disclosure, in the virtual area DA where the pixel block PB is not formed, the virtual pixel array group DPAG of the virtual pixel array area DPA and the virtual circuit DC of the virtual circuit area DSA are provided, so that the regularity of the alternating arrangement of the pixel array group PAG and the driving circuits GC and EC for driving them can be maintained even in the virtual area DA.

[0196] Therefore, it is possible to prevent the display quality from being reduced, which may occur when the regularity of the alternating arrangement of the pixel array group PAG and the driving circuits GC and EC for driving them is disrupted and one or both sides of the dummy pixel DP in the virtual area DA or the virtual pixel array group DPAG are identified as stains.

[0197] In addition, although the virtual pixel array group DPAG and the virtual circuit DC of the virtual circuit area DSA are alternately arranged so that regularity is maintained even in the virtual area, the second-first voltage line PL2-1 and the second-second voltage line PL2-2 transmitting the low potential driving voltage VSS are arranged in the virtual circuit area DSA, so there is no need to form a separate power line outside the display area AA. Therefore, the display device according to the embodiment of the present disclosure can achieve a narrow frame.

[0198] In the modified display device according to the present disclosure, a dummy circuit area is further provided in a dummy area where no pixel block is formed, so that the regularity of the alternating arrangement of pixel array groups and driving circuits for driving them can be maintained even in the dummy area.

[0199] Therefore, it is possible to prevent the display quality from being degraded in the virtual area.

[0200] In addition, the second-first voltage line and the second-second voltage line for transmitting the low potential driving voltage are arranged in the virtual circuit area, so that it is not necessary to form a separate power line outside the display area, and the regularity of the alternating arrangement of the pixel array group and the driving circuit is maintained even in the virtual area. Therefore, the low potential driving voltage can be balanced and a narrow frame can also be achieved.

[0201] Those skilled in the art will appreciate that various modifications and changes may be made to the display device of the present disclosure without departing from the technical concept or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and changes of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A deformable display device, comprising: a display area, the display area comprising a plurality of pixel array areas in which a plurality of pixel array groups are arranged and a plurality of circuit areas in which a plurality of driving circuits are arranged, wherein the pixel array groups and the driving circuits form a pixel block; and a virtual area disposed on one side of the display area, the virtual area including a plurality of virtual pixel array areas in which a plurality of virtual pixel array groups are arranged and a plurality of virtual circuit areas in which a plurality of virtual circuits are arranged, wherein the virtual pixel array groups and the virtual circuits do not form the pixel blocks, Each pixel array group includes a plurality of pixels and at least one common control circuit block arranged between adjacent pixels. Each pixel includes multiple sub-pixels that emit light of different colors. The common control circuit block controls the sub-pixels of the pixels adjacent to it in common. Each virtual pixel array group includes a plurality of virtual pixels and at least one virtual common control circuit block arranged between adjacent virtual pixels. Each virtual pixel includes a plurality of virtual sub-pixels emitting light of different colors, and The virtual common control circuit block collectively controls the virtual sub-pixels of the virtual pixel.

2. A deformable display device, comprising: a display area including a plurality of pixel array areas in which a plurality of pixel array groups are arranged and a plurality of circuit areas in which a plurality of driving circuits are arranged, wherein a first number of pixel array groups and the first number of driving circuits form a pixel block; and a virtual area disposed at one side of the display area, the virtual area comprising a plurality of virtual pixel array areas in which a plurality of virtual pixel array groups are disposed and a plurality of virtual circuit areas in which a plurality of virtual circuits are disposed, wherein a second number of the virtual pixel array groups and the second number of the virtual circuits are disposed at one end of a row of the display area, the second number being less than the first number, Each pixel array group includes a plurality of pixels and at least one common control circuit block arranged between adjacent pixels. Each pixel includes multiple sub-pixels that emit light of different colors. The common control circuit block controls the sub-pixels of the pixels adjacent to it in common. Each virtual pixel array group includes a plurality of virtual pixels and at least one virtual common control circuit block arranged between adjacent virtual pixels. Each virtual pixel includes a plurality of virtual sub-pixels emitting light of different colors, and The virtual common control circuit block collectively controls the virtual sub-pixels of the virtual pixel.

3. The deformed display device according to claim 1 or 2, wherein: The pixel array area is arranged along each row line of the display panel, and the dummy pixel array area is arranged along each row line of the display panel.

4. The deformed display device according to claim 3, wherein: The virtual pixel array group receives a signal from the circuit area disposed in the pixel block through a transmission line.

5. The deformed display device according to claim 1 or 2, wherein: Each of the driving circuit and the dummy circuit includes a first power supply line and a clock signal line transmitting a clock signal, and Wherein, no signal is applied to the clock signal line in the virtual circuit.

6. The deformed display device according to claim 1 or 2, wherein: Each of the driving circuit and the dummy circuit includes a first power supply line and a clock signal line transmitting a clock signal, and Wherein, the virtual circuit includes multiple levels.

7. The deformed display device according to claim 6, wherein: The dummy circuit has the same configuration as a gate signal generating circuit of the driving circuit.

8. The deformed display device according to claim 1 or 2, wherein: The driving circuit includes a first power line and a clock signal line for transmitting a clock signal. Wherein, the virtual circuit includes a second power line, and The first power line transmits a low logic voltage or a high logic voltage provided to the driving circuit, and the second power line transmits a low potential driving voltage provided to the cathode electrode of the light emitting diode in the display area.

9. The deformed display device according to claim 3, wherein: The common control circuit block has the same width as the circuit area.

10. The deformed display device according to claim 1 or 2, wherein: Transmission lines for transmitting signals are provided between adjacent circuit areas.

11. The deformed display device according to claim 3, wherein: The common control circuit block of the nth row line comprises: a first common control transistor connected to the gate line of the (n-1)th row line, receiving a reference voltage, and connected to an output terminal of the common control circuit block; a second common control transistor connected to the gate line of the nth row line, receiving the reference voltage, and connected to the output terminal of the common control circuit block; and A third common control transistor is connected to the emission line of the nth row line, receives a high potential driving voltage, and is connected to the output end of the common control circuit block, wherein n is a natural number.

12. The deformed display device according to claim 1 or 2, wherein: A non-display area is provided at the edge of the display area, and Wherein, at least a portion of a boundary between the display area and the non-display area has one of a circular shape, an elliptical shape, a curved shape, and an oblique shape.

13. The deformed display device according to claim 1 or 2, wherein: The pixel block is a minimum unit for driving pixels and / or driving circuits.

14. The deformed display device according to claim 1 or 2, wherein: The common control circuit block is connected to the storage capacitor of the sub-pixel of the pixel adjacent thereto.

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