Display substrate, manufacturing method thereof and display device

Abstract

A display substrate, a manufacturing method thereof and a display device, in which the display substrate comprises a first sub-pixel (M1) and a second sub-pixel (M2), each of which comprises a power signal line pattern (91), the power signal line pattern (91) comprises a power main body part, the power main body part comprises a first part (911) and a second part (912) which are electrically connected; in the first sub-pixel (M1), the orthogonal projection of the first part (911) on a substrate overlaps the orthogonal projection of a data line main body part of a data line pattern in a sub-pixel adjacent in a first direction on the substrate, and the orthogonal projection of the second part (912) on the substrate does not overlap the orthogonal projection of the data line main body part (9801) of the data line pattern in the sub-pixel adjacent in the first direction on the substrate; in the second sub-pixel (M2), the orthogonal projection of a second data line pattern (982) on the substrate overlaps the orthogonal projection of the first part (911) in the sub-pixel adjacent in the first direction on the substrate, and the orthogonal projection of the second data line pattern (982) on the substrate does not overlap the orthogonal projection of the second part (912) in the sub-pixel adjacent in the first direction on the substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a manufacturing method therefor, and a display device. BACKGROUND

[0002] An AMOLED (Active-matrix Organic Light-Emitting Diode) display device has many advantages such as self-emission, ultra-thin, fast response, high contrast, wide viewing angle, etc., and is a display device that is currently widely concerned. The AMOLED display device includes a plurality of pixel driving circuits and a plurality of light-emitting elements, and the pixel driving circuit is used to drive the corresponding light-emitting element to emit light, thereby realizing the display function of the AMOLED display device.

[0003] The pixel driving circuit includes a low-frequency driving mode and a high-frequency driving mode when driving the light-emitting element to emit light. When the low-frequency driving mode is used to drive the light-emitting element, the data writing time of the pixel controlled by each row of pixel driving circuits is relatively long. When the high-frequency driving mode is used to drive the light-emitting element, the data writing time of each row of pixels is compressed, so that the data writing time of the pixel controlled by each row of pixel driving circuits is relatively short. SUMMARY

[0004] The purpose of the present disclosure is to provide a display substrate and a manufacturing method therefor, and a display device.

[0005] A first aspect of the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arranged in an array on the substrate, the plurality of sub-pixels comprising:

[0006] a first sub-pixel and a second sub-pixel arranged along a second direction, the first sub-pixel comprising a first data line pattern, the second sub-pixel comprising a second data line pattern, at least part of the first data line pattern and at least part of the second data line pattern extending along the second direction, the first data line pattern being located at a first side of a same column of first sub-pixels extending along the second direction, the second data line pattern being located at a second side of a same column of second sub-pixels extending along the second direction, the first side and the second side being opposite along a first direction, the first direction intersecting the second direction;

[0007] the first data line pattern is configured to provide a first data signal to the first sub-pixel, and the second data line pattern is configured to provide a second data signal to the second sub-pixel;

[0008] the first sub-pixel and the second sub-pixel each comprising:

[0009] a power signal line pattern, at least part of the power signal line pattern extends along the second direction, the power signal line pattern comprises a power main body part, the power main body part comprises a first part and a second part which are electrically connected, the second part protrudes the first part along the first direction;

[0010] in the first sub-pixel, the first part has a projection on the base which overlaps a data line main body part of a data line pattern in a sub-pixel adjacent along the first direction, the second part has a projection on the base which does not overlap a data line main body part of a data line pattern in a sub-pixel adjacent along the first direction;

[0011] in the second sub-pixel, the data line main body part of the second data line pattern has a projection on the base which overlaps the first part in a sub-pixel adjacent along the first direction, the data line main body part of the second data line pattern has a projection on the base which does not overlap the second part in a sub-pixel adjacent along the first direction.

[0012] Optionally, the plurality of sub-pixels further comprise:

[0013] a third sub-pixel and a fourth sub-pixel arranged along the second direction, along the first direction, the third sub-pixel is located in the same row as the first sub-pixel, the fourth sub-pixel is located in the same row as the second sub-pixel;

[0014] the third sub-pixel comprises a third data line pattern, the fourth sub-pixel comprises a fourth data line pattern, at least part of the third data line pattern and at least part of the fourth data line pattern both extend along the second direction, the third data line pattern is located on the second side of the same column of third sub-pixels extending along the second direction, the fourth data line pattern is located on the first side of the same column of fourth sub-pixels extending along the second direction;

[0015] the third sub-pixel and the fourth sub-pixel both comprise: the power signal line pattern;

[0016] in the first sub-pixel, the first part has a projection on the base which overlaps a data line main body part of a third data line pattern adjacent along the first direction, the second part has a projection on the base which does not overlap a data line main body part of the third data line pattern.

[0017] Optionally, the power signal line pattern further comprises a power protruding part which is electrically connected to the power main body part;

[0018] In the first sub-pixel, the normal projection of the power supply protruding part on the substrate overlaps with the normal projection of the first data line pattern on the substrate.

[0019] Optionally, the power supply signal line pattern further comprises a power supply protruding part electrically connected with the power supply main body part.

[0020] In the fourth sub-pixel, the normal projection of the power supply protruding part on the substrate overlaps with the normal projection of the fourth data line pattern on the substrate.

[0021] Optionally, the first data line pattern, the second data line pattern, the third data line pattern and the fourth data line pattern each comprise a data line main body part and a data line protruding part, the data line main body part extends along the second direction, and the data line protruding part protrudes from the data line main body part along the first direction.

[0022] The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each comprise a first conductive connection part and a data writing transistor,

[0023] In each sub-pixel, the data line protruding part is electrically connected with the first electrode of the data writing transistor through the first conductive connection part, and the normal projection of the second part on the substrate overlaps with the first conductive connection part arranged along the first direction.

[0024] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each comprise:

[0025] an initialization signal line pattern, a second transistor, a driving transistor and a second conductive connection part;

[0026] At least part of the initialization signal line pattern extends along the second direction, and the initialization signal line pattern is used for transmitting an initialization signal.

[0027] The first electrode of the second transistor is electrically connected with the initialization signal line pattern through the second conductive connection part, and the second electrode of the second transistor is electrically connected with the gate electrode of the driving transistor.

[0028] In the first sub-pixel, the normal projection of the second conductive connection part on the substrate overlaps with the normal projection of the first data line pattern on the substrate.

[0029] In the third sub-pixel, the normal projection of the second conductive connection part on the substrate does not overlap with the normal projection of the third data line pattern on the substrate.

[0030] Optionally, in the second sub-pixel, the second conductive connection portion has a projection on the substrate that does not overlap with a projection of the second data line pattern on the substrate.

[0031] In the fourth sub-pixel, the second conductive connection portion has a projection on the substrate that overlaps with a projection of the fourth data line pattern on the substrate.

[0032] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include:

[0033] a power signal line pattern, at least part of the power signal line pattern extending along the second direction;

[0034] a power compensation pattern, at least part of the power compensation pattern extending along the first direction, the power compensation pattern and the power signal line pattern being located on a surface of an interlayer insulating layer of the display substrate away from the substrate; in each sub-pixel, the power compensation pattern is electrically connected to the power signal line pattern in the sub-pixel and the power signal line pattern in a sub-pixel adjacent to the sub-pixel along the first direction, respectively.

[0035] Optionally, the third sub-pixel includes a power compensation pattern that is electrically connected to a power signal line pattern included in the third sub-pixel and a power signal line pattern in a first sub-pixel adjacent to the third sub-pixel along the first direction, respectively.

[0036] The fourth sub-pixel includes a power compensation pattern that is electrically connected to a power signal line pattern included in the fourth sub-pixel and a power signal line pattern in a second sub-pixel adjacent to the fourth sub-pixel along the first direction, respectively.

[0037] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include: a reset signal line pattern, a gate line pattern and a light-emitting control signal line pattern distributed along the second direction; at least part of the reset signal line pattern extends along the first direction, at least part of the gate line pattern extends along the first direction, and at least part of the light-emitting control signal line pattern extends along the first direction; in the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, the power compensation pattern has a projection on the substrate that is located between a projection of the gate line pattern on the substrate and a projection of the light-emitting control signal line pattern on the substrate.

[0038] Optionally, in the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, at least part of the power supply protruding part extends along the second direction, and a gap is formed between the power supply protruding part and the power supply main part; a first end of the power supply compensation pattern is electrically connected to the power supply protruding part; and a second end of the power supply compensation pattern is electrically connected to the power supply main part in the sub-pixel adjacent to the first sub-pixel along the first direction.

[0039] Optionally, the first sub-pixel comprises a sixth transistor, and a third conductive connection part, a fourth conductive connection part and a light emitting element are arranged in a stack along a direction away from the substrate; the light emitting element comprises a first anode pattern; and a second electrode of the sixth transistor is electrically connected to the first anode pattern through the third conductive connection part and the fourth conductive connection part.

[0040] In at least part of the first sub-pixel,

[0041] The fourth conductive connection part comprises a solid part.

[0042] A projection of the solid part on the substrate at least partially overlaps a projection of the first anode pattern on the substrate.

[0043] The projection of the first anode pattern on the substrate does not overlap a projection of the first data line pattern on the substrate.

[0044] Optionally, the second sub-pixel comprises a sixth transistor, and a third conductive connection part, a fourth conductive connection part and a light emitting element are arranged in a stack along a direction away from the substrate; the light emitting element comprises a second anode pattern; and a second electrode of the sixth transistor is electrically connected to the second anode pattern through the third conductive connection part and the fourth conductive connection part.

[0045] In at least part of the second sub-pixel,

[0046] A projection of the second anode pattern on the substrate overlaps a projection of the second data line pattern on the substrate.

[0047] Optionally, the third sub-pixel comprises a sixth transistor, and a third conductive connection part, a fourth conductive connection part and a light emitting element are arranged in a stack along a direction away from the substrate; the light emitting element comprises a third anode pattern; and a second electrode of the sixth transistor is electrically connected to the third anode pattern through the third conductive connection part and the fourth conductive connection part.

[0048] In part of the third sub-pixel,

[0049] The fourth conductive connection part comprises a solid part and a hollow part.

[0050] a third anode pattern on the substrate overlaps in projection with a third data line pattern on the substrate, and overlaps in projection with a data line pattern adjacent to the third data line pattern in a first direction on the substrate;

[0051] the third anode pattern on the substrate overlaps in projection with the solid portion on the substrate; and / or, the third anode pattern on the substrate overlaps in projection with the hollow portion on the substrate.

[0052] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each comprise: an anode pattern, an initialization signal line pattern, a shielding pattern, a driving transistor, a second transistor and a seventh transistor;

[0053] In the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, a first pole of the second transistor is electrically connected with the initialization signal line pattern, and a second pole of the second transistor is electrically connected with a gate of the driving transistor;

[0054] a first pole of the seventh transistor is electrically connected with an initialization signal line pattern in a next sub-pixel adjacent to the second direction, and a second pole of the seventh transistor is electrically connected with an anode pattern in the sub-pixel to which the seventh transistor belongs;

[0055] the shielding pattern is electrically connected with the power signal line pattern, and a projection of the shielding pattern on the substrate overlaps with a projection of the first pole of the second transistor on the substrate.

[0056] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each comprise: a first conductive connection part and a fifth conductive connection part,

[0057] In the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, a second pole of the second transistor is electrically connected with a gate of the driving transistor through the fifth conductive connection part;

[0058] the first conductive connection part is electrically connected with a first pole of a data writing transistor; and a second pole of the data writing transistor is electrically connected with a first pole of the driving transistor;

[0059] a projection of the shielding pattern on the substrate at least partially overlaps with a projection of the first conductive connection part on the substrate.

[0060] Optionally, a projection of the shielding pattern on the substrate at least partially overlaps with a projection of the first conductive connection on the substrate.

[0061] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each comprise a first transistor;

[0062] In each sub-pixel, a first electrode of the first transistor is electrically connected with a second electrode of the driving transistor, and a second electrode of the first transistor is electrically connected with a gate electrode of the driving transistor;

[0063] The active pattern of the first transistor comprises two semiconductor portions arranged in a spaced manner, and a first conductor portion connecting the two semiconductor portions respectively;

[0064] The projection of the shielding pattern on the substrate at least partially overlaps with a projection of the first conductor portion on the substrate.

[0065] Optionally, in a direction perpendicular to the substrate, the shielding pattern is located between the first electrode of the second transistor and the first conductive connection.

[0066] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each comprise a light emitting element, an initialization signal line pattern, a reset signal line pattern, a gate line pattern and a light emitting control signal line pattern; at least part of the initialization signal line pattern, at least part of the reset signal line pattern, at least part of the gate line pattern and at least part of the light emitting control signal line pattern each extend along the first direction;

[0067] The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each further comprise a first transistor, a second transistor, a driving transistor, a data writing transistor, a fifth transistor, a sixth transistor, a seventh transistor and a storage capacitor;

[0068] In each sub-pixel, a gate electrode of the driving transistor is electrically connected with a second electrode of the first transistor, a first electrode of the driving transistor is electrically connected with a second electrode of the fifth transistor, and a second electrode of the driving transistor is electrically connected with a first electrode of the first transistor;

[0069] A gate electrode of the first transistor is electrically connected with the gate line pattern;

[0070] A gate electrode of the second transistor is electrically connected with the reset signal line pattern, a first electrode of the second transistor is electrically connected with the initialization signal line pattern, and a second electrode of the second transistor is electrically connected with a gate electrode of the driving transistor;

[0071] a gate of the data write transistor is electrically connected with the gate line pattern, a first electrode of the data write transistor is electrically connected with the data line pattern in the sub-pixel, and a second electrode of the data write transistor is electrically connected with the first electrode of the drive transistor;

[0072] a gate of the fifth transistor is electrically connected with the light-emitting control signal line pattern, and a first electrode of the fifth transistor is electrically connected with the power signal line pattern;

[0073] a gate of the sixth transistor is electrically connected with the light-emitting control signal line pattern, a first electrode of the sixth transistor is electrically connected with the second electrode of the drive transistor, and a second electrode of the sixth transistor is electrically connected with the light-emitting element;

[0074] a gate of the seventh transistor is electrically connected with the reset signal line pattern in a next sub-pixel adjacent to the sub-pixel along the second direction, a first electrode of the seventh transistor is electrically connected with the initialization signal line pattern in the next sub-pixel adjacent to the sub-pixel along the second direction, and a second electrode of the seventh transistor is electrically connected with the light-emitting element;

[0075] a first plate of the storage capacitor is multiplexed as the gate of the drive transistor, and a second plate of the storage capacitor is electrically connected with the power signal line pattern.

[0076] Based on the technical solution of the display substrate, a second aspect of the present disclosure provides a display device including the display substrate.

[0077] Based on the technical solution of the display substrate, a third aspect of the present disclosure provides a manufacturing method of a display substrate, including: manufacturing a plurality of sub-pixels in an array distribution on a substrate; the plurality of sub-pixels includes:

[0078] a first sub-pixel and a second sub-pixel arranged along a second direction, the first sub-pixel including a first data line pattern, and the second sub-pixel including a second data line pattern, at least part of the first data line pattern and at least part of the second data line pattern extending along the second direction, the first data line pattern being located on a first side of a same column of sub-pixels extending along the second direction, the second data line pattern being located on a second side of the same column of sub-pixels extending along the second direction, the first side being opposite to the second side along a first direction, and the first direction intersecting the second direction;

[0079] the first data line pattern is configured to provide a first data signal to the first sub-pixel, and the second data line pattern is configured to provide a second data signal to the second sub-pixel;

[0080] the first sub-pixel and the second sub-pixel each include:

[0081] A power signal line pattern, at least a portion of which extends along the second direction, the power signal line pattern including a power body portion, the power body portion including a first portion and a second portion electrically connected, the second portion protruding from the first portion along the first direction;

[0082] In the first sub-pixel, the orthographic projection of the first portion on the substrate overlaps with the orthographic projection of the main body of the data line pattern in the adjacent sub-pixel along the first direction on the substrate, and the orthographic projection of the second portion on the substrate does not overlap with the orthographic projection of the main body of the data line pattern in the adjacent sub-pixel along the first direction on the substrate.

[0083] In the second sub-pixel, the orthographic projection of the second data line pattern on the substrate overlaps with the orthographic projection of the first portion of the adjacent sub-pixel along the first direction on the substrate, and the orthographic projection of the second data line pattern on the substrate does not overlap with the orthographic projection of the second portion of the adjacent sub-pixel along the first direction on the substrate. Attached Figure Description

[0084] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0085] Figure 1a This is a schematic diagram of sub-pixel layout in the prior art;

[0086] Figure 1b Figure 1 shows a schematic diagram of the layout of the active layer;

[0087] Figure 1c This is a schematic diagram of the layout of the first gate metal layer in Figure 1;

[0088] Figure 1d This is a schematic diagram of the layout of the second gate metal layer in Figure 1;

[0089] Figure 1e This is a schematic diagram of the source and drain metal layer layout in Figure 1;

[0090] Figure 2 A circuit diagram of a sub-pixel driving circuit provided in an embodiment of this disclosure;

[0091] Figure 3 This is a timing diagram of the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0092] Figure 4 This is a schematic diagram of the first layout of sub-pixels provided in an embodiment of the present disclosure;

[0093] Figure 5 This is a schematic diagram of the second layout of sub-pixels provided in an embodiment of the present disclosure;

[0094] Figure 6 for Figure 5 A schematic diagram showing the layout of the active layer and the first gate metal layer;

[0095] Figure 7 for Figure 5 Schematic diagram of the layout of the second gate metal layer;

[0096] Figure 8 for Figure 5 A schematic diagram of the layout of the first source / drain metal layer in the middle;

[0097] Figure 9 for Figure 5 A schematic diagram of the structure of the power supply compensation diagram;

[0098] Figure 10 for Figure 5 A schematic diagram of the layout of the first and second source / drain metal layers in the middle;

[0099] Figure 11 for Figure 5 A schematic diagram of the layout of the second source / drain metal layer in the middle;

[0100] Figure 12 This is a layout diagram for eight sub-pixels;

[0101] Figure 13a for Figure 12 A schematic diagram of the cross-section along the A1A2 direction;

[0102] Figure 13b for Figure 12 A schematic diagram of the cross-section along the B1B2 direction;

[0103] Figure 13c for Figure 12 A schematic diagram of the cross-section along the C1C2 direction;

[0104] Figure 13d for Figure 12 A schematic diagram of the cross-section along the D1D2 direction;

[0105] Figure 14 for Figure 12 A schematic diagram of the layout of the two source / drain metal layers and the anode layer;

[0106] Figure 15 for Figure 12 A schematic diagram of the layout of the second source / drain metal layer and the anode layer;

[0107] Figure 16 for Figure 12 A schematic diagram of the layout of the active layer;

[0108] Figure 17 for Figure 12 A schematic diagram of the layout of the first gate metal layer;

[0109] Figure 18 for Figure 12 Schematic diagram of the layout of the second gate metal layer;

[0110] Figure 19 for Figure 12 A schematic diagram of the layout of the first source / drain metal layer. Detailed Implementation

[0111] To further illustrate the display substrate, its manufacturing method, and the display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0112] The structure of an AMOLED display panel includes: a substrate, multiple sub-pixel driving circuits disposed on the substrate, and multiple light-emitting elements disposed on the side of the sub-pixel driving circuits facing away from the substrate. Each light-emitting element corresponds to a sub-pixel driving circuit, and the sub-pixel driving circuit is used to drive the corresponding light-emitting element to emit light, thereby realizing the display function of the display panel.

[0113] In related technologies, the sub-pixel driving circuit generally includes multiple thin-film transistors, such as... Figure 1a As shown, Figure 1a The diagram illustrates the specific layout of the seven thin-film transistors Q1 to Q7 in the sub-pixel driving circuit. When arranged in this manner, the sub-pixel driving circuit includes... Figure 1b The active layer shown is as follows: Figure 1c The first metal layer shown, such as Figure 1d The second metal layer shown, and as shown Figure 1e The third metal layer shown; the active layer includes active patterns (such as those for forming the channel regions of each thin-film transistor) for forming the channel regions of each thin-film transistor. Figure 1b The portion within the dashed box in the image), and the doped active pattern (such as...) electrically connected to the active pattern and having conductive properties. Figure 1b The first metal layer includes the gate of each thin-film transistor, the scan signal line GATE electrically connected to the gate, one electrode CE1 of the storage capacitor in the sub-pixel driving circuit, the reset signal line RST, and the light emission control signal line EM; the second metal layer includes the initialization signal line VINT, and the other electrode CE2 of the storage capacitor in the sub-pixel driving circuit; the third metal layer includes the data line DATA, the power signal line VDD, and some conductive connections (such as those marked 341-343).

[0114] It is worth noting that, as shown in FIG. 1, in the layout of the sub-pixel driving circuit, in order to realize the electrical connection between the function patterns arranged in different layers, some vias (such as marks: 381-388) can also be arranged.

[0115] In the related art, when the sub-pixel driving circuit is implemented to realize high-frequency driving, since the data writing time of each row of pixel driving circuits controlling the pixels is short, the problem of insufficient data writing time of each row of pixels is prone to occur.

[0116] Referring to Figures 2-4 The display substrate provided by the present disclosure includes a substrate and a plurality of sub-pixels arranged on the substrate, the plurality of sub-pixels can be divided into a plurality of rows of sub-pixels arranged in sequence along a second direction and a plurality of columns of sub-pixels arranged in sequence along a first direction, each sub-pixel includes a light emitting element, an initialization signal line pattern 94, a reset signal line pattern 95, a gate line pattern 92, and a light emitting control signal line pattern 93.

[0117] The plurality of sub-pixels includes:

[0118] The first sub-pixel and the second sub-pixel arranged along the second direction, the first sub-pixel includes a first data line pattern 981, the second sub-pixel includes a second data line pattern 982, at least part of the first data line pattern 981 and at least part of the second data line pattern 982 extend along the second direction, the first data line pattern 981 is located on the first side of the same column of the first sub-pixel extending along the second direction, the second data line pattern 982 is located on the second side of the same column of the second sub-pixel extending along the second direction, the first side and the second side are opposite along the first direction, and the first direction intersects the second direction. For example, the first side is the right side in Figure 4 , and the second side is the left side in Figure 4 .

[0119] The plurality of sub-pixels further includes a third sub-pixel and a fourth sub-pixel arranged along the second direction, the third sub-pixel and the first sub-pixel are located in the same row along the first direction, the fourth sub-pixel and the second sub-pixel are located in the same row along the first direction, the third sub-pixel includes a third data line pattern 983, and the orthographic projection of the third data line pattern 983 on the substrate overlaps the orthographic projection of the power signal line pattern 91 in the adjacent first sub-pixel on the substrate.

[0120] The first sub-pixel and the second sub-pixel each include a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor (i.e., a third transistor T3) and a data writing transistor (i.e., a fourth transistor T4), in the first sub-pixel, a first electrode of the data writing transistor is electrically connected with the first data line pattern 981, and a second electrode of the data writing transistor is electrically connected with a first electrode of the driving transistor; in the second sub-pixel, a first electrode of the data writing transistor is electrically connected with the second data line pattern 982, and a second electrode of the data writing transistor is electrically connected with a first electrode of the driving transistor. According to the specific structure of the display substrate, in the display substrate provided by the present disclosure, in the same column of sub-pixels extending along the second direction, the first electrode of the data writing transistor included in one of the adjacent sub-pixels is electrically connected with the first data line pattern 981, and the first electrode of the data writing transistor included in the other of the adjacent sub-pixels is electrically connected with the second data line pattern 982. In the display substrate provided by the present disclosure, by arranging different data line patterns to which the data writing transistors in the adjacent sub-pixels are electrically connected in the same column of sub-pixels, it is realized that the adjacent sub-pixels in the same column of sub-pixels are provided with data signals by different data line patterns, and it is ensured that each sub-pixel has sufficient data signal writing time, thereby solving the problem of insufficient data signal writing time of each row of sub-pixels of the display substrate when the display substrate is high-frequency displayed.

[0121] However, in the display substrate, the overlapping area between the orthogonal projection of the data line pattern (such as the first data line pattern 981 and the second data line pattern 982) included in each sub-pixel on the substrate and the orthogonal projection of the power signal line pattern 91 on the substrate is relatively large, so that the load of the data line pattern included in each sub-pixel is relatively large, which is not conducive to the display picture quality of the display substrate.

[0122] Please refer to Figure 5 、 Figures 8-12 The display substrate provided by the present disclosure includes a substrate and a plurality of sub-pixels arranged in an array on the substrate, and the plurality of sub-pixels include:

[0123] The first sub-pixel M1 and the second sub-pixel M2 are arranged along the second direction, the first sub-pixel M1 includes the first data line pattern 981, the second sub-pixel M2 includes the second data line pattern 982, at least part of the first data line pattern 981 and at least part of the second data line pattern 982 each extend along the second direction, the first data line pattern 981 is located on a first side of the same column of first sub-pixels M1 extending along the second direction, the second data line pattern 982 is located on a second side of the same column of second sub-pixels M2 extending along the second direction, the first side and the second side are opposite along a first direction, and the first direction intersects the second direction.

[0124] The first data line pattern 981 is configured to provide a first data signal to the first sub-pixel M1, and the second data line pattern 982 is configured to provide a second data signal to the second sub-pixel M2.

[0125] The first sub-pixel M1 and the second sub-pixel M2 each include:

[0126] A power signal line pattern 91, at least part of the power signal line pattern 91 extends along the second direction, the power signal line pattern 91 includes a power main body part, the power main body part includes a first part 911 and a second part 912 which are electrically connected, and the second part 912 protrudes from the first part 911 along the first direction.

[0127] In the first sub-pixel M1, the first part 911 has a projection on the substrate which overlaps with a projection on the substrate of a data line main body part 9801 of a data line pattern in a sub-pixel adjacent along the first direction, and the second part 912 has a projection on the substrate which does not overlap with a projection on the substrate of the data line main body part 9801 of the data line pattern in the sub-pixel adjacent along the first direction.

[0128] In the second sub-pixel M2, a data line main body part of the second data line pattern 982 has a projection on the substrate which overlaps with a projection on the substrate of the first part 911 in a sub-pixel adjacent along the first direction, and the data line main body part of the second data line pattern 982 has a projection on the substrate which does not overlap with a projection on the substrate of the second part 912 in the sub-pixel adjacent along the first direction.

[0129] Specifically, the display substrate includes a plurality of sub-pixels arranged in an array on a substrate, the plurality of sub-pixels can be divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels. The plurality of rows of sub-pixels are arranged along a second direction, and each row of sub-pixels includes a plurality of the sub-pixels arranged in sequence along a first direction. The plurality of columns of sub-pixels are arranged along the first direction, and each column of sub-pixels includes a plurality of the sub-pixels arranged in sequence along the second direction.

[0130] For example, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0131] At least part of the first data line pattern 981 and at least part of the second data line pattern 982 extend along the second direction. The first data line pattern 981 included by each first sub-pixel M1 in the same column of sub-pixels is electrically connected in sequence and can form an integrated structure. The second data line pattern 982 included by each second sub-pixel M2 in the same column of sub-pixels is electrically connected in sequence and can form an integrated structure.

[0132] As shown in the example, Figure 15 The first data line pattern 981 is, for example, a data line portion between a data writing position of a current first sub-pixel M1 (e.g., a position of a data line protrusion 9802) and a data writing position of a next row of adjacent first sub-pixel M1 along the second direction.

[0133] In the example, the first sub-pixels M1 and the second sub-pixels M2 are arranged alternately in the same column of sub-pixels.

[0134] In the example, in the same column of sub-pixels, the first sub-pixels M1 are odd-numbered sub-pixels that receive first data signals provided by the first data line pattern 981 included therein, and the second sub-pixels M2 are even-numbered sub-pixels that receive second data signals provided by the second data line pattern 982 included therein.

[0135] In the example, the first side is, for example, a right side in Figure 5 , and the second side is, for example, a left side in Figure 5 . In the same column of sub-pixels, the first data line pattern 981 is located at the first side of the same column of sub-pixels, and the second data line pattern 982 is located at the second side of the same column of sub-pixels.

[0136] The first sub-pixel M1 and the second sub-pixel M2 each include a sub-pixel driving circuit. The sub-pixel driving circuit includes a storage capacitor and a plurality of thin film transistors, as shown in the example, Figure 2 and Figure 5 In the example, the sub-pixel driving circuit includes 7T1C, i.e., 7 transistors and one storage capacitor. The sub-pixel driving circuit is configured to generate a driving signal for driving a light emitting element to emit light.

[0137] For example, the sub-pixel driving circuit includes a driving transistor and a data writing transistor. In the first sub-pixel M1, the first electrode of the data writing transistor is electrically connected to the first data line pattern 981. In the second sub-pixel M2, the first electrode of the data writing transistor is electrically connected to the second data line pattern 982. The second electrode of the data writing transistor in each sub-pixel is electrically connected to the first electrode of the driving transistor. The data writing transistor can transmit the data signal received by the first electrode to the first electrode of the driving transistor.

[0138] In the same column of sub-pixels, the data line patterns to which the first electrodes of the data writing transistors in adjacent sub-pixels are electrically connected are different. In more detail, in the same column of sub-pixels, the first electrode of the data writing transistor included in one of the adjacent sub-pixels is electrically connected to the first data line pattern 981, and the first electrode of the data writing transistor included in the other of the adjacent sub-pixels is electrically connected to the second data line pattern 982.

[0139] Each sub-pixel includes a light-emitting element located on the side of the sub-pixel driving circuit away from the substrate. The light-emitting element includes, in order from the side away from the substrate, an anode pattern, a light-emitting functional layer, and a cathode. The anode pattern is electrically connected to the sub-pixel driving circuit in the sub-pixel to which the anode pattern belongs, and receives a driving signal provided by the sub-pixel driving circuit. The light-emitting functional layer includes an organic light-emitting material layer, and in addition to the organic light-emitting material layer, the light-emitting functional layer can also include common layers such as an election transporting layer (ETL), an election injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL) in an integral layer structure. The cathode is electrically connected to the negative power supply signal line in the display substrate, and receives a negative power supply signal provided by the negative power supply signal line. The light-emitting functional layer emits light under the joint action of the anode pattern and the cathode, thereby realizing the display function of the display substrate.

[0140] Each sub-pixel includes the power supply signal line pattern 91, at least part of the power supply signal line pattern 91 extending along the second direction. In the same column of sub-pixels, the power supply signal line patterns 91 included in each sub-pixel are electrically connected in turn and can form an integral structure.

[0141] The power supply signal line pattern 91 in each sub-pixel includes a power supply main portion and a power supply protruding portion 913 that are electrically connected. The power supply main portion includes a first portion 911 and a second portion 912 that are electrically connected, and the first portion 911 and the second portion 912 are arranged alternately.

[0142] For example, at least a portion of the first portion 911 extends along the second direction, and at least a portion of the second portion 912 extends along the second direction. In a direction perpendicular to the second direction, the width of the first portion 911 is equal to the width of the second portion 912, or the width of the first portion 911 is greater than the width of the second portion 912, or the width of the first portion 911 is less than the width of the second portion 912.

[0143] For example, in the first sub-pixel M1, the orthographic projection of the power supply protrusion 913 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate, and the orthographic projection of the power supply body portion on the substrate at least partially overlaps with the orthographic projection of the third data line pattern 983 adjacent along the first direction on the substrate.

[0144] For example, in the first sub-pixel M1, the orthographic projection of the first portion 911 on the substrate overlaps with the orthographic projection of the data line body portion 9801 of the third data line pattern 983 adjacent along the first direction on the substrate, and the orthographic projection of the second portion 912 on the substrate does not overlap with the orthographic projection of the data line body portion 9801 of the third data line pattern 983 on the substrate.

[0145] In the display substrate provided in the above embodiments, the overlap area between the orthographic projection of the second data line pattern on the substrate and the orthographic projection of the power signal line pattern 91 on the substrate is effectively reduced, so that the overlap area between the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate is close to that between the orthographic projection of the second data line pattern on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate. This effectively reduces the load difference between the first data line pattern 981 and the second data line pattern, and better improves the display quality of the display substrate.

[0146] It should be noted that the functional pattern with fixed units includes: power signal line pattern 91, initialization signal line pattern 94, and conductive functional pattern (such as: second conductive connection part 962) electrically connected to the power signal line pattern 91 or the initialization signal line pattern 94.

[0147] like Figures 12-15 As shown, in some embodiments, the plurality of sub-pixels further includes:

[0148] a third sub-pixel M3 and a fourth sub-pixel M4 arranged along a second direction, along the first direction, the third sub-pixel M3 is located in the same row as the first sub-pixel M1, and the fourth sub-pixel M4 is located in the same row as the second sub-pixel M2;

[0149] The third sub-pixel M3 includes a third data line pattern 983, and the fourth sub-pixel M4 includes a fourth data line pattern 984. At least part of the third data line pattern 983 and at least part of the fourth data line pattern 984 extend along the second direction. The third data line pattern 983 is located on the second side of the same column of third sub-pixels M3 extending along the second direction, and the fourth data line pattern 984 is located on the first side of the same column of fourth sub-pixels M4 extending along the second direction.

[0150] The third sub-pixel M3 and the fourth sub-pixel M4 each include the power signal line pattern 91.

[0151] In the first sub-pixel M1, the orthogonal projection of the first part 911 on the substrate overlaps the orthogonal projection of the data line main body part of the third data line pattern 983 on the substrate along the first direction, and the orthogonal projection of the second part 912 on the substrate does not overlap the orthogonal projection of the data line main body part of the third data line pattern 983 on the substrate.

[0152] Specifically, at least part of the third data line pattern 983 and at least part of the fourth data line pattern 984 extend along the second direction. The third data line patterns 983 included in each third sub-pixel M3 in the same column of sub-pixels are electrically connected in sequence and can form an integrated structure. The fourth data line patterns 984 included in each fourth sub-pixel M4 in the same column of sub-pixels are electrically connected in sequence and can form an integrated structure. The third data line pattern is configured to provide a third data signal to the third sub-pixel, and the fourth data line pattern is configured to provide a fourth data signal to the fourth sub-pixel.

[0153] For example, along the first direction, the third sub-pixel M3 is located in the same row as the first sub-pixel M1, and the fourth sub-pixel M4 is located in the same row as the second sub-pixel M2.

[0154] For example, in the same column of sub-pixels, the third sub-pixel M3 and the fourth sub-pixel M4 are arranged alternately.

[0155] Similarly, both the third sub-pixel M3 and the fourth sub-pixel M4 include sub-pixel driving circuits. In the third sub-pixel M3, the first terminal of the data writing transistor is electrically connected to the third data line pattern 983. In the fourth sub-pixel M4, the first terminal of the data writing transistor is electrically connected to the fourth data line pattern 984. In each sub-pixel, the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor, and the data writing transistor can transmit the data signal received at its first terminal to the first terminal of the driving transistor.

[0156] For example, the first side is set as Figure 5 The right side of the middle, the second side is Figure 5 The third data line pattern 983 is located on the second side of the third sub-pixel in the same column extending along the second direction, and the fourth data line pattern 984 is located on the first side of the fourth sub-pixel in the same column extending along the second direction.

[0157] For example, among sub-pixels located in the same row along the first direction, the first data line pattern 981 and the third data line pattern 983 are both located between the first sub-pixel M1 to which the first data line pattern 981 belongs and the third sub-pixel M3 to which the third data line pattern 983 belongs. Among sub-pixels located in the same row along the first direction, the second data line pattern 982 and the fourth data line pattern 984 are both located between the second sub-pixel M2 to which the second data line pattern 982 belongs and the fourth sub-pixel M4 to which the fourth data line pattern 984 belongs.

[0158] Both the third sub-pixel M3 and the fourth sub-pixel M4 include: the power signal line pattern and the power compensation pattern. The structure of the power signal line pattern is the same as that of the power signal line pattern in the first sub-pixel M1 and the second sub-pixel M2, and the structure of the power compensation pattern is the same as that of the power compensation pattern in the first sub-pixel M1 and the second sub-pixel M2.

[0159] It is worth noting that the sub-pixel driving circuits included in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 have the same structure. The difference between the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 lies in the arrangement of the data lines and the structure of the light-emitting elements.

[0160] The first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 all include a sub-pixel driving circuit. The sub-pixel driving circuit includes a storage capacitor and multiple thin-film transistors, such as... Figure 2 and Figure 5As shown, the exemplary sub-pixel driving circuit includes 7T1C, i.e. 7 transistors and one storage capacitor. The sub-pixel driving circuit is used to generate a driving signal for driving the light emitting element to emit light.

[0161] Exemplarily, the sub-pixel driving circuit includes a driving transistor and a data writing transistor. In the first sub-pixel M1, the first electrode of the data writing transistor is electrically connected with the first data line pattern 981. In the second sub-pixel M2, the first electrode of the data writing transistor is electrically connected with the second data line pattern 982. In the third sub-pixel M3, the first electrode of the data writing transistor is electrically connected with the third data line pattern 983. In the fourth sub-pixel M4, the first electrode of the data writing transistor is electrically connected with the fourth data line pattern 984. The second electrode of the data writing transistor in each sub-pixel is electrically connected with the first electrode of the driving transistor, and the data writing transistor can transmit the data signal received by the first electrode to the first electrode of the driving transistor.

[0162] The third sub-pixel M3 and the fourth sub-pixel M4 each include the power signal line pattern and the power compensation pattern, the structure of the power signal line pattern is the same as that of the power signal line pattern in the first sub-pixel M1 and the second sub-pixel M2, and the structure of the power compensation pattern is the same as that of the power compensation pattern in the first sub-pixel M1 and the second sub-pixel M2.

[0163] The display substrate provided by the above embodiment realizes that adjacent sub-pixels in the same column of sub-pixels are provided with data signals by different data line patterns, ensures that each sub-pixel has sufficient data signal writing time, and thus solves the problem of insufficient data signal writing time for each row of sub-pixels of the display substrate when the display substrate displays at high frequency.

[0164] In addition, in the display substrate provided by the above embodiment, the overlapping area between the orthographic projection of the third data line pattern on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate is effectively reduced, thereby effectively reducing the load difference between the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984, and better improving the display picture quality of the display substrate.

[0165] It should be noted that Figure 12The plurality of sub-pixels further include a fifth sub-pixel M5, a sixth sub-pixel M6, a seventh sub-pixel M7, and an eighth sub-pixel M8; the fifth sub-pixel M5 and the sixth sub-pixel M6 are arranged alternately along the second direction, and the seventh sub-pixel M7 and the eighth sub-pixel M8 are arranged alternately along the second direction; along the first direction, the first sub-pixel M1, the third sub-pixel M3, the fifth sub-pixel M5, and the seventh sub-pixel M7 are located in the same row; and along the first direction, the second sub-pixel M2, the fourth sub-pixel M4, the sixth sub-pixel M6, and the eighth sub-pixel M8 are located in the same row.

[0166] As shown in FIG. 1, the display substrate includes a plurality of sub-pixels M1-M8 arranged in an array. Figure 12 The eight sub-pixels M1-M8 form a repeating unit in the display substrate, and the display substrate includes a plurality of the repeating units.

[0167] As shown in FIG. 1, the display substrate includes a plurality of sub-pixels M1-M8 arranged in an array. Figure 12 As shown in FIG. 1, in some embodiments, in the fourth sub-pixel M4, the first portion 911 has a projection on the substrate that overlaps with a projection on the substrate of a data line main body portion of the sixth data line pattern 986, and the second portion has a projection on the substrate that does not overlap with a projection on the substrate of the data line main body portion of the sixth data line pattern 986.

[0168] As shown in FIG. 1, the display substrate includes a plurality of sub-pixels M1-M8 arranged in an array. Figure 12 As shown in FIG. 1, in some embodiments, the power signal line pattern 91 has a projection on the substrate that does not overlap with a projection on the substrate of the third data line pattern 983.

[0169] The above arrangement effectively reduces the overlapping area between the projection on the substrate of the third data line pattern and the projection on the substrate of the functional pattern having a fixed potential, thereby effectively reducing the load difference between the first data line pattern 981 and the third data line pattern, and better improving the display picture quality of the display substrate.

[0170] As shown in FIG. 1, the display substrate includes a plurality of sub-pixels M1-M8 arranged in an array. Figure 12 As shown in FIG. 1, in some embodiments, the power signal line pattern 91 further includes a power protruding portion 913 electrically connected to the power main body portion; in the first sub-pixel M1, the power protruding portion 913 has a projection on the substrate that overlaps with a projection on the substrate of the first data line pattern 981.

[0171] The above arrangement effectively reduces the load difference between the first data line pattern 981 and the third data line pattern, and better improves the display picture quality of the display substrate.

[0172] As shown in FIG. 1, the display substrate includes a plurality of sub-pixels M1-M8 arranged in an array. Figure 12As shown, in some embodiments, the power signal line pattern 91 further includes a power protrusion 913 electrically connected to the power body portion; in the fourth sub-pixel M4, the orthographic projection of the power protrusion 913 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate.

[0173] The above configuration effectively reduces the load difference between the fourth data line pattern 984 and other data line patterns, thereby improving the display quality of the display substrate.

[0174] like Figure 5 , Figure 8 , Figure 12 and Figure 14 As shown, in some embodiments, in the fourth sub-pixel M4, the orthographic projection of the power supply protrusion 913 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate, and the orthographic projection of the power supply body portion on the substrate overlaps with the orthographic projection of the adjacent data line pattern along the first direction on the substrate.

[0175] like Figure 5 , Figure 8 , Figure 12 and Figure 14 As shown, in some embodiments, in the fourth sub-pixel M4, the orthographic projection of the power supply protrusion 913 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate. The power supply body portion includes a first portion 911 and a second portion 912. The orthographic projection of the first portion 911 on the substrate overlaps with the orthographic projection of the data line body portion 9801 of the adjacent data line pattern along the first direction on the substrate. The orthographic projection of the second portion 912 on the substrate does not overlap with the orthographic projection of the data line body portion 9801 of the data line pattern on the substrate.

[0176] For example, in the fourth sub-pixel M4, the power supply body portion includes a first portion 911 and a second portion 912. The orthographic projection of the first portion 911 on the substrate overlaps with the orthographic projection of the data line body portion 9801 of the sixth data line pattern 986 adjacent along the first direction on the substrate. The orthographic projection of the second portion 912 on the substrate does not overlap with the orthographic projection of the data line body portion 9801 of the sixth data line pattern 986 on the substrate.

[0177] The display substrate provided by the above embodiment makes the overlapping area between the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the functional pattern with fixed potential on the substrate close to the overlapping area between the orthographic projection of the adjacent data line pattern on the substrate and the orthographic projection of the functional pattern with fixed potential on the substrate, thereby effectively reducing the load difference between the fourth data line pattern 984 and the adjacent data line pattern.

[0178] As shown in Figure 5 , Figure 8 , Figure 12 and Figure 14 indicate that, in some embodiments, in the second sub-pixel M2, the orthographic projection of the power supply protruding part 913 on the substrate overlaps with the orthographic projection of the first data line 981 adjacent in the second direction on the substrate. In the third sub-pixel M3, the orthographic projection of the power supply protruding part 913 on the substrate overlaps with the orthographic projection of the fourth data line 984 adjacent in the second direction on the substrate.

[0179] As shown in Figure 10 and Figure 11 indicate that, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 each include a data line main part extending in the second direction and a data line protruding part protruding from the data line main part in the first direction; the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 each include a first conductive connection part 961 and a data writing transistor, and in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4, the data line protruding part 9802 and the first electrode of the data writing transistor are electrically connected through the first conductive connection part 961; the orthographic projection of the second part on the substrate and the first conductive connection part are arranged in the first direction.

[0180] Exemplarily, at least part of the first conductive connection 961 extends along the second direction. A first end of the first conductive connection 961 has a first overlapping area with a normal projection of the data line protrusion 9802 on the substrate, and the first end of the first conductive connection 961 is electrically connected to the data line protrusion 9802 through a via provided in the first overlapping area. A second end of the first conductive connection 961 has a second overlapping area with a normal projection of a first electrode of the data write transistor on the substrate, and the second end of the first conductive connection 961 is electrically connected to the first electrode of the data write transistor through a via provided in the second overlapping area. The first electrode of the data write transistor receives a data signal provided by the corresponding data line pattern through the first conductive connection 961.

[0181] Exemplarily, a normal projection of the second part 912 of the power signal line pattern 91 on the substrate is arranged along the first direction with the first overlapping area.

[0182] Along the first direction, the distance between the first conductive connection 961 and the power signal line pattern 91 is far, and by arranging the normal projection of the second part 912 of the power signal line pattern 91 on the substrate along the first direction with the first overlapping area, the second part 912 has sufficient layout space, so as to better reduce the layout difficulty of the display substrate while ensuring that the second part 912 has a larger area.

[0183] As shown in Figure 5 , Figure 10 and Figure 12 In some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 each include an initialization signal line pattern 94, a second transistor T2, a driving transistor and a second conductive connection 962.

[0184] At least part of the initialization signal line pattern 94 extends along the second direction, and the initialization signal line pattern 94 is used for transmitting an initialization signal.

[0185] The first electrode of the second transistor T2 is electrically connected with the initialization signal line pattern 94 through the second conductive connection part 962, and the second electrode of the second transistor T2 is electrically connected with the gate electrode of the driving transistor; in the first sub-pixel M1, the orthogonal projection of the second conductive connection part 962 on the substrate overlaps with the orthogonal projection of the first data line pattern 981 on the substrate; in the third sub-pixel M3, the orthogonal projection of the second conductive connection part 962 on the substrate does not overlap with the orthogonal projection of the third data line pattern 983 on the substrate.

[0186] As shown in Figure 12 In some embodiments, the second sub-pixel M2 and the fourth sub-pixel M4 each include an initialization signal line pattern 94, a second transistor T2, a driving transistor and a second conductive connection part 962.

[0187] At least part of the initialization signal line pattern 94 extends along the second direction, and the initialization signal line pattern 94 is used for transmitting an initialization signal.

[0188] The first electrode of the second transistor T2 is electrically connected with the initialization signal line pattern 94 through the second conductive connection part 962, and the second electrode of the second transistor T2 is electrically connected with the gate electrode of the driving transistor.

[0189] In the second sub-pixel M2, the orthogonal projection of the second conductive connection part 962 on the substrate does not overlap with the orthogonal projection of the second data line pattern 982 on the substrate.

[0190] In the fourth sub-pixel M4, the orthogonal projection of the second conductive connection part 962 on the substrate overlaps with the orthogonal projection of the fourth data line pattern 984 on the substrate.

[0191] Specifically, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 each include the initialization signal line pattern 94, the second transistor T2 and the second conductive connection part 962. For example, the orthogonal projection of the first electrode of the second transistor T2 on the substrate overlaps with the orthogonal projection of the first end of the second conductive connection part 962 on the substrate, and the first electrode of the second transistor T2 is electrically connected with the first end of the second conductive connection part 962 through a via located at the overlapping position. The orthogonal projection of the second end of the second conductive connection part 962 on the substrate overlaps with the orthogonal projection of the initialization signal line pattern 94 on the substrate, and the second end of the second conductive connection part 962 is electrically connected with the initialization signal line pattern 94 through a via located at the overlapping position.

[0192] The second electrode of the second transistor T2 is electrically connected with the gate electrode of the driving transistor. During the reset period, the second transistor T2 can transmit the received initialization signal to the gate electrode of the driving transistor, so as to reset the gate electrode of the driving transistor.

[0193] The second conductive connection part 962 is electrically connected with the initialization signal line pattern 94, so that the initialization signal line pattern 94 has a stable potential. The above-mentioned second conductive connection part 962 is arranged in the first sub-pixel M1, and the orthographic projection of the second conductive connection part 962 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate; so that the overlapping area between the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, and the overlapping area between the orthographic projection of the third data line pattern on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate are closer, thereby further reducing the load difference between the first data line pattern 981 and the third data line pattern.

[0194] The above-mentioned second conductive connection part 962 is arranged in the fourth sub-pixel M4, and the orthographic projection of the second conductive connection part 962 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate, so that the overlapping area between the orthographic projection of the second data line pattern 982 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, and the overlapping area between the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate are closer, thereby further reducing the load difference between the second data line pattern 982 and the fourth data line pattern 984.

[0195] In some embodiments, the orthographic projection of the third data line pattern on the substrate and the orthographic projection of the first part 911 on the substrate form an overlapping area with a first area; the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the power supply protruding part 913 on the substrate form an overlapping area with a second area, and the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the second conductive connection part 962 on the substrate have a third area; the sum of the second area and the third area is substantially the same as the first area. The above-mentioned sum of the second area and the third area is substantially the same as the first area, so that the load of the first data line pattern 981 and the load of the third data line pattern are substantially the same, thereby better improving the display uniformity of the display substrate.

[0196] In some embodiments, the second data line pattern has a first area of an overlapping region formed by a projection of the second data line pattern on the substrate and a projection of the first portion 911 on the substrate; the fourth data line pattern 984 has a second area of an overlapping region formed by a projection of the fourth data line pattern 984 on the substrate and a projection of the power supply protruding portion 913 on the substrate, and a third area of an overlapping region formed by a projection of the fourth data line pattern 984 on the substrate and a projection of the second conductive connection 962 in the display substrate on the substrate; and a sum of the second area and the third area is substantially the same as the first area. The above arrangement of the sum of the second area and the third area being substantially the same as the first area makes the load of the second data line pattern 982 and the load of the fourth data line pattern 984 substantially the same, thereby better improving the display uniformity of the display substrate.

[0197] As shown in Figure 5 , Figure 8 , Figure 9 , Figure 12 and Figure 19 In some embodiments, the power supply protruding portion 913 includes a third portion 9130, a fourth portion 9131, and a fifth portion 9132; the third portion 9130 extends along the second direction, and in the first sub-pixel M1, a projection of the third portion 9130 on the substrate overlaps with a projection of the first data line pattern 981 on the substrate. In the fourth sub-pixel M4, a projection of the third portion 9130 on the substrate overlaps with a projection of the fourth data line pattern 984 on the substrate.

[0198] In the first sub-pixel M1, by setting the length of the third portion 9130 along the second direction, the area of the first data line pattern 981 overlapping with the third portion 9130 can be controlled, and thus the load of the first data line pattern 981 can be adjusted. In the third sub-pixel M3, by setting the length of the third portion 9130 along the second direction, the area of the fourth data line pattern 984 overlapping with the third portion 9130 can be controlled, and thus the load of the fourth data line pattern 984 can be adjusted.

[0199] As shown in Figure 5 , as shown in Figure 8 , Figure 10 , Figure 12 and Figure 19 The first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include:

[0200] a power supply signal line pattern 91, at least part of the power supply signal line pattern 91 extending along the second direction;

[0201] A power supply compensation pattern 97, at least part of the power supply compensation pattern 97 extends along the first direction, the power supply signal line pattern 91 and the power supply compensation pattern 97 are located on a side of the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 close to the substrate;

[0202] The power supply compensation pattern 97 is electrically connected with the power supply signal line pattern 91 in the sub-pixel to which the power supply compensation pattern 97 belongs respectively, and the power supply signal line pattern 91 in the sub-pixel adjacent along the first direction.

[0203] Specifically, the sub-pixel further includes a power supply compensation pattern 97, the power supply signal line pattern 91 and the power supply compensation pattern 97 are located on a side of the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 close to the substrate; for example, the side of the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 close to the substrate is provided with an interlayer insulation layer ILD, and the power supply compensation pattern 97 and the power supply signal line pattern 91 are located on the surface of the interlayer insulation layer ILD away from the substrate. This arrangement allows the power supply signal line pattern 91 and the power supply compensation pattern 97 to be formed in the same layer, and when the power supply signal line pattern 91 and the power supply compensation pattern 97 are made of the same material, the power supply signal line pattern 91 and the power supply compensation pattern 97 can be formed in the same patterning process, thereby better simplifying the manufacturing process of the display substrate and saving manufacturing costs.

[0204] It should be noted that the power supply signal line pattern 91 and the power supply compensation pattern 97 can form a first source-drain metal layer in the display substrate, of course, the first source-drain metal layer can also include other structures.

[0205] As Figure 5 For example, the power supply compensation pattern 97 is electrically connected with the power supply signal line pattern 91 in the sub-pixel to which the power supply compensation pattern 97 belongs respectively, and the power supply signal line pattern 91' in the sub-pixel adjacent along the first direction.

[0206] For example, the power supply compensation pattern 97 and the two power supply signal line patterns 91 to which the power supply compensation pattern 97 is electrically connected are formed as an integral structure. It is worth noting that the integral structure includes the power supply compensation pattern 97 and the power supply signal line pattern 91 which are formed by one patterning process at the same time by using the same material.

[0207] Exemplarily, the power supply compensation pattern included in the third sub-pixel M3 is electrically connected with the power supply signal line pattern included in the third sub-pixel M3 and the power supply signal line pattern in the first sub-pixel M1 adjacent to the third sub-pixel M3 along the first direction, respectively;

[0208] Exemplarily, the power supply compensation pattern included in the fourth sub-pixel M4 is electrically connected with the power supply signal line pattern included in the fourth sub-pixel M4 and the power supply signal line pattern in the second sub-pixel M2 adjacent to the fourth sub-pixel M4 along the first direction, respectively.

[0209] In the display substrate provided by the above embodiment, the power supply compensation pattern 97 is electrically connected with the power supply signal line pattern 91 in the sub-pixel to which the power supply compensation pattern 97 belongs and the power supply signal line pattern 91' in the adjacent sub-pixel located in the same row as the sub-pixel along the first direction, respectively; the power supply signal line patterns 91 included in each sub-pixel located in the same row are electrically connected together, the overall resistance of the power supply signal line pattern 91 is reduced, and the display uniformity of the display substrate is improved. Meanwhile, the power supply signal line patterns 91 in each sub-pixel located in the same column are electrically connected in sequence, the power supply signal line patterns 91 included in the display substrate are collectively formed in a mesh structure, and the display uniformity of the display substrate is further improved.

[0210] In the display substrate provided by the above embodiment, the power supply compensation pattern 97 and the power supply signal line pattern 91 are located on the surface of the substrate away from the interlayer insulating layer ILD of the display substrate, and the power supply signal line pattern 91 and the power supply compensation pattern 97 are formed as the first source-drain metal layer in the display substrate, so that the power supply signal line pattern 91 and the power supply compensation pattern 97 can be formed in the same patterning process, thereby simplifying the manufacturing process of the display substrate and saving manufacturing cost. Moreover, since the power supply compensation pattern 97 and the power supply signal line pattern 91 are made of the same source-drain metal material, the resistance of the power supply compensation pattern 97 and the power supply signal line pattern 91 is small, and the display uniformity of the display substrate is improved.

[0211] In the display substrate provided by the above embodiment, all the power supply signal line patterns 91 are collectively formed in a mesh structure, which effectively improves the stability of the power supply signal transmitted by the power supply signal line pattern, and the power supply signal is used to provide the source of the driving transistor in the sub-pixel driving circuit, and the light-emitting current I oled =k[(Vgs-Vth)] 2 generated by the sub-pixel driving circuit, Vg is the gate voltage of the driving transistor, Vs is the source voltage of the driving transistor, and Vth is the threshold voltage of the driving transistor. Therefore, the power supply signal is used as Vs, which affects the light-emitting current I oledThe size of the power supply signal line layer has an impact, so the above setting mode can better ensure the stability of the light-emitting current I oled The stability of the power supply signal line layer has an impact, so the above setting mode can better ensure the stability of the light-emitting current I

[0212] As shown in Figure 5 and Figure 8 In some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include a reset signal line pattern 95, a gate line pattern 92, and a light-emitting control signal line pattern 93 distributed along a second direction; at least part of the reset signal line pattern 95 extends along a first direction, at least part of the gate line pattern 92 extends along the first direction, and at least part of the light-emitting control signal line pattern 93 extends along the first direction.

[0213] In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the orthographic projection of the power supply compensation pattern 97 on the substrate is located between the orthographic projection of the gate line pattern 92 on the substrate and the orthographic projection of the light-emitting control signal line pattern 93 on the substrate.

[0214] Specifically, the sub-pixel further includes a reset signal line pattern 95, a gate line pattern 92, and a light-emitting control signal line pattern 93 distributed along a second direction in sequence. The reset signal line is used to transmit a reset signal, and the gate line pattern 92 is used to transmit a scanning signal. The light-emitting control signal line pattern 93 is used to transmit a light-emitting control signal.

[0215] At least part of the reset signal line pattern 95 extends along a first direction, and the reset signal line patterns 95 included in each sub-pixel located in the same row along the first direction are electrically connected in sequence and can be formed as an integral structure. At least part of the gate line pattern 92 extends along the first direction, and the gate line patterns 92 included in each sub-pixel located in the same row along the first direction are electrically connected in sequence and can be formed as an integral structure. At least part of the light-emitting control signal line pattern 93 extends along the first direction, and the light-emitting control signal line patterns 93 included in each sub-pixel located in the same row along the first direction are electrically connected in sequence and can be formed as an integral structure.

[0216] The specific layout position of the power supply compensation pattern 97 is various. Exemplarily, in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4, the orthogonal projection of the power supply compensation pattern 97 on the substrate does not overlap with the orthogonal projection of the reset signal line pattern 95 on the substrate, the orthogonal projection of the power supply compensation pattern 97 on the substrate does not overlap with the orthogonal projection of the gate line pattern 92 on the substrate, and the orthogonal projection of the power supply compensation pattern 97 on the substrate does not overlap with the orthogonal projection of the light-emitting control signal line pattern 93 on the substrate.

[0217] Exemplarily, the orthogonal projection of the power supply compensation pattern 97 on the substrate is located between the orthogonal projection of the gate line pattern 92 on the substrate and the orthogonal projection of the light-emitting control signal line pattern 93 on the substrate.

[0218] Exemplarily, along the second direction, the minimum distance between the orthogonal projection of the power supply compensation pattern 97 on the substrate and the orthogonal projection of the gate line pattern 92 on the substrate is greater than the minimum distance between the orthogonal projection of the power supply compensation pattern 97 on the substrate and the orthogonal projection of the light-emitting control signal line pattern 93 on the substrate.

[0219] The power supply compensation pattern 97 is arranged in the above manner, so that the power supply compensation pattern 97 has a relatively far distance from the reset signal line pattern 95, the gate line pattern 92 and the light-emitting control signal line pattern 93, thereby avoiding increasing the load of the reset signal line pattern 95, the gate line pattern 92 and the light-emitting control signal line pattern 93.

[0220] In some embodiments, the minimum distance between the orthogonal projection of the power supply compensation pattern 97 on the substrate and the orthogonal projection of the gate line pattern 92 on the substrate is greater than a threshold value; and the minimum distance between the orthogonal projection of the power supply compensation pattern 97 on the substrate and the orthogonal projection of the light-emitting control signal line pattern 93 on the substrate is greater than the threshold value.

[0221] Exemplarily, the threshold value is 5 μm. The minimum distance between the orthogonal projection of the power supply compensation pattern 97 on the substrate and the orthogonal projection of the gate line pattern 92 on the substrate is greater than 5 μm; and the minimum distance between the orthogonal projection of the power supply compensation pattern 97 on the substrate and the orthogonal projection of the light-emitting control signal line pattern 93 on the substrate is greater than 5 μm.

[0222] The power supply compensation pattern 97 is far away from the reset signal line pattern 95, the gate line pattern 92 and the light-emitting control signal line pattern 93, so as to avoid increasing the load of the reset signal line pattern 95, the gate line pattern 92 and the light-emitting control signal line pattern 93.

[0223] As shown in Figure 5 , Figure 8 , Figure 10 , Figure 12 and Figure 19 In some embodiments, at least part of the power supply protruding part 913 extends along the second direction, and a gap 50 is formed between the power supply protruding part 913 and the power supply main part in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4; the first end of the power supply compensation pattern 97 is electrically connected to the power supply protruding part 913; and the second end of the power supply compensation pattern 97 is electrically connected to the power supply main part in the adjacent sub-pixel along the first direction (i.e., the power supply main part of the power supply signal line pattern 91' in Figure 8 ).

[0224] For example, at least part of the power supply protruding part 913 extends along the second direction, and the second end of the power supply compensation pattern 97 is electrically connected to the middle part of the power supply protruding part 913.

[0225] The above arrangement can shorten the length of the power supply compensation pattern 97, so as to effectively reduce the layout difficulty of the power supply compensation pattern 97.

[0226] More specifically, the power supply protruding part 913 includes a third part 9130, a fourth part 9131 and a fifth part 9132; the third part 9130 is electrically connected to the power supply compensation pattern 97 and extends along the second direction; the fourth part 9131 is electrically connected to one end of the third part 9130 and the power supply main part respectively; the fifth part 9132 is electrically connected to the other end of the third part 9130 and the power supply main part respectively; and a gap 50 is formed between the third part 9130 and the power supply main part.

[0227] Specifically, the specific structure of the power supply protruding part 913 is various, for example, the power supply protruding part 913 includes the third part 9130, the fourth part 9131 and the fifth part 9132 in an integrated structure.

[0228] By configuring the fourth part 9131 to be electrically connected to one end of the third part 9130 and the power supply main body, and the fifth part 9132 to be electrically connected to the other end of the third part 9130 and the power supply main body, the connection performance between the power supply protrusion 913 and the power supply main body is better guaranteed, and the display uniformity of the display substrate is more effectively improved.

[0229] Additionally, the display substrate may also include a fingerprint recognition module. For example, the fingerprint recognition module is located on the side of the substrate facing away from the sub-pixel driving circuit. For example, the orthographic projection of the fingerprint recognition area of ​​the fingerprint recognition module onto the substrate overlaps with the orthographic projection of the gap 50 onto the substrate. During fingerprint recognition, a finger touches the side of the light-emitting element facing away from the substrate, and the light reflected by the finger passes through the gap 50 and is received by the fingerprint recognition module, thus realizing the fingerprint recognition function.

[0230] The aforementioned configuration provides a gap 50 between the third part 9130 and the power supply body, which improves the light transmittance of the display substrate. Therefore, when the display substrate provided in the above embodiment is compatible with optical fingerprint recognition technology, it can provide good conditions for the sensor to collect light signals, thereby effectively improving the speed and accuracy of fingerprint recognition.

[0231] In addition, in the display substrate provided in the above embodiments, the gap 50 is only formed on the power signal line pattern 91, and no operations such as narrowing the metal trace width, compressing the size of the light-emitting element, or compressing the size of the transistor or capacitor are performed except for the power signal line pattern 91. Therefore, the display substrate provided in the above embodiments is not likely to have a negative impact on the performance of the display substrate while improving the resolution.

[0232] like Figure 5 and Figure 9 As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include a storage capacitor Cst and a driving transistor. In each sub-pixel, the first plate Cst1 of the storage capacitor Cst is electrically connected to the gate of the driving transistor, and the second plate Cst2 of the storage capacitor Cst is electrically connected to the power supply protrusion 913.

[0233] For example, the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate overlaps with the orthographic projection of the power supply protrusion 913 on the substrate, and the second plate Cst2 of the storage capacitor Cst and the power supply protrusion are electrically connected at the overlap.

[0234] Exemplarily, the third portion 9130 includes a first sub-portion 9130a and a second sub-portion 9130b, the first sub-portion 9130a is close to the fourth portion 9131, and the second sub-portion 9130b is close to the fifth portion 9132. In a direction perpendicular to the second direction, on a plane parallel to the substrate, a width L1 of the first sub-portion 9130a is greater than a width L2 of the second sub-portion 9130b.

[0235] A second plate Cst2 of the storage capacitor Cst is overlapped with a projection of the first sub-portion 9130a on the substrate, and the second plate Cst2 of the storage capacitor Cst is electrically connected with the first sub-portion 9130a through a via hole arranged at the overlap.

[0236] The above arrangement manner enables the second plate Cst2 of the storage capacitor Cst to form a larger overlapped area with the first sub-portion 9130a, thereby being more conducive to reducing the layout difficulty of the via hole. It should be noted that, Figure 13a The mark 40 in FIG. 1 represents a substrate and some film layers (such as a buffer layer, an isolation layer, etc.) arranged on the substrate.

[0237] As shown in FIGS. 1 and 2, Figure 5 and Figure 9 In some embodiments, in a direction perpendicular to the first direction, the first end D of the power supply compensation pattern 97 has a first width which gradually increases in a direction (i.e., the direction indicated by the arrowed dashed line in FIG. 1) close to the power signal line pattern in the sub-pixel to which the first sub-pixel belongs. Figure 9

[0238] The above arrangement manner not only enables the power supply compensation pattern 97 to have better connection performance with the power signal line pattern 91, but also avoids the connection between the power supply compensation pattern 97 and the power signal line pattern 91 from forming a right-angle structure, thereby avoiding the risk of static electricity.

[0239] As shown in FIGS. 1 and 2, Figure 5 , Figure 12 and Figure 13a In some embodiments, the display substrate further includes an interlayer insulating layer ILD and a first planarization layer PLN1 which are sequentially arranged in a direction away from the substrate; the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 are located on a surface of the first planarization layer PLN1 away from the substrate; and the power signal line pattern 91 and the power supply compensation pattern 97 are located on a surface of the interlayer insulating layer ILD away from the substrate.

[0240] ​Specifically, the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 are all located on the surface of the first planar layer PLN1 facing away from the substrate, so that the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 are all in the same layer, and when the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 are made of the same material, the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 can be formed in the same patterning process, thereby better simplifying the manufacturing process of the display substrate and saving manufacturing costs.

[0241] It should be noted that the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 can form a second source-drain metal layer in the display substrate. It is worth noting that the second source-drain metal layer can also include other structures.

[0242] As shown in FIGS. Figure 12 , Figure 13a and Figure 15 In some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 each include a sixth transistor T6, a third conductive connection part 963, a fourth conductive connection part 964 and a light emitting element stacked in sequence in a direction away from the substrate; the light emitting element includes an anode pattern (such as the fifth anode pattern 75 in FIG. Figure 13a In each sub-pixel, the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor (i.e., the third transistor); the second electrode of the sixth transistor T6 is electrically connected to the anode pattern through the third conductive connection part 963 and the fourth conductive connection part 964 in sequence;

[0243] For example, in each of the sub-pixels, the gate of the sixth transistor T6 is electrically connected to the light-emitting control signal line pattern 93, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the driving transistor, the orthographic projection of the second electrode of the sixth transistor T6 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have a third overlapping region, and the second electrode of the sixth transistor T6 and the third conductive connection portion 963 are electrically connected through a first via 61 disposed in the third overlapping region; the orthographic projection of the third conductive connection portion 963 on the substrate and the light-emitting control signal line pattern 93 are electrically connected to the first electrode of the driving transistor T6. The orthographic projection of the fourth conductive connection 964 onto the substrate has a fourth overlapping region, and the third conductive connection 963 is electrically connected to the fourth conductive connection 964 through a second via 62 disposed in the fourth overlapping region; the orthographic projection of the fourth conductive connection 964 onto the substrate and the orthographic projection of the anode pattern (e.g., the first anode pattern 71, the second anode pattern 72, and the third anode pattern 73) onto the substrate have a fifth overlapping region, and the fourth conductive connection 964 is electrically connected to the anode pattern through a third via 63 disposed in the fifth overlapping region.

[0244] During the light-emitting period, the sixth transistor T6 transmits the driving signal output from the second electrode of the driving transistor to the anode of the light-emitting element through the third conductive connection 963 and the fourth conductive connection 964 in sequence.

[0245] In the display substrate provided in the above embodiment, the second electrode of the sixth transistor T6 is provided, and is electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964 in sequence, thereby better ensuring the electrical connection performance between the second electrode of the sixth transistor T6 and the anode pattern.

[0246] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, in the fifth sub-pixel M5, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the hollow portion 9642 on the substrate both at least partially overlap with the orthographic projection of the anode pattern on the substrate; the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the fifth data line pattern 985 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the seventh data line pattern 987 adjacent along the first direction on the substrate.

[0247] Specifically, in the fifth sub-pixel M5, the light-emitting element includes a fifth light-emitting element including a fifth anode pattern 75, a fifth light-emitting functional layer and a cathode which are sequentially stacked in a direction away from the substrate. Illustratively, the fifth light-emitting element includes a blue light-emitting element.

[0248] Illustratively, in the fifth sub-pixel M5, the orthographic projection of the solid part 9641 on the substrate and the orthographic projection of the third conductive connection part 963 on the substrate have the fourth overlapping area; the orthographic projection of the solid part 9641 on the substrate and the orthographic projection of the fifth anode pattern 75 on the substrate have the fifth overlapping area.

[0249] Illustratively, the orthographic projection of the first side of the fifth anode pattern 75 on the substrate overlaps with the orthographic projection of the fifth data line pattern 985 in the sub-pixel to which the first side belongs on the substrate, and overlaps with the orthographic projection of the seventh data line pattern 987 adjacent to the fifth data line pattern 985 in the first direction on the substrate; the orthographic projection of the second side of the fifth anode pattern 75 on the substrate overlaps with the orthographic projection of the hollow part 9642 on the substrate; the first side and the second side are oppositely arranged in the first direction.

[0250] Illustratively, the hollow part 9642 is formed in a mouth-shaped type, and the orthographic projection of the second side of the fifth anode pattern 75 on the substrate overlaps with the orthographic projection of the two sides opposite to each other in the first direction in the hollow part 9642 on the substrate. Illustratively, the orthographic projection of the second side of the fifth anode pattern 75 on the substrate overlaps with the orthographic projection of the two sides opposite to each other in the second direction in the hollow part 9642 on the substrate.

[0251] Illustratively, the two sides opposite to each other in the first direction in the hollow part 9642 have a first distance L3, and the fifth data line pattern 985 and the seventh data line pattern 987 adjacent to each other in the first direction have a second distance L4, and the first distance L3 is equal to the second distance L4.

[0252] The above arrangement enables the fourth conductive connection part 964 to compensate for the step difference generated by the fifth data line pattern 985 and the seventh data line pattern 987 under the fifth anode pattern 75, so that the fifth anode pattern 75 can be formed on a relatively flat surface, thereby making the fifth anode pattern 75 have a higher flatness, effectively reducing the color deviation phenomenon generated by the display substrate during display.

[0253] As Figure 11 , Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 In some embodiments, the first sub-pixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion and a light emitting element stacked in a direction away from the substrate; the light emitting element includes a first anode pattern; a second electrode of the sixth transistor is electrically connected to the first anode pattern through the third conductive connection portion and the fourth conductive connection portion; in the first sub-pixel M1, the fourth conductive connection portion 964 includes a solid portion; a projection of the solid portion on the substrate at least partially overlaps with a projection of the first anode pattern on the substrate; the projection of the first anode pattern on the substrate does not overlap with a projection of the first data line pattern 981 on the substrate.

[0254] For example, the projection of the anode pattern on the substrate at least partially overlaps with a projection of the second data line pattern 982 on the substrate.

[0255] Specifically, in the first sub-pixel M1, the light emitting element includes a first light emitting element, and the first light emitting element includes a first anode pattern 71, a first light emitting functional layer and a cathode stacked in a direction away from the substrate. For example, the first light emitting element includes a red light emitting element.

[0256] For example, in the first sub-pixel M1, the projection of the solid portion on the substrate has the fourth overlapping area with a projection of the third conductive connection portion 963 on the substrate; the projection of the solid portion on the substrate has the fifth overlapping area with the projection of the first anode pattern 71 on the substrate.

[0257] For example, the projection of the first anode pattern 71 on the substrate does not overlap with the projection of the first data line pattern 981 on the substrate, the projection of the first anode pattern 71 on the substrate does not overlap with a projection of a third data line pattern 983 adjacent to the first anode pattern 71 in the first direction on the substrate, and the projection of the first anode pattern 71 on the substrate at least partially overlaps with a projection of a second data line pattern 982 adjacent to the first anode pattern 71 in a second direction on the substrate.

[0258] For example, the orthographic projection of the first side portion of the first anode pattern 71 on the substrate overlaps with the orthographic projection of the second data line pattern 982 adjacent along the second direction on the substrate; the orthographic projection of the second side portion of the first anode pattern 71 on the substrate overlaps with the orthographic projection of the eighth data line pattern 988 adjacent along the first direction of the second data line pattern 982 on the substrate; the first side portion and the second side portion are disposed opposite to each other along the first direction.

[0259] The above configuration enables the second data line pattern 982 and the eighth data line pattern 988 to compensate for the step difference generated below the first anode pattern 71, so that the first anode pattern 71 can be formed on a relatively flat surface, thereby giving the first anode pattern 71 a high flatness and effectively reducing the color shift phenomenon generated by the display substrate during display.

[0260] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, the second sub-pixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and a light-emitting element stacked along a direction away from the substrate; the light-emitting element includes a second anode pattern; the second electrode of the sixth transistor is electrically connected to the second anode pattern through the third conductive connection portion and the fourth conductive connection portion; in at least a portion of the second sub-pixel M2, the orthographic projection of the second anode pattern on the substrate overlaps with the orthographic projection of the second data line pattern on the substrate.

[0261] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, in at least a portion of the second sub-pixel M2, the fourth conductive connection portion 964 includes a solid portion and a cutout portion; the orthographic projection of the solid portion on the substrate and the orthographic projection of the cutout portion on the substrate both at least partially overlap with the orthographic projection of the anode pattern on the substrate.

[0262] Specifically, in the second sub-pixel M2, the light-emitting element includes a second light-emitting element, which comprises a second anode pattern 72, a second light-emitting functional layer, and a cathode sequentially stacked along a direction away from the substrate. For example, the second light-emitting element includes a blue light-emitting element.

[0263] For example, in the second sub-pixel M2, the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping region; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the second anode pattern 72 on the substrate have the fifth overlapping region.

[0264] For example, the orthographic projection of the second side portion of the second anode pattern 72 onto the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 in its corresponding sub-pixel onto the substrate; the orthographic projection of the second side portion of the second anode pattern 72 onto the substrate overlaps with the orthographic projections of the solid portion and the hollow portion onto the substrate; the orthographic projection of the first side portion of the second anode pattern 72 onto the substrate overlaps with the orthographic projection of the first data line pattern 981 adjacent along the second direction onto the substrate, and also overlaps with the orthographic projection of the third data line pattern 983 adjacent to the first data line pattern 981 along the second direction onto the substrate. The first side portion and the second side portion are disposed opposite each other along the first direction.

[0265] For example, the hollow portion 9642 is formed in a square shape, and the orthographic projection of the second side of the second anode pattern 72 on the substrate overlaps with the orthographic projections of the two opposite sides of the hollow portion 9642 along the first direction on the substrate. For example, the orthographic projection of the second side of the second anode pattern 72 on the substrate overlaps with the orthographic projections of the two opposite sides of the hollow portion 9642 along the second direction on the substrate.

[0266] The above configuration enables the fourth conductive connection portion 964 and the second data line pattern 982 to compensate for the step difference generated below the second anode pattern 72 by the extended portions of the first data line pattern 981 and the third data line pattern 983, so that the second anode pattern 72 can be formed on a relatively flat surface, thereby giving the second anode pattern 72 a high flatness and effectively reducing the color shift phenomenon generated by the display substrate during display.

[0267] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, in the sixth sub-pixel M6, the fourth conductive connection portion 964 includes a solid portion;

[0268] The orthographic projection of the solid portion onto the substrate at least partially overlaps with the orthographic projection of the anode pattern onto the substrate;

[0269] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the sixth data line pattern 986 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the fourth data line pattern 984 adjacent to the anode pattern in the first direction on the substrate.

[0270] Specifically, in the sixth sub-pixel M6, the light emitting element includes a sixth light emitting element, and the sixth light emitting element includes a sixth anode pattern 76, a sixth light emitting functional layer and a cathode which are sequentially stacked in a direction away from the substrate. Illustratively, the sixth light emitting element includes a red light emitting element.

[0271] Illustratively, in the sixth sub-pixel M6, the orthographic projection of the solid part on the substrate has the fourth overlap area with the orthographic projection of the third conductive connection part 963 on the substrate, and the orthographic projection of the solid part on the substrate has the fifth overlap area with the orthographic projection of the sixth anode pattern 76 on the substrate.

[0272] Illustratively, the orthographic projection of the first side of the sixth anode pattern 76 on the substrate at least partially overlaps with the orthographic projection of the sixth data line pattern 986 on the substrate, and the orthographic projection of the second side of the sixth anode pattern 76 on the substrate at least partially overlaps with the orthographic projection of the fourth data line pattern 984 adjacent to the anode pattern in the first direction on the substrate. The first side and the second side are oppositely arranged in the first direction.

[0273] The above arrangement enables the sixth data line pattern 986 and the fourth data line pattern 984 to compensate for the step difference caused by each other under the sixth anode pattern 76, so that the sixth anode pattern 76 can be formed on a relatively flat surface, thereby making the sixth anode pattern 76 have a higher flatness and effectively reducing the color deviation phenomenon caused by the display substrate during display.

[0274] As Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15As shown in some embodiments, in part of the third sub-pixel, the fourth conductive connection portion comprises a solid portion and a hollow portion; the third anode pattern overlaps with the third data line pattern on the substrate, and overlaps with the data line pattern adjacent to the third data line pattern in the first direction on the substrate; the third anode pattern overlaps with the solid portion on the substrate; and / or, the third anode pattern overlaps with the hollow portion on the substrate.

[0275] As shown in some embodiments, in part of the third sub-pixel, the fourth conductive connection portion comprises a solid portion and a hollow portion; the third anode pattern overlaps with the third data line pattern on the substrate, and overlaps with the data line pattern adjacent to the third data line pattern in the first direction on the substrate; the third anode pattern overlaps with the solid portion on the substrate; and / or, the third anode pattern overlaps with the hollow portion on the substrate. Figure 11 、 Figure 12 、 Figure 13a 、 Figure 14 and Figure 15 As shown in some embodiments, in part of the third sub-pixel M3, the fourth conductive connection portion 964 comprises a solid portion 9641 and a hollow portion 9642; the solid portion 9641 on the substrate, and the hollow portion 9642 on the substrate at least partially overlap with the anode pattern on the substrate; the anode pattern on the substrate at least partially overlaps with the third data line pattern 983 on the substrate.

[0276] Specifically, in the third sub-pixel M3, the light emitting element comprises a third light emitting element, which comprises a third anode pattern 73, a third light emitting functional layer and a cathode, which are sequentially stacked in a direction away from the substrate. For example, the third light emitting element comprises a green light emitting element.

[0277] For example, in part of the third sub-pixel M3, the solid portion 9641 on the substrate has the fourth overlapping area with the third conductive connection portion 963 on the substrate; the solid portion 9641 on the substrate has the fifth overlapping area with the third anode pattern 73 on the substrate.

[0278] For example, the second side of the third anode pattern 73 on the substrate at least partially overlaps with the third data line pattern 983 on the substrate in the sub-pixel to which it belongs, and at least partially overlaps with the first data line 981 adjacent in the first direction on the substrate; the first side of the third anode pattern 73 on the substrate overlaps with the solid portion on the substrate, and overlaps with the hollow portion on the substrate; and the first side and the second side are oppositely arranged in the first direction.

[0279] Exemplarily, the hollow portion 9642 is formed in a mouth-shaped form, and a first side of the third anode pattern 73 has a projection on the substrate which overlaps with projections on the substrate of two opposite sides of the hollow portion 9642 in the first direction.

[0280] The above arrangement enables the fourth conductive connection portion 964 to compensate for a step difference generated by the first data line pattern 981 and the third data line pattern 983 under the third anode pattern 73, so that the third anode pattern 73 can be formed on a relatively flat surface, thereby enabling the fifth anode pattern 75 to have a higher flatness and effectively reducing color cast phenomenon generated by the display substrate during display.

[0281] As shown in Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 indicate that, in some embodiments, in the seventh sub-pixel M7, the fourth conductive connection portion includes a solid portion and a hollow portion;

[0282] The projection on the substrate of the solid portion at least partially overlaps with the projection on the substrate of the anode pattern, and the projection on the substrate of the hollow portion does not overlap with the projection on the substrate of the anode pattern.

[0283] The projection on the substrate of the anode pattern at least partially overlaps with the projection on the substrate of the seventh data line pattern 987, and the projection on the substrate of the anode pattern at least partially overlaps with the projection on the substrate of the fifth data line pattern 985 adjacent to the seventh data line pattern 987 in the first direction.

[0284] Specifically, in the seventh sub-pixel M7, the light emitting element includes a seventh light emitting element, and the seventh light emitting element includes a seventh anode pattern 77, a seventh light emitting functional layer and a cathode which are sequentially stacked in a direction away from the substrate. Exemplarily, the seventh light emitting element includes a green light emitting element.

[0285] Exemplarily, in the seventh sub-pixel M7, the projection on the substrate of the solid portion 9641 has the fourth overlapping area with the projection on the substrate of the third conductive connection portion 963, and the projection on the substrate of the solid portion 9641 has the fifth overlapping area with the projection on the substrate of the seventh anode pattern 77.

[0286] For example, the orthographic projection of the second side of the seventh anode pattern 77 onto the substrate at least partially overlaps with the orthographic projection of the seventh data line pattern 987 in its corresponding sub-pixel onto the substrate; the orthographic projection of the second side of the seventh anode pattern 77 onto the substrate at least partially overlaps with the orthographic projection of the fifth data line pattern 985 adjacent along the first direction onto the substrate; the orthographic projection of the first side of the seventh anode pattern 77 onto the substrate overlaps with the orthographic projection of the solid portion onto the substrate; the first side and the second side are disposed opposite to each other along the first direction.

[0287] The above configuration enables the fourth conductive connection portion 964 to compensate for the step difference generated by the seventh data line pattern 987 and the fifth data line pattern 985 below the seventh anode pattern 77, so that the seventh anode pattern 77 can be formed on a relatively flat surface, thereby giving the seventh anode pattern 77 a high flatness and effectively reducing the color shift phenomenon generated by the display substrate during display.

[0288] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, in the eighth sub-pixel M8, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642.

[0289] The orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the hollow portion 9642 on the substrate both overlap at least partially with the orthographic projection of the anodized pattern on the substrate.

[0290] The orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the eighth data line pattern 988 on the substrate, nor with the orthographic projection of the sixth data line pattern 986 adjacent along the first direction on the substrate.

[0291] Specifically, in the eighth sub-pixel M8, the light-emitting element includes an eighth light-emitting element, which comprises an eighth anode pattern 78, an eighth light-emitting functional layer, and a cathode sequentially stacked along a direction away from the substrate. For example, the eighth light-emitting element includes a green light-emitting element.

[0292] For example, in part of the eighth sub-pixel M8, the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping region; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the eighth anode pattern 78 on the substrate have the fifth overlapping region.

[0293] For example, the orthographic projection of the second side of the eighth anode pattern 78 onto the substrate at least partially overlaps with the orthographic projection of the seventh data line pattern 987 adjacent to it along the second direction onto the substrate; the orthographic projection of the second side of the eighth anode pattern 78 onto the substrate at least partially overlaps with the orthographic projection of the fifth data line pattern 985 adjacent to the seventh data line pattern 987 along the first direction onto the substrate; the orthographic projection of the first side of the eighth anode pattern 78 onto the substrate overlaps with the orthographic projection of the solid portion onto the substrate, and also overlaps with the orthographic projection of the hollow portion onto the substrate; the first side and the second side are disposed opposite to each other along the first direction.

[0294] The above configuration enables the fourth conductive connection portion 964 to compensate for the step difference generated by the seventh data line pattern 987 and the fifth data line pattern 985 below the eighth anode pattern 78, so that the eighth anode pattern 78 can be formed on a relatively flat surface, thereby giving the eighth anode pattern 78 a high flatness and effectively reducing the color shift phenomenon generated by the display substrate during display.

[0295] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, in the fourth sub-pixel M4, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642;

[0296] The orthographic projection of the solid portion 9641 on the substrate at least partially overlaps with the orthographic projection of the anode pattern on the substrate, while the orthographic projection of the hollow portion 9642 on the substrate does not overlap with the orthographic projection of the anode pattern on the substrate.

[0297] The orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the fourth data line pattern 984 on the substrate, and the orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the second data line pattern 982 adjacent along the first direction on the substrate.

[0298] Specifically, in the fourth sub-pixel M4, the light-emitting element includes a fourth light-emitting element, which comprises a fourth anode pattern 74, a fourth light-emitting functional layer, and a cathode sequentially stacked along a direction away from the substrate. For example, the fourth light-emitting element includes a green light-emitting element.

[0299] Exemplarily, in the fourth sub-pixel M4, the orthogonal projection of the solid portion 9641 on the base has the fourth overlapping area with the orthogonal projection of the third conductive connection portion 963 on the base; and the orthogonal projection of the solid portion 9641 on the base has the fifth overlapping area with the orthogonal projection of the fourth anode pattern 74 on the base.

[0300] Exemplarily, the orthogonal projection of the second side of the fourth anode pattern 74 on the base at least partially overlaps with the orthogonal projection of the third data line pattern 983 adjacent to the second side of the fourth anode pattern 74 in the second direction on the base; the orthogonal projection of the second side of the fourth anode pattern 74 on the base at least partially overlaps with the orthogonal projection of the first data line pattern 981 adjacent to the third data line pattern 983 in the first direction on the base; the orthogonal projection of the first side of the fourth anode pattern 74 on the base overlaps with the orthogonal projection of the solid portion on the base and does not overlap with the orthogonal projection of the hollow portion on the base; and the first side and the second side are oppositely arranged in the first direction.

[0301] The above arrangement enables the fourth conductive connection portion 964 to compensate for the step difference caused by the first data line pattern 981 and the third data line pattern 983 under the fourth anode pattern 74, so that the fourth anode pattern 74 can be formed on a relatively flat surface, thereby making the fourth anode pattern 74 have a higher flatness and effectively reducing the color deviation phenomenon of the display substrate during display.

[0302] Notably, Figure 16 To Figure 12 a layout schematic diagram of an active layer in the display substrate; Figure 17 To Figure 12 a layout schematic diagram of a first gate metal layer in the display substrate; Figure 18 To Figure 12 a layout schematic diagram of a second gate metal layer in the display substrate; Figure 19 To Figure 12 a layout schematic diagram of a first source-drain metal layer in the display substrate. The active layer, the first gate metal layer, the second gate metal layer, and the first source-drain metal layer are sequentially stacked in a direction away from the base.

[0303] As Figure 5 , Figure 7 and Figure 18 shown in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include an anode pattern, an initialization signal line pattern 94, a shielding pattern 80, a driving transistor, a second transistor T2, and a seventh transistor T7.

[0304] The first electrode of the second transistor T2 is electrically connected with the initialization signal line pattern 94, and the second electrode of the second transistor T2 is electrically connected with the gate electrode of the driving transistor.

[0305] The first electrode of the seventh transistor T7 is electrically connected with the initialization signal line pattern 94' in the next sub-pixel adjacent to the second direction, and the second electrode of the seventh transistor T7 is electrically connected with the anode pattern in the sub-pixel.

[0306] The shielding pattern 80 is electrically connected with the power signal line pattern 91, and the orthogonal projection of the shielding pattern 80 on the substrate at least partially overlaps with the orthogonal projection of the first electrode of the second transistor T2 on the substrate.

[0307] Specifically, each of the sub-pixels further comprises an anode pattern, an initialization signal line pattern 94, a shielding pattern 80, a driving transistor, a second transistor T2 and a seventh transistor T7; the gate electrode of the second transistor T2 is electrically connected with the reset signal line pattern 95, the first electrode of the second transistor T2 is electrically connected with the initialization signal line pattern 94, the second electrode of the second transistor T2 is electrically connected with the gate electrode of the driving transistor, and the second transistor T2 is used for resetting the gate electrode of the driving transistor.

[0308] The gate electrode of the seventh transistor T7 is electrically connected with the reset signal line pattern 95' included in the next sub-pixel adjacent to the second direction of the sub-pixel, the first electrode of the seventh transistor T7 is electrically connected with the initialization signal line pattern 94' in the next sub-pixel adjacent to the second direction, the second electrode of the seventh transistor T7 is electrically connected with the anode pattern in the sub-pixel, and the seventh transistor T7 is used for resetting the anode pattern.

[0309] Each of the sub-pixels further comprises a shielding pattern 80, the orthogonal projection of the shielding pattern 80 on the substrate overlaps with the orthogonal projection of the power signal line pattern 91 on the substrate, and the shielding pattern 80 is electrically connected with the power signal line pattern 91 through the via hole arranged at the overlapping position. Specifically, the orthogonal projection of the shielding pattern 80 on the substrate overlaps with the orthogonal projection of the second part 912 of the power signal line pattern 91 on the substrate, and the shielding pattern 80 is directly electrically connected with the second part 912 of the power signal line pattern 91 through the via hole arranged at the overlapping position.

[0310] The above-mentioned electrical connection between the shielding pattern 80 and the power signal line pattern 91 makes the shielding pattern 80 have a stable potential, which not only helps the sub-pixel driving circuit to be in a stable working state, but also better guarantees the shielding effect of the shielding pattern 80.

[0311] By setting the orthographic projection of the shielding pattern 80 on the substrate to overlap with the orthographic projection of the first electrode of the second transistor T2 on the substrate, and / or, setting the orthographic projection of the shielding pattern 80 on the substrate to overlap with the orthographic projection of the first electrode of the seventh transistor T7 in the adjacent sub-pixel along the second direction on the substrate, the shielding pattern 80 shields the influence of data signal transitions on the first electrode of the second transistor T2 and / or the first electrode of the seventh transistor T7, thereby avoiding any impact on the initialization signal transmitted on the initialization signal line pattern 94.

[0312] like Figure 5 , Figure 7 and Figure 18 As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include: a first conductive connection portion and a fifth conductive connection portion 965;

[0313] In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor through the fifth conductive connection portion 965;

[0314] The first conductive connection portion 961 is electrically connected to the first terminal of the data writing transistor; the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor.

[0315] The orthographic projection of the shielding pattern 80 on the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion 961 on the substrate.

[0316] Specifically, in each sub-pixel, at least a portion of the fifth conductive connection portion 965 extends along the second direction. The orthographic projection of one end of the fifth conductive connection portion 965 onto the substrate and the orthographic projection of the second electrode of the second transistor T2 onto the substrate have a sixth overlapping region. One end of the fifth conductive connection portion 965 is electrically connected to the second electrode of the second transistor T2 through a via disposed in the sixth overlapping region. The orthographic projection of the other end of the fifth conductive connection portion 965 onto the substrate overlaps with the orthographic projection of the gate of the driving transistor onto the substrate. The other end of the fifth conductive connection portion 965 is electrically connected to the gate of the driving transistor through a via disposed at the overlapping region.

[0317] Each sub-pixel further includes a first conductive connection portion 961, exemplarily, at least a portion of the first conductive connection portion 961 extending along the second direction. The orthographic projection of a first end of the first conductive connection portion 961 onto the substrate has a first overlapping region with the orthographic projection of the corresponding data line protrusion 9802 onto the substrate, and the first end of the first conductive connection portion 961 and the data line protrusion 9802 are electrically connected through a via disposed in the first overlapping region. The orthographic projection of a second end of the first conductive connection portion 961 onto the substrate has a second overlapping region with the orthographic projection of the first electrode of the data writing transistor onto the substrate, and the second end of the first conductive connection portion 961 and the first electrode of the data writing transistor are electrically connected through a via disposed in the second overlapping region. The first electrode of the data writing transistor receives data signals provided by the corresponding data line pattern through the first conductive connection portion 961.

[0318] For example, the shielding pattern 80 includes a first shielding part 801 and a second shielding part 802 that are electrically connected. The orthographic projection of the first shielding part 801 on the substrate overlaps with the orthographic projection of the power signal line pattern 91 on the substrate. The first shielding part 801 and the power signal line pattern 91 are directly electrically connected through a via provided at the overlap.

[0319] For example, the first shielding part 801 and the second shielding part 802 are formed as an integral structure.

[0320] For example, the first shielding portion 801 is a square structure extending along the first direction, and the orthographic projection of the first shielding portion 801 on the substrate overlaps with the orthographic projection of the first electrode of the second transistor T2 on the substrate, and / or, the orthographic projection of the first shielding portion 801 on the substrate overlaps with the orthographic projection of the first electrode of the seventh transistor T7 in the adjacent sub-pixel along the second direction on the substrate.

[0321] For example, the orthographic projection of the first shielding portion 801 on the substrate does not overlap with the orthographic projection of the reset signal line pattern 95 on the substrate.

[0322] For example, the orthographic projection of the first shielding portion 801 in the shielding pattern 80 onto the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion 961 onto the substrate.

[0323] like Figure 5 As shown, in some embodiments, at least a portion of the shielding pattern 80 is projected onto the substrate in an orthographic projection between the first conductive connection 961 and the fifth conductive connection 965 on the substrate.

[0324] As shown in Figure 13b The second shielding part 802 in the shielding pattern 80 is located between the second overlap area and the sixth overlap area in the orthogonal projection on the substrate.

[0325] The second shielding part 802 is a square structure extending along the second direction.

[0326] The above arrangement can better shield the influence of the data signal change on the second electrode of the second transistor T2, and further avoid the influence of the data signal change on the gate signal of the driving transistor. Since the gate signal of the driving transistor directly affects the brightness of the sub-pixel, the above arrangement makes the gate potential of the driving transistor more stable, so that the display substrate can obtain better display effect when used for display.

[0327] As shown in Figure 5 , Figure 7 and Figure 18 In some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 each include a first transistor T1.

[0328] In each sub-pixel, the first electrode of the first transistor T1 is electrically connected to the second electrode of the driving transistor, and the second electrode of the first transistor T1 is electrically connected to the gate electrode of the driving transistor.

[0329] The active pattern of the first transistor T1 includes two semiconductor parts arranged at intervals, and a first conductor part respectively connecting the two semiconductor parts.

[0330] The projection of the shielding pattern 80 on the substrate at least partially overlaps the orthogonal projection of the first conductor part on the substrate.

[0331] Specifically, each of the sub-pixels further includes a first transistor T1, the gate electrode of the first transistor T1 is electrically connected to the gate line pattern 92, the first electrode of the first transistor T1 is electrically connected to the second electrode of the driving transistor, and the second electrode of the first transistor T1 is electrically connected to the gate electrode of the driving transistor.

[0332] The first transistor T1 is formed in a double-gate structure, the active pattern of the first transistor T1 includes two semiconductor parts arranged at intervals, and a first conductor part respectively connecting the two semiconductor parts, the orthogonal projection of the gate electrode of the first transistor T1 on the substrate covers the orthogonal projection of the two semiconductor parts on the substrate, and the orthogonal projection of the gate electrode of the first transistor T1 on the substrate does not overlap the orthogonal projection of the first conductor part on the substrate.

[0333] Exemplarily, the shielding pattern 80 further includes a third shielding portion 803 electrically connected with the first shielding portion 801, and at least part of the third shielding portion 803 is a square structure extending along the second direction.

[0334] Exemplarily, the first shielding portion 801 and the third shielding portion 803 are formed as an integral structure.

[0335] Exemplarily, the shielding pattern 80 further includes a third shielding portion 803 electrically connected with the first shielding portion 801, and a projection of the third shielding portion 803 on the substrate overlaps with a projection of the first conductor portion on the substrate.

[0336] The projection of the third shielding portion 803 on the substrate overlaps with the projection of the first conductor portion on the substrate. In this way, the third shielding pattern 80 can shield the first conductor portion, so that the change of the data signal does not affect the first transistor T1, and the change of the data signal does not affect the gate signal of the driving transistor.

[0337] In some embodiments, the shielding pattern 80 is located between the first electrode of the second transistor T2 and the first conductive connection portion 961 along a direction perpendicular to the substrate.

[0338] Exemplarily, the display substrate further includes a second gate insulating layer located between the first electrode of the second transistor T2 and the first conductive connection portion 961, and in each sub-pixel, the initialization signal line pattern 94 and the shielding pattern 80 are located on a surface of the second gate insulating layer away from the substrate.

[0339] In this way, the initialization signal line pattern 94 and the shielding pattern 80 are located on the surface of the second gate insulating layer away from the substrate, so that the initialization signal line pattern 94 and the shielding pattern 80 are formed in the same layer. When the initialization signal line pattern 94 and the shielding pattern 80 are made of the same material, the initialization signal line pattern 94 and the shielding pattern 80 can be formed in the same patterning process, so that the manufacturing process of the display substrate is simplified and the manufacturing cost is saved.

[0340] As Figure 2 , Figure 5 and Figure 12As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 each comprises a light emitting element, an initialization signal line pattern 94, a reset signal line pattern 95, a gate line pattern 92 and a light emitting control signal line pattern 93; at least part of the initialization signal line pattern 94, at least part of the reset signal line pattern 95, at least part of the gate line pattern 92 and at least part of the light emitting control signal line pattern 93 each extend along the first direction;

[0341] The first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 each further comprises a first transistor T1, a second transistor T2, a driving transistor (such as a third transistor), a data writing transistor (such as a fourth transistor), a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst;

[0342] In each sub-pixel, a gate of the driving transistor is electrically connected with a second electrode of the first transistor T1, a first electrode of the driving transistor is electrically connected with a second electrode of the fifth transistor T5, and a second electrode of the driving transistor is electrically connected with a first electrode of the first transistor T1;

[0343] A gate of the first transistor T1 is electrically connected with the gate line pattern 92;

[0344] A gate of the second transistor T2 is electrically connected with the reset signal line pattern 95, a first electrode of the second transistor T2 is electrically connected with the initialization signal line pattern 94, and a second electrode of the second transistor T2 is electrically connected with the gate of the driving transistor;

[0345] A gate of the data writing transistor is electrically connected with the gate line pattern 92, a first electrode of the data writing transistor is electrically connected with a data line pattern included in the sub-pixel, and a second electrode of the data writing transistor is electrically connected with the first electrode of the driving transistor;

[0346] A gate of the fifth transistor T5 is electrically connected with the light emitting control signal line pattern 93, and a first electrode of the fifth transistor T5 is electrically connected with the power signal line pattern 91;

[0347] A gate of the sixth transistor T6 is electrically connected with the light emitting control signal line pattern 93, a first electrode of the sixth transistor T6 is electrically connected with the second electrode of the driving transistor, and a second electrode of the sixth transistor T6 is electrically connected with the light emitting element;

[0348] The gate of the seventh transistor T7 is electrically connected with the reset signal line pattern 95 in the next sub-pixel adjacent along the second direction, the first pole of the seventh transistor T7 is electrically connected with the initialization signal line pattern 94 in the next sub-pixel adjacent along the second direction, and the second pole of the seventh transistor T7 is electrically connected with the light emitting element;

[0349] The first pole plate of the storage capacitor is multiplexed as the gate of the driving transistor, and the second pole plate of the storage capacitor is electrically connected with the power signal line pattern 91.

[0350] Exemplarily, each sub-pixel in the display substrate includes a sub-pixel driving circuit, and each sub-pixel driving circuit includes a first transistor T1, a second transistor T2, a driving transistor (such as a third transistor), a data writing transistor (such as a fourth transistor), a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, a first conductive connection part 961, a second conductive connection part 962, a third conductive connection part 963, a fourth conductive connection part 964, and a fifth conductive connection part 965, etc.

[0351] Specifically, the plurality of sub-pixels can be divided into a plurality of rows of sub-pixels arranged in sequence along the second direction and a plurality of columns of sub-pixels arranged in sequence along the first direction, the initialization signal line patterns 94 included in the sub-pixels in the same row are electrically connected in sequence and formed into an integrated structure, the gate line patterns 92 included in the sub-pixels in the same row are electrically connected in sequence and formed into an integrated structure, the light emitting control signal line patterns 93 included in the sub-pixels in the same row are electrically connected in sequence and formed into an integrated structure, the reset signal line patterns 95 included in the sub-pixels in the same row are electrically connected in sequence and formed into an integrated structure, the first data line patterns 981 included in the sub-pixels in the same column are electrically connected in sequence and formed into an integrated structure, the second data line patterns 982 included in the sub-pixels in the same column are electrically connected in sequence and formed into an integrated structure, and the power signal line patterns 91 included in the sub-pixels in the same column are electrically connected in sequence and formed into an integrated structure.

[0352] As shown in FIG. 1, taken one sub-pixel driving circuit as an example, the sub-pixel driving circuit includes 7 thin film transistors and 1 capacitor. Figure 2 As shown in FIG. 1, taken one sub-pixel driving circuit as an example, the sub-pixel driving circuit includes 7 thin film transistors and 1 capacitor.

[0353] The first transistor T1 is a double-gate structure, the gate 201g of the first transistor T1 is electrically connected with the gate line pattern 92, the source S1 of the first transistor T1 is electrically connected with the drain D3 of the third transistor T3 (i.e. the driving transistor), and the drain D1 of the first transistor T1 is electrically connected with the gate 203g of the third transistor T3.

[0354] The second transistor T2 has a dual-gate structure. The gate 202g of the second transistor T2 is electrically connected to the reset signal line pattern 95, the source S2 of the second transistor T2 is electrically connected to the initialization signal line pattern 94, and the drain D2 of the second transistor T2 is electrically connected to the gate 203g of the third transistor T3.

[0355] The gate 204g of the fourth transistor T4 (i.e., the data write transistor) is electrically connected to the gate line pattern 92, the source S4 of the fourth transistor T4 is electrically connected to the first data line pattern 981 or the second data line pattern 982, and the drain D4 of the fourth transistor T4 is electrically connected to the source S3 of the third transistor T3.

[0356] The gate 205g of the fifth transistor T5 is electrically connected to the light-emitting control signal line pattern 93, the source S5 of the fifth transistor T5 is electrically connected to the power supply signal line pattern 91, and the drain D5 of the fifth transistor T5 is electrically connected to the source S3 of the third transistor T3.

[0357] The gate 206g of the sixth transistor T6 is electrically connected to the light-emitting control signal line pattern 93, the source S6 of the sixth transistor T6 is electrically connected to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL.

[0358] The gate 207g of the seventh transistor T7 is electrically connected to the reset signal line pattern 95' in the next sub-pixel adjacent to the second direction, the drain D7 of the seventh transistor T7 is electrically connected to the anode of the corresponding light-emitting element EL, and the source S7 of the seventh transistor T7 is electrically connected to the initialization signal line pattern 94' in the next sub-pixel adjacent to the second direction.

[0359] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is electrically connected to the power signal line pattern 91.

[0360] like Figure 3 As shown, when the sub-pixel driving circuit of the above structure is working, each working cycle includes a reset period P1, a write compensation period P2, and a light emission period P3. Figure 3 In this context, E1 represents the light emission control signal transmitted on the light emission control signal line pattern 93 in the current sub-pixel, R1 represents the reset signal transmitted on the reset signal line pattern 95 in the current sub-pixel, D1 represents the data signal transmitted on the target data line pattern in the current sub-pixel, G1 represents the gate scan signal transmitted on the gate line pattern 92 in the current sub-pixel, and R1' represents the reset signal transmitted on the reset signal line pattern 95' in the next sub-pixel adjacent to the current sub-pixel along the second direction.

[0361] In the first reset period P1, the reset signal input by the reset signal line pattern 95 is at an active level, the second transistor T2 is turned on, and the initialization signal transmitted by the initialization signal line pattern 94 is input to the gate 203g of the third transistor T3, so that the gate-source voltage Vgs of the previous frame kept on the third transistor T3 is cleared, and the reset of the gate 203g of the third transistor T3 is realized.

[0362] In the write compensation period P2, the reset signal input by the reset signal line pattern 95 is at an inactive level, the second transistor T2 is turned off, the gate scanning signal input by the gate line pattern 92 is at an active level, the first transistor T1 and the fourth transistor T4 are controlled to be turned on, the target data signal is input by the data line pattern, and is transmitted to the source S3 of the third transistor T3 through the fourth transistor T4. At the same time, the first transistor T1 and the fourth transistor T4 are turned on, so that the third transistor T3 forms a diode structure, and thus the threshold voltage compensation of the third transistor T3 is realized through the cooperation of the first transistor T1, the third transistor T3 and the fourth transistor T4. When the compensation time is long enough, the gate 203g potential of the third transistor T3 can finally reach Vdata+Vth, where Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3.

[0363] In the write compensation period P2, the reset signal input by the reset signal line pattern 95 is at an inactive level, the second transistor T2 is turned off, the gate scanning signal input by the gate line pattern 92 is at an active level, the first transistor T1 and the fourth transistor T4 are controlled to be turned on, the target data signal is input by the data line pattern, and is transmitted to the source S3 of the third transistor T3 through the fourth transistor T4. At the same time, the first transistor T1 and the fourth transistor T4 are turned on, so that the third transistor T3 forms a diode structure, and thus the threshold voltage compensation of the third transistor T3 is realized through the cooperation of the first transistor T1, the third transistor T3 and the fourth transistor T4. When the compensation time is long enough, the gate 203g potential of the third transistor T3 can finally reach Vdata+Vth, where Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3.

[0364] In the light emitting period P3, the light emitting control signal input by the light emitting control signal line pattern 93 is at an active level, the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the power signal line pattern 91 is input to the source S3 of the third transistor T3. At the same time, the gate 203g of the third transistor T3 is kept at Vdata+Vth, so that the third transistor T3 is turned on, the corresponding gate-source voltage of the third transistor T3 is Vdata+Vth-VDD, VDD is the voltage value corresponding to the power signal, the drain current generated based on the gate-source voltage flows to the anode of the corresponding light emitting element EL, and the corresponding light emitting element EL is driven to emit light.

[0365] As Figures 6-8 , Figure 10 As shown in FIG. 13, when the above-mentioned sub-pixel is manufactured, the layout of each film layer corresponding to the sub-pixel is as follows:

[0366] The active film layer, the first gate insulating layer GI1, the first gate metal layer, the second gate insulating layer GI2, the second gate metal layer, the interlayer insulating layer ILD, the first source-drain metal layer, the first planar layer PLN1, the second source-drain metal layer, the second planar layer PLN2 and the anode layer are sequentially stacked in the direction away from the substrate.

[0367] As shown in Figure 6 , the active film layer is used to form the channel region (the part covered by the gate of each transistor) of each transistor in the sub-pixel driving circuit, the source (such as S1-S7) and the drain (such as D1-D7) of each transistor. The active film layer corresponding to the source and the drain has better conductivity than the active film layer corresponding to the channel region due to the doping effect. The active film layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor material, etc. It should be noted that the source and the drain can be doped with n-type impurities or p-type impurities.

[0368] As shown in Figure 6 , the first gate metal layer is used to form the gate (such as 201g-207g) of each transistor in the sub-pixel driving circuit, and the gate line pattern 92, the light-emitting control signal line pattern 93, the reset signal line pattern 95 and other structures included in the sub-pixel. The gate 203g of the third transistor T3 in each sub-pixel driving circuit is multiplexed as the first plate Cst1 of the second storage capacitor Cst in the sub-pixel driving circuit.

[0369] As shown in Figure 7 , the second gate metal layer is used to form the second plate Cst2 of the second storage capacitor Cst, the initialization signal line pattern 94 included in the sub-pixel, and the shielding pattern 80.

[0370] As shown in Figure 8 , the first source-drain metal layer is used to form the power signal line pattern 91 included in the sub-pixel, the power compensation pattern and some conductive connection parts.

[0371] As shown in Figure 11 , the second source-drain metal layer is used to form the first data line pattern 981, the second data line pattern 982 and some conductive connection parts included in the sub-pixel.

[0372] In addition, as shown in Figure 5As shown, in the display substrate provided by the present disclosure, in the second direction, the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1 and the gate 202g of the second transistor T2 are all located on the first side of the gate of the driving transistor (i.e. the gate 203g of the third transistor T3), and the gate of the seventh transistor T7, the gate 206g of the sixth transistor T6 and the gate of the fifth transistor T5 are all located on the second side of the gate of the driving transistor. Exemplarily, the first side and the second side of the gate of the driving transistor are two sides opposite in the second direction, and further, the first side of the gate of the driving transistor can be the upper side of the gate of the driving transistor, and the second side of the gate of the driving transistor can be the lower side of the gate of the driving transistor. The lower side, for example, the side of the display substrate for binding IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor closer to the IC. The upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor farther away from the IC.

[0373] In the first direction, the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, and the gate 201g of the first transistor T1 and the gate 206g of the sixth transistor T6 are both located on the fourth side of the gate of the driving transistor. Exemplarily, the third side and the fourth side of the gate of the driving transistor are two sides opposite in the first direction; further, the third side of the gate of the driving transistor can be the right side of the gate of the driving transistor, and the fourth side of the gate of the driving transistor can be the left side of the gate of the driving transistor. The left side and the right side, for example, in the same sub-pixel, the second data line pattern 982 is located on the right side of the gate of the driving transistor, and the first data line pattern 981 is located on the left side of the gate of the driving transistor.

[0374] The display device provided by the present disclosure also includes the display substrate provided by the above-mentioned embodiments.

[0375] In the display substrate provided by the above-mentioned embodiments, the overlapping area between the orthographic projection of the second data line pattern on the substrate and the orthographic projection of the power signal line pattern 91 on the substrate is effectively reduced, so that the overlapping area between the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the functional pattern with fixed potential on the substrate and the overlapping area between the orthographic projection of the second data line pattern on the substrate and the orthographic projection of the functional pattern with fixed potential on the substrate are close, thereby effectively reducing the load difference between the first data line pattern 981 and the second data line pattern, and better improving the display picture quality of the display substrate.

[0376] Therefore, the display device provided by the embodiments of the present disclosure has the above-mentioned beneficial effects when including the display substrate, and can achieve higher picture display quality.

[0377] It should be noted that the display device can be any product or component with display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer, etc.

[0378] The embodiments of the present disclosure also provide a manufacturing method of a display substrate, including: manufacturing a plurality of sub-pixels in an array distribution on a substrate; the plurality of sub-pixels include:

[0379] The first sub-pixel and the second sub-pixel arranged along a second direction, the first sub-pixel including a first data line pattern, the second sub-pixel including a second data line pattern, at least part of the first data line pattern and at least part of the second data line pattern extending along the second direction, the first data line pattern being located at a first side of a same column of sub-pixels extending along the second direction, the second data line pattern being located at a second side of the same column of sub-pixels extending along the second direction, the first side being opposite to the second side along a first direction, the first direction intersecting the second direction;

[0380] The first data line pattern is configured to provide a first data signal to the first sub-pixel, and the second data line pattern is configured to provide a second data signal to the second sub-pixel;

[0381] The first sub-pixel and the second sub-pixel both include:

[0382] A power signal line pattern, at least part of the power signal line pattern extending along the second direction, the power signal line pattern including a power main body part, the power main body part including a first part and a second part electrically connected, the second part protruding from the first part along the first direction;

[0383] In the first sub-pixel, a projection of the first part on the substrate overlaps a projection of a data line main body part of a data line pattern in a sub-pixel adjacent along the first direction on the substrate, and a projection of the second part on the substrate does not overlap a projection of the data line main body part of the data line pattern in the sub-pixel adjacent along the first direction on the substrate;

[0384] In the second sub-pixel, a projection of the second data line pattern on the substrate overlaps a projection of the first part in a sub-pixel adjacent along the first direction on the substrate, and a projection of the second data line pattern on the substrate does not overlap a projection of the second part in the sub-pixel adjacent along the first direction on the substrate.

[0385] The display substrate manufactured by the manufacturing method provided in the embodiment of the present disclosure effectively reduces the overlapping area between the orthographic projection of the second data line pattern on the substrate and the orthographic projection of the power signal line pattern 91 on the substrate, so that the overlapping area between the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate and the overlapping area between the orthographic projection of the second data line pattern on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate are close, thereby effectively reducing the load difference between the first data line pattern 981 and the second data line pattern, and better improving the display picture quality of the display substrate.

[0386] It should be noted that each of the embodiments in the present specification is described in a progressive manner, and the same or similar parts between each embodiment can be referred to each other, and each embodiment mainly describes the difference from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, it is described more simply, and the relevant part can be referred to the part of the description of the product embodiment.

[0387] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as the common meaning of the same to those having ordinary skills in the art to which the present disclosure belongs. The terms "first", "second" and similar words used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different components. The terms "include" or "contain" and similar words mean that the elements or objects before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The terms "connect", "couple" or "link" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right" and the like only represent relative positional relationships, which can change accordingly when the absolute position of the described object changes.

[0388] It can be understood that when an element such as a layer, a film, a region or a substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0389] In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0390] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising: A substrate and a plurality of sub-pixels distributed on the substrate, the plurality of sub-pixels comprising: a first sub-pixel and a second sub-pixel arranged along a second direction, the first sub-pixel comprising a first data line pattern, the second sub-pixel comprising a second data line pattern, at least part of the first data line pattern and at least part of the second data line pattern each extending along the second direction, the first data line pattern being located at a first side of a same column of first sub-pixels extending along the second direction, the second data line pattern being located at a second side of a same column of second sub-pixels extending along the second direction, the first side being opposite to the second side along a first direction, the first direction intersecting the second direction; the first data line pattern being configured to provide a first data signal to the first sub-pixel, the second data line pattern being configured to provide a second data signal to the second sub-pixel; the first sub-pixel and the second sub-pixel each comprising: a power signal line pattern, at least part of the power signal line pattern extending along the second direction, the power signal line pattern comprising a power body portion, the power body portion comprising a first portion and a second portion electrically connected, the second portion protruding out of the first portion along the first direction; in the first sub-pixel, a projection of the first portion on the substrate overlaps with a projection of a data line body portion of a data line pattern in an adjacent sub-pixel along the first direction, a projection of the second portion on the substrate does not overlap with a projection of a data line body portion of a data line pattern in an adjacent sub-pixel along the first direction; a projection of the first data line pattern on the substrate does not overlap with a projection of the first portion on the substrate; in the second sub-pixel, a projection of a data line body portion of the second data line pattern on the substrate overlaps with a projection of the first portion on the substrate in an adjacent sub-pixel along the first direction, a projection of a data line body portion of the second data line pattern on the substrate does not overlap with a projection of the second portion on the substrate in an adjacent sub-pixel along the first direction. 2.The display substrate of claim 1, wherein, the plurality of sub-pixels further comprising: a third sub-pixel and a fourth sub-pixel arranged along a second direction, along the first direction, the third sub-pixel being located in a same row as the first sub-pixel, the fourth sub-pixel being located in a same row as the second sub-pixel; the third sub-pixel comprising a third data line pattern, the fourth sub-pixel comprising a fourth data line pattern, at least part of the third data line pattern and at least part of the fourth data line pattern each extending along the second direction, the third data line pattern being located at a second side of a same column of third sub-pixels extending along the second direction, the fourth data line pattern being located at a first side of a same column of fourth sub-pixels extending along the second direction; the third sub-pixel and the fourth sub-pixel each comprising: the power signal line pattern; In the first sub-pixel, the normal projection of the first portion on the base overlaps with the normal projection of a data line main portion of a third data line pattern adjacent to the first data line pattern in the first direction on the base, and the normal projection of the second portion on the base does not overlap with the normal projection of the data line main portion of the third data line pattern on the base.

3. The display substrate of claim 2, wherein The power signal line pattern further comprises a power protruding portion electrically connected with the power main portion; In the first sub-pixel, the normal projection of the power protruding portion on the base overlaps with the normal projection of the first data line pattern on the base.

4. The display substrate of claim 2, wherein The power signal line pattern further comprises a power protruding portion electrically connected with the power main portion; In the fourth sub-pixel, the normal projection of the power protruding portion on the base overlaps with the normal projection of the fourth data line pattern on the base.

5. The display substrate of claim 2, wherein The first data line pattern, the second data line pattern, the third data line pattern and the fourth data line pattern each comprise a data line main portion and a data line protruding portion, the data line main portion extends along the second direction, and the data line protruding portion protrudes from the data line main portion along the first direction; The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each comprise a first conductive connection portion and a data write transistor, In each sub-pixel, the data line protruding portion is electrically connected with a first electrode of the data write transistor through the first conductive connection portion, and the normal projection of the second portion on the base overlaps with the first conductive connection portion arranged along the first direction. 6.The display substrate of claim 2, wherein, The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each comprise: an initialization signal line pattern, a second transistor, a driving transistor and a second conductive connection portion; At least part of the initialization signal line pattern extends along the second direction, and the initialization signal line pattern is used for transmitting an initialization signal; A first electrode of the second transistor is electrically connected with the initialization signal line pattern through the second conductive connection portion, and a second electrode of the second transistor is electrically connected with a gate electrode of the driving transistor; In the first sub-pixel, the normal projection of the second conductive connection portion on the base overlaps with the normal projection of the first data line pattern on the base; In the third sub-pixel, the normal projection of the second conductive connection portion on the base does not overlap with the normal projection of the third data line pattern on the base.

7. The display substrate of claim 6, wherein, In the second sub-pixel, the normal projection of the second conductive connection portion on the base does not overlap with the normal projection of the second data line pattern on the base; In the fourth sub-pixel, the normal projection of the second conductive connection portion on the base overlaps with the normal projection of the fourth data line pattern on the base. 8.The display substrate of claim 3, wherein, The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each comprise: A power signal line pattern, at least part of the power signal line pattern extending along the second direction; A power compensation pattern, at least part of the power compensation pattern extending along the first direction, the power compensation pattern and the power signal line pattern being located on a surface of the display substrate opposite to the base; In each of the sub-pixels, the power compensation pattern is electrically connected with the power signal line pattern in the sub-pixel to which the power compensation pattern belongs and the power signal line pattern in the sub-pixel adjacent to the sub-pixel in the first direction.

9. The display substrate of claim 8, wherein The power compensation pattern included in the third sub-pixel is electrically connected with the power signal line pattern included in the third sub-pixel and the power signal line pattern in the first sub-pixel adjacent to the third sub-pixel in the first direction; 10.The display substrate of claim 8, wherein, The power compensation pattern included in the fourth sub-pixel is electrically connected with the power signal line pattern included in the fourth sub-pixel and the power signal line pattern in the second sub-pixel adjacent to the fourth sub-pixel in the first direction. 11.The display substrate of claim 8, wherein, The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include a reset signal line pattern, a gate line pattern and a light-emitting control signal line pattern distributed along the second direction; at least part of the reset signal line pattern extends along the first direction, at least part of the gate line pattern extends along the first direction, and at least part of the light-emitting control signal line pattern extends along the first direction; in the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, a projection of the power compensation pattern on the base is located between a projection of the gate line pattern on the base and a projection of the light-emitting control signal line pattern on the base. In the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, at least part of the power protruding portion extends along the second direction, and a gap is formed between the power protruding portion and the power main portion; a first end of the power compensation pattern is electrically connected with the power protruding portion; 12.The display substrate of claim 1, wherein, A second end of the power compensation pattern is electrically connected with the power main portion in the sub-pixel adjacent to the sub-pixel in the first direction. The first sub-pixel includes a sixth transistor, a third conductive connection portion, a fourth conductive connection portion and a light-emitting element stacked in a direction away from the base; the light-emitting element includes a first anode pattern; a second electrode of the sixth transistor is electrically connected with the first anode pattern through the third conductive connection portion and the fourth conductive connection portion; In at least part of the first sub-pixel, The fourth conductive connection portion includes a solid portion; A projection of the solid portion on the base at least partially overlaps with a projection of the first anode pattern on the base; A projection of the first anode pattern on the base does not overlap with a projection of the first data line pattern on the base. 13.The display substrate of claim 1, wherein, The second sub-pixel comprises a sixth transistor, and a third conductive connection part, a fourth conductive connection part and a light emitting element arranged in a stack along a direction away from the substrate; the light emitting element comprises a second anode pattern; a second electrode of the sixth transistor is electrically connected with the second anode pattern through the third conductive connection part and the fourth conductive connection part; In at least part of the second sub-pixel, A normal projection of the second anode pattern on the substrate overlaps with a normal projection of the second data line pattern on the substrate. 14.The display substrate of claim 2, wherein, The third sub-pixel comprises a sixth transistor, and a third conductive connection part, a fourth conductive connection part and a light emitting element arranged in a stack along a direction away from the substrate; the light emitting element comprises a third anode pattern; a second electrode of the sixth transistor is electrically connected with the third anode pattern through the third conductive connection part and the fourth conductive connection part; In part of the third sub-pixel, The fourth conductive connection part comprises a solid part and a hollow part; A normal projection of the third anode pattern on the substrate overlaps with a normal projection of the third data line pattern on the substrate, and overlaps with a normal projection of a data line pattern adjacent to the third data line pattern in a first direction on the substrate; A normal projection of the third anode pattern on the substrate overlaps with a normal projection of the solid part on the substrate; And / or, a normal projection of the third anode pattern on the substrate overlaps with a normal projection of the hollow part on the substrate. 15.The display substrate of claim 2, wherein, The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each comprise an anode pattern, an initialization signal line pattern, a shielding pattern, a driving transistor, a second transistor and a seventh transistor; In the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, a first electrode of the second transistor is electrically connected with the initialization signal line pattern, and a second electrode of the second transistor is electrically connected with a gate electrode of the driving transistor; A first electrode of the seventh transistor is electrically connected with an initialization signal line pattern in a next sub-pixel adjacent to the second direction, and a second electrode of the seventh transistor is electrically connected with an anode pattern in the sub-pixel to which the seventh transistor belongs; The shielding pattern is electrically connected with the power signal line pattern, and a normal projection of the shielding pattern on the substrate overlaps with a normal projection of the first electrode of the second transistor on the substrate. 16.The display substrate of claim 15, wherein, The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each comprise a first conductive connection part and a fifth conductive connection part, In the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, a second electrode of the second transistor is electrically connected with the gate electrode of the driving transistor through the fifth conductive connection part; The first conductive connection part is electrically connected with a first electrode of a data writing transistor, and a second electrode of the data writing transistor is electrically connected with a first electrode of the driving transistor; A normal projection of the shielding pattern on the substrate at least partially overlaps with a normal projection of the first conductive connection part on the substrate. 17.The display substrate of claim 16, wherein, A normal projection of at least part of the shielding pattern on the substrate is located between a normal projection of the first conductive connection on the substrate and a normal projection of the fifth conductive connection on the substrate.

18. The display substrate of claim 15, wherein, The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include a first transistor; In each sub-pixel, a first electrode of the first transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the first transistor is electrically connected to a gate electrode of the driving transistor; An active pattern of the first transistor includes two semiconductor portions arranged at intervals, and a first conductor portion connecting the two semiconductor portions respectively; A projection of the shielding pattern on the substrate also at least partially overlaps a normal projection of the first conductor portion on the substrate.

19. The display substrate of claim 15, wherein, The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include a first conductive connection; in the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, the shielding pattern is located between a first electrode of the second transistor and the first conductive connection in a direction perpendicular to the substrate. 20.The display substrate of claim 2, wherein, The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each include a light emitting element, an initialization signal line pattern, a reset signal line pattern, a gate line pattern and a light emitting control signal line pattern; at least part of the initialization signal line pattern, at least part of the reset signal line pattern, at least part of the gate line pattern and at least part of the light emitting control signal line pattern each extend in the first direction; The first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel each further include a first transistor, a second transistor, a driving transistor, a data writing transistor, a fifth transistor, a sixth transistor, a seventh transistor and a storage capacitor; In each sub-pixel, a gate electrode of the driving transistor is electrically connected to a second electrode of the first transistor, a first electrode of the driving transistor is electrically connected to a second electrode of the fifth transistor, and a second electrode of the driving transistor is electrically connected to a first electrode of the first transistor; A gate electrode of the first transistor is electrically connected to the gate line pattern; A gate electrode of the second transistor is electrically connected to the reset signal line pattern, a first electrode of the second transistor is electrically connected to the initialization signal line pattern, and a second electrode of the second transistor is electrically connected to the gate electrode of the driving transistor; A gate electrode of the data writing transistor is electrically connected to the gate line pattern, a first electrode of the data writing transistor is electrically connected to a data line pattern in the sub-pixel, and a second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor; A gate electrode of the fifth transistor is electrically connected to the light emitting control signal line pattern, and a first electrode of the fifth transistor is electrically connected to the power supply signal line pattern; a gate of the sixth transistor is electrically connected with the light-emitting control signal line pattern, a first electrode of the sixth transistor is electrically connected with the second electrode of the driving transistor, and a second electrode of the sixth transistor is electrically connected with the light-emitting element; a gate of the seventh transistor is electrically connected with a reset signal line pattern in a next sub-pixel adjacent to the second direction, a first electrode of the seventh transistor is electrically connected with the initialization signal line pattern in the next sub-pixel adjacent to the second direction, and a second electrode of the seventh transistor is electrically connected with the light-emitting element; a first plate of the storage capacitor is multiplexed as a gate of the driving transistor, and a second plate of the storage capacitor is electrically connected with the power signal line pattern.

21. A display device, comprising the display substrate according to any one of claims 1 to 20.

22. A method for manufacturing a display substrate, comprising: manufacturing a plurality of sub-pixels distributed in an array on a substrate; the plurality of sub-pixels comprises: a first sub-pixel and a second sub-pixel arranged along a second direction, the first sub-pixel comprises a first data line pattern, and the second sub-pixel comprises a second data line pattern, at least part of the first data line pattern and at least part of the second data line pattern extend along the second direction, the first data line pattern is located at a first side of a same column of sub-pixels extending along the second direction, the second data line pattern is located at a second side of the same column of sub-pixels extending along the second direction, the first side and the second side are opposite along a first direction, and the first direction intersects the second direction; the first data line pattern is configured to provide a first data signal to the first sub-pixel, and the second data line pattern is configured to provide a second data signal to the second sub-pixel; the first sub-pixel and the second sub-pixel each comprise: a power signal line pattern, at least part of the power signal line pattern extends along the second direction, and the power signal line pattern comprises a power main part, the power main part comprises a first part and a second part which are electrically connected, and the second part protrudes from the first part along the first direction; in the first sub-pixel, a projection of the first part on the substrate overlaps a projection of a data line main part of a data line pattern in a sub-pixel adjacent to the first direction on the substrate, and a projection of the second part on the substrate does not overlap a projection of a data line main part of a data line pattern in a sub-pixel adjacent to the first direction on the substrate; and a projection of the first data line pattern on the substrate does not overlap a projection of the first part on the substrate; in the second sub-pixel, a projection of the second data line pattern on the substrate overlaps a projection of the first part on the substrate in a sub-pixel adjacent to the first direction, and a projection of the second data line pattern on the substrate does not overlap a projection of the second part on the substrate in a sub-pixel adjacent to the first direction.

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