Thread group scheduling method and device for GPU (Graphics Processing Unit), graphics processing unit and equipment

Abstract

The invention discloses a thread group scheduling method and device for a GPU (Graphics Processing Unit), the GPU and equipment. The method comprises the following steps of: 1) receiving a scheduling request of a thread group; 2) task type priority scheduling; according to a thread group weight value set by a user, obtaining execution priorities of the vertex thread group and the fragment thread group in the current scheduling period; 3) instruction type priority scheduling; pre-analyzing to-be-executed instructions of the thread group, and determining a priority sequence of schedulable instruction types; and 4) priority scheduling of the thread groups: selecting the thread group with the highest priority for scheduling according to the specified task type priority and instruction type priority in combination with the thread group generation time. The invention provides a thread group three-level scheduling strategy so as to improve the instruction throughput rate and the key task response speed of the GPU under the complex load.

Description

Technical Field

[0001] This invention relates to computer technology, and more particularly to a thread group scheduling method, apparatus, graphics processor, and device for GPUs. Background Technology

[0002] The GPU (Graphics Processing Unit) unified rendering architecture adopts a SIMT (Single Instruction Multiple Threads) architecture, replacing dedicated units with unified programmable cores. It executes the same instruction in parallel through thread groups (Warp / Wavefront), with each thread independently handling data and control flow. Threads are organized and scheduled using thread groups (Warp or Wavefront) as the basic unit, aiming to improve computational throughput, hide memory latency, maximize hardware utilization, and reduce the waiting time of long-latency operations, making it key to performance optimization.

[0003] Patent CN119902875A proposes an adaptive collaborative optimization method that combines Warp scheduling with cache replacement. It dynamically detects Warp access behavior in the L1 data cache through a locality-aware unit, identifies the locality preference of the workload, and adaptively selects a Warp scheduling algorithm based on the locality preference. The scheduling algorithm is selected between the GTO algorithm and the LRR algorithm.

[0004] CN118916178A patent proposes a new thread bundle scheduling strategy, which obtains the valid field and ready field of the thread bundle by decoding the cached thread bundle instructions; determines the idle state of the stream processor SP array according to the thread bundle scheduler; and allocates the ready thread bundle instructions corresponding to the buffer instruction table entries to the corresponding SP arrays based on each idle state and the preset instruction allocation rules.

[0005] Patent CN114880082A proposes a dynamic warp scheduling system based on sampling technology. Its core lies in dynamically adjusting the warp scheduling strategy by monitoring and utilizing the execution status of sampled thread blocks in real time, so as to solve the storage resource contention problem caused by traditional static scheduling strategies.

[0006] However, existing technologies still have significant limitations when dealing with complex and ever-changing workloads. They either focus on optimizing thread group scheduling order in a single dimension or only involve simple linkage with cache replacement, lacking layered and collaborative management of task type, instruction characteristics, and thread group state. This singular scheduling dimension leads to resource imbalances between different task types (such as vertex and fragment processing) in mixed-load scenarios like graphics rendering, resulting in some computing units being idle while others are overloaded, leading to a decrease in overall resource utilization. Secondly, existing scheduling strategies mostly employ passive response mechanisms, relying on sampling feedback or cache state to indirectly adjust scheduling behavior. They lack the ability to proactively identify and prioritize long-latency instructions (such as memory access), missing the optimal opportunity to effectively "mask" waiting time using short-latency instruction execution, resulting in inefficient latency hiding. Thirdly, because scheduling tends to continuously serve highly active thread groups, long-ready but unexecuted thread groups may experience scheduling starvation due to unchanged priorities, causing long-tail latency problems and affecting the fairness and determinism of system response. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a thread group scheduling method, apparatus, graphics processor and device for GPU, which addresses the deficiencies in the prior art.

[0008] The technical solution adopted by this invention to solve its technical problem is: A thread group scheduling method for GPUs includes the following steps: 1) Receive scheduling requests from thread groups; 2) Task type priority scheduling; Based on the thread group weight values ​​set by the user, the execution priorities of the vertex thread group and the fragment thread group in the current scheduling cycle are obtained; 3) Instruction type priority scheduling; The instructions to be executed in the thread group are pre-parsed to determine the priority order of instruction types; the details are as follows: 3.1) Read the instruction stream of the thread group from the instruction cache and obtain the next instruction to be executed for each thread group; pre-parse the next instruction to be executed for the thread group and extract its instruction type; determine whether it is a high-latency instruction or a short-latency instruction based on the instruction type. 3.2) Obtain thread group information without dependency information to get the ready thread group instruction type; 3.3) Collect the congestion status of various long-delay instruction queues in the execution unit in real time, and obtain the long-delay instruction queues that are not full; 3.4) Combining the ready thread group instruction types and the congestion status of various long-delay instruction queues, dynamically generate the current optimal instruction type priority sequence according to the priority of schedulable instruction types. 4) Thread groups are prioritized for scheduling; Based on the specified task type priority and instruction type priority, and combined with the time when the thread group was generated, the thread group with the highest priority is selected as the thread group to be executed.

[0009] According to the above scheme, in step 2), the user-defined thread group weight value is compared with the loop count value: when the loop count value is less than or equal to the user-defined thread group weight value, the vertex thread group is scheduled first; when the loop count value is greater than the user-defined thread group weight value, the fragment thread group is scheduled first; wherein, the loop count value increases in each scheduling cycle.

[0010] According to the above scheme, in step 3.3), long-delay instructions refer to instructions that need to wait for memory access or synchronization operations; the long-delay instruction queue includes a texture instruction queue, an atomic operation queue, and a loading instruction queue. According to the above scheme, in step 3.4), the current optimal instruction type priority sequence is dynamically generated according to the priority of the schedulable instruction type, as follows: First, combine the ready thread group instruction types and the congestion status of various long-delay instruction queues to obtain ready thread groups containing long-delay instruction types whose queues are not full. Then, the current optimal instruction type priority sequence is generated according to the preset priority order of the long-delay instruction queue.

[0011] According to the above scheme, step 4) specifically includes the following: 4.1) Write the thread group into the encoding unit according to the time the thread group was generated; the encoding unit works as follows: When a new thread group is injected, it is written to the cell with the largest number in the encoding unit; at the same time, the recursive logic is triggered, so that all existing thread groups move forward one by one in the direction of smaller numbers, ensuring that the new thread group enters from the tail of the queue and the old thread groups gradually move closer to the head of the queue; when a thread group finishes execution, its corresponding cell is marked as inactive, and the recycling logic is immediately triggered, so that all valid thread groups with numbers after it move forward to fill the empty space and keep the queue compact. 4.2) Obtain the thread group information written to the encoding unit, and determine the task type and instruction type of each unit's thread group; 4.3) Integrate the task types and instruction types of all ready thread groups and feed them back to the thread scheduler; Select the task type and instruction type of the thread group to be scheduled based on task type priority and instruction type priority, and then initiate a scheduling request; 4.4) Among the selected task types and instruction types, select the thread group with the smallest number as the highest priority thread group for scheduling and execution.

[0012] The present invention also provides a thread group scheduling device for a GPU, comprising: The receiving module is used to receive scheduling requests from thread groups; The task type priority arbiter is used to obtain the execution priority of the vertex thread group and the fragment thread group based on the thread group weight value set by the user. The task type priority arbiter includes: a configuration register for storing user-defined weight values ​​and a loop counter; the configuration register stores user-defined thread group weight values, and the loop counter increments in each scheduling cycle; When the counter value is less than or equal to the configuration register value, the vertex thread group is scheduled first; when the counter value is greater than the configuration register value, the fragment thread group is scheduled first. The instruction type priority arbiter is used to pre-parse the instructions to be executed in the thread group and determine the instruction type priority order. The instruction type priority arbiter includes an instruction pre-decoding module, a dependency detection module, a priority encoder, an execution unit status feedback module, and an instruction type priority confirmation module connected in sequence. The instruction pre-decoding module is used to pre-parse the next instruction to be executed in the thread group and extract its instruction type; The dependency detection module is used to determine whether the execution of an instruction depends on occupied resources; The priority encoder stores all information about the thread group and categorizes and integrates the thread group information based on the dependency detection results, and provides feedback on the ready thread group instruction type. The execution unit status feedback module collects congestion status information of various long-latency instruction queues in real time, including texture instruction queues, atomic operation instruction queues, and loading instruction queues. The instruction type priority confirmation module is used to dynamically generate the current optimal instruction type priority sequence according to the priority of schedulable instruction types based on the instruction types of ready thread groups and the congestion status of various long-delay instruction queues. The thread group scheduling priority encoder is used to select the thread group with the highest priority among specified task types and instruction types, taking into account the time when the thread group was generated.

[0013] According to the above scheme, the task type priority arbiter includes: a configuration register for storing user-defined weight values ​​and a loop counter; the configuration register stores user-defined thread group weight values, and the loop counter increments in each scheduling cycle; When the counter value is less than or equal to the configuration register value, the vertex thread group is scheduled first; when the counter value is greater than the configuration register value, the fragment thread group is scheduled first.

[0014] According to the above scheme, the thread group scheduling priority encoder includes an encoding unit, a type judgment unit, an encoding unit type integration module, and a priority arbitration module; The encoding unit is used to record thread group information and thread group instruction pre-decoding information written into the encoding unit; in the encoding unit, the thread group is written into the encoding unit according to the time when the thread group is generated. When a new thread group is injected, the cell with the largest number is written; at the same time, the recursive logic is triggered, causing all existing thread groups to move forward one by one in the direction of smaller numbers, ensuring that the new thread group enters from the tail of the queue and the old thread groups gradually move closer to the head of the queue; when a thread group finishes execution, its corresponding cell is marked as inactive, and the recycling logic is immediately triggered, causing all valid thread groups with numbers after it to move forward to fill the empty space and maintain the queue compactness. The type determination unit is used to determine the task type and instruction type of each thread group. The encoding unit type integration module is used to feed back the task type and instruction type of all ready thread groups to the thread scheduler; then, based on the priority arbitration result, the task type and instruction type of the thread group to be scheduled are selected, and a scheduling request is initiated. The priority arbitration module is used to select the valid thread group with the smallest current number as the highest priority thread group for scheduling in each cycle among the selected task types and instruction types.

[0015] A graphics processing unit (GPU) includes a pipeline controller, multiple compute clusters, multiple local memories, a global cache, and a global memory. Each computing cluster corresponds to a local memory, and each computing cluster includes a thread group scheduling device as described in the above scheme. After the pipeline controller generates a thread group, it assigns it to a compute cluster; The thread group scheduler in each computing cluster schedules the allocated thread groups to operate on the data in the corresponding local memory or global memory; Each local memory interacts with the global cache; The global cache interacts with the global memory.

[0016] An electronic device includes a graphics processor as described above.

[0017] The beneficial effects of this invention are: 1. This invention proposes a three-level scheduling strategy for thread groups to improve the instruction throughput and critical task response speed of GPUs under complex loads.

[0018] 2. The three-level scheduling strategy of this invention introduces a dynamic load balancing mechanism at the task type level to dynamically adjust the execution weight of different types of tasks and proactively avoid resource waste caused by task imbalance. At the instruction type level, based on the long-delay instruction queue status fed back by the execution unit, the priority is dynamically determined, and thread groups containing long-delay instructions are scheduled first, proactively using short instruction execution to achieve efficient latency masking. At the thread group level, a dynamic recursive mechanism based on a priority encoder is adopted to achieve "first-in, first-out" scheduling, ensuring that the priority of thread groups that are ready earlier gradually increases with the waiting time.

[0019] 3. The priority encoder adopts a dynamic insertion and forward shift mechanism. This design avoids priority mismatch problems caused by fixed thread group numbers and enhances scheduling flexibility. Attached Figure Description

[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings: Figure 1 This is a flowchart of a method according to an embodiment of the present invention; Figure 2 This is a structural schematic diagram of an embodiment of the present invention; Figure 3 This is a structural diagram of the task type priority arbitrator according to an embodiment of the present invention; Figure 4 This is a structural diagram of the instruction type priority arbitrator according to an embodiment of the present invention; Figure 5 This is a structural diagram of the priority encoder according to an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0022] like Figure 1 As shown, a thread group scheduling method for GPUs includes the following steps: 1) Receive scheduling requests from thread groups and obtain task and instruction information for thread groups that are ready; 2) Task type priority scheduling; For thread groups that are ready, the execution priorities of the vertex thread group and the fragment thread group are obtained according to the thread group weight value and scheduling period set by the user. The system stores the user-defined thread group weight values ​​(ranging from 0 to 15), and the loop counter increments in each scheduling cycle. When the counter value is less than or equal to the user-defined thread group weight value, the vertex thread group is scheduled first; when the counter value is greater than the user-defined thread group weight value, the fragment thread group is scheduled first.

[0023] Task type priority scheduling can effectively adjust the execution ratio of vertex thread group and fragment thread group; 3) Instruction type priority scheduling; By prioritizing instruction type scheduling, thread groups containing high-latency instructions can be scheduled first, and other short-latency instructions can be processed in parallel during their execution intervals. Read the instruction stream of the thread group from the instruction cache and obtain the next instruction to be executed for the thread group; pre-parse the next instruction to be executed for the thread group and extract its instruction type (determine whether the instruction type is long delay or short delay). Retrieve information about thread groups that have no dependencies; The type of thread group instruction that is ready to provide feedback; Real-time acquisition of congestion status of various long-latency instruction queues in the execution unit, including texture instruction queues, atomic operation queues, and loading instruction queues; Based on the ready thread group instruction types and the congestion status of various long-delay instruction queues, the current optimal instruction type priority sequence is dynamically generated according to the priority of schedulable instruction types. The priority order for various long-latency instruction queues is: refresh instructions > atomic operation instructions > texture instructions > loading instructions > arithmetic operation instructions.

[0024] That is, by combining the ready thread group instruction types and the congestion status of various long-delay instruction queues, we can obtain ready thread groups that include long-delay instruction types whose queues are not full. Then, the current optimal instruction type priority sequence is generated according to the priority order of atomic operation instructions, texture instructions, and loading instructions.

[0025] Through this mechanism, the system can prioritize scheduling thread groups containing high-latency instructions, and use their execution gaps to process other short-latency instructions in parallel, effectively masking waiting time, significantly reducing the idle rate of execution units, and improving overall throughput efficiency.

[0026] 4) Thread groups are prioritized for scheduling; Select the thread group with the highest priority (the earliest generated thread group is the highest priority) from the specified task type and instruction type for scheduling and execution.

[0027] Write the thread group into the encoding unit according to the time it was generated; specifically as follows: When a new thread group is injected, it is written to the cell with the largest number in the encoding unit; at the same time, the recursive logic is triggered, so that all existing thread groups move forward one by one in the direction of smaller numbers, ensuring that the new thread group enters from the tail of the queue and the old thread groups gradually move closer to the head of the queue; when a thread group finishes execution, its corresponding cell is marked as inactive, and the recycling logic is immediately triggered, so that all valid thread groups after it (with larger numbers) move forward to fill the empty space and keep the queue compact; Obtain the thread group information for writing to the encoding unit, and determine the task type and instruction type of each unit's thread group; The task types and instruction types of all ready thread groups are integrated and fed back to the thread scheduler; Select the task type and instruction type of the thread group to be scheduled based on task type priority and instruction type priority, and then initiate a scheduling request; Among the selected task types and instruction types, the thread group with the smallest number is selected as the highest priority thread group for scheduling and execution.

[0028] The method of this invention introduces a dynamic load balancing mechanism at the task type level, which dynamically adjusts the execution weight of different tasks based on the configuration register to proactively avoid resource waste caused by task imbalance. At the instruction type level, based on the long-latency instruction queue status fed back by the execution unit, the priority is dynamically determined, and thread groups containing long-latency instructions are scheduled first, proactively using short instruction execution to achieve efficient latency masking. At the thread group level, a dynamic recursive mechanism of priority encoder is adopted to achieve "first-in, first-out" scheduling, ensuring that the priority of thread groups that are ready earlier gradually increases with the waiting time.

[0029] Based on the method of the present invention, the present invention also provides a thread group scheduling device for a GPU, the schematic diagram of which is shown below. Figure 2 , The thread group scheduler includes: The receiving module is used to receive scheduling requests from thread groups; The task type priority arbiter is used to obtain the execution priority of the vertex thread group and the fragment thread group based on the thread group weight value set by the user. like Figure 3 The task type priority arbiter includes: a configuration register for storing user-defined weight values ​​and a loop counter; the configuration register stores user-defined thread group weight values, and the loop counter increments in each scheduling cycle; When the counter value is less than or equal to the configuration register value, the vertex thread group is scheduled first; when the counter value is greater than the configuration register value, the fragment thread group is scheduled first. The instruction type priority arbiter is used to pre-parse the instructions to be executed in the thread group and determine the instruction type priority order. like Figure 4The instruction type priority scheduling module includes instruction pre-decoding, dependency detection, priority encoder, execution unit status feedback and instruction type priority connected in sequence; The instruction pre-decoding module is used to pre-parse the next instruction to be executed in the thread group and extract its instruction type; The dependency detection module is used to determine whether the execution of an instruction depends on occupied resources; The priority encoder stores all information about the thread group and categorizes and integrates the thread group information based on the dependency detection results, and provides feedback on the ready thread group instruction type. Execution unit status feedback, real-time collection of congestion status information of various long-latency instruction queues, including texture instruction queues, atomic operation instruction queues and loading instruction queues; Instruction type priority is used to dynamically generate the current optimal instruction type priority sequence based on the instruction types of ready thread groups and the congestion status of various long-delay instruction queues, according to the priority of schedulable instruction types. The thread group priority encoder is used to select the highest priority thread group for scheduling, based on the thread group's creation time and the specified task and instruction types. like Figure 5 The thread group priority encoder uses a dynamic priority encoder composed of n priority units to uniformly manage the scheduling priority of all active thread groups, realizing a scheduling mechanism that combines "first-in, first-out" and "dynamic priority promotion".

[0030] The thread group priority encoder includes an encoding unit, a type judgment unit, an encoding unit type integration module, and a priority arbitration module; The encoding unit is used to record the thread group information and the pre-decoding information of the instructions to be executed by the thread group. In the encoding unit, the thread group writes the information into the encoding unit according to the time when the thread group is generated. When a new thread group is injected, the highest priority unit is written; at the same time, the recursive logic is triggered, causing all existing thread groups to move forward one by one in the direction of smaller numbers, ensuring that the new thread group enters from the tail of the queue and the old thread groups gradually move closer to the head of the queue; when a thread group finishes execution, its corresponding unit is marked as inactive, and the recycling logic is immediately triggered, causing all valid thread groups after it to move forward to fill the empty space and maintain the queue compactness. The type determination unit is used to determine the task type and instruction type of each thread group. Encoding unit type integration: The task type and instruction type of all ready thread groups are fed back to the thread scheduler. The thread scheduler selects the task type and instruction type of the thread group to be scheduled by combining the first and second priority arbitration with the ready task type and ready instruction type, and initiates a scheduling request; The priority arbitration module is used to select the valid thread group with the smallest current number as the highest priority thread group for scheduling in each cycle among the selected task types and instruction types. The thread sequencer adjusts the execution timing of the scheduled thread group and sends the thread group information to the processor array for execution.

[0031] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A thread group scheduling method for GPUs, characterized in that, Includes the following steps: 1) Receive scheduling requests from thread groups; 2) Task type priority scheduling; Based on the thread group weight values ​​set by the user, the execution priorities of the vertex thread group and the fragment thread group in the current scheduling cycle are obtained; 3) Instruction type priority scheduling; Pre-parse the instructions to be executed in the thread group to determine the priority order of the schedulable instruction types; 4) Thread groups are prioritized for scheduling; Based on the specified task type priority and instruction type priority, and combined with the time when the thread group was created, the thread group with the highest priority is selected for scheduling.

2. The thread group scheduling method for GPU according to claim 1, characterized in that, In step 2), the user-defined thread group weight value is compared with the loop count value: when the loop count value is less than or equal to the user-defined thread group weight value, the vertex thread group is scheduled first; when the loop count value is greater than the user-defined thread group weight value, the fragment thread group is scheduled first; wherein, the loop count value increases in each scheduling cycle.

3. The thread group scheduling method for GPU according to claim 1, characterized in that, In step 3), the specific details are as follows: 3.1) Obtain the next instruction to be executed for each thread group and perform pre-parsing to extract its instruction type; 3.2) Obtain information about thread groups without dependencies, and get the instruction types of ready thread groups; 3.3) Collect the congestion status of various long-delay instruction queues in the execution unit in real time, and obtain the long-delay instruction queues that are not full; 3.4) Combining the ready thread group instruction types and the congestion status of various long-delay instruction queues, dynamically generate the current optimal instruction type priority sequence according to the priority of schedulable instruction types.

4. The thread group scheduling method for GPU according to claim 3, characterized in that, In step 3.4), the current optimal instruction type priority sequence is dynamically generated according to the priority of schedulable instruction types, as follows: First, combine the ready thread group instruction types and the congestion status of various long-delay instruction queues to obtain ready thread groups containing long-delay instruction types whose queues are not full. Then, the current optimal instruction type priority sequence is generated according to the preset priority order of the long-delay instruction queue.

5. A thread group scheduling device for a GPU, characterized in that, include: The receiving module is used to receive scheduling requests from thread groups; The task type priority arbiter is used to obtain the execution priority of the vertex thread group and the fragment thread group based on the thread group weight value set by the user. The instruction type priority arbiter is used to pre-parse the instructions to be executed in the thread group and determine the instruction type priority order. The instruction type priority arbiter includes an instruction pre-decoding module, a dependency detection module, a priority encoder, an execution unit status feedback module, and an instruction type priority confirmation module connected in sequence. The instruction pre-decoding module is used to pre-parse the next instruction to be executed in the thread group and extract its instruction type; The dependency detection module is used to determine whether the execution of an instruction depends on occupied resources; The priority encoder stores all information about the thread group and categorizes and integrates the thread group information based on the dependency detection results, and provides feedback on the ready thread group instruction type. The execution unit status feedback module collects congestion status information of various long-latency instruction queues in real time, including texture instruction queues, atomic operation instruction queues, and loading instruction queues. The instruction type priority confirmation module is used to dynamically generate the current optimal instruction type priority sequence according to the priority of schedulable instruction types based on the instruction types of ready thread groups and the congestion status of various long-delay instruction queues. The thread group scheduling priority encoder is used to select the thread group with the highest priority based on the priority of task type and instruction type, combined with the time when the thread group was generated.

6. The thread group scheduling device for a GPU according to claim 5, characterized in that, The task type priority arbiter includes: a configuration register for storing user-defined weight values ​​and a loop counter; the configuration register stores user-defined thread group weight values, and the loop counter increments in each scheduling cycle; When the counter value is less than or equal to the configuration register value, the vertex thread group is scheduled first; when the counter value is greater than the configuration register value, the fragment thread group is scheduled first.

7. The thread group scheduling device for a GPU according to claim 5, characterized in that, In the instruction type priority confirmation module, the current optimal instruction type priority sequence is dynamically generated according to the priority of schedulable instruction types, as follows: First, combine the ready thread group instruction types and the congestion status of various long-delay instruction queues to obtain ready thread groups containing long-delay instruction types whose queues are not full. Then, the current optimal instruction type priority sequence is generated according to the preset priority order of the long-delay instruction queue.

8. The thread group scheduling device for a GPU according to claim 5, characterized in that, The thread group scheduling priority encoder includes an encoding unit, a type judgment unit, an encoding unit type integration module, and a priority arbitration module; The encoding unit is used to record thread group information and thread group instruction pre-decoding information written into the encoding unit; in the encoding unit, the thread group is written into the encoding unit according to the time when the thread group is generated. When a new thread group is injected, the unit with the largest number is written; at the same time, the recursive logic is triggered, causing all existing thread groups to move forward one by one in the direction of smaller numbers; when a thread group finishes execution, its corresponding unit is marked as inactive, and the recycling logic is triggered, causing all valid thread groups with numbers after it to move forward to fill the gap. The type determination unit is used to determine the task type and instruction type of each thread group. The encoding unit type integration module is used to feed back the task type and instruction type of all ready thread groups to the thread scheduler. Then, based on the priority arbitration results, the task type and instruction type of the thread group to be scheduled are selected, and a scheduling request is initiated. The priority arbitration module is used to select the valid thread group with the smallest current number as the highest priority thread group for scheduling in each cycle among the selected task types and instruction types.

9. A graphics processor, characterized in that, The graphics processor includes a pipeline controller, multiple compute clusters, multiple local memories, a global cache, and a global memory; Each computing cluster corresponds to a local memory, and each computing cluster includes the thread group scheduling device as described in any one of claims 5 to 8; After the pipeline controller generates a thread group, it assigns it to a compute cluster; The thread group scheduler in each computing cluster schedules the allocated thread groups to operate on the data in the corresponding local memory or global memory; Each local memory interacts with the global cache; The global cache interacts with the global memory.

10. An electronic device, comprising: The graphics processor as described in claim 9.

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