Semiconductor device and semiconductor module

Abstract

This invention provides a semiconductor device capable of reducing parasitic inductance in high-frequency circuits comprising elemental semiconductor-based semiconductor elements and compound semiconductor-based semiconductor elements. A switch made of elemental semiconductor-based semiconductor elements is disposed in a first component. A second component, comprising a high-frequency circuit comprising compound semiconductor-based semiconductor elements, is coupled to the first component. The switch and the high-frequency circuit are connected by a path. This path includes inter-component connection wiring formed by a metal pattern disposed on an interlayer insulating film from the surface of the second component to the surface of the first component, or a conductive component that allows current to flow in a direction intersecting the interface where the first and second components are coupled.

Description

Technical Field

[0001] This invention relates to semiconductor devices and semiconductor modules. Background Technology

[0002] One of the key components in mobile terminals is the high-frequency power amplifier. To maximize the wireless transmission capacity of mobile terminals, wireless communication standards utilizing multiple frequency bands, such as carrier aggregation (CA), have been implemented. As the number of frequency bands used increases, the circuit structure of the RF front-end becomes more complex. Furthermore, to utilize the sub-6GHz frequency band of fifth-generation mobile communication systems (5G), the circuit structure of the RF front-end becomes even more complex.

[0003] If the circuit structure of the RF front end becomes complex, the losses caused by filters, switches, etc., inserted in the transmission line from the high-frequency power amplifier to the antenna increase. As a result, in addition to being compatible with multiple frequency bands, high output is also required for the high-frequency power amplifier. Non-Patent Document 1 disclosed below discloses a technique for combining the outputs of multiple CMOS power amplifiers and performing impedance transformation.

[0004] If the frequency bands used increase, it is preferable to adjust the component constants of the impedance matching circuit according to the frequency bands. For example, the component constants can be adjusted by turning the switch connected to the reactive component on and off. In addition, high-frequency power amplifiers may use heterojunction bipolar transistors based on compound semiconductors, for example.

[0005] Non-patent document 1: Kyu Hwan An et.al., "Power-Combining TransformerTechniques for Fully-Integrated CMOS Power Amplifiers", IEEE J. of Solid-stateCircuits, Vol. 43, No. 5, MAY (2008)

[0006] To form a switch for constant element adjustment in a semiconductor chip with a compound semiconductor heterojunction bipolar transistor, a BiFET or BiHEMT structure must be used, for example. This complicates the manufacturing process. If the switch is formed on a silicon-based semiconductor chip and a high-frequency power amplifier is formed using a compound semiconductor chip, a BiFET or BiHEMT structure is unnecessary. However, in structures where two semiconductor chips are mounted separately on a module substrate, the size of the semiconductor module increases.

[0007] By stacking silicon-based semiconductor chips and compound semiconductor chips and connecting them with bonding wires, semiconductor modules can be miniaturized. However, if the signal to be processed is high-frequency, the parasitic inductance of the bonding wires cannot be ignored, and the desired characteristics cannot be obtained. Summary of the Invention

[0008] The purpose of this invention is to provide a semiconductor device and semiconductor module that can reduce parasitic inductance in high-frequency circuits containing elemental semiconductor-based semiconductor elements and compound semiconductor-based semiconductor elements.

[0009] According to one aspect of the present invention, a semiconductor device is provided, comprising:

[0010] The first component is equipped with a switch made of semiconductor elements of the elemental semiconductor system;

[0011] The second component includes a high-frequency circuit comprising a compound semiconductor element and is coupled to the first component; and

[0012] The path connects the aforementioned switch and the aforementioned high-frequency circuit.

[0013] The aforementioned path includes: inter-component connection wiring formed by a metal pattern disposed on an interlayer insulating film from the surface of the second component to the surface of the first component, or a conductive component that allows current to flow in a direction intersecting the interface connecting the first component and the second component.

[0014] According to another aspect of the present invention, a semiconductor module is provided, comprising:

[0015] A semiconductor device includes a first component having a switch made of an elemental semiconductor system and a second component having a high-frequency circuit having a semiconductor element made of a compound semiconductor system and being coupled to the first component.

[0016] Module substrate, on which the aforementioned semiconductor device is mounted; and

[0017] The path connects the aforementioned switch and the aforementioned high-frequency circuit.

[0018] The aforementioned semiconductor device includes a first conductor protrusion connected to the aforementioned switch and a second conductor protrusion connected to the aforementioned high-frequency circuit.

[0019] The aforementioned path includes the aforementioned first conductor protrusion, wiring disposed on the aforementioned module substrate, and the aforementioned second conductor protrusion.

[0020] Since the switch of the first component and the high-frequency circuit of the second component are not connected by bonding wires, the increase of parasitic inductance in the path connecting the two can be suppressed. Attached Figure Description

[0021] Figure 1 This is a schematic equivalent circuit diagram of the high-frequency power amplifier in the first embodiment.

[0022] Figure 2 This is a schematic cross-sectional view of the semiconductor device mounted on the high-frequency power amplifier in the first embodiment.

[0023] Figure 3A This is the equivalent circuit diagram of a unit that constitutes the power stage differential amplifier circuit formed in the second component. Figure 3B This is a cross-sectional view of a unit that constitutes a power stage differential amplifier circuit formed in the second component.

[0024] Figure 4 This is a schematic cross-sectional view of the high-frequency power module of the first embodiment.

[0025] Figures 5A to 5F The accompanying drawing is a cross-sectional view of a semiconductor device during the manufacturing process.

[0026] Figures 6A to 6C The attached figure is a cross-sectional view of a semiconductor device during the manufacturing process. Figure 6D This is a cross-sectional view of the completed semiconductor device.

[0027] Figure 7A as well as Figure 7B The graphs show the simulation results under the conditions of zero parasitic inductance and 2nH parasitic inductance in the variable capacitor circuit.

[0028] Figure 8 This is an equivalent circuit diagram of the variable capacitor circuit used in the high-frequency power amplifier of the first embodiment.

[0029] Figure 9 This is a schematic cross-sectional view of the semiconductor device mounted on the high-frequency power amplifier in the second embodiment.

[0030] Figure 10 This is a schematic equivalent circuit diagram of the high-frequency power amplifier in the third embodiment.

[0031] Figure 11 This is a schematic cross-sectional view of the high-frequency power module of the third embodiment.

[0032] Figure 12 This is a schematic equivalent circuit diagram of the high-frequency power amplifier in the fourth embodiment.

[0033] Figure 13 This is a schematic equivalent circuit diagram of a high-frequency power amplifier in a variation of the fourth embodiment.

[0034] Figure 14This is a schematic equivalent circuit diagram of a high-frequency power amplifier of another variation of the fourth embodiment.

[0035] Figure 15 This is a schematic equivalent circuit diagram of a high-frequency power amplifier, which is another variation of the fourth embodiment.

[0036] Figure 16 This is a schematic equivalent circuit diagram of the high-frequency power amplifier in the fifth embodiment.

[0037] Explanation of reference numerals in the attached figures

[0038] 20…High-frequency power amplifier; 21…First component; 21A…First surface of the first component; 22…Second component; 23…Semiconductor device; 25…Module substrate; 26, 27, 28…Wiring; 31…Driver stage amplifier circuit; 31T…Transistor of the driver stage amplifier circuit; 32…Power stage differential amplifier circuit; 32T…Transistor of the power stage differential amplifier circuit; 33…First balancing converter; 34…Variable capacitance circuit; 34A, 34B, 34C, 34D…Capacitors; 34S…Switch; 35…Second balancing converter; 36…Decoupling capacitor; 37…DC cutoff capacitor; 38…Output matching circuit; 38C…Capacitor; 38L…Inductor; 39…Switch control circuit; 40…Inductor; 51…Semiconductor substrate; 52…Multilayer wiring structure; 53, 54…Wiring; 55…Adhesive layer; 55A, 55B…Metal region; 55C…Insulating region; 56…Wiring; 71…Inter-component connection Wiring; 72, 73… Pads; 74, 75, 76… Inter-component connection wiring; 77… Interlayer insulating film; 78… Protective film; 82… Conductor protrusion; 82A… Cu pillar; 82B… Solder layer; 83, 84, 85, 86… Conductor protrusion; 101… Substrate semiconductor layer; 101A… Conductive region; 101B… Component separation region; 102B… Base layer; 102C… Collector layer; 102E… Emitter layer; 103B… Base electrode; 10 3C…Collector electrode; 103E…Emitter electrode; 104B…First layer base wiring; 104BB…Base bias wiring; 104C…First layer collector wiring; 104E…First layer emitter wiring; 105E…Second layer emitter wiring; 105RF…High-frequency signal input wiring; 111, 112…Interlayer insulating film; 200…Mother substrate; 201…Release layer; 202…Component forming layer; 204…Connector support; 210…Substrate. Detailed Implementation

[0039] [First Embodiment]

[0040] Reference Figures 1 to 7B The accompanying drawings illustrate a semiconductor device according to a first embodiment. The semiconductor device of the first embodiment is a high-frequency power amplifier.

[0041] Figure 1 This is a schematic equivalent circuit diagram of the high-frequency power amplifier 20 according to the first embodiment. The high-frequency power amplifier 20 of the first embodiment includes a driver stage amplifier circuit 31, a first balancing converter 33, a variable capacitor circuit 34, a power stage differential amplifier circuit 32, a second balancing converter 35, an output matching circuit 38, and a switching control circuit 39. The driver stage amplifier circuit 31 includes at least one transistor 31T, and the power stage differential amplifier circuit 32 includes multiple transistors 32T connected in parallel. The driver stage amplifier circuit 31 amplifies the single-ended signal input from the input terminal Pin.

[0042] The first balanced converter 33 includes a primary coil and a secondary coil, converting a single-ended signal into a differential signal. Specifically, one end of the primary coil is connected to the output port of the driver stage amplifier circuit 31, and the other end is connected to ground. The two ends of the secondary coil are connected to the two input ports of the differential amplifier circuit 32 via differential transmission lines.

[0043] A variable capacitor circuit 34 is connected between a pair of wires that transmit the differential signal input to the differential amplifier circuit 32. The variable capacitor circuit 34 includes capacitors 34A and 34B connected in parallel, and a switch 34S connected in series with capacitor 34A.

[0044] The second balanced converter 35 includes a primary coil and a secondary coil, converting the differential signal output from the differential amplifier circuit 32 into a single-ended signal. The two ends of the primary coil are connected to the two output ports of the differential amplifier circuit 32, respectively. A power supply voltage Vcc is applied to the center tap of the primary coil, supplying power to the differential amplifier circuit 32 via the primary coil. A decoupling capacitor 36 is connected to the power supply line for purposes such as preventing oscillation, suppressing noise, and ensuring linearity during modulation. Additionally, the center tap of the primary coil is grounded at high frequency via a DC cutoff capacitor 37. Figure 1 In this circuit, the inductance of the wiring is represented as inductor 40. The resonant circuit composed of DC cut-off capacitor 37 and inductor 40 functions as a high-order harmonic suppression filter for the second and third harmonics of high-frequency signals. However, there are also cases where DC cut-off capacitor 37 and inductor 40 are not used as filters. In this case, DC cut-off capacitor 37 functions solely as a capacitor for DC cut-off.

[0045] The single-ended signal converted from the differential signal by the second balancing converter 35 is output from the output terminal Pout via the output matching circuit 38. The output matching circuit 38 includes an inductor 38L connected in series with the load and a capacitor 38C connected in parallel with the load and the inductor 38L.

[0046] The switch control circuit 39 controls the switching of switch 34S to be on or off based on the frequency of the high-frequency signal of the amplified object. When switch 34S is switched on or off, the capacitance of the variable capacitor circuit 34 changes. This allows for appropriate impedance matching based on the frequency.

[0047] See below for reference. Figures 2 to 4 As illustrated in the accompanying drawings, the high-frequency power amplifier 20 of the first embodiment includes: a semiconductor device 23 having a first component 21 and a second component 22, and a module substrate 25 on which the semiconductor device 23 is mounted. Figure 4 A driver-stage amplifier circuit 31 and a power-stage differential amplifier circuit 32 are formed in the second component 22. A switch 34S is formed in the first component 21. A first balancing converter 33, capacitors 34A and 34B, a second balancing converter 35, a decoupling capacitor 36, a DC cutoff capacitor 37, and an output matching circuit 38 are mounted on the module substrate 25. Figure 4 It consists of surface-mount passive circuit components.

[0048] Figure 1 The solid square and the hollow square shown represent connections to the module substrate 25 via conductor protrusions on the first component 21 and the second component 22, respectively. Additionally, Figure 1 The relatively thick solid lines shown indicate that the circuits located in the first component 21 and the circuits located in the second component 22, as described later, are connected by the inter-component connection wiring 71 contained in the rewiring layer.

[0049] Figure 2 This is a schematic cross-sectional view of the semiconductor device 23 mounted on the high-frequency power amplifier 20 in the first embodiment. Figure 2 In the diagram, the driver stage amplifier circuit 31 and the power stage differential amplifier circuit 32 are shown using circuit diagram symbols, and the wiring and vias of the multilayer wiring structure are shown using broken lines. These wirings actually include metal patterns within the wiring layers and vias connecting the wiring layers.

[0050] The semiconductor device 23 of the high-frequency power amplifier in the first embodiment includes a first component 21 and a second component 22. For example, the first component 21 is made of an elemental semiconductor, and the second component 22 is made of a compound semiconductor. The first component 21 includes a semiconductor region of the elemental semiconductor system. For example, the first component 21 includes a semiconductor substrate 51 and a multilayer wiring structure 52 disposed on one side of the semiconductor substrate 51. As the semiconductor substrate 51, for example, a silicon substrate, a silicon-on-insulator (SOI) substrate, or other elemental semiconductor substrate can be used. The first component 21 includes an elemental semiconductor element formed on the surface portion of the semiconductor substrate 51, such as a switch 34S made of a MOSFET.

[0051] On the surface of the multilayer wiring structure 52 (hereinafter referred to as the first surface 21A), a second component 22 is bonded via a surface contact. The second component 22 comprises a semiconductor region of a compound semiconductor system. (See below for further details.) Figure 3A , Figure 3B The structure of the second component 22 will be described in detail.

[0052] The second component 22 includes a driver stage amplifier circuit 31 and a power stage differential amplifier circuit 32. An interlayer insulating film 77 is disposed to cover the first surface 21A of the first component 21 and the second component 22. The upper surface of the interlayer insulating film 77 is planarized. On the interlayer insulating film 77, inter-component connection wiring 71, pads 72, 73, etc., formed by metal patterns are disposed.

[0053] The pad 72 connects to the transistor 32T of the power stage differential amplifier circuit 32 through an opening in the interlayer insulating film 77. Figure 1 The emitter of the circuit is connected. Another pad 73 is connected to the switch 34S via a wiring 54 within the multilayer wiring structure 52 through an opening in the interlayer insulating film 77. The inter-component connection wiring 71 is connected to the power stage differential amplifier circuit 32 via an opening in the interlayer insulating film 77, and is connected to the switch 34S via wiring 53 within the multilayer wiring structure 52 through other openings in the interlayer insulating film 77.

[0054] The wiring layer, which includes inter-component connection wiring 71, pads 72, 73, etc., is sometimes referred to as a rewiring layer. An insulating protective film 78 is disposed on the interlayer insulating film 77 to cover the rewiring layer. The protective film 78 has an opening that is included by each of the pads 72, 73, etc., when viewed from above. Conductor protrusions 82, 83 are disposed on the pads 72, 73 exposed within the openings. The conductor protrusions 82, 83 protrude from the upper surface of the protective film 78 and extend to the upper surface of the protective film 78 around the opening.

[0055] The conductor bump 82 includes a Cu pillar 82A connected to the pad 72 and a solder layer 82B disposed on the upper surface of the Cu pillar 82A. This type of conductor bump 82 is also called a Cu pillar bump. Alternatively, to improve adhesion, a bump under-metal layer can be disposed on the bottom surface of the Cu pillar 82A. Other conductor bumps 83 also have the same stacked structure as the conductor bump 82. Furthermore, conductor bumps 82, 83, etc., can replace Cu pillar bumps with Au bumps, solder ball bumps, conductor pillars erected on the pad, etc. Like Au bumps, bumps without a solder layer are also called pillars. Conductor pillars erected on the pad are also called posts.

[0056] The ground conductor in the second component 22 and the ground conductor in the first component 21 are connected by rewiring within the rewiring layer (not shown in the rewiring layer). Figure 2 On the cross-section.) They are interconnected. Furthermore, the ground conductor in the second component 22 and the ground conductor in the first component 21 are connected to the common ground conductor of the module substrate via conductor protrusions provided in the first component 21 and the second component 22, respectively. The switch 34S provided in the first component 21 is connected to the capacitor 34A mounted on the module substrate via conductor protrusion 83. Figure 1 )connect.

[0057] Figure 3A It constitutes the power stage differential amplifier circuit 32 formed in the second component 22. Figure 1 The equivalent circuit diagram of one unit of the power stage differential amplifier circuit 32 is shown below. The power stage differential amplifier circuit 32 comprises multiple units connected in parallel. Each unit includes a transistor 32T, an input capacitor Cin, and a ballast resistor element Rb. The base of transistor 32T is connected to the high-frequency signal input wiring 105RF via the input capacitor Cin. Furthermore, the base of transistor 32T is connected to the base bias wiring 104BB via the ballast resistor element Rb. The emitter of transistor 32T is grounded. A power supply voltage is applied to the collector of transistor 32T, and the amplified high-frequency signal is output from the collector.

[0058] Figure 3B This is a schematic cross-sectional view of a unit constituting a power stage differential amplifier circuit 32 formed in the second component 22. The second component 22 includes a substrate semiconductor layer 101. The second component 22 is bonded to the first component 21 through surface contact between the substrate semiconductor layer 101 and the first component 21. The substrate semiconductor layer 101 is divided into a conductive region 101A and a component separation region 101B. The substrate semiconductor layer 101 is, for example, made of GaAs. The conductive region 101A is formed of n-type GaAs, and the component separation region 101B is formed by ion implantation of insulating impurities into the n-type GaAs layer.

[0059] A transistor 32T is disposed on the conductive region 101A. The transistor 32T comprises a collector layer 102C, a base layer 102B, and an emitter layer 102E, sequentially stacked from the conductive region 101A. The emitter layer 102E is disposed on a portion of the base layer 102B. As an example, the collector layer 102C is formed of n-type GaAs, the base layer 102B is formed of p-type GaAs, and the emitter layer 102E is formed of n-type InGaP. That is, the transistor 32T is a heterojunction bipolar transistor.

[0060] A base electrode 103B is disposed on the base layer 102B and is electrically connected to the base layer 102B. An emitter electrode 103E is disposed on the emitter layer 102E and is electrically connected to the emitter layer 102E. A collector electrode 103C is disposed on the conductive region 101A. The collector electrode 103C is electrically connected to the collector layer 102C via the conductive region 101A.

[0061] A first interlayer insulating film 111 is configured on the substrate semiconductor layer 101 to cover the transistor 32T, collector electrode 103C, base electrode 103B, and emitter electrode 103E. The first interlayer insulating film 111 is formed, for example, from an inorganic insulating material such as SiN. Multiple openings are provided in the interlayer insulating film 111.

[0062] A first layer of emitter wiring 104E, base wiring 104B, collector wiring 104C, and base bias wiring 104BB are disposed on the interlayer insulating film 111. A ballast resistor element Rb is also disposed on the interlayer insulating film 111. Emitter wiring 104E is connected to emitter electrode 103E through an opening in the interlayer insulating film 111. Base wiring 104B is connected to base electrode 103B through other openings in the interlayer insulating film 111. Collector wiring 104C is connected to collector electrode 103C through other openings in the interlayer insulating film 111.

[0063] The base wiring 104B extends into the region where no transistor 32T is configured, and its front end overlaps with one end of the ballast resistor element Rb. At the overlap, the base wiring 104B is electrically connected to the ballast resistor element Rb. The other end of the ballast resistor element Rb overlaps with the base bias wiring 104BB. At the overlap, the ballast resistor element Rb is electrically connected to the base bias wiring 104BB.

[0064] A second interlayer insulating film 112 is configured on the interlayer insulating film 111 to cover the first layer emitter wiring 104E, base wiring 104B, base bias wiring 104BB, and ballast resistor element Rb. The second interlayer insulating film 112 is also formed of an inorganic insulating material such as SiN.

[0065] A second emitter wiring 105E and a high-frequency signal input wiring 105RF are disposed on the interlayer insulating film 112. The second emitter wiring 105E is connected to the first emitter wiring 104E through an opening in the interlayer insulating film 112. In top view, a portion of the high-frequency signal input wiring 105RF overlaps with the first base wiring 104B. An input capacitor Cin is formed in the overlapping area.

[0066] The third interlayer insulating film 77 is configured to cover the second layer emitter wiring 105E and the high-frequency signal input wiring 105RF. The third interlayer insulating film 77 is formed, for example, of an organic insulating material such as polyimide. Furthermore, as... Figure 2 As shown, the third interlayer insulating film 77 extends onto the first component 21.

[0067] A pad 72 is disposed on the third interlayer insulating film 77. The pad 72 is connected to the second layer emitter wiring 105E through an opening provided in the interlayer insulating film 77.

[0068] Figure 4 This is a schematic cross-sectional view of the high-frequency power amplifier 20 of the first embodiment. A semiconductor device 23, a capacitor 34A, a first balancer 33, a second balancer 35, etc., are mounted on the component mounting surface of the module substrate 25. The semiconductor device 23 is mounted in an orientation such that the surface of the first component 21 that engages with the second component 22 faces the module substrate 25.

[0069] A switch 34S is formed in the first component 21 of the semiconductor device 23, and a power stage differential amplifier circuit 32 is formed in the second component 22. The differential amplifier circuit 32 ( Figure 1 One input port of the first component 21 is connected to a contact of the switch 34S of the first component 21 via inter-component connection wiring 71. The other contact of the switch 34S is connected to a terminal of the capacitor 34A via a conductor protrusion 83 in the first component 21 and wiring 27 within the module substrate 25. The other terminal of the capacitor 34A is connected to another input port of the differential amplifier circuit 32 via wiring 26 within the module substrate 25 and a conductor protrusion 84 in the second component 22.

[0070] Next, refer to Figures 5A to 6D The accompanying drawings illustrate the semiconductor device 23 mounted on the high-frequency power amplifier in the first embodiment. Figure 2 The manufacturing method of ) will be explained. Figures 5A to 6C The attached figure is a cross-sectional view of the semiconductor device 23 during the intermediate stage of manufacturing. Figure 6D This is a cross-sectional view of the completed semiconductor device 23.

[0071] like Figure 5A As shown, a release layer 201 is epitaxially grown on a single-crystal mother substrate 200 of a compound semiconductor such as GaAs, and a device forming layer 202 is formed on the release layer 201. A device forming layer 202 is formed on the device forming layer 202. Figure 3A , Figure 3B The second component 22 shown includes transistor 32T, a first wiring layer, a second wiring layer, etc. These circuit elements and wiring layers are formed using conventional semiconductor processes. Figure 5AThe element structure formed on the element forming layer 202 is omitted from the description. At this stage, the element forming layer 202 is not separated into individual second components 22.

[0072] Next, as Figure 5B As shown, the resist pattern (not shown) is used as an etching mask to form the element layer 202. Figure 5A The element forming layer 202 is patterned, along with the release layer 201. Figure 5A It is separated into each second component 22.

[0073] Next, as Figure 5C As shown, the connecting support 204 is attached to the separated second component 22. Thus, multiple second components 22 are interconnected via the connecting support 204. Alternatively, it can be left unattached... Figure 5B The resist pattern used as an etching mask in the patterning process is sandwiched between the second component 22 and the connecting support 204.

[0074] Next, as Figure 5D As shown, the release layer 201 is selectively etched onto the mother substrate 200 and the second component 22. As a result, the second component 22 and the connecting support 204 are peeled off from the mother substrate 200. To selectively etch the release layer 201, a compound semiconductor with an etching resistance different from both the mother substrate 200 and the second component 22 is used as the release layer 201.

[0075] like Figure 5E As shown, a structure is prepared to be formed on the first component 21 ( Figure 2 The switch 34S and the multi-layer wiring structure 52 ( Figure 2 The substrate 210, etc. At this stage, the substrate 210 is not separated into individual first components 21.

[0076] like Figure 5F As shown, the second component 22 is bonded to the substrate 210. The bonding between the second component 22 and the substrate 210 is based on van der Waals bonds or hydrogen bonds. Alternatively, the second component 22 can also be bonded to the substrate 210 by electrostatic force, covalent bonds, eutectic alloy bonds, etc. For example, if a portion of the surface of the substrate 210 is formed of Au, the two can be bonded by pressing the second component 22 tightly against the Au region.

[0077] Next, as Figure 6A As shown, the connecting support 204 is peeled off from the second component 22. After peeling off the connecting support 204, as... Figure 6B As shown, an interlayer insulating film 77 and a redistribution layer are formed on the substrate 210 and the second component 22. The redistribution layer includes inter-component connection wiring 71, pads 72, and pads 73. Figure 2 )wait.

[0078] Next, as Figure 6C As shown, a protective film 78 is formed on the redistribution layer, and an opening is formed at a predetermined position on the protective film 78. Then, conductor protrusions 82 are formed within the openings and on the protective film 78. Simultaneously with the formation of the conductor protrusions 82, other conductor protrusions 83 are also formed. Figure 4 ), conductor protrusion 84 ( Figure 4 )wait.

[0079] Finally, as Figure 6D As shown, substrate 210 is cut. This yields semiconductor device 23. When viewed from above, the first component 21 of the monolithic semiconductor device 23 is larger than the second component 22.

[0080] Next, the superior effects of the first embodiment will be explained.

[0081] In the first embodiment, by making the capacitor variable circuit 34 ( Figure 1 The capacitor can be appropriately impedance matched for each frequency band according to the frequency band variation.

[0082] Furthermore, in the first embodiment, the switch 34S, which is composed of MOSFETs, is... Figure 2 The first component 21, which is disposed on a semiconductor substrate 51 containing an elemental semiconductor system, and the transistor 32T, which contains a compound semiconductor system, is also disposed thereon. Figure 3A , Figure 3B The power stage differential amplifier circuit 32 is disposed in the second component 22. Since the switch 34S is not disposed in the second component 22, the second component 22 does not need to adopt a BiFET structure or a BiHEMT structure. Therefore, the complexity of the manufacturing process of the second component 22 can be avoided, and the increase in manufacturing cost can be suppressed.

[0083] Furthermore, in the first embodiment, the second component 22 is bonded to the first component 21 and mounted on the module substrate 25 as a semiconductor device 23. Therefore, compared with the structure in which compound semiconductor chips and elemental semiconductor chips are respectively mounted on the module substrate 25, miniaturization of the high-frequency power amplifier can be achieved.

[0084] Next, refer to Figure 7A as well as Figure 7B The power stage differential amplifier circuit 32 and the switch 34S are connected via a path made of conductors. Figure 2 The superior effects obtained are explained, wherein the conductor includes inter-component connection wiring 71 of the redistribution layer. Figure 2 ) and wiring 53 within the multi-layer wiring structure 52 ( Figure 2For example, high-frequency current flows through this path. In this case, the path formed by the conductor functions as a "current path." Furthermore, there are cases where the switch 34S is inserted in a position where almost no current flows even when the switch 34S is turned on. For example, there are also cases where, when the switch 34S is turned on, high-frequency voltage signals are primarily transmitted via the switch 34S. In either case, the path formed by the conductor functions as a signal path for propagating high-frequency signals.

[0085] In conventional semiconductor devices with structures of overlapping element semiconductor chips and compound semiconductor chips, a structure is generally used in which two stacked semiconductor chips are connected by bonding wires. If the power stage differential amplifier circuit 32 of the second component 22 and the switch 34S of the first component 21 are connected by bonding wires, the parasitic inductance of the bonding wires cannot be ignored. Figure 1 In the equivalent circuit diagram shown, when switch 34S is turned on, a parasitic inductor is inserted in series with capacitor 34A.

[0086] To estimate the effect of parasitic inductance, the capacitor 34A is calculated with and without parasitic inductance, when the switch is on for 34 seconds. Figure 1 The S-parameter S21 of )

[0087] Figure 7A as well as Figure 7B The graphs show the simulation results under the conditions of zero parasitic inductance and 2nH parasitic inductance, respectively. The horizontal axis represents frequency in "GHz" and the vertical axis represents parameter S21 in "dB". Figure 7A as well as Figure 7B The six curves shown represent the parameter S21 when the capacitor 34A is 2pF, 4pF, 6pF, 8pF, 10pF and 12pF respectively.

[0088] It is known that resonance occurs in an LC series circuit when the parasitic inductance is 2nH. Therefore, if the parasitic impedance increases to a non-negligible level, impedance transformation as designed cannot be performed. In the first embodiment, the power stage differential amplifier circuit 32 and the switch 34S are not connected using bond wires, but rather via the path of the inter-component connection wiring 71 including the redistribution layer and the wiring 53 within the multilayer wiring structure 52. Therefore, the increase in parasitic inductance inserted in series with the capacitor 34A can be suppressed.

[0089] In the first embodiment ( Figure 2 In the second component 22, since the second component 22 is in contact with the first component 21, the transistor 32T disposed in the second component 22 ( Figure 1The thermal resistance of the heat conduction path to the first component 21 is reduced. The heat generated in the transistor 32T is conducted to the first component 21 through the interface between the first component 21 and the second component 22. The heat conducted to the first component 21 diffuses within the first component 21 and is dissipated to the outside from the surface of the first component 21. In addition, since the first component 21 itself has a larger heat capacity than the second component 22, the first component 21 functions as a heat sink.

[0090] To improve the heat dissipation characteristics through the first component 21, the semiconductor region of the first component 21 is preferably, for example, the semiconductor substrate 51. Figure 2 A semiconductor material with a higher thermal conductivity than the compound semiconductor material constituting transistor 32T is used. For example, the semiconductor region of the first component 21 preferably uses elemental semiconductors such as silicon and germanium.

[0091] Furthermore, in the first embodiment ( Figure 2 In transistor 32T, the heat generated is transmitted through pad 72 and conductor protrusion 82. Figure 2 ) Conducted to module substrate 25 ( Figure 4 Thus, by forming two heat conduction paths—one from transistor 32T to the first component 21 and the other via conductor protrusion 82 to the module substrate 25—the effect of suppressing the temperature rise of transistor 32T can be improved.

[0092] Next, refer to Figure 8 A variation of the first embodiment will be described.

[0093] Figure 8 This is an equivalent circuit diagram of the variable capacitance circuit 34 used in the high-frequency power amplifier 20 of the first embodiment. In the first embodiment, the two capacitors 34A and 34B constituting the variable capacitance circuit 34 are connected in parallel. In contrast, in Figure 8 In the modified example shown, the two capacitors 34C and 34D constituting the variable capacitance circuit 34 are connected in series. The switch 34S is connected in parallel with one capacitor 34D.

[0094] In this variation, the switch 34S and one input port of the power stage differential amplifier circuit 32 are connected via inter-component connection wiring 71 in the redistribution layer, without using bonding wires. In this variation, the capacitance of the variable capacitance circuit 34 changes by switching the switch 34S on and off. Various circuit structures can be used as the variable capacitance circuit 34, including a switch and multiple capacitors, where the capacitance changes by switching the switch on and off.

[0095] In the first embodiment described above, an example of a high-frequency power amplifier was given, but the technical concept of the above embodiment can be applied to various high-frequency circuit devices other than high-frequency power amplifiers. For example, when a switch for a high-frequency circuit that operates on a semiconductor element comprising a compound semiconductor system formed in the second component 22 is formed in the first component 21, the high-frequency circuit in the second component 22 and the switch in the first component 21 can be connected via inter-component connection wiring 71 in the redistribution layer. This reduces the parasitic inductance inserted in series with the switch.

[0096] [Second Embodiment]

[0097] Next, refer to Figure 9 The high-frequency power amplifier of the second embodiment will be described below. Hereinafter, the amplifier will be compared with the one described above. Figures 1 to 7B The structure of the high-frequency power amplifier in the first embodiment described in the accompanying drawings is omitted.

[0098] Figure 9 This is a schematic cross-sectional view of the semiconductor device 23 mounted on the high-frequency power amplifier in the second embodiment. In the first embodiment ( Figure 2 In the first embodiment, the switch 34S formed in the first component 21 and the power stage differential amplifier circuit 32 formed in the second component are connected via inter-component connection wiring 71 in the redistribution layer. In contrast, in the second embodiment, the switch 34S and the power stage differential amplifier circuit 32 are connected via a path containing conductive components that allow current to flow in a direction that intersects with the interface connecting the first component 21 and the second component 22.

[0099] In addition to the semiconductor substrate 51 and the multilayer wiring structure 52, the first component 21 also includes an adhesive layer 55 disposed on the upper surface of the multilayer wiring structure 52. The adhesive layer 55 is divided into multiple metal regions 55A and 55B and an insulating region 55C. The insulating region 55C electrically isolates the multiple metal regions 55A and 55B. The metal region 55A is connected to an input port of the power stage differential amplifier circuit 32 in the second component 22. The metal region 55A is connected to the switch 34S via wiring 56 in the multilayer wiring structure 52. The path including the metal region 55A and the wiring 56 connects the power stage differential amplifier circuit 32 and the switch 34S, and this path allows current to flow in a direction that intersects the interface that contacts the surfaces of the first component 21 and the second component 22.

[0100] The pad 73 is connected to the metal region 55B through an opening in the interlayer insulating film 77. The conductor protrusion 83 is connected to the switch 34S via the pad 73, the metal region 55B, and the wiring 54 within the multilayer wiring structure 52. The conductor protrusion 83 is mounted on the module substrate 25. Figure 4 Connect the 34A capacitor.

[0101] Next, the superior effects of the second embodiment will be explained.

[0102] In the second embodiment, bonding wires are not used to connect the power stage differential amplifier circuit 32 of the second component 22 and the switch 34S of the first component 21. Therefore, the increase in parasitic inductance inserted in series with the switch 34S can be suppressed. Furthermore, similar to the first embodiment, the second embodiment achieves various effects such as miniaturization of the high-frequency power amplifier, suppression of increased manufacturing costs, and suppression of temperature rise in the transistor 32T included in the power stage differential amplifier circuit 32.

[0103] [Third Embodiment]

[0104] Next, refer to Figure 10 as well as Figure 11 The semiconductor module of the third embodiment will be described. The semiconductor module of the third embodiment is a high-frequency power amplifier. Hereinafter, compared with the reference... Figures 1 to 7B The description of the common structure of the semiconductor device in the first embodiment of the accompanying drawings is omitted.

[0105] Figure 10 This is a schematic equivalent circuit diagram of the high-frequency power amplifier 20 in the third embodiment. Figure 11 This is a schematic cross-sectional view of the high-frequency power amplifier 20 according to the third embodiment. In the first embodiment ( Figure 1 In the first embodiment, switch 34S and an input port of power stage differential amplifier circuit 32 are interconnected via inter-component connection wiring 71 in the redistribution layer. In contrast, in the third embodiment, switch 34S is connected to an input port of power stage differential amplifier circuit 32 via conductor protrusion 85 provided in the first component 21, wiring 28 in the module substrate 25, and conductor protrusion 86 provided in the second component 22.

[0106] Next, the superior effects of the third embodiment will be explained.

[0107] In the third embodiment, bonding wires are not used to connect the power stage differential amplifier circuit 32 of the second component 22 and the switch 34S of the first component 21. Therefore, the increase in parasitic inductance inserted in series with the switch 34S can be suppressed. Furthermore, similar to the first embodiment, the third embodiment achieves various effects such as miniaturization of the high-frequency power amplifier, suppression of increased manufacturing costs, and suppression of temperature rise in the transistor 32T included in the power stage differential amplifier circuit 32.

[0108] [Fourth Embodiment]

[0109] Next, refer to Figure 12 The high-frequency power amplifier of the fourth embodiment will be described. Hereinafter, compared with the reference... Figures 1 to 7BThe structure of the high-frequency power amplifier in the first embodiment described in the accompanying drawings is omitted.

[0110] Figure 12 This is a schematic equivalent circuit diagram of the high-frequency power amplifier 20 in the fourth embodiment. In the first embodiment ( Figure 1 In the variable capacitance circuit 34, the two capacitors 34A and 34B are mounted on the module substrate 25. Figure 4 The surface-mount passive component is configured as such. In contrast, in the fourth embodiment, two capacitors 34A and 34B are disposed within the first component 21. For example, the multilayer wiring structure 52 of the first component 21 (…) Figure 2 The metal patterns contained in the first wiring layer and the metal patterns contained in the second wiring layer constitute capacitor 34A and capacitor 34B.

[0111] An electrode of capacitors 34A and 34B, which are configured in the first component 21, is connected to an input port of the power stage differential amplifier circuit 32 via inter-component connection wiring 74 included in the redistribution layer.

[0112] Next, refer to Figures 13 to 15 The accompanying drawings illustrate a modified high-frequency power amplifier of the fourth embodiment. Figure 13 , Figure 14 as well as Figure 15 These are schematic equivalent circuit diagrams of the high-frequency power amplifier 20, which are variations of the fourth embodiment.

[0113] exist Figure 13 In the variant shown, in addition to capacitors 34A and 34B, a first balancing converter 33 is also disposed in the first component 21. One end of the primary coil of the first balancing converter 33 is connected to the output port of the driver stage amplifier circuit 31 of the second component 22 via inter-component connection wiring 75 included in the redistribution layer.

[0114] exist Figure 14 In the variant shown, two capacitors 34A and 34B are disposed in the second component 22. Capacitors 34A and 34B, for example, can be connected to the input capacitor Cin(…). Figure 3B Similarly, it consists of the metal pattern contained in the first wiring layer and the metal pattern contained in the second wiring layer.

[0115] Switch 34S and capacitor 34A are interconnected via inter-component connection wiring 76 included in the rewiring layer. Additionally, capacitors 34A and 34B are connected via conductor protrusions provided on the second component 22 (in... Figure 14 The hollow square in the middle is connected to the secondary coil of the first balancing converter 33.

[0116] exist Figure 15 In the illustrated variation, in addition to the two capacitors 34A and 34B, the first balancing converter 33 is also disposed in the second component 22. As an example, the primary and secondary coils of the first balancing converter 33 can be respectively connected to the second component 22 (…). Figure 3B The first wiring layer contains a metal pattern, and the second wiring layer contains a metal pattern.

[0117] As another variation, the second balancing converter 35 and the output matching circuit 38 can also be configured in the first component 21 or the second component 22, respectively.

[0118] Next, the superior effects of the fourth embodiment and its variations will be explained.

[0119] As shown in the fourth embodiment and its variations, instead of surface-mount circuit components mounted on the module substrate 25, the various circuit elements constituting the high-frequency power amplifier 20 can be constituted by metal patterns or the like within the wiring layer of the first component 21 or the second component 22. By arranging the circuit elements in the first component 21 or the second component 22, compared to a structure composed of surface-mount circuit components, miniaturization of the high-frequency power amplifier 20 can be achieved.

[0120] Conversely, if various circuit elements are constructed from surface-mount circuit components as in the first embodiment, the deviation of circuit constants of passive components can be suppressed compared to a structure in which circuit elements are arranged within the first component 21 or the second component 22. Furthermore, the increase in the number of wiring layers included in the multilayer wiring structure provided in the first component 21 and the second component 22 can be suppressed. Whether the various circuit elements of the high-frequency power amplifier 20 are constructed from surface-mount circuit components mounted on the module substrate 25, or from metal patterns within the first component 21 or the second component 22, can be determined according to the specifications required for the high-frequency power amplifier 20.

[0121] [Fifth Embodiment]

[0122] Next, refer to Figure 16 The high-frequency power amplifier of the fifth embodiment will be described below. Hereinafter, compared with the reference... Figures 1 to 7B The structure of the high-frequency power amplifier in the first embodiment described in the accompanying drawings is omitted.

[0123] Figure 16 This is a schematic equivalent circuit diagram of the high-frequency power amplifier 20 in the fifth embodiment. In the first embodiment ( Figure 1In the first embodiment, the driver stage amplifier circuit 31 uses a single-ended signal amplifier circuit. In contrast, in the fifth embodiment, the driver stage amplifier circuit 31 uses a differential amplifier circuit, just like the power stage.

[0124] In the first embodiment ( Figure 1 In the first embodiment, the first balancing converter 33 and the variable capacitor circuit 34 are inserted between the driver stage amplifier circuit 31 and the power stage differential amplifier circuit 32. However, in the fifth embodiment, the first balancing converter 33 and the variable capacitor circuit 34 are connected to the input side of the driver stage amplifier circuit 31. The differential signal converted from the single-ended signal by the first balancing converter 33 is input to the two input ports of the driver stage amplifier circuit 31. One input port of the driver stage amplifier circuit 31 is interconnected with the switch 34S via the component connection wiring 71 in the rewiring layer.

[0125] Next, the superior effects of the fifth embodiment will be explained.

[0126] In the fifth embodiment, bonding wires are not used to connect the driver stage amplifier circuit 31 of the second component 22 and the switch 34S of the first component 21. Therefore, the increase in parasitic inductance inserted in series with the switch 34S can be suppressed. Furthermore, similar to the first embodiment, the fifth embodiment also achieves various effects such as miniaturization of the high-frequency power amplifier, suppression of increased manufacturing costs, and suppression of temperature rise in the transistor 32T of the power stage differential amplifier circuit 32.

[0127] The above embodiments are illustrative, and it can be said that partial substitutions or combinations of the structures shown in different embodiments are possible. The same effects achieved by the same structures in multiple embodiments are not mentioned sequentially in each embodiment. Furthermore, the present invention is not limited to the above embodiments. For example, it will be apparent to those skilled in the art that various changes, improvements, combinations, etc., can be made.

Claims

1. A semiconductor device comprising: The first component is equipped with a switch made of semiconductor elements of the elemental semiconductor system; The second component includes a high-frequency circuit comprising a compound semiconductor element and is coupled to the first component; and The path connects the aforementioned switch and the aforementioned high-frequency circuit. The aforementioned path includes inter-component connection wiring or conductive components. The inter-component connection wiring is arranged in a metallic pattern on an interlayer insulating film from the surface of the second component to the surface of the first component. The conductive components allow current to flow in a direction that intersects with the interface connecting the first and second components. The aforementioned high-frequency circuit includes a differential amplifier circuit. The aforementioned semiconductor device also includes a variable capacitance circuit connected between a pair of wires transmitting a differential signal input to the aforementioned differential amplifier circuit, comprising a capacitor and the aforementioned switch, wherein the capacitance between the pair of wires changes according to the opening and closing of the aforementioned switch.

2. The semiconductor device according to claim 1, wherein, The capacitor constituting the above-mentioned variable capacitance circuit is formed in the above-mentioned first component.

3. The semiconductor device according to claim 1, further comprising: The first balanced converter converts the single-ended signal into a differential signal input to the aforementioned differential amplifier circuit; and The second balanced converter converts the differential signal output from the differential amplifier circuit into a single-ended signal.

4. The semiconductor device according to claim 3, wherein, The aforementioned first balance converter and the aforementioned second balance converter are formed in the aforementioned first component.

5. The semiconductor device according to claim 3 or 4, wherein, It also includes a driver stage amplifier circuit, which outputs a single-ended signal that is input to the first balanced converter.

6. The semiconductor device according to claim 3 or 4, wherein, It also includes a power stage differential amplifier circuit, which amplifies the signal output from the differential amplifier circuit and outputs a differential signal input to the second balanced converter.

7. A semiconductor module, comprising: A semiconductor device includes a first component having a switch made of an elemental semiconductor system, and a second component having a high-frequency circuit having a semiconductor element made of a compound semiconductor system and being coupled to the first component. Module substrate, on which the aforementioned semiconductor device is mounted; and The path connects the aforementioned switch and the aforementioned high-frequency circuit. The aforementioned semiconductor device includes a first conductor protrusion connected to the aforementioned switch and a second conductor protrusion connected to the aforementioned high-frequency circuit. The aforementioned path includes the first conductor protrusion, the wiring disposed on the module substrate, and the second conductor protrusion. The aforementioned high-frequency circuit includes a differential amplifier circuit. The aforementioned semiconductor device also includes a variable capacitance circuit connected between a pair of wires transmitting a differential signal input to the aforementioned differential amplifier circuit, comprising a capacitor and the aforementioned switch, wherein the capacitance between the pair of wires changes according to the opening and closing of the aforementioned switch.

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