Electromigration test structure, semiconductor structure, and three-dimensional memory

Abstract

The application provides an electromigration test structure, a semiconductor structure and a three-dimensional memory. The electromigration test structure comprises a test line and a substrate. The test line is connected with an anode lead and a cathode lead; the substrate is connected with the cathode lead, and the substrate is configured to receive static electricity in the test line through the cathode lead. The application connects the cathode lead to the substrate, so that the substrate can receive the static electricity in the test line through the cathode lead. Therefore, even if static electricity is introduced during the test process and the subsequent failure analysis process, the static electricity can be led out to the substrate through the cathode lead, so as to reduce the possibility of explosion of the test line during the test and failure analysis processes.

Description

Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and more specifically, to an electromigration test structure, a semiconductor structure, and a three-dimensional memory. Background Technology

[0002] In recent years, as the feature size of semiconductor structures has become increasingly smaller, reliability assessment has become increasingly important, and electromigration testing is a crucial method for evaluating the reliability of back-end metal interconnect processes. Currently, electromigration testing is commonly performed using the electromigration effect. Figure 1A A commonly used electromigration test structure 1 is shown, including a metal line under test 11, an anode signal input line 12, and a cathode signal input line 13. The metal line under test 11 is connected to the anode signal input line 12 and the cathode signal input line 13 through a through-hole structure 14.

[0003] However, due to the formation of voids 15 inside the metal wire during electromigration testing using the electromigration effect, see reference... Figure 1A and Figure 1B As shown, the test structure utilizing the electromigration effect is also a typical floating structure. If static electricity is introduced into the metal wire 11 under test, it may cause the metal wire to burn out at the location of the void 15. (Refer to...) Figure 1C As shown.

[0004] For example, introducing static electricity when disconnecting the wire at the end of the electromigration test may cause the sample to explode at the void location, as shown in the reference. Figure 2A As shown.

[0005] For example, after electromigration testing, scanning the sample with a scanning electron microscope (SEM) during failure analysis may also cause deflagration at the void location, as described above. Figure 2B As shown. Summary of the Invention

[0006] This application provides an electromigration test structure, a semiconductor structure, and a three-dimensional memory that can at least partially solve the above-mentioned problems existing in the related art.

[0007] This application provides an electromigration test structure, including test lines and a substrate. The test lines are connected to an anode lead and a cathode lead; the substrate is connected to the cathode lead and configured to receive static charge from the test lines through the cathode lead.

[0008] In some embodiments, the cathode lead includes a stacked structure comprising a first metal layer and a second metal layer alternately stacked in a direction perpendicular to the substrate; one end of the stacked structure is connected to a test line via a signal transmission plug, and the other end of the stacked structure is connected to the substrate.

[0009] In some embodiments, the first metal layer includes multiple interwoven metal wires arranged in a grid; the second metal layer includes multiple arrayed metal via structures. The interweaving positions of the metal wires in the first metal layer correspond one-to-one with the metal via structures in the second metal layer.

[0010] An electromigration test structure includes a substrate and test lines. The test lines are connected to a first lead and a second lead. The first and second leads are respectively connected to the substrate via unidirectional current conduction structures, with the conduction directions of the two unidirectional current conduction structures being opposite. The substrate is configured to receive static charge from the test lines through the first and second leads.

[0011] In some embodiments, the first lead and the second lead are respectively disposed on the side of the test line closer to the substrate and the side farther from the substrate. Alternatively, both the first lead and the second lead are disposed on the side of the test line closer to the substrate or the side farther from the substrate.

[0012] In some embodiments, two unidirectional current-conducting structures are formed in the substrate. Each unidirectional current-conducting structure includes a first doped region and a second doped region. The first doped region has first doped ions, and a first lead and a second lead are respectively connected to the first doped region. The second doped region is located at least below and in contact with the first doped region, and has second doped ions with a conductivity type opposite to that of the first doped ions.

[0013] In some embodiments, both the cathode lead and the anode lead include a stacked structure, which includes alternating first and second metal layers; one end of the stacked structure is connected to the test line via a signal transmission plug, and the other end of the stacked structure is connected to the substrate.

[0014] In some embodiments, the first metal layer includes multiple interwoven metal wires arranged in a grid; the second metal layer includes multiple arrayed metal via structures. The interweaving positions of the metal wires in the first metal layer correspond one-to-one with the metal via structures in the second metal layer.

[0015] Another embodiment of this application provides a semiconductor structure, including the electromigration test structure as described above.

[0016] In some implementations, the semiconductor structure also includes multiple chips with cleavage channels between adjacent chips; an electromigration test structure is disposed within the cleavage channels.

[0017] Another embodiment of this application provides a three-dimensional memory, including: a first wafer and a second wafer. The outer surface of the first wafer has a semiconductor structure as described above, and the inner surface of the first wafer has peripheral circuitry. The inner surface of the second wafer has a memory cell array and interconnection structure. The inner surfaces of the first wafer and the second wafer are bonded to each other.

[0018] The electromigration test structure provided in this application connects the cathode lead to the substrate, enabling the substrate to receive static charge in the test line through the cathode lead. Therefore, even if static electricity is introduced into the test line when the line is pulled out at the end of the test, or when the test line is scanned with a scanning electron microscope during subsequent failure analysis, this static electricity can be discharged to the substrate through the cathode lead, thereby reducing the possibility of the test line exploding during the test and failure analysis process.

[0019] The electromigration test structure provided in this application sets the metal lines of the first metal layer of the lead stack structure into a grid, and sets the metal via structure of the second metal layer of the stack structure into an array. This transforms the large-sized metal structure capable of withstanding large currents in related technologies into an array structure of numerous small-sized metal lines and metal via structures. This avoids introducing large-sized metals into the dicing channels of the semiconductor structure, thus enabling the lead to withstand large currents while avoiding the presence of large-sized metals in the dicing channels.

[0020] The electromigration test structure provided in this application provides a unidirectional current conduction structure with opposite conduction directions between the lead and the substrate. This eliminates the need to limit the first lead and the second lead to being either anode or cathode leads, thus avoiding the situation where incorrect lead connection would damage the performance of the semiconductor structure. It also improves the operability for testers. Attached Figure Description

[0021] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0022] Figures 1A to 1C These are schematic diagrams of electromigration test structures in some implementation methods;

[0023] Figure 2A and 2B These are schematic diagrams illustrating the deflagration phenomenon of test samples in some implementation methods;

[0024] Figure 3 This is a schematic diagram of the electromigration test structure according to the first embodiment of this application;

[0025] Figure 4 yes Figure 3 Enlarged view of a section at point I;

[0026] Figure 5 yes Figure 4 A partial schematic diagram of the AA-direction cross-sectional structure in the image;

[0027] Figure 6 yes Figure 4 A partial schematic diagram of the BB-direction cross-sectional structure in the middle;

[0028] Figure 7 This is a schematic diagram of an electromigration test structure according to the second embodiment of this application;

[0029] Figure 8 yes Figure 7 Enlarged view of section II in the middle;

[0030] Figure 9 yes Figure 8 A partial schematic diagram of the CC-direction cross-sectional structure in the image;

[0031] Figure 10 yes Figure 8 A partial schematic diagram of the DD-direction cross-sectional structure; and

[0032] Figure 11 This is a schematic diagram of an electromigration test structure according to the third embodiment of this application. Detailed Implementation

[0033] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first part discussed herein may also be referred to as the second part, and vice versa.

[0035] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0036] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0037] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0038] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0039] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0040] Figure 3 A schematic diagram of an electromigration test structure 100 according to a first embodiment of this application is shown. Figure 3 As shown, the electromigration test structure 100 includes a test line 120 and a substrate 110. The test line 120 is connected to an anode lead 130 and a cathode lead 140; the substrate 110 is connected to the cathode lead 140 and is configured to receive static charge in the test line 120 through the cathode lead 140.

[0041] In some embodiments, one end of the anode lead 130 and the cathode lead 140 is connected to the test lead 120 via a signal transmission plug 150, and the other end can be connected to a signal input line (not shown) in an external circuit to introduce a test signal during the electromigration test.

[0042] By connecting the cathode lead 140 to the substrate 110, the substrate 110 can receive static charge from the test line 120 through the cathode lead 140. Therefore, even if static electricity is introduced into the test line 120 when it is disconnected at the end of the test, or when the test line 120 is scanned with a scanning electron microscope during subsequent failure analysis, this static electricity can be discharged to the substrate 110 through the cathode lead 140, thereby reducing the possibility of burnout of the test line 120 during testing and failure analysis. It is understood that the above-described scenario of introducing static electricity is only an illustrative example, and the above technical solution of this application can also solve the technical problem of introducing static electricity and causing burnout in other scenarios. This application does not limit this.

[0043] In some embodiments, the material of the substrate 110 may be selected from monocrystalline silicon, polycrystalline silicon, or amorphous silicon; or the material of the substrate 110 may be selected from compounds such as silicon, germanium, gallium arsenide, or germanium silicon; or the substrate 110 may be other semiconductor materials.

[0044] In other words, in the above embodiments of this application, the substrate 110 can be approximately equivalent to a ground wire, and the cathode lead 140 of the electromigration test structure 100 is connected to the substrate 110, thereby grounding the entire electromigration test structure 100. This can effectively reduce the possibility of burnout of the test line 120 during testing and failure analysis, thereby improving the reliability of the semiconductor structure.

[0045] Furthermore, in the above scheme, only the cathode lead 140 is connected to the substrate 110, while the anode lead 130 is not connected to the substrate 110. Therefore, during the electromigration test, no current loop is formed between the test line 120 and the substrate 110, which means that the current density of the test line 120 during the electromigration test will not be changed, and the reliability test data will not be affected.

[0046] In some implementations, such as Figure 4 As shown, the cathode lead 140 includes a stacked structure 141, which includes a first metal layer 142 and a second metal layer 143 alternately stacked in a direction perpendicular to the substrate 110. One end of the stacked structure 141 is connected to the test line 120 through a signal transmission plug 150, and the other end of the stacked structure 141 is connected to the substrate 110.

[0047] It is understood that both the anode lead 130 and the cathode lead 140 are formed in the dielectric layer (not shown) of the semiconductor structure, and the anode lead 130 and the cathode lead 140 are formed synchronously with other devices in the same process of the semiconductor structure, depending on their location. Therefore, the number of layers in the stacked structure 141, such as the first metal layer 142 and the second metal layer 143, can be designed as 2, 3, or 4 layers, depending on the actual situation, and this application does not impose any restrictions on this. The above scheme enables the electromigration test structure 100 of this application to be formed using existing processes, saving manufacturing costs.

[0048] As mentioned above, introducing static electricity into the test line 120 can cause deflagration. Static electricity damage is often characterized by instantaneous high voltage and high current. Therefore, in the above-mentioned scheme of this application, the cathode lead 140 is set as a metal laminate structure, which enables the cathode lead 140 to withstand a large current and further reduces the possibility of static electricity damage.

[0049] In some implementations, refer to Figure 5 and Figure 6 As shown, the first metal layer 142 includes multiple interwoven metal wires 1421 arranged in a grid pattern; the second metal layer 143 includes multiple arrayed metal via structures 1431. The interlacing positions 1422 of the metal wires 1421 in the first metal layer 142 are connected one-to-one with the metal via structures 1431 in the second metal layer 143.

[0050] In some embodiments, the linewidth of each metal line 1421 is between 300 nm and 500 nm, and the spacing between two adjacent metal lines 1421 is between 200 nm and 400 nm.

[0051] In some embodiments, the first metal layer 142 of each layer may include approximately 11*11 metal wires 1421, and correspondingly, the second metal layer 143 of each layer may include approximately 11*11 metal via structures 1431. It should be noted that the above-described limitations on the number of metal wires 1421 and metal via structures 1431 are merely illustrative examples, and the appropriate numbers can be set as needed in practical applications.

[0052] For example, the material of the metal wire 1421 is copper, and the material of the metal via structure 1431 is tungsten. Those skilled in the art can also choose other materials to form the metal wire 1421 and the metal via structure 1431 according to actual needs, as long as they have good conductivity and can guide electrons in the test line 120 to the substrate 110. Furthermore, it should be noted that since the first metal layer 142 and the second metal layer 143 in the stacked structure 141 are formed layer by layer, the material of the metal wire 1421 in each first metal layer 142 should be the same. Similarly, the material of the metal via structure 1431 in each second metal layer 143 should be the same. However, the materials of the metal wire 1421 or the metal via structure 1431 in different first metal layers 142 can be the same or different.

[0053] Since electrostatic breakdown often involves a high voltage and a large current passing through the cathode lead 140 in a short period of time, the dimensions of the aforementioned stacked structure 141 need to be increased to withstand the large current. However, the electromigration test structure is generally placed in the dicing channel of the semiconductor structure. If there is a large piece of metal in the dicing channel, it will make the laser cutting process of the semiconductor structure very difficult.

[0054] Based on this, in the above technical solution of this application, the metal lines 1421 of the first metal layer 142 of the stacked structure 141 are set in a grid shape, and the metal via structure 1431 of the second metal layer 143 of the stacked structure 141 is set in an array shape. The large-sized metal structure that can withstand large current in the related technology is transformed into an array structure of a large number of small-sized metal lines and metal via structures. This avoids the introduction of large-sized metal in the dicing channel of the semiconductor structure, so that the cathode lead 140 can withstand large current while avoiding the appearance of large-sized metal in the dicing channel.

[0055] Figure 7 A schematic diagram of an electromigration test structure 200 according to a second embodiment of this application is shown. Figure 7 As shown, the electromigration test structure 200 includes a test line 220 and a substrate 210. The test line 220 is connected to a first lead 230 and a second lead 240. The first lead 230 and the second lead 240 are connected to the substrate 210 via a first unidirectional current conduction structure 260 and a second unidirectional current conduction structure 270, respectively, with the conduction directions of the first unidirectional current conduction structure 260 and the second unidirectional current conduction structure 270 being opposite. The substrate 210 is configured to receive static charge from the test line 220 via the first lead 230 and the second lead 240.

[0056] It should be noted that the above "conduction direction opposite" means that the conduction direction is opposite in the direction of current flow.

[0057] In some embodiments, one end of the first lead 230 and the second lead 240 is connected to the test lead 220 via a signal transmission plug 250, and the other end can be connected to a signal input line (not shown) in an external circuit to introduce a test signal during the electromigration test.

[0058] In the above scheme, the first unidirectional current conduction structure 260 and the second unidirectional current conduction structure 270 have a blocking effect on current, but no blocking effect on static charge. Therefore, by connecting the first lead 230 and the second lead 240 to the substrate 210 through the first unidirectional current conduction structure 260 and the second unidirectional current conduction structure 270, the substrate 210 can receive the static charge in the test line 220 through the first lead 230 and the second lead 240. Thus, even if static electricity is introduced into the test line 220 when the line is disconnected at the end of the test, or when the test line 220 is scanned with a scanning electron microscope during subsequent failure analysis, this static electricity can be discharged to the substrate 210 through the first lead 230 and the second lead 240, thereby reducing the possibility of burnout of the test line 220 during testing and failure analysis. It is understood that the above scenario of introducing static electricity is only an illustrative example, and the above technical solution of this application can also solve the technical problem of introducing static electricity and causing burnout in other scenarios. This application does not limit this.

[0059] Furthermore, it should be noted that in this embodiment, since the first lead 230 and the second lead 240 are connected to the substrate through the first unidirectional current conduction structure 260 and the second unidirectional current conduction structure 270 respectively, when the first lead 230 is connected to the positive terminal of the peripheral signal input line and the second lead 240 is connected to the negative terminal of the peripheral signal input line, or when the first lead 230 is connected to the negative terminal of the peripheral signal input line and the second lead 240 is connected to the positive terminal of the peripheral signal input line, since the conduction directions of the first unidirectional current conduction structure 260 and the second unidirectional current conduction structure 270 are opposite, one of the first unidirectional current conduction structure 260 and the second unidirectional current conduction structure 270 will necessarily have a blocking effect on the current. Therefore, during the electromigration test, no current loop will be formed between the test line 220 and the substrate 210, that is, the current density of the test line 220 during the electromigration test will not be changed, and the reliability test data will not be affected.

[0060] As can be seen, the first lead 230 and the second lead 240 in the above embodiments do not need to be limited to anode leads or cathode leads, which can avoid the situation where incorrect lead connection causes damage to the performance of the semiconductor structure, and can also improve the operability of testers.

[0061] In some embodiments, the material of the substrate 210 may be selected from monocrystalline silicon, polycrystalline silicon, or amorphous silicon; or the material of the substrate 210 may be selected from compounds such as silicon, germanium, gallium arsenide, or germanium silicon; or the substrate 210 may be other semiconductor materials.

[0062] In other words, in the above embodiments of this application, the substrate 210 can be approximately equivalent to a ground wire. The first lead 230 and the second lead 240 of the electromigration test structure 200 are connected to the substrate 210, thereby grounding the entire electromigration test structure 200. This can effectively reduce the possibility of burnout of the test line 220 during testing and failure analysis, thereby improving the reliability of the semiconductor structure.

[0063] In some implementations, such as Figure 7 As shown, the first lead 230 and the second lead 240 are respectively connected to the side of the test line 220 that is close to the substrate 210 and the side that is far away from the substrate 210.

[0064] In the above scheme, the lead-out directions of the first lead 230 and the second lead 240 can be respectively set on both sides of the test line 220, so that the electromigration test structure 200 can be used for both upper and lower purposes.

[0065] In some embodiments, two unidirectional current-conducting structures (a first unidirectional current-conducting structure 260 and a second unidirectional current-conducting structure 270) are both formed in the substrate 210. Each unidirectional current-conducting structure includes a first doped region 280 and a second doped region 290. The first doped region 280 has first doped ions and is connected to a first lead 230 or a second lead 240. The second doped region 290 contacts and surrounds the first doped region 280 to electrically isolate the first doped region 280 from the substrate 210. The second doped region 290 has second doped ions, and the second doped ions have the opposite conductivity type to the first doped ions.

[0066] For example, refer to Figure 7As shown, the first doped ion is an N-type ion, the second doped ion is a P-type ion, and the second doped region 290 can form a P-well. Therefore, a PN junction can be formed at the contact point between the first doped region 280 and the second doped region 290. When the first lead 230 is connected to a positive voltage of the external test signal and the second lead 240 is connected to a negative voltage of the external test signal, the PN junction in the second unidirectional current conduction structure 270 is in a non-conductive state. Therefore, during electromigration testing, no current loop is formed between the test line 220 and the substrate 210. When the first lead 230 is connected to a negative voltage of the external test signal and the second lead 240 is connected to a positive voltage of the external test signal, the PN junction in the first unidirectional current conduction structure 270 is in a non-conductive state. Therefore, during electromigration testing, no current loop is formed between the test line 220 and the substrate 210.

[0067] It is understood that the first doped ion can also be a P-type ion, and the second doped ion can be an N-type ion. In this case, a PN junction is also formed at the contact position between the first doped region 280 and the second doped region 290. The specific implementation method can be referred to the example above, and will not be repeated here.

[0068] In some implementations, such as Figure 8 As shown, the first lead 230 and the second lead 240 include a stacked structure 241, which includes a first metal layer 242 and a second metal layer 243 alternately stacked in a direction perpendicular to the substrate 210. One end of the stacked structure 241 is connected to the test line 220 through a signal transmission plug 250, and the other end of the stacked structure 241 is connected to the substrate 210.

[0069] As mentioned above, introducing static electricity into the test lead 220 can cause a deflagration phenomenon. Static electricity damage is often characterized by instantaneous high voltage and high current. Therefore, in the above-mentioned solution of this application, the second lead 240 is set as a metal laminate structure, which enables the second lead 240 to withstand a large current and further reduces the possibility of static electricity damage.

[0070] In some implementations, such as Figure 9 and Figure 10 As shown, the first metal layer 242 includes multiple interwoven metal wires 2421 arranged in a grid pattern; the second metal layer 243 includes multiple arrayed metal via structures 2431. The interlacing positions 2422 of the metal wires 2421 in the first metal layer 242 correspond one-to-one with the metal via structures 2431 in the second metal layer 243.

[0071] In some embodiments, the linewidth of each metal line 2421 is between 300nm and 500nm, and the spacing between two adjacent metal lines 2421 is between 200nm and 400nm.

[0072] In some embodiments, the first metal layer 242 of each layer may include approximately 11*11 metal wires 2421, and correspondingly, the second metal layer 243 of each layer may include approximately 11*11 metal via structures 2431. It should be noted that the above-described limitations on the number of metal wires 2421 and metal via structures 2431 are merely illustrative examples, and the appropriate numbers can be set as needed in practical applications.

[0073] Furthermore, it should be noted that both the first lead 230 and the second lead 240 are formed in the dielectric layer (not shown) of the semiconductor structure. Since the first metal layer 242 and the second metal layer 243 in the stacked structure 241 are formed layer by layer and synchronously with the semiconductor device in the same process of the semiconductor structure, when the first lead 230 and the second lead 240 are respectively disposed on both sides of the test line 220, the number of layers in the stacked structure in the first lead 230 is different from the number of layers in the stacked structure in the second lead 240. Moreover, the material of the metal lines 2421 in each first metal layer 242 should be the same; similarly, the material of the metal via structures 2431 in each second metal layer 243 should be the same. However, the materials of the metal lines 2421 between different first metal layers 242 or the metal via structures 2431 in different second metal layers 243 can be the same or different.

[0074] For example, the material of the metal line 2421 is copper, and the material of the metal through-hole structure 2431 is tungsten. Those skilled in the art can also choose other materials to form the metal line 2421 and the metal through-hole structure 2431 according to actual needs, as long as they have good conductivity and can guide the electrons in the test line 220 to the substrate 210.

[0075] Since electrostatic breakdown often involves a high voltage and a large current passing through the second lead 240 in a short period of time, the dimensions of the aforementioned stacked structure 241 need to be increased to withstand the large current. However, electromigration test structures are generally placed in the dicing channels of semiconductor structures. If there are large pieces of metal in the dicing channels, it will make the laser cutting process of the semiconductor structure very difficult.

[0076] Based on this, in the above technical solution of this application, the metal lines 2421 of the first metal layer 242 of the stacked structure 241 are set in a grid shape, and the metal via structure 2431 of the second metal layer 243 of the stacked structure 241 is set in an array shape. The large-sized metal structure that can withstand large current in the related technology is transformed into an array structure of a large number of small-sized metal lines and metal via structures. This avoids the introduction of large-sized metal in the dicing channel of the semiconductor structure, so that the second lead 240 can withstand large current while avoiding the appearance of large-sized metal in the dicing channel.

[0077] Figure 11 A schematic diagram of an electromigration test structure 200 according to a second embodiment of this application is shown. Figure 11 As shown, the electromigration test structure 300 includes a test line 320 and a substrate 310. The test line 320 is connected to a first lead 330 and a second lead 340. The first lead 330 and the second lead 340 are connected to the substrate 310 via a first unidirectional current conduction structure 360 ​​and a second unidirectional current conduction structure 370, respectively, with the conduction directions of the first unidirectional current conduction structure 360 ​​and the second unidirectional current conduction structure 370 being opposite. The substrate 310 is configured to receive static charge from the test line 320 through the first lead 330 and the second lead 340.

[0078] In some embodiments, one end of the first lead 330 and the second lead 340 is connected to the test lead 320 via a signal transmission plug 350, and the other end can be connected to an external signal input line (not shown) to introduce a test signal during the electromigration test.

[0079] As mentioned above Figure 7 The second embodiment shown differs in that the first lead 330 and the second lead 340 are both connected to the side of the test line 320 that is close to the substrate 310 or away from the substrate 310.

[0080] It should be noted that, unless otherwise specified, other features in this embodiment can be referred to in the foregoing embodiments, such as... Figures 7 to 10 The features shown are therefore not described again here.

[0081] This application also provides a semiconductor structure (not shown) including the electromigration test structure provided in the first, second, or third embodiment above.

[0082] The semiconductor structure also includes multiple chips (not shown), with cleavage channels (not shown) between adjacent chips, and electromigration test structures 100, 200, and 300 disposed within the cleavage channels.

[0083] It is understandable that the substrates 110, 210, and 310 in the electromigration test structures 100, 200, and 300 are semiconductor substrates.

[0084] In the above scheme, the electromigration test structure is set on the dicing channel of the semiconductor structure, without occupying the chip fabrication space on the semiconductor structure. Furthermore, the leads of the electromigration test structure are set in a grid and array shape to avoid large-size metal in the dicing channel, which would be detrimental to laser cutting of the semiconductor structure.

[0085] Another embodiment of this application provides a three-dimensional memory, including: a first wafer and a second wafer. The outer surface of the first wafer has a semiconductor structure as described above, and the inner surface of the first wafer has peripheral circuitry. The inner surface of the second wafer has a memory cell array and interconnection structure. The inner surfaces of the first wafer and the second wafer are bonded to each other.

[0086] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. An electromigration test structure, characterized in that, include: Test leads, wherein the test leads are connected to an anode lead and a cathode lead; A substrate connected to the cathode lead, the substrate being configured to receive static charge in the test line via the cathode lead; The cathode lead includes a stacked structure, which includes a first metal layer and a second metal layer alternately stacked in a direction perpendicular to the substrate; The first metal layer comprises multiple metal wires interwoven in a grid pattern; The second metal layer includes a plurality of metal via structures arranged in an array; The interlacing positions of the metal wires in the first metal layer are connected one-to-one with the metal via structures in the second metal layer.

2. The electromigration test structure according to claim 1, wherein, One end of the stacked structure is connected to the test line via a signal transmission plug, and the other end of the stacked structure is connected to the substrate.

3. An electromigration test structure, characterized in that, include: Substrate; A test lead, wherein the test lead is connected to a first lead and a second lead; The first lead and the second lead are respectively connected to the substrate through a unidirectional current conduction structure, and the conduction directions of the two unidirectional current conduction structures are opposite; the substrate is configured to receive static charge in the test line through the first lead and the second lead; Both the first lead and the second lead include a stacked structure, wherein the stacked structure includes alternating first metal layers and second metal layers; The first metal layer comprises multiple metal wires interwoven in a grid pattern; The second metal layer includes a plurality of metal via structures arranged in an array; The interlacing positions of the metal wires in the first metal layer are connected one-to-one with the metal via structures in the second metal layer.

4. The electromigration test structure according to claim 3, wherein, The first lead and the second lead are respectively connected to the side of the test line closer to the substrate and the side farther from the substrate; Alternatively, both the first lead and the second lead are connected to the test line on the side closer to the substrate or the side farther from the substrate.

5. The electromigration test structure according to claim 3, wherein, Two of the aforementioned unidirectional current conduction structures are formed in the substrate; Each of the current unidirectional conduction structures includes: The first doped region has a first doped ion and is connected to the first lead or the second lead; A second doped region is in contact with and surrounds the first doped region to electrically isolate the first doped region from the substrate. The second doped region has a second doped ion with the opposite conductivity type to the first doped ion.

6. The electromigration test structure according to any one of claims 3-5, wherein, One end of the stacked structure is connected to the test line via a signal transmission plug, and the other end of the stacked structure is connected to the substrate.

7. A semiconductor structure, characterized in that, It includes the electromigration test structure as described in any one of claims 1-2 or the electromigration test structure as described in any one of claims 3-6.

8. The semiconductor structure according to claim 7, wherein, It also includes multiple chips, with cleaving channels between adjacent chips; The electromigration test structure is located within the cut channel.

9. A three-dimensional memory, characterized in that, include: A first wafer, wherein the outer surface of the first wafer has a semiconductor structure as described in claim 7 or 8, and the inner surface of the first wafer has a peripheral circuit. as well as The second wafer has a memory cell array and interconnect structure on its inner surface; The inner surfaces of the first wafer and the inner surfaces of the second wafer are bonded to each other.

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