A processing method, device, apparatus and storage medium of atomic operation
By monitoring and locating memory exclusive events in multi-core processors and dynamically disabling the cache of the target memory address, the performance degradation caused by atomic operations is resolved, ensuring the correctness of atomic operations and overall system performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ALIBABA (CHINA) CO LTD
- Filing Date
- 2022-03-03
- Publication Date
- 2026-07-17
AI Technical Summary
Atomic operations can cause performance degradation in multi-core processors, especially when variables span multiple cache lines. The MESI protocol cannot meet atomicity requirements, leading to memory monopoly events that affect the performance of other cores.
By monitoring memory exclusive events in computing devices, the target memory address is located, and the cache corresponding to the target memory address is dynamically closed when the trigger condition is met, so that atomic operations can directly access memory and avoid accessing the cache.
It effectively mitigates memory monopoly events caused by accessing the cache during atomic operations, ensuring the normal execution of atomic operations while reducing the impact on the performance of other cores.
Smart Images
Figure CN114661428B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, device, and storage medium for processing atomic operations. Background Technology
[0002] Atomic operations are a fundamental feature of multi-core processors. They enable a set of operations, such as comparisons, arithmetic additions, and swaps in CAS operations, to be performed in a transactional manner, with either all operations being performed or none being performed. In practice, atomic operations heavily rely on cache coherency protocols, such as Intel x86's MESI protocol, which can guarantee the correctness of operations like CAS at the cache line level.
[0003] However, when the variables involved in an atomic operation span multiple cache lines, the atomicity provided by protocols such as MESI will not meet the requirements. In this case, Intel x86 handles it by locking the memory bus, so that only the CPU core to which the current atomic operation belongs can access the corresponding memory variables, thereby preventing instructions from other CPU cores from interfering with the operation.
[0004] While this approach ensures the correctness of atomic operations, it introduces serious performance problems for multi-core processors. Summary of the Invention
[0005] This application provides a method, apparatus, device, and storage medium for processing atomic operations, which aims to mitigate the performance degradation of multi-core processors caused by atomic operations.
[0006] This application provides a method for processing atomic operations, including:
[0007] Monitor memory exclusive events occurring in a computing device, where the memory exclusive events are caused by atomic operations;
[0008] Locate the target memory address corresponding to the memory exclusive event;
[0009] If the memory exclusive event occurring at the target memory address meets the triggering condition, the cache corresponding to the target memory address is closed, so that the atomic operation carried by the target memory address can access memory instead of accessing the cache.
[0010] This application also provides a computing device, including a memory and a processor;
[0011] The memory is used to store one or more computer instructions that implement virtualization functions;
[0012] The processor is coupled to the memory and is used to execute the one or more computer instructions for:
[0013] Monitor memory exclusive events occurring in the computing device, where the memory exclusive events are caused by atomic operations;
[0014] Locate the target memory resource corresponding to the memory exclusive event;
[0015] If a memory exclusive event occurring on the target memory resource meets the triggering condition, the cache resource corresponding to the target memory resource is closed, so that the atomic operations carried by the target memory resource can access the memory resource instead of accessing the cache resource.
[0016] This application embodiment also provides a control device, including:
[0017] A monitoring module is used to monitor memory exclusive events occurring in the computing device, the memory exclusive events being caused by atomic operations;
[0018] The positioning module is used to locate the target memory address corresponding to the memory exclusive event;
[0019] The processing module is configured to close the cache corresponding to the target memory resource if the memory exclusive event occurring at the target memory address meets the triggering condition, so as to guide the atomic operation carried by the target memory address to access memory instead of accessing the cache.
[0020] This application also provides a computer-readable storage medium storing computer instructions, which, when executed by one or more processors, causes the one or more processors to perform the aforementioned atomic operations.
[0021] In this embodiment, when a memory monopoly event occurs in a computing device, the target memory address corresponding to the memory monopoly event can be located. If the memory monopoly event occurring at the target memory address meets the triggering conditions, the cache corresponding to the target memory address is dynamically disabled. This guides the atomic operations carried by the target memory address to directly access memory without going through the cache. In this way, the atomic operations carried by the target memory address can read and write the required data through memory, ensuring the normal execution of the atomic operations. Since the atomic operations that might lead to a memory monopoly event are guided to memory instead of accessing the cache, the memory monopoly event caused by the atomic operations accessing the cache can be effectively mitigated. Attached Figure Description
[0022] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0023] Figure 1aA schematic diagram of the structure of a computing device including a multi-core processor is provided for an exemplary embodiment of this application;
[0024] Figure 1b A flowchart illustrating an atomic operation processing method provided for an exemplary embodiment of this application;
[0025] Figure 2 A logical schematic diagram of a method for processing atomic operations provided in an exemplary embodiment of this application;
[0026] Figure 3 A schematic diagram illustrating the dynamic change of a status identifier provided for an exemplary embodiment of this application;
[0027] Figure 4 A schematic diagram of the structure of a computing device is provided for another exemplary embodiment of this application;
[0028] Figure 5 This is a schematic diagram of the structure of a control device provided as another exemplary embodiment of this application. Detailed Implementation
[0029] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0030] Currently, ensuring the correctness of atomic operations has led to serious performance issues for multi-core processors. To address this, some embodiments of this application propose the following: When a memory monopoly event occurs in a computing device, the target memory address corresponding to the memory monopoly event can be located. If the memory monopoly event occurring at the target memory address meets the triggering conditions, the cache corresponding to the target memory address can be dynamically disabled. This guides the atomic operations carried by the target memory address to directly access memory without going through the cache. In this way, the atomic operations carried by the target memory address can read and write the required data through memory, ensuring the normal execution of atomic operations. Since atomic operations that might lead to memory monopoly events are guided to memory instead of accessing the cache, memory monopoly events caused by atomic operations accessing the cache can be effectively mitigated.
[0031] Before introducing the technical solution of this application, a brief explanation of the technical concepts involved in this application will be given first:
[0032] Atomic operations are a set of operations (such as read, write, or arithmetic operations) performed on a variable that satisfy the transaction semantics of either all operations are performed or none are performed. When multiple threads access shared resources, once an atomic operation begins in one thread, it runs continuously until completion without being interrupted by other threads.
[0033] Memory exclusive event: In architectures such as Intel x86, if an atomic operation involves data that spans two or more cache lines, the entire memory bus operation will be stopped, and only the atomic operation will be allowed to execute to ensure the atomicity of the operation. Such an event is referred to as a memory exclusive event in this application. Typical memory exclusive events may include Split Lock events.
[0034] Cache line: A cache consists of many cache lines. A cache line is the smallest unit of data exchange between the cache and RAM, typically 64 bytes. When the CPU loads data from memory into the cache, it places adjacent data (64 bytes in total) into the same cache line.
[0035] Memory address: Used to describe the location of data in memory. The memory mentioned here can be the memory in a regular computer or the memory resources in a cloud computing scenario.
[0036] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.
[0037] Figure 1b This is a flowchart illustrating an exemplary embodiment of the present application for a method of processing atomic operations. Figure 2 This is a logical diagram illustrating a method for processing atomic operations provided in an exemplary embodiment of this application. Atomic operations are a fundamental function of multi-core processors, enabling a set of operations, such as comparison, arithmetic addition, and swap operations in CAS operations, to be performed in a transactional manner where all operations are performed or none are performed. Figure 1a A schematic diagram of a computing device including a multi-core processor is provided for an exemplary embodiment of this application, with reference to... Figure 1a As can be seen, a computing device can contain multiple cores, and each core can contain multiple CPUs (which can be virtual CPUs). Figure 1aThe diagram also illustrates the storage structure of a computing device, where L1, L2, and L3 represent the Level 1, Level 2, and Level 3 caches, respectively. The closer the cache is to the CPU, the faster it is, but the smaller its capacity. The L1 cache is small but fast, and is located close to the CPU using it; it can be divided into instruction cache and data cache. L2 is larger and slower, and can still only be used by a single core. L3 is even larger and slower, and is shared by all cores on a single socket. Finally, there is main memory, shared by all cores across all sockets. When the CPU performs a calculation, it defaults to first looking for the required data in L1, then L2, then L3. If the data is not found in any of these caches, it must be retrieved from main memory. The further away the cache is, the longer the calculation time will be. It should be understood that for typical computer scenarios… Figure 1a The CPU, cache, and memory mentioned can be hardware components on a computer; however, in a cloud computing scenario, Figure 1a The CPU in this context can be the CPU resources provided in a cloud computing scenario. Similarly, cache and memory can be the corresponding storage resources provided in a cloud computing scenario.
[0038] In either scenario, an intermediate control layer is typically deployed between the hardware system and operating system of a computing device containing a multi-core processor. This intermediate control layer allows multiple operating systems and applications to share a set of basic physical hardware resources, and can therefore be considered a "meta" operating system in the virtual environment. It coordinates access to all physical hardware resources and virtual machines on the computing device. This intermediate control layer is the core of all virtualization technologies, supporting non-disruptive migration of multiple workloads. When the computing device starts and executes this intermediate control layer, it allocates appropriate physical hardware resources such as memory, CPU, network, and disk to each virtual machine and loads the guest operating system for all virtual machines. A typical intermediate control layer can be a hypervisor; however, this application is not limited to this. The intermediate control layer in this application can also employ other existing or future virtualization technologies besides the hypervisor. Furthermore, the atomic operation processing method provided in this application can be implemented under the control of this intermediate control layer.
[0039] During their research, the inventors discovered that atomic operations are highly dependent on cache coherency protocols, such as Intel x86's MESI protocol, which can guarantee the correctness of operations like CAS at the cache line level. However, when the variables of an atomic operation span multiple cache lines, the atomicity provided by the MESI protocol cannot meet the requirements. In this case, the x86 implementation locks the memory bus, ensuring that only the operation can access the corresponding memory variable, thus preventing other CPU instructions from interfering with the operation. This type of atomic operation leads to memory monopoly events. Although memory monopoly events can guarantee the correctness of atomic operations, they introduce serious performance problems to computing devices because when a memory monopoly event occurs, the reference... Figure 1a In multi-core processors, only one core can actually access memory, while the other cores cannot, which severely impacts the performance of the other cores. The inventors discovered this problem and proposed the technical solution in this application.
[0040] refer to Figure 1a The atomic operation processing method provided in this application may include:
[0041] Step 100: Monitor memory exclusive events occurring in the computing device, which are caused by atomic operations;
[0042] Step 101: Locate the target memory address corresponding to the memory exclusive event;
[0043] Step 102: If the memory exclusive event occurring at the target memory address meets the triggering condition, then close the cache corresponding to the target memory address to guide the atomic operation carried by the target memory address to access memory instead of accessing the cache.
[0044] Currently, Intel provides a hardware exception feature to allow system software to understand whether the operating system (Guest OS) has triggered memory exclusive events such as Split Lock. This hardware exception feature is an existing function on Intel chips, and its specific logic will not be detailed here. Based on this feature, memory exclusive events occurring in computing devices can be detected promptly.
[0045] Based on this, refer to Figure 1a and Figure 2 In step 100, this existing functionality can be used to monitor memory exclusive events occurring in the computing device, specifically memory exclusive events caused by atomic operations. There can be one or more memory exclusive events occurring in the computing device, and the memory addresses involved in different memory exclusive events may be different.
[0046] refer to Figure 1a and Figure 2In step 101, the target memory address corresponding to each memory exclusive event can be located separately. Accordingly, there can be one or more target memory addresses. However, for ease of description, different target memory addresses are not distinguished in this document. It should be understood that the atomic operation processing method provided in this embodiment is applicable to different target memory addresses.
[0047] Taking Hypervisor as an example, Hypervisor can first use the hardware anomaly detection function provided by x86 to detect memory monopoly events that occur in the computing device, and can locate the target memory address where the memory monopoly event is located.
[0048] In this embodiment, the target memory address is used to describe the location in memory of the data required by the atomic operation that leads to the memory exclusive event. Optionally, the target memory address can be a memory page. In this case, the memory page corresponding to the memory exclusive event can be located in step 101. A memory page is a unit of memory management by the operating system. For details, please refer to the memory paging mechanism. Further explanation of memory pages is not provided here. Of course, besides memory pages, the target memory address in this embodiment can also adopt other current or future data storage location representations. For example, the target memory address can be an address range. This embodiment is not limited to this.
[0049] Based on this, refer to Figure 1a and Figure 2 In step 102, if the memory exclusive event occurring at the target memory address meets the triggering condition, the cache corresponding to the target memory address can be closed. This guides the atomic operation carried by the target memory address to directly access memory instead of accessing the cache. As mentioned earlier, the normal access path of an atomic operation is to access the cache first and then access memory. However, based on the closure process performed on the cache corresponding to the target memory address in step 102, from a hardware perspective, a physical page only has one copy in memory and no copy in the cache. This causes the atomic operation that leads to the memory exclusive event to access the data directly in memory instead of accessing the cache, thus avoiding the memory exclusive event caused by the atomic operation accessing the cache. With the cache closed, the memory exclusive event caused by the atomic operation will no longer occur at the target memory address.
[0050] In an optional implementation, in step 102, the usage status of the cache corresponding to the target memory address can be dynamically adjusted using registers that control memory policies in the computing device. Taking the target memory address as a memory page as an example, a page-level caching policy can be used to control the opening and closing of the cache corresponding to the target memory address. For example, x86 provides a Page Attribute Table (PAT) to provide fine-grained page-level caching policy control. The PAT can set memory attributes at the page level, where memory attributes may include, but are not limited to, write-back, uncached, write-combined, and uncached minus. Thus, when the target memory address uses a memory page, in step 102, the PAT can be used to modify the memory attribute of the relevant memory page to uncached, thereby closing the cache corresponding to the relevant memory page. Of course, this is only an example; in this embodiment, other methods can also be used to close the cache for the target memory address, and this embodiment is not limited to this.
[0051] In step 102, a conditional judgment is also made on the memory exclusive event that occurs at the target memory address. This is mainly because disabling the cache operation will impair the performance of the atomic operation carried at the target memory address. Therefore, it is desirable to trigger the cache disable action only when the memory exclusive event that occurs at the target memory address is severe enough, so as to avoid causing too much performance loss to the application / virtual machine VM corresponding to the relevant atomic operation.
[0052] Accordingly, in this embodiment, ensuring the correctness of atomic operations introduces serious performance problems to multi-core processors. To address this, in some embodiments of this application: when a memory monopoly event occurs in the computing device, the target memory address corresponding to the memory monopoly event can be located. If the memory monopoly event occurring at the target memory address meets the triggering conditions, the cache corresponding to the target memory address can be dynamically disabled. This guides the atomic operations carried by the target memory address to directly access memory without going through the cache. In this way, the atomic operations carried by the target memory address can read and write the required data through memory, ensuring the normal execution of atomic operations. Since atomic operations that might lead to memory monopoly events are guided to memory instead of accessing the cache, memory monopoly events caused by atomic operations accessing the cache can be effectively mitigated.
[0053] In the above or following embodiments, as mentioned earlier, disabling the cache operation impairs the performance of atomic operations carried at the target memory address, while not disabling the cache will impair the performance of virtual machines (VMs) / applications running on other cores of the computing device due to memory exclusive events. To balance these two performance aspects, step 102 proposes determining whether to disable the cache corresponding to the target memory address by judging whether a memory exclusive event at the target memory address meets the triggering condition. In this embodiment, various implementation methods can be used to determine whether a memory exclusive event at the target memory address meets the triggering condition.
[0054] In one implementation, a status identifier can be introduced for the memory address in the computing device, and this status identifier can change dynamically. Thus, the triggering condition in step 102 can be set as follows: a memory exclusive event occurring at the target memory address triggers the target memory address to switch to a first state. Therefore, whether to disable the cache corresponding to the target memory address can be determined by detecting whether the status identifier of the target memory address is in the first state. In this implementation, the first state can be used to indicate that the target memory address needs to undergo cache disabling processing. In this implementation, one or more preset requirements can be configured as conditions for triggering the target memory address to switch to the first state. The requirements for memory exclusive events in different preset requirements may not be exactly the same. Thus, if a memory exclusive event occurring at the target memory address satisfies any one of the preset requirements, the target memory address can be triggered to switch to the first state, and the first state can trigger the cache disabling operation for the target memory address. Specifically, the target memory address can be triggered to enter the first state when the occurrence time and / or the number of occurrences of a memory exclusive event that has already occurred at the target memory address meets any one of at least one preset requirement. Some exemplary preset requirements could be: the number of occurrences in the last minute exceeds a first specified number, the number of occurrences in the last two hours exceeds a second specified number, the time interval between the current event and the previous event is less than a specified duration, etc., and will not be listed exhaustively here. These different preset requirements are used to discover from different perspectives that the memory exclusive events occurring at the target memory address have reached the conditions for disabling caching.
[0055] In this implementation, a status identifier is introduced for the memory address in the computing device, and the status identifier can be identified to determine whether the memory exclusive event occurring at the target memory address has reached the condition that the cache needs to be closed, thereby controlling the timing of the cache closure operation.
[0056] Of course, other implementation methods can also be used in this embodiment to determine whether a memory exclusive event occurring at the target memory address meets the triggering condition; this embodiment is not limited to this. For example, as mentioned in the above implementation methods, different preset requirements are used to discover from different perspectives that a memory exclusive event occurring at the target memory address has reached the condition for disabling the cache. Therefore, the triggering condition can also be set as follows: the memory exclusive event occurring at the target memory address meets any one of the preset requirements. In this way, when the memory exclusive event occurring at the target memory address meets any one of the preset requirements, the cache disabling operation can be triggered.
[0057] Therefore, in this embodiment, the decision to disable the cache corresponding to the target memory address can be determined by judging whether the memory exclusive event occurring at the target memory address meets the triggering conditions. This provides a solution for determining the timing of the cache disable operation, enabling timely disabling of the cache corresponding to the target memory address at the appropriate time. By promptly disabling the cache corresponding to the target memory page, the performance loss caused by memory exclusive events to VMs / applications on other cores in the computing device can be effectively mitigated.
[0058] In the above or below embodiments, the maliciousness of the atomic operation that leads to the memory exclusive event may also be considered, and different levels of cache restrictions may be adopted for atomic operations with different degrees of maliciousness.
[0059] Therefore, in this embodiment, a cache shutdown duration corresponding to the target memory address can be set. After the cache corresponding to the target memory address has reached its shutdown duration, the cache corresponding to the target memory address is temporarily enabled to continue observing memory exclusive events occurring at the target memory address, thereby perceiving the maliciousness of the atomic operation that caused the memory exclusive event at the target memory address. Optionally, following the technical concept of introducing a status identifier for memory addresses in the computing device mentioned in the previous embodiments, in this embodiment, the status identifier may include a second state. The first state is used to indicate that the target memory address no longer needs to be closed. Based on this, after the cache corresponding to the target memory address has reached its shutdown duration, the target memory address can be switched from the first state to the second state; based on the second state, the cache corresponding to the target memory address can be reopened.
[0060] In this embodiment, after re-enabling the cache corresponding to the target memory address, monitoring continues to detect new memory exclusive events occurring at the target memory address. Three scenarios are possible: First, new memory exclusive events continue to occur at the target memory address, and there are a sufficient number of these events; second, new memory exclusive events continue to occur at the target memory address, but the number is insufficient; third, no new memory exclusive events occur at the target memory address. In this embodiment, for the first scenario, it can be determined that the atomic operation causing the memory exclusive event at the target memory address is highly malicious; therefore, the cache corresponding to the target memory address can be disabled again. For the second and third scenarios, the cache corresponding to the target memory address can remain enabled, and monitoring continues to detect new memory exclusive events occurring at the target memory address.
[0061] Optionally, following the technical concept of introducing state identifiers for memory addresses in computing devices mentioned in the preceding embodiments, in this embodiment, if a newly occurring memory exclusive event triggers the target memory address to switch from the second state to the first state, the cache corresponding to the target memory address can be closed again. Thus, corresponding to the three situations described above, Figure 3 A schematic diagram illustrating the dynamic change of a status indicator is provided for an exemplary embodiment of this application, with reference to... Figure 3 In the first scenario, the target memory address will switch from the second state to the first state. In the second scenario, the target memory address will remain in the second state. In the third scenario, the target memory address can switch from the first state to the third state, where the third state indicates that no memory exclusive events have occurred at the target memory address within a preset time range. For the third scenario, one or more switching requirements can be set for the transition from the second to the third state. Different switching requirements can examine from different perspectives whether atomic operations on the target memory address will no longer lead to memory exclusive events. Furthermore, for the third scenario, historical memory exclusive event records can be retained for the target memory address to prevent the problem of atomic operations using brief pauses to initiate memory exclusive events to trick the cache into opening.
[0062] In this way, the status flag of the target memory address can be dynamically adjusted based on the new memory exclusive events that occur on the target memory address after the cache corresponding to the target memory address is reopened. This allows for an accurate assessment of the malice of the atomic operation that caused the memory exclusive event, and the adoption of appropriate cache restrictions for atomic operations with different degrees of malice.
[0063] In addition, in this embodiment, the cache shutdown duration can be proportional to the occurrence time and / or the number of memory exclusive events that have occurred at the target memory address. Of course, the factors affecting the cache shutdown duration are not limited to the occurrence time or the number of memory exclusive events; other influencing factors can also be included, which are not limited here. Specifically, the further back the time of the most recent memory exclusive event and the more times the memory exclusive events have occurred, the longer the cache shutdown duration will be. For example, the state of the target memory address may continuously switch between the aforementioned first state, second state, and third state. Whenever the target memory address is switched back to the first state, the time it remains in the first state will be extended, and correspondingly, the cache shutdown duration will be extended. Thus, the more times the target memory address is switched back to the first state, the longer it remains in the first state will be, and correspondingly, the cache shutdown duration will also be longer. If the number of events in which the target memory address remains in the first state exceeds a preset threshold, the target memory address can be permanently set to the first state, and correspondingly, the cache corresponding to the target memory address will be permanently shut down.
[0064] Accordingly, in this embodiment, the cache corresponding to the target memory address can be triggered to close only after determining whether the memory exclusive event occurring at the target memory address is sufficiently severe. This allows for a reasonable determination of when to close the cache corresponding to the target memory address. Furthermore, by continuously monitoring the memory exclusive event occurring at the target memory address, the opening and closing durations of the cache corresponding to the target memory address can be reasonably controlled. This effectively balances the performance loss between the atomic operations carried at the target memory address and the virtual machines (VMs) / applications running on other cores in the computing device, avoiding excessive caching restrictions on the atomic operations carried at the target memory address and minimizing the performance loss of virtual machines (VMs) / applications running on other cores.
[0065] It should be noted that the execution subject of each step in the method provided in the above embodiments can be the same device, or the method can be executed by different devices. Furthermore, some processes described in the above embodiments and accompanying drawings include multiple operations appearing in a specific order; however, it should be clearly understood that these operations may not be executed in the order they appear herein, or may be executed in parallel. The operation numbers, such as 801, 802, etc., are merely used to distinguish different operations and do not represent any execution order. Additionally, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that the descriptions such as "first" and "second" in this document are used to distinguish different state identifiers, etc., and do not represent a sequential order, nor do they limit "first" and "second" to different types.
[0066] Figure 4This is a schematic diagram of the structure of a computing device provided for another exemplary embodiment of this application. For example... Figure 4 As shown, the computing device may include: memory 40 and processor 41.
[0067] Memory 40 is used to store one or more computer instructions that implement virtualization functions;
[0068] The processor 41 is coupled to the memory 40 and is used to execute one or more computer instructions for:
[0069] Monitor memory monopoly events occurring in computing devices, which are caused by atomic operations;
[0070] Determine the target memory address corresponding to the memory exclusive event;
[0071] If a memory exclusive event occurring at the target memory address meets the triggering conditions, the cache corresponding to the target memory resource is closed, so that the atomic operation carried by the target memory address can access memory instead of accessing the cache.
[0072] In terms of physical implementation, the computing device provided in this embodiment can be a small or micro computer device such as a personal computer or tablet computer, a medium or large server device installed within an enterprise, or a cloud server that provides basic physical hardware resources in a cloud computing environment. This embodiment does not limit the physical implementation of the computing device; in principle, computers of various specifications can be applied to the technical solution provided in this embodiment. Furthermore, one or more computer instructions storing virtualization functions in the memory can be implemented as various types of computer program products, such as a hypervisor, and this embodiment does not limit this either. Additionally, it should be understood that the processor 41 mentioned in this embodiment is used to run one or more computer instructions storing virtualization functions in the memory to implement the technical logic in this embodiment. This processor 41 can operate independently of the processor running atomic operations to better manage atomic operations.
[0073] In an optional embodiment, the triggering condition may include: a memory exclusive event occurring at the target memory address triggers the target memory address to switch to a first state, the first state being used to indicate that the target memory address needs to undergo cache disabling processing;
[0074] The state corresponding to the target memory address changes dynamically.
[0075] In an optional embodiment, the first state corresponds to at least one preset requirement, and the processor 41 can also be used for:
[0076] When the occurrence time and / or the number of occurrences of the memory exclusive event that has occurred at the target memory address meet any of the at least one preset requirement, the target memory address is triggered to enter the first state.
[0077] In an alternative embodiment, processor 41 may also be used for:
[0078] Set the cache shutdown duration corresponding to the target memory address;
[0079] After the cache corresponding to the target memory address has reached the cache shutdown time, the target memory address is switched from the first state to the second state. The second state is used to indicate that the target memory address no longer needs to be processed to close the cache.
[0080] Based on the second state, the cache corresponding to the target memory address is reopened.
[0081] In an alternative embodiment, processor 41 may also be used for:
[0082] After re-enabling the cache corresponding to the target memory address, continue to monitor new memory exclusive events occurring at the target memory address;
[0083] If a newly occurring memory exclusive event triggers the target memory address to switch from the second state to the first state, the cache corresponding to the target memory address will be closed again.
[0084] In one alternative embodiment, the cache shutdown duration is proportional to the occurrence time and / or the number of times a memory exclusive event has occurred.
[0085] In an optional embodiment, the processor 41 is further configured to: permanently close the cache corresponding to the target memory address if the cache closure duration exceeds a preset threshold.
[0086] In an optional embodiment, the target memory address includes a memory page, and the processor 41, during the process of closing the cache corresponding to the target memory address, can be used to:
[0087] Using the Page Attribute Table (PAT) technique, the page attributes of memory pages are set to uncached (uncached).
[0088] Furthermore, such as Figure 4 As shown, the computing device also includes other components such as a communication component 42, a display 43, a power supply component 44, and an audio component 45. Figure 4 The diagram only shows some components and does not mean that the computing device includes only these components. Figure 4 The components shown.
[0089] It is worth noting that the technical details of the above embodiments of the computing device can be referred to the relevant descriptions in the foregoing method embodiments. To save space, they will not be repeated here, but this should not cause any loss to the scope of protection of this application.
[0090] Figure 5 This is a schematic diagram of a control device provided as another exemplary embodiment of this application. (Reference) Figure 5 The control device includes:
[0091] Monitoring module 50 is used to monitor memory exclusive events occurring in the computing device, which are caused by atomic operations;
[0092] The positioning module 51 is used to determine the target memory address corresponding to the memory exclusive event;
[0093] The processing module 52 is used to close the cache corresponding to the target memory resource if the memory exclusive event occurring at the target memory address meets the triggering condition, so as to guide the atomic operation carried by the target memory address to access memory instead of accessing the cache.
[0094] In an optional embodiment, the triggering condition may include: a memory exclusive event occurring at the target memory address triggers the target memory address to switch to a first state, the first state being used to indicate that the target memory address needs to undergo cache disabling processing;
[0095] The state corresponding to the target memory address changes dynamically.
[0096] In an optional embodiment, the first state corresponds to at least one preset requirement, and the processor 41 can also be used for:
[0097] When the occurrence time and / or the number of occurrences of the memory exclusive event that has occurred at the target memory address meet any of the at least one preset requirement, the target memory address is triggered to enter the first state.
[0098] In an optional embodiment, the processing module 52 may also be used for:
[0099] Set the cache shutdown duration corresponding to the target memory address;
[0100] After the cache corresponding to the target memory address has reached the cache shutdown time, the target memory address is switched from the first state to the second state. The second state is used to indicate that the target memory address no longer needs to be processed to close the cache.
[0101] Based on the second state, the cache corresponding to the target memory address is reopened.
[0102] In an optional embodiment, the monitoring module 50 may also be used for:
[0103] After re-enabling the cache corresponding to the target memory address, continue to monitor new memory exclusive events occurring at the target memory address;
[0104] The processing module 52 can also be used to: close the cache corresponding to the target memory address again when a newly occurring memory exclusive event triggers the target memory address to switch from the second state to the first state.
[0105] In one alternative embodiment, the cache shutdown duration is proportional to the occurrence time and / or the number of times a memory exclusive event has occurred.
[0106] In an optional embodiment, the processing module 52 is further configured to: permanently close the cache corresponding to the target memory address if the cache closure duration exceeds a preset threshold.
[0107] In an optional embodiment, the target memory address includes a memory page, and the processing module 52, during the process of closing the cache corresponding to the target memory address, can be used to:
[0108] Using the Page Attribute Table (PAT) technique, the page attributes of memory pages are set to uncached (uncached).
[0109] It is worth noting that the technical details of the various embodiments of the control device described above can be found in the relevant descriptions in the foregoing method embodiments. To save space, they will not be repeated here, but this should not cause any loss to the scope of protection of this application.
[0110] Accordingly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed, can implement the steps in the above method embodiments.
[0111] The above Figure 4 The memory in a computer is used to store computer programs and can be configured to store various other data to support operation on a computing platform. Examples of this data include instructions for any application or method operating on the computing platform, contact data, phone book data, messages, pictures, videos, etc. The memory can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disks, or optical disks.
[0112] The above Figure 4The communication component is configured to facilitate wired or wireless communication between the device containing the communication component and other devices. The device containing the communication component can access wireless networks based on communication standards, such as WiFi, 2G, 3G, 4G / LTE, 5G, or combinations thereof. In one exemplary embodiment, the communication component receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID), Infrared Data Association (IrDA) technology, Ultra-Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
[0113] The above Figure 4 The display includes a screen, which may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touchscreen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation.
[0114] The above Figure 4 The power supply component provides power to the various components of the device in which it resides. The power supply component may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which it resides.
[0115] The above Figure 4 The audio component can be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC) configured to receive external audio signals when the device containing the audio component is in an operating mode, such as call mode, recording mode, or voice recognition mode. The received audio signals can be further stored in memory or transmitted via a communication component. In some embodiments, the audio component also includes a speaker for outputting audio signals.
[0116] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0117] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.
[0118] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.
[0119] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.
[0120] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.
[0121] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.
[0122] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.
[0123] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0124] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for processing atomic operations, comprising: Monitor memory exclusive events occurring in a computing device, where the memory exclusive events are caused by atomic operations; Determine the target memory address corresponding to the memory exclusive event; If a memory exclusive event occurring at the target memory address triggers the target memory address to switch to the first state, then the cache corresponding to the target memory address is closed, so that the atomic operation carried by the target memory address can access memory instead of accessing the cache. The state corresponding to the target memory address changes dynamically. When the occurrence time and / or number of occurrences of the memory exclusive event that has occurred at the target memory address meet the preset requirements, the target memory address is triggered to switch to the first state. The occurrence time is the moment corresponding to the occurrence of the memory exclusive event.
2. The method according to claim 1, further comprising: Set the cache shutdown duration corresponding to the target memory address; After the cache corresponding to the target memory address has reached the cache shutdown time, the target memory address is switched from the first state to the second state, whereby the second state indicates that the target memory address no longer needs to be closed. Based on the second state, the cache corresponding to the target memory address is reopened.
3. The method according to claim 2, further comprising: After re-enabling the cache corresponding to the target memory address, continue to monitor new memory exclusive events occurring at the target memory address; If the newly occurring memory exclusive event triggers the target memory address to switch from the second state to the first state, the cache corresponding to the target memory address is closed again.
4. According to the method of claim 3, the further back in time the most recent memory exclusive event occurred at the target memory address and the more times the memory exclusive event has occurred, the longer the cache shutdown time shall be.
5. According to the method of claim 4, if the cache shutdown duration exceeds a preset threshold, the cache corresponding to the target memory address is permanently shut down.
6. The method according to claim 1, wherein the target memory address includes a memory page, and closing the cache corresponding to the target memory address includes: Using the Page Attribute Table (PAT) technique, the page attribute of the memory page is set to Uncached (uncached).
7. The method according to claim 1, wherein the memory exclusive event includes a Split Lock event.
8. A computing device, comprising a memory and a processor; The memory is used to store one or more computer instructions that implement virtualization functions; The processor is coupled to the memory and is used to execute the one or more computer instructions for: Monitor memory exclusive events occurring in the computing device, where the memory exclusive events are caused by atomic operations; Determine the target memory address corresponding to the memory exclusive event; If a memory exclusive event occurring at the target memory address triggers the target memory address to switch to the first state, then the cache corresponding to the target memory address is closed, so that the atomic operation carried by the target memory address can access memory instead of accessing the cache. The state corresponding to the target memory address changes dynamically. When the occurrence time and / or number of occurrences of the memory exclusive event that has occurred at the target memory address meet the preset requirements, the target memory address is triggered to switch to the first state. The occurrence time is the moment corresponding to the occurrence of the memory exclusive event.
9. A control device, comprising: The monitoring module is used to monitor memory exclusive events occurring in the computing device, the memory exclusive events being caused by atomic operations; The positioning module is used to determine the target memory address corresponding to the memory exclusive event; The processing module is configured to, if a memory exclusive event occurring at the target memory address triggers the target memory address to switch to the first state, close the cache corresponding to the target memory address, so as to guide the atomic operation carried by the target memory address to access memory instead of accessing the cache. The state corresponding to the target memory address changes dynamically. When the occurrence time and / or number of occurrences of the memory exclusive event that has occurred at the target memory address meet the preset requirements, the target memory address is triggered to switch to the first state. The occurrence time is the moment corresponding to the occurrence of the memory exclusive event.
10. A computer-readable storage medium storing computer instructions, which, when executed by one or more processors, cause the one or more processors to perform a processing method of the atomic operation according to any one of claims 1-7.