Thin film transistor and display device comprising the same

Abstract

Disclosed is a thin film transistor and a display device including the same, wherein the thin film transistor includes an active layer; a barrier layer on the active layer; a gate insulating layer on the barrier layer; and a gate electrode on the gate insulating layer, wherein at least a portion of the gate electrode overlaps at least a portion of the active layer, the barrier layer includes an oxide semiconductor material, a resistivity of the barrier layer is greater than a resistivity of the active layer, and a thickness of the barrier layer is less than a thickness of the active layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2020-0182551, filed on December 23, 2020, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a thin film transistor and a display device including the thin film transistor. Background Art

[0004] Since thin film transistors can be manufactured on glass substrates or plastic substrates, they have been widely used as switching elements or driving elements of display devices such as liquid crystal display devices or organic light emitting devices.

[0005] Based on the material constituting the active layer, thin film transistors can be divided into amorphous silicon thin film transistors in which amorphous silicon is used as the active layer, polycrystalline silicon thin film transistors in which polycrystalline silicon is used as the active layer, and oxide semiconductor thin film transistors in which oxide semiconductor is used as the active layer.

[0006] Because amorphous silicon can be deposited in a short time to form an active layer, amorphous silicon thin-film transistors (a-SiTFTs) have the advantages of a short manufacturing process time and low production cost. On the other hand, amorphous silicon thin-film transistors have the disadvantage that they are limited to active-matrix organic light-emitting diodes (AMOLEDs) because amorphous silicon thin-film transistors have poor current driving capabilities due to low mobility and their threshold voltage varies.

[0007] Polycrystalline silicon thin film transistors (poly-Si TFTs) are made by depositing amorphous silicon and crystallizing the deposited amorphous silicon. Polycrystalline silicon thin film transistors have the advantages of high electron mobility, good stability, thinness, high resolution, and high power efficiency. Examples of polycrystalline silicon thin film transistors include low-temperature polycrystalline silicon (LTPS) thin film transistors and polycrystalline silicon thin film transistors. However, because the process for manufacturing polycrystalline silicon thin film transistors requires a step of crystallizing amorphous silicon, the increase in the number of process steps increases the manufacturing cost, and crystallization needs to be performed at high temperatures. Therefore, polycrystalline silicon thin film transistors are difficult to apply to large-scale display devices.

[0008] The advantage of an oxide semiconductor thin film transistor (TFT) having high mobility and a large resistance change depending on the oxygen content is that the desired characteristics can be easily obtained. In addition, in the process of manufacturing an oxide semiconductor thin film transistor, the manufacturing cost of the oxide semiconductor thin film transistor is reduced because the oxide constituting the active layer can be grown at a relatively low temperature. In addition, considering the characteristics of the oxide, since the oxide semiconductor is transparent, it is conducive to the realization of a transparent display. However, compared with polycrystalline silicon thin film transistors, oxide semiconductor thin film transistors have problems with stability and mobility degradation.

[0009] To develop high-quality display devices and improve the mobility of oxide semiconductor thin-film transistors, research is underway to use high-mobility materials. However, the use of high-mobility materials can lead to degradation in the reliability and stability of oxide semiconductor thin-film transistors. Therefore, there is a need to improve the driving stability of oxide semiconductor thin-film transistors using high-mobility materials. Summary of the Invention

[0010] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to provide a thin film transistor having improved driving stability due to the arrangement of a barrier layer including an oxide semiconductor material.

[0011] Another object of the present disclosure is to provide a thin film transistor having improved interface stability between a gate insulating film and an active layer because a barrier layer made of an oxide semiconductor material and having a thin profile and high resistance is provided on an active layer.

[0012] Another object of the present invention is to provide a thin film transistor having excellent driving stability due to being provided with a barrier film made of an oxide semiconductor material and having a high oxygen concentration.

[0013] Another object of the present invention is to provide a display device including the above-mentioned thin film transistor.

[0014] In addition to the above-mentioned objects of the present disclosure, additional objects and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0015] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing a thin film transistor, which includes: an active layer; a blocking layer on the active layer; a gate insulating layer on the blocking layer; and a gate electrode on the gate insulating layer, wherein at least a portion of the gate electrode overlaps with at least a portion of the active layer, the blocking layer includes an oxide semiconductor material, the resistivity of the blocking layer is greater than the resistivity of the active layer, and the thickness of the blocking layer is less than the thickness of the active layer.

[0016] The active layer includes an oxide semiconductor material.

[0017] The barrier layer may include at least one of an IGZO (InGaZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, or a GO (GaO)-based oxide semiconductor material.

[0018] The barrier layer may have a 1.0×10 6 Resistivity of Ω·cm or more.

[0019] The carrier concentration of the blocking layer may be lower than the carrier concentration of the active layer.

[0020] The barrier layer may have a 1.0×10 17 ea / cm 3 or smaller carrier concentration.

[0021] The barrier layer may have a 1 cm 2 / V·s to 2cm 2 / V·s mobility.

[0022] The oxygen atomic concentration of the barrier layer is higher than the oxygen atomic concentration of the active layer.

[0023] The barrier layer may include metal atoms and oxygen atoms, and the number of oxygen atoms in the barrier layer may be 1.2 to 2.5 times the total number of metal atoms in the barrier layer.

[0024] The barrier layer may have a thickness of 0.5 nm to 5 nm.

[0025] The barrier layer may have a thickness of 1 nm to 3 nm.

[0026] The barrier layer may cover an upper surface and side surfaces of the active layer.

[0027] The barrier layer may extend to the outside of the active layer.

[0028] The barrier layer may include a first region overlapping the gate electrode and a second region not overlapping the gate electrode.

[0029] The thickness of the first region may be greater than the thickness of the second region.

[0030] A thickness ratio of the first region to the second region (thickness of the first region:thickness of the second region) may be 1:0.3 to 1:0.9.

[0031] The first region and the second region may have the same thickness.

[0032] The barrier layer may be disposed between the active layer and the gate insulating layer.

[0033] The gate insulating layer may be patterned.

[0034] The active layer may include: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0035] The second oxide semiconductor layer may include a FIZO (FeInZnO)-based oxide semiconductor material.

[0036] The blocking layer may be provided between the second oxide semiconductor layer and the gate insulating layer.

[0037] The gate insulating layer may be patterned.

[0038] The gate insulating layer may be patterned to correspond to the gate electrode.

[0039] At least a portion of the blocking layer may be removed in a region not overlapping with the gate insulating layer.

[0040] The barrier layer may be provided only on the channel portion.

[0041] In one embodiment, a thin film transistor includes: an active layer comprising an oxide semiconductor material; a blocking layer on the active layer, wherein the blocking layer is a different layer from the active layer; a gate insulating layer on the blocking layer; and a gate electrode on the gate insulating layer, wherein at least a portion of the gate electrode overlaps with at least a portion of the active layer, and a carrier concentration of the oxide semiconductor material contained in the blocking layer is less than a carrier concentration of the oxide semiconductor material contained in the active layer.

[0042] According to another aspect of the present disclosure, the above and other objects can be achieved by providing a display device including the above thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other objects, features and other advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0044] Figure 1 is a cross-sectional view illustrating a thin film transistor according to one embodiment of the present disclosure;

[0045] Figure 2 It is an icon Figure 1 A detailed view of a portion of

[0046] Figure 3 is a cross-sectional view illustrating a thin film transistor according to another embodiment of the present disclosure;

[0047] Figure 4 It is an icon Figure 3 A detailed view of a portion of

[0048] Figure 5 is a cross-sectional view illustrating a thin film transistor according to yet another embodiment of the present disclosure;

[0049] Figure 6 is a cross-sectional view illustrating a thin film transistor according to yet another embodiment of the present disclosure;

[0050] Figure 7 is a cross-sectional view illustrating a thin film transistor according to yet another embodiment of the present disclosure;

[0051] Figure 8 is a graph illustrating changes in threshold voltage of a thin film transistor according to a comparative example;

[0052] Figure 9 is a graph illustrating changes in the threshold voltage of a thin film transistor according to another embodiment of the present disclosure;

[0053] Figure 10 is a schematic diagram illustrating a display device according to yet another embodiment of the present disclosure;

[0054] Figure 11 It is an icon Figure 10 The circuit diagram of any pixel;

[0055] Figure 12 It is an icon Figure 11 A plan view of pixels;

[0056] Figure 13 It is along Figure 12 A cross-sectional view taken along line II';

[0057] Figure 14 is a circuit diagram illustrating a pixel of a display device according to another embodiment of the present disclosure;

[0058] Figure 15 is a circuit diagram illustrating any one pixel of a display device according to still another embodiment of the present disclosure;

[0059] Figure 16 is a circuit diagram illustrating any one pixel of a display device according to still another embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] The advantages and features of the present disclosure and their implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the present disclosure comprehensive and complete and to fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present invention is limited only by the scope of the claims.

[0061] The shapes, sizes, proportions, angles, and quantities disclosed in the accompanying drawings for the purpose of describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited to the details shown. Like reference numerals denote like elements throughout. In the following description, when it is determined that a detailed description of a related known function or structure would unnecessarily obscure the key points of the present disclosure, such detailed description will be omitted.

[0062] When “including,” “having,” and “comprising” are used in the present specification for description, another part may also be present unless “only” is used. Terms in the singular form may include plural forms unless otherwise indicated.

[0063] When interpreting an element, although not explicitly stated, the element should be interpreted as including an error area.

[0064] When describing a positional relationship, for example, when the positional relationship is described as "on", "over", "below", and "after", one or more parts may be arranged between two other parts unless "immediately" or "directly" is used.

[0065] Spatially relative terms such as “below,” “beneath,” “lower,” “above,” or “upper” may be used herein to easily describe the relationship of one or more elements illustrated in the accompanying drawings to other elements or elements. It should be understood that these terms are intended to encompass different orientations of an apparatus in addition to the orientation depicted in the accompanying drawings. For example, if an apparatus illustrated in a drawing is turned upside down, an apparatus described as being disposed “below” or “beneath” other apparatuses could be disposed “above” the other apparatuses. Thus, the exemplary terms “below or below” could encompass both an orientation of “below or below” and “above.” In the same manner, the exemplary terms “above” or “upper” could encompass both an orientation of “above” and “below or below.”

[0066] When describing a temporal relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "immediately" or "directly" is used.

[0067] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish elements from each other. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure.

[0068] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first, second, and third items" refers to all combinations of items listed from two or more of the first, second, and third items, as well as the first, second, or third item.

[0069] Those skilled in the art will fully understand that the features of the various embodiments of the present disclosure may be combined or combined in part or in whole, and may interoperate and drive each other in various technical aspects. The embodiments of the present disclosure may be implemented independently of each other, or implemented together in a mutually dependent relationship.

[0070] In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0071] In the embodiments of the present disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode can be used interchangeably. The source electrode can be a drain electrode, and the drain electrode can be a source electrode. In addition, the source electrode in any embodiment of the present disclosure can be a drain electrode in another embodiment of the present disclosure, and the drain electrode in any embodiment of the present disclosure can be a source electrode in another embodiment of the present disclosure.

[0072] In some embodiments of the present disclosure, for ease of description, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode. However, the embodiments of the present disclosure are not limited to this structure. For example, the source region can be the source electrode, and the drain region can be the drain electrode. In addition, the source region can be the drain electrode, and the drain region can be the source electrode.

[0073] Figure 1 is a cross-sectional view illustrating a thin film transistor 100 according to one embodiment of the present disclosure.

[0074] The thin film transistor 100 according to one embodiment of the disclosure includes an active layer 130, a barrier layer 140, a gate insulating layer 145, and a gate electrode 150.

[0075] Referring to Figure 1 The active layer 130 is disposed on the substrate 110.

[0076] A glass substrate or a polymer resin substrate can be used as the substrate 110. A plastic substrate can be used as the polymer resin substrate. The plastic substrate having flexibility can include at least one of polyimide (PI), polycarbonate (PC), polyethylene (PE), polyester, polyethylene terephthalate (PET), or polystyrene (PS).

[0077] The light blocking layer 120 can be disposed on the substrate 110. The light blocking layer 120 has a light blocking characteristic. The light blocking layer 120 can shield light incident from the substrate 110 to protect the active layer 130. The light blocking layer 120 can be omitted.

[0078] The buffer layer 125 is disposed on the light blocking layer 120. The buffer layer 125 covers an upper surface of the substrate 110 and an upper surface of the light blocking layer 120. The buffer layer 125 has an insulating characteristic and protects the active layer 130. The buffer layer 125 can be omitted.

[0079] The active layer 130 is disposed on the buffer layer 125.

[0080] According to one embodiment of the disclosure, the active layer 130 includes an oxide semiconductor material. According to one embodiment of the disclosure, the active layer 130 is, for example, an oxide semiconductor layer made of an oxide semiconductor material.

[0081] The active layer 130 can include at least one of a ZO (ZnO)-based, IZO (InZnO)-based, IGZO (InGaZnO)-based, TO (SnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, GO (GaO)-based, IO (InO)-based, or ITZO (InSnZnO)-based oxide semiconductor material. In more detail, the active layer 130 can include at least one of a ZO (ZnO)-based, IZO (InZnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, FIZO (FeInZnO)-based, or TO (SnO)-based oxide semiconductor material. For example, the active layer 130 can include a FIZO (FeInZnO)-based oxide semiconductor material.

[0082] The active layer 130 may have a single-layer structure or a multi-layer structure including two or more oxide semiconductor layers.

[0083] According to one embodiment of the present disclosure, the active layer 130 includes a channel portion 130a, a first connection portion 130b, and a second connection portion 130c. The first connection portion 130b and the second connection portion 130c can be formed by selective conduction of the active layer 130. The first connection portion 130b and the second connection portion 130c are generally disposed on both sides of the channel portion 130a.

[0084] The channel portion 130 a has semiconductor characteristics. According to one embodiment of the present invention, the channel portion 130 a overlaps with the light shielding layer 120 .

[0085] The barrier layer 140 is disposed on the active layer 130. The barrier layer 140 may completely cover the upper surface of the active layer 130 or partially cover the active layer 130. The barrier layer 140 is disposed on the channel portion 130a of the active layer 130 to protect the channel portion 130a.

[0086] The barrier layer 140 includes an oxide semiconductor material and has a resistivity greater than that of the active layer 130. The barrier layer 140 may have the same or similar metal composition as that of the active layer 130. The barrier layer 140 has a thickness thinner than that of the active layer 130. Figure 2 The barrier layer 140 is described.

[0087] A gate insulating layer 145 is disposed on the barrier layer 140. The gate insulating layer 145 may include at least one of silicon oxide and silicon nitride. The gate insulating layer 145 may have a single-layer structure or a multi-layer structure. Furthermore, the gate insulating layer 145 may be patterned and disposed only on a portion of the active layer 130, or may be disposed to completely cover the active layer 130, or may be disposed to completely cover the upper surface of the substrate 110.

[0088] The gate electrode 150 is disposed on the gate insulating layer 145. The gate electrode 150 is spaced apart from the active layer 130 and at least partially overlaps the active layer 130. At least a portion of the gate electrode 150 overlaps at least a portion of the active layer 130. The gate electrode 150 overlaps the channel portion 130a of the active layer 130.

[0089] The gate electrode 150 can include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), or titanium (Ti). The gate electrode 150 can have a multi-layer structure including at least two conductive layers having different physical properties from each other, respectively.

[0090] According to one embodiment of the present disclosure, the active layer 130 can be selectively made conductive by using selective conductivization of the gate electrode 150 as a mask.

[0091] The area of the active layer 130 overlapping the gate electrode 150 is not made conductive, and thus becomes a channel portion 130a. The area of the active layer 130 not overlapping the gate electrode 150 is made conductive, and thus becomes a first connection portion 130b and a second connection portion 130c.

[0092] According to one embodiment of the present disclosure, the active layer 130 can be selectively made conductive by, for example, plasma treatment or dry etching, but embodiments of the present disclosure are not limited thereto. The active layer 130 can be selectively made conductive by doping using a dopant. At this time, the doped area is made conductive. For the doping, at least one of, for example, boron (B) ions, phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions can be used. In addition, the active layer 130 can be selectively made conductive by light irradiation.

[0093] According to one embodiment of the present disclosure, any one of the first connection portion 130b and the second connection portion 130c can be a source region, and the other can be a drain region. The source region is a source connection portion connected to the source electrode 161. The drain region is a drain connection portion connected to the drain electrode 162.

[0094] For convenience of description, the first connection portion 130b and the second connection portion 130c shown in the drawings are distinguished from each other, and the first connection portion 130b and the second connection portion 130c can also be used interchangeably. According to one embodiment of the present disclosure, the first connection portion 130b can be a source region, and the second connection portion 130c can be a drain region. In addition, the first connection portion 130b can be a drain region, and the second connection portion 130c can be a source region.

[0095] According to one embodiment of the present disclosure, the first connection portion 130b can be used as a source electrode, and also as a drain electrode. In addition, the second connection portion 130c can be used as a drain electrode, and also as a source electrode.

[0096] The interlayer dielectric layer 170 is disposed on the gate electrode 150. The interlayer dielectric layer 170 is an insulating layer made of an insulating material. Specifically, the interlayer dielectric layer 170 may be made of an organic material or an inorganic material, or may be made of a deposited body of an organic layer and an inorganic layer.

[0097] The source electrode 161 and the drain electrode 162 are disposed on the interlayer dielectric layer 170. The source electrode 161 and the drain electrode 162 are spaced apart from each other and are respectively connected to the active layer 130. The source electrode 161 and the drain electrode 162 may be connected to the active layer 130 through contact holes passing through the interlayer dielectric layer 170 and the barrier layer 140.

[0098] Each of the source electrode 161 and the drain electrode 162 may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. Each of the source electrode 161 and the drain electrode 162 may be formed of a single layer made of a metal or a metal alloy, or may be formed of two or more layers.

[0099] In the following, reference will be made to Figure 2 The barrier layer 140 is described in detail.

[0100] Figure 2 yes Figure 1 Specifically, Figure 2 yes Figure 1 Detailed view of the active layer 130, the barrier layer 140, the gate insulating layer 145 and the gate electrode 150.

[0101] refer to Figure 2 The gate insulating layer 145 according to one embodiment of the present disclosure may be patterned. For example, the gate insulating layer 145 may be patterned to correspond to the shape of the gate electrode 150 .

[0102] The barrier layer 140 is disposed between the active layer 130 and the gate insulating layer 145 .

[0103] refer to Figure 1 and Figure 2 , the barrier layer 140 covers the upper surface US and the side surface LS of the active layer 130. In detail, the barrier layer 140 may be disposed on the upper surface US and the side surface LS of the active layer 130.

[0104] According to one embodiment of the present disclosure, the upper surface US of the active layer 130 refers to the surface of the active layer 130 facing the direction opposite to the substrate 110. The surface of the active layer 130 facing the substrate 110 is called the back surface. The side surface LS of the active layer 130 refers to the surface of the active layer 130 between the upper surface US and the back surface.

[0105] According to one embodiment of the present disclosure, the barrier layer 140 may extend to the outside of the active layer 130. Figure 1 and Figure 2 The barrier layer 140 may extend from the upper surface US and the side surface LS of the active layer 130 and may be disposed outside the active layer 130. According to one embodiment of the present disclosure, the barrier layer 140 may be disposed on the entire surface of the substrate 110 including the upper surface US and the side surface LS of the active layer 130.

[0106] The region of the barrier layer 140 may be distinguished according to whether the barrier layer 140 overlaps the gate electrode 150. According to one embodiment of the present disclosure, the barrier layer 140 may include a first region 140a overlapping the gate electrode 150 and a second region 140b not overlapping the gate electrode 150.

[0107] The blocking layer 140 may be made of an oxide semiconductor material.

[0108] According to one embodiment of the present disclosure, the blocking layer 140 may include at least one of an IGZO (InGaZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, or a GO (GaO)-based oxide semiconductor material.

[0109] The blocking layer 140 according to one embodiment of the present disclosure includes an oxide semiconductor material, but has electrical characteristics similar to those of an insulating layer.

[0110] The resistance of the barrier layer 140 is greater than the resistance of the active layer 130 .

[0111] According to one embodiment of the present disclosure, the resistivity of the barrier layer 140 is greater than the resistivity of the active layer 130. According to one embodiment of the present disclosure, the barrier layer 140 is not configured to increase the carrier concentration or mobility of the active layer 130, but is configured to improve the electrical stability of the active layer 130 and the thin film transistor 100.

[0112] The barrier layer 140 has a resistivity greater than that of the active layer 130 and is thinner than the active layer 130 so as not to affect electrical characteristics of the active layer 130 .

[0113] According to one embodiment of the present disclosure, the oxygen atomic concentration of the barrier layer 140 is higher than that of the active layer 130. By increasing the oxygen partial pressure in the step of manufacturing the barrier layer 140, the barrier layer 140 may include a high concentration of oxygen.

[0114] For example, when the barrier layer 140 is formed by deposition, the oxygen partial pressure of the barrier layer 140 may be 50% or higher. In more detail, the barrier layer 140 may be formed by deposition under the condition that the oxygen partial pressure is 50% to 75%.

[0115] Since the oxygen atomic concentration of the barrier layer 140 is higher than that of the active layer 130 , the resistivity of the barrier layer 140 may be higher than that of the active layer 130 .

[0116] According to one embodiment of the present disclosure, the barrier layer 140 includes metal atoms and oxygen atoms, wherein the number of oxygen atoms may be 1.2 to 2.5 times the total number of metal atoms. More specifically, the total number of oxygen atoms included in the barrier layer 140 may be 1.5 to 2.5 times the total number of metal atoms. According to one embodiment of the present disclosure, when the barrier layer 140 includes oxygen in an amount 1.5 to 2.5 times the number of metal atoms, the metal included in the barrier layer 140 may be stably coupled with the oxygen in a stoichiometric manner.

[0117] As an example, a barrier layer 140 containing indium (In), zinc (Zn), gallium (Ga), and tin (Sn) as metal atoms will be described. Indium (In), zinc (Zn), gallium (Ga), and tin (Sn) contained in the barrier layer 140 may be combined with oxygen in the form of In2O3, ZnO, ZnO2, GaO, Ga2O3, GaO2, and SnO2. Considering the stoichiometry when indium (In), zinc (Zn), gallium (Ga), and tin (Sn) contained in the barrier layer 140 are combined with oxygen to form an oxide, the number of oxygen atoms is 1.5 to 2.5 times the number of metal atoms, and the metal contained in the barrier layer 140 may have a composition with oxygen in a stoichiometrically stable state. As a result, the barrier layer 140 may have excellent chemical stability.

[0118] According to one embodiment of the present disclosure, the barrier layer 140 has a thickness of 1.0×10 6 Ω·cm or greater. According to one embodiment of the present disclosure, the active layer 130 may have a resistivity of 1.0×10 6 Ω·cm or less. In more detail, the channel portion 130a may have a resistivity of 1.0×10 6 Resistivity of Ω·cm or less According to one embodiment of the present disclosure, the resistivity of the barrier layer 140 is greater than that of the active layer 130 .

[0119] In addition, the barrier layer 140 having a high oxygen concentration according to one embodiment of the present disclosure has a low carrier concentration. According to one embodiment of the present disclosure, the carrier concentration of the barrier layer 140 is lower than that of the active layer 130 .

[0120] According to one embodiment of the present disclosure, the barrier layer 140 can have a carrier concentration of 1.0 x 10 17 ea / cm 3 or less. On the other hand, the active layer 130 can have a carrier concentration of 1.0 x 10 17 ea / cm 3 or more. In more detail, the channel portion 130a can have a carrier concentration of 1.0 x 10 17 ea / cm 3 or more. When an oxide semiconductor material with high mobility is used, the channel portion 130a can have a carrier concentration of 1.0 x 10 18 ea / cm 3 or more. For example, when an IGZTO (InGaZnSnO)-based oxide semiconductor material or a FIZO (FeInZnO)-based oxide semiconductor material is used, the channel portion 130a can have a carrier concentration of 1.0 x 10 18 ea / cm 3 or more.

[0121] According to one embodiment of the present disclosure, the barrier layer 140 can have a mobility of 2 cm 2 / V·s or less. In more detail, the barrier layer 140 can have a mobility of 1.5 cm 2 / V·s or less, or can have a mobility of 1 cm 2 / V·s or less. For example, the barrier layer 140 can have a mobility of 0.01 cm 2 / V·s to 2 cm 2 / V·s, can have a mobility of 0.1 cm 2 / V·s to 2 cm 2 / V·s, or can have a mobility of 0.5 cm 2 / V·s to 2 cm 2 / V·s.

[0122] The active layer 130 can have a mobility of 5 cm 2 / V·s or more. In more detail, the active layer 130 can have a mobility of 10 cm 2 / V·s or more. For example, the active layer 130 can have a mobility of 5 cm 2 / V·s to 40 cm 2 / V·s. In addition, according to one embodiment of the present disclosure, the channel portion 130a can have a mobility of 5 cm 2 / V·s or more, or can have a mobility of 10 cm 2 / V·s or higher. For example, the channel portion 130a may have a mobility of 5 cm 2 / V·s to 40cm 2 When a high-mobility oxide semiconductor material is used, the channel portion 130a may have a mobility of 20 cm 2 / V·s to 40cm 2 / V·s mobility.

[0123] As described above, the barrier layer 140 according to one embodiment of the present disclosure has a greater resistivity, a lower carrier concentration, and a lower mobility than the active layer 130 , and thus does not greatly contribute to improving the on-current characteristics of the active layer 130 .

[0124] Because the blocking layer 140 according to one embodiment of the present disclosure is made of an oxide semiconductor material, the blocking layer 140 can have a composition similar to that of the oxide semiconductor material constituting the active layer 130. Therefore, the blocking layer 140 and the active layer 130 have excellent interface characteristics, and the interface between the blocking layer 140 and the active layer 130 is very stable. In addition, because the blocking layer 140 has electrical or chemical properties close to those of an insulator, the blocking layer 140 can form a stable interface with the gate insulating layer 145 made of an insulating material.

[0125] According to one embodiment of the present disclosure, the carrier concentration and mobility of barrier layer 140 are lower than those of active layer 130. More specifically, the carrier concentration and mobility of barrier layer 140 are lower than those of channel portion 130a. Compared to channel portion 130a, barrier layer 140 is less sensitive to factors that affect the stability of thin film transistor 100. Therefore, barrier layer 140 can protect active layer 130 and channel portion 130a from external factors that affect the electrical characteristics of active layer 130 and channel portion 130a.

[0126] For example, even if oxygen (O) or hydrogen (H), which are external factors affecting the electrical characteristics of thin film transistor 100, penetrates into barrier layer 140, the electrical characteristics of barrier layer 140 do not significantly change. Furthermore, even if a change in the electrical characteristics occurs in barrier layer 140, because barrier layer 140 is very thin, the change in the electrical characteristics of barrier layer 140 does not affect the electrical characteristics of active layer 130 and channel portion 130a. Therefore, barrier layer 140 serves to protect active layer 130 and channel portion 130a from external factors. As a result, barrier layer 140 can improve the electrical stability of active layer 130, particularly channel portion 130a.

[0127] In order to improve the mobility of a thin film transistor including an active layer 130 made of an oxide semiconductor, when using a high-mobility oxide semiconductor material such as FIZO (FeInZnO), IGZTO (InGaZnSnO), and IZO (InZnO), the stability of the active layer 130 may deteriorate due to external environmental factors such as light irradiation and external temperature changes, thereby causing a problem of a threshold voltage change of the thin film transistor. Because the blocking layer 140 according to one embodiment of the present invention has a composition similar to that of the high-mobility oxide semiconductor material, when the blocking layer 140 is provided on the active layer 130, the stability of the active layer 130 can be improved without degrading the electrical characteristics of the active layer 130.

[0128] Furthermore, the barrier layer 140 has insulating properties and electrochemical properties similar to those of an insulator, so the barrier layer 140 can maintain strong coupling with the gate insulating layer 145. As described above, the barrier layer 140 is disposed between the active layer 130 and the gate insulating layer 145, serving as an intermediate to prevent or at least reduce rapid changes in material properties. As a result, defects between the active layer 130 and the gate insulating layer 145 due to differences in physical or chemical properties can be prevented or at least reduced.

[0129] In addition, due to the presence of a gap between the valence bands of the blocking layer 140 and the active layer 130, an energy barrier may exist between the blocking layer 140 and the active layer 130. Therefore, when the blocking layer 140 is disposed between the active layer 130 and the gate insulating layer 145, holes formed in the active layer 130 are less likely to be trapped in the gate insulating layer 145 due to the energy barrier between the blocking layer 140 and the active layer 130. Therefore, degradation and instability of the active layer 130 can be prevented.

[0130] If the blocking layer 140 is not present, in a state where light is irradiated to the active layer 130, when a voltage, for example, a negative (-) voltage is applied to the gate electrode 140, electron-hole pairs may be formed in the active layer 130, and the formed electron-hole pairs may be trapped at the interface between the active layer 130 and the gate insulating layer 145. In this case, the electrical stability of the active layer 130 and the thin film transistor 100 including the active layer 130 may be deteriorated.

[0131] Because the barrier layer 140 according to one embodiment of the present disclosure has high resistance and is thin, the barrier layer 140 may not directly affect the electrical characteristics of the active layer 130. Although the barrier layer 140 is disposed on the active layer 130, the mobility or carrier concentration of the active layer 130 may not be substantially changed. As a result, the effect of the barrier layer 140 on the electrical characteristics of the thin film transistor 100 may be minimized.

[0132] In addition, the barrier layer 140 according to one embodiment of the present disclosure can be used to prevent damage and stress applied to the active layer 130 during the process. For example, because the barrier layer 140 is provided on the active layer 130, the active layer 130 can be prevented from being contaminated by the photoresist during the etching process, and the active layer 130 can be prevented from being damaged during the etching process or the stripping process. As a result, the stability of the active layer 130 can be improved.

[0133] According to one embodiment of the present disclosure, the barrier layer 140 may have a predetermined thickness so as not to affect electrical characteristics of the active layer 130 and to prevent damage and stress applied to the active layer 130 .

[0134] According to one embodiment of the present disclosure, the barrier layer 140 may have a thickness of 0.5 nm to 5 nm.

[0135] When the thickness of the barrier layer 140 is less than 0.5 nm, the barrier layer 140 may not sufficiently protect the active layer 130 due to its thin thickness. In addition, when the thickness of the barrier layer 140 is designed to be less than 0.5 nm, the stability of the process for forming the barrier layer 140 may be deteriorated. Therefore, according to one embodiment of the present disclosure, the thickness of the barrier layer 140 may be designed to be 0.5 nm or greater.

[0136] On the other hand, even if the blocking layer 140 has a high resistivity, when the blocking layer 140 is thick, charge flow through the blocking layer 140 may occur. Specifically, when the thickness of the blocking layer 140 increases, electron-hole pairs are formed in the blocking layer 140, and the formed electron-hole pairs may be trapped at the interface between the blocking layer 140 and the gate insulating layer 145, thereby deteriorating the electrical stability of the thin film transistor. In addition, when the blocking layer 140 is thick, oxygen vacancies may occur in the blocking layer 140, and the driving performance of the thin film transistor may become unstable.

[0137] Thus, when the barrier layer 140 becomes thicker, the barrier layer 140 may cause electrical defects in the thin film transistor.

[0138] For example, when the thickness of the blocking layer 140 exceeds 5 nm, electron-hole pairs may be formed or oxygen vacancies may occur in the blocking layer 140, whereby the electrical stability of the thin film transistor may be degraded due to the blocking layer 140, and the blocking layer 140 may cause electrical defects. For example, when the thickness of the blocking layer 140 exceeds 5 nm, the blocking layer 140 may cause degradation caused by negative bias temperature illumination stress (NBTIS).

[0139] Therefore, according to one embodiment of the present disclosure, the thickness of the barrier layer 140 may be designed to be 5 nm or less.

[0140] In more detail, the barrier layer 140 may have a thickness of 1 nm to 3 nm. When the thickness of the barrier layer 140 is 1 nm or greater, the barrier layer 140 may more effectively protect the active layer 130. In addition, when the thickness of the barrier layer 140 is 3 nm or less, the barrier layer 140 may have little or no effect on the electrical characteristics of the active layer 130.

[0141] According to one embodiment of the present disclosure, the barrier layer 140 may have a thickness of, for example, 1.2 nm to 2.5 nm.

[0142] The first region 140 a and the second region 140 b of the barrier layer 140 may have the same thickness or their respective thicknesses may be different from each other.

[0143] refer to Figure 2 , during the patterning process of the gate insulating layer 145, the second region 140b of the blocking layer 140 may be partially removed. Therefore, according to one embodiment of the present disclosure, the thickness of the first region 140a of the blocking layer 140 may be thicker than the thickness of the second region 140b. Figure 2 , the thickness t1a of the first region 140a of the barrier layer 140 is thicker than the thickness t1b of the second region 140b (t1a>t1b).

[0144] In one embodiment of the present disclosure, the thickness ratio of the first region 140a and the second region 140b of the barrier layer 140 is not particularly limited. According to one embodiment of the present disclosure, the first region 140a and the second region 140b may have a thickness ratio of 1:0.3 to 1:0.9 (thickness of the first region: thickness of the second region). According to one embodiment of the present disclosure, the second region 140b of the barrier layer 140 may have a thickness of approximately 30% to 90% relative to the thickness of the first region 140a. However, the embodiments of the present disclosure are not limited to this embodiment. According to one embodiment of the present disclosure, the second region 140b may be almost or entirely removed, so that the thickness of the second region 140b can be substantially unmeasurable.

[0145] According to one embodiment of the present disclosure, since the barrier layer 140 is provided on the active layer 130, even when a high-mobility material is used to develop a high-quality display device, the reliability and stability of the thin film transistor can be prevented from being degraded. In addition, since the barrier layer 140 according to one embodiment of the present disclosure can be provided on the entire upper portion of the active layer 130 or the entire upper portion of the substrate 110, the thin film transistor 100 can be manufactured without an additional process using a patterned mask.

[0146] refer to Figure 1 and Figure 2, the barrier layer 140 covers the channel portion 130a of the active layer 130, and also covers the first connection portion 130b and the second connection portion 130c, which are conductive regions. The carrier concentration and mobility of the barrier layer 140 are lower than those of the active layer 130, and compared with the channel portion 130a, it is less sensitive to factors that affect the stability of the thin film transistor 100. Therefore, even if oxygen (O) or hydrogen (H), which are external factors affecting the electrical characteristics of the thin film transistor 100, penetrate into the barrier layer 140, the electrical characteristics of the barrier layer 140 do not change significantly. In this way, the barrier layer 140 serves to protect the active layer 130 from external factors. As a result, the electrical stability of the active layer 130 can be improved due to the barrier layer 140.

[0147] Figure 3 is a cross-sectional view illustrating a thin film transistor 200 according to another embodiment of the present disclosure, Figure 4 It is an icon Figure 3 Detailed view of a part of a .

[0148] refer to Figure 3 , the active layer 130 includes a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131 .

[0149] The first oxide semiconductor layer 131 is provided on the buffer layer 125 and may function as a supporting layer supporting the second oxide semiconductor layer 132. The second oxide semiconductor layer 132 may function as a main channel layer.

[0150] The first oxide semiconductor layer 131 used as a supporting layer may have excellent film stability and mechanical stability. The first oxide semiconductor layer 131 may include, for example, at least one of an IGZO (InGaZnO)-based, an IGO (InGaO)-based, an IGZTO (InGaZnSnO)-based, a GZTO (GaZnSnO)-based, a GZO (GaZnO)-based, or a GO (GaO)-based oxide semiconductor material. However, the embodiments of the present disclosure are not limited to this example, and the first oxide semiconductor layer 131 may be made of other oxide semiconductor materials known in the art.

[0151] The second oxide semiconductor layer 132 can be made of an oxide semiconductor material, such as an IZO (InZnO)-based, FIZO (FeInZnO)-based, TO (SnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, or ITZO (InSnZnO)-based oxide semiconductor material. For example, the second oxide semiconductor layer 132 can include a FIZO (FeInZnO)-based oxide semiconductor material. However, embodiments of the present disclosure are not limited to this example, and the second oxide semiconductor layer 132 can be made of other oxide semiconductor materials known in the art.

[0152] In the thin film transistor 200 according to another embodiment of the present disclosure, the first oxide semiconductor layer 131 can have a mobility of 5 cm 2 / V·s or more. In detail, the first oxide semiconductor layer 131 can have a mobility of 5 cm 2 / V·s to 15 cm 2 / V·s. In addition, the channel portion 130a of the first oxide semiconductor layer 131 can have a mobility of 5 cm 2 / V·s or more, and can have a mobility of 5 cm 2 / V·s to 15 cm 2 / V·s.

[0153] In the thin film transistor 200 according to another embodiment of the present disclosure, the second oxide semiconductor layer 132 can have a mobility of 10 cm 2 / V·s or more, and can have a mobility of 20 cm 2 / V·s to 40 cm 2 / V·s. For example, the channel portion 130a of the second oxide semiconductor layer 132 can have a mobility of 10 cm 2 / V·s or more, and can have a mobility of 20 cm 2 / V·s to 40 cm 2 / V·s.

[0154] Referring to Figure 4 , the gate insulating layer 145 can be patterned. For example, the gate insulating layer 145 can be patterned in a shape corresponding to the gate electrode 150.

[0155] The barrier layer 140 is provided between the active layer 130 and the gate insulating layer 145. Referring to Figure 3 and Figure 4, the barrier layer 140 covers the upper surface US and the side surface LS of the active layer 130. In detail, the barrier layer 140 may be provided on the upper surface US and the side surface LS of the active layer 130. In addition, the barrier layer 140 may extend from the upper surface US and the side surface LS of the active layer 130 and be provided outside the active layer 130.

[0156] According to another embodiment of the present disclosure, the barrier layer 140 may include a first region 140 a overlapping with the gate electrode 150 and a second region 140 b not overlapping with the gate electrode 150 .

[0157] According to another embodiment of the present disclosure, the thickness of the first region 140a of the barrier layer 140 may be greater than the thickness of the second region 140b. Figure 4 , the thickness t2a of the first region 140a of the barrier layer 140 is greater than the thickness t2b of the second region 140b (t2a>t2b).

[0158] Figure 5 is a cross-sectional view illustrating a thin film transistor 300 according to yet another embodiment of the present disclosure.

[0159] refer to Figure 5 , the gate insulating layer 145 is not patterned and covers the entire upper surface of the active layer 130. The gate insulating layer 145 may cover the entire upper portion of the substrate 110.

[0160] When the gate insulating layer 145 is not patterned and covers the entire upper surface of the active layer 130, the active layer 130 can be selectively made conductive by doping with a dopant. As a result, even if the gate insulating layer 145 is not patterned, the first and second connection portions 130b and 130c of the active layer 130 can be formed.

[0161] The barrier layer 140 is disposed between the active layer 130 and the gate insulating layer 145. Figure 5 The barrier layer 140 covers the upper surface and the side surface of the active layer 130. In addition, the barrier layer 140 may extend from the upper surface and the side surface of the active layer 130 and be disposed outside the active layer 130.

[0162] According to yet another embodiment of the present disclosure, the barrier layer 140 may have the same thickness in a region overlapping with the gate electrode 150 and a region not overlapping with the gate electrode 150. In more detail, the barrier layer 140 includes a first region overlapping with the gate electrode 150 and a second region not overlapping with the gate electrode 150, wherein the first region and the second region may have the same thickness.

[0163] Figure 6 is a cross-sectional view illustrating a thin film transistor 400 according to yet another embodiment of the present disclosure.

[0164] refer to Figure 6 , the barrier layer 140 is provided between the active layer 130 and the gate insulating layer 145. Figure 6 The gate insulating layer 145 may be patterned. For example, the gate insulating layer 145 may be patterned to correspond to the shape of the gate electrode 150 .

[0165] refer to Figure 6 , the blocking layer 140 may be removed during the patterning process of the gate insulating layer 145. Therefore, according to another embodiment of the present disclosure, as Figure 6 As shown, the barrier layer 140 may be formed only in a region overlapping with the gate insulating layer 145, and the barrier layer 140 may be removed in other regions. Figure 6 In the illustrated thin film transistor 400 , the active layer 130 may include a FIZO (FeInZnO)-based oxide semiconductor material. In more detail, the active layer 130 may be made of a FIZO (FeInZnO)-based oxide semiconductor material.

[0166] Figure 7 is a cross-sectional view illustrating a thin film transistor 500 according to yet another embodiment of the present disclosure.

[0167] refer to Figure 7 , the active layer 130 includes a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131 .

[0168] The first oxide semiconductor layer 131 is provided on the buffer layer 125 and may serve as a supporting layer for supporting the second oxide semiconductor layer 132. The second oxide semiconductor layer 132 may serve as a main channel layer. According to another embodiment of the present disclosure, the second oxide semiconductor layer 132 may include a FIZO (FeInZnO)-based oxide semiconductor material.

[0169] refer to Figure 7 The gate insulating layer 145 may be patterned. For example, the gate insulating layer 145 may be patterned to correspond to the shape of the gate electrode 150 .

[0170] The barrier layer 140 is disposed between the active layer 130 and the gate insulating layer 145. Figure 7 , the blocking layer 140 may be removed during the patterning process of the gate insulating layer 145. Therefore, according to another embodiment of the present disclosure, as Figure 7As shown, the blocking layer 140 is formed only in the region overlapping with the gate insulating layer 145, and the blocking layer 140 may be removed in other regions. According to another embodiment of the present disclosure, at least a portion of the blocking layer 140 may be removed in the region not overlapping with the gate insulating layer 145. Figure 7 , the barrier layer 140 may be disposed only on the channel portion 130 a .

[0171] Figure 8 is a graph illustrating changes in the threshold voltage of a thin film transistor according to a comparative example, Figure 9 is a graph illustrating changes in the threshold voltage of a thin film transistor according to another embodiment of the present disclosure.

[0172] about Figure 9 As shown in the graph, the thin film transistor 200 according to another embodiment of the present disclosure has Figure 3 and Figure 4 In detail, Figure 9 The graph shown is a threshold voltage graph of a thin film transistor, in which a 20 nm IGZO (InGaZnO)-based oxide semiconductor layer is used as the first oxide semiconductor layer 131, a 10 nm IGZTO (InGaZnSnO)-based oxide semiconductor layer is used as the second oxide semiconductor layer 132, and a 2.5 nm IGZO (InGaZnO)-based oxide semiconductor layer is used as the blocking layer 140.

[0173] and Figure 9 Compared to the graph shown, Figure 8 The graph shown is a threshold voltage graph of a thin film transistor without using the barrier layer 140. In detail, Figure 8 is a threshold voltage curve graph of a thin film transistor according to a comparative example, in which a 20 nm IGZO (InGaZnO)-based oxide semiconductor layer is used as the first oxide semiconductor layer 131, a 10 nm IGZTO (InGaZnSnO)-based oxide semiconductor layer is used as the second oxide semiconductor layer 132, and the barrier layer 140 is not used.

[0174] exist Figure 8 and Figure 9 In FIG. 1 , “initial” indicates a threshold voltage curve measured after manufacturing the thin film transistor, and “NBTIS” is a threshold voltage curve measured after a negative bias temperature illumination stress (NBTIS) test.

[0175] In detail, with Figure 8 and Figure 9The relevant NBTIS conditions are stress conditions in which 4500 nit of visible light (white light) is irradiated to the thin film transistor at a temperature of 60° C. and a gate voltage of −30 V is applied for 1000 seconds (1000 sec).

[0176] refer to Figure 8 In the thin film transistor according to the comparative example, the initial threshold voltage Vth was -1.49 V, and the threshold voltage Vth after the NBTIS test was -6.23 V. It was noted from the NBTIS test that the threshold voltage of the thin film transistor according to the comparative example shifted by approximately -4.74 V.

[0177] refer to Figure 9 In the thin film transistor 200 according to another embodiment of the present disclosure, the initial threshold voltage Vth is -1.47 V, and the threshold voltage Vth after the NBTIS test is -5.39 V. According to the NBTIS test, it is noted that the threshold voltage of the thin film transistor 200 according to another embodiment of the present disclosure shifts by approximately -3.92 V.

[0178] Thus, according to an embodiment of the present disclosure, when the barrier layer 140 is provided on the active layer 130, less variation in the threshold voltage Vth under NBTIS stress conditions is noted compared to a case where the barrier layer 140 is not provided on the active layer 130. Therefore, the thin film transistors 100, 200, 300, 400, and 500 according to the embodiments of the present disclosure have excellent driving stability.

[0179] Figure 10 is a schematic diagram illustrating a display device 600 according to yet another embodiment of the present disclosure.

[0180] like Figure 10 As shown, the display device 600 includes a display panel 310 , a gate driver 320 , a data driver 330 , and a controller 340 .

[0181] The gate lines GL and the data lines DL are provided in the display panel 310 , and the pixels P are provided in the intersection areas of the gate lines GL and the data lines DL. The pixels P are driven to display an image.

[0182] The controller 340 controls the gate driver 320 and the data driver 330 .

[0183] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 by using a signal provided from an external system (not shown). In addition, the controller 340 samples input image data input from the external system, rearranges the sampled data, and provides the rearranged digital image data RGB to the data driver 330.

[0184] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, a control signal for controlling the shift register may be included in the gate control signal GCS.

[0185] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0186] The data driver 330 supplies data voltages to the data lines DL of the display panel 310. In detail, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltages and supplies the data voltages to the data lines DL.

[0187] The gate driver 320 may include a shift register 350 .

[0188] The shift register 350 sequentially supplies gate pulses of one frame to the gate lines GL using a start signal and a gate clock transmitted from the controller 340. In this case, one frame means a period of time during which one image is output through the display panel 310. The gate pulses have a turn-on voltage that can turn on a switching element (thin film transistor) provided in a pixel P.

[0189] In addition, the shift register 350 provides a gate-off signal that can turn off the switching element to the gate line GL during other periods of a frame when no gate pulse is provided. Hereinafter, the gate pulse and the gate-off signal will be collectively referred to as a scan signal SS or Scan.

[0190] According to one embodiment of the present disclosure, the gate driver 320 may be packaged on the display panel 310. In this way, the structure in which the gate driver 320 is directly packaged on the display panel 310 will be referred to as a gate-in-panel (GIP) structure. The gate driver 320 may include Figures 1 to 7 At least one of the thin film transistors 100 , 200 , 300 , 400 or 500 shown.

[0191] Figure 11 It is an icon Figure 10 The circuit diagram of any pixel P, Figure 12 It is an icon Figure 10 The plane diagram of pixel P, Figure 13 It is along Figure 12 A cross-sectional view taken along line II'.

[0192] Figure 11The circuit diagram of FIG. 7 is an equivalent circuit diagram of a pixel P of the display device 600 including an organic light emitting diode (OLED) as a display element 710 .

[0193] The pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710 .

[0194] Figure 11 The pixel driving circuit PDC includes a first thin film transistor TR1 as a switching transistor and a second thin film transistor TR2 as a driving transistor.

[0195] A display device 600 according to another embodiment of the present disclosure may include Figure 1 、 Figure 3 、 Figure 5 、 Figure 6 ,and Figure 7 At least one of the thin film transistors 100 , 200 , 300 , 400 or 500 shown. Figure 1 、 Figure 3 、 Figure 5 、 Figure 6 and Figure 7 Any one of the illustrated thin film transistors 100 , 200 , 300 , 400 , and 500 may be used as the first thin film transistor TR1 or the second thin film transistor TR2 .

[0196] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by a scan signal SS supplied from the gate line GL.

[0197] The data line DL supplies a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls application of the data voltage Vdata.

[0198] The driving power line PL supplies a driving voltage Vdd to the display element 710 , and the second thin film transistor TR2 controls application of the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving an organic light emitting diode (OLED) as the display element 710 .

[0199] When the first thin film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 through the gate line GL, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode G2 of the second thin film transistor TR1 connected to the display element 710. The data voltage Vdata is charged in the first capacitor C1 formed between the gate electrode G2 and the source electrode S2 of the second thin film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

[0200] The amount of current supplied to an organic light emitting diode (OLED) as the display element 710 is controlled by the second thin film transistor TR2 according to the data voltage Vdata, whereby the gradation of light emitted from the display element 710 can be controlled.

[0201] Referring to Figure 12 and Figure 13 The first thin film transistor TR1 and the second thin film transistor TR2 are disposed on the substrate 110.

[0202] The substrate 110 can be made of glass or plastic. Plastic having flexibility, such as polyimide (PI), can be used as the substrate 110.

[0203] The light blocking layer 120 is disposed on the substrate 110. The light blocking layer 120 can shield light incident from the outside to protect the active layers A1 and A2.

[0204] The buffer layer 125 is disposed on the light blocking layer 120. The buffer layer 125 is made of an insulating material and protects the active layers A1 and A2 from external moisture or oxygen.

[0205] The active layer A1 of the first thin film transistor TR1 and the active layer A2 of the second thin film transistor TR2 are disposed on the buffer layer 125.

[0206] Each of the active layers A1 and A2 includes an oxide semiconductor material. According to another embodiment of the disclosure, the active layers A1 and A2 are oxide semiconductor layers made of an oxide semiconductor material.

[0207] The barrier layer 140 is disposed on the active layers A1 and A2. The barrier layer 140 can cover the entire upper surfaces of the active layers A1 and A2, or can cover only a portion of the active layers A1 and A2. The barrier layer 140 is disposed on the channel portions of the active layers A1 and A2 to protect the channel portions.

[0208] The barrier layer 140 includes an oxide semiconductor material, and the resistivity of the barrier layer 140 is greater than the resistivity of the active layers A1 and A2. The barrier layer 140 can have the same or similar metal components as those of the active layers A1 and A2. The thickness of the barrier layer 140 is thinner than the thickness of the active layers A1 and A2.

[0209] The gate insulating layer 145 is disposed on the barrier layer 140. The gate insulating layer 145 has insulating properties and separates the active layers A1 and A2 from the gate electrodes G1 and G2. Figure 13 It is shown that the gate insulating layer 145 is patterned, but another embodiment of the disclosure is not limited thereto. The gate insulating layer 145 can not be patterned.

[0210] The gate electrode G1 of the first thin film transistor TR1 and the gate electrode G2 of the second thin film transistor TR2 are disposed on the gate insulating layer 145.

[0211] The gate electrode G1 of the first thin film transistor TR1 overlaps at least a portion of the active layer A1 of the first thin film transistor TR1. The gate electrode G2 of the second thin film transistor TR2 overlaps at least a portion of the active layer A2 of the second thin film transistor TR2.

[0212] The gate electrodes G1 and G2 also overlap with the barrier layer 140.

[0213] refer to Figure 12 and 13 The first capacitor electrode C11 of the first capacitor C1 is provided in the same layer as the gate electrodes G1 and G2. The gate electrodes G1 and G2 and the first capacitor electrode C11 may be manufactured together using the same material and through the same process.

[0214] An interlayer dielectric layer 170 is disposed on the gate electrodes G1 and G2 and the first capacitor electrode C11 .

[0215] Source electrodes S1 and S2 and drain electrodes D1 and D2 are disposed on the interlayer dielectric layer 170. For ease of description, source electrodes S1 and S2 and drain electrodes D1 and D2 are distinguished, but the terms source electrodes S1 and S2 and drain electrodes D1 and D2 may also be used interchangeably. Thus, source electrodes S1 and S2 may be drain electrodes D1 and D2, and drain electrodes D1 and D2 may be source electrodes S1 and S2.

[0216] The data line DL and the driving power line PL are disposed on the interlayer dielectric layer 170. The source electrode S1 of the first thin film transistor TR1 may be integrally formed with the data line DL, and the drain electrode D2 of the second thin film transistor TR2 may be integrally formed with the driving power line PL.

[0217] According to one embodiment of the present disclosure, the source electrode S1 and the drain electrode D1 of the first thin film transistor TR1 are spaced apart from each other and connected to the active layer A1 of the first thin film transistor TR1. The source electrode S2 and the drain electrode D2 of the second thin film transistor TR2 are spaced apart from each other and connected to the active layer A2 of the second thin film transistor TR2.

[0218] In detail, the source electrode S1 of the first thin film transistor TR1 contacts the source region of the active layer A1 through the first contact hole H1.

[0219] The drain electrode D1 of the first thin film transistor TR1 contacts the drain region of the active layer A1 through the second contact hole H2, and is connected to the first capacitor electrode C11 of the first capacitor C1 through the third contact hole H3.

[0220] The source electrode S2 of the second thin film transistor TR2 extends over the interlayer dielectric layer 170 and a portion thereof functions as a second capacitor electrode C12 of the first capacitor C1. The first capacitor electrode C11 and the second capacitor electrode C12 overlap each other to form the first capacitor C1.

[0221] The source electrode S2 of the second thin film transistor TR2 contacts the source region of the active layer A2 through the fourth contact hole H4.

[0222] The drain electrode D2 of the second thin film transistor TR2 contacts the drain region of the active layer A2 through the fifth contact hole H5.

[0223] The first thin film transistor TR1 includes an active layer A1, a barrier layer 140, a gate electrode G1, a source electrode S1, and a drain electrode D1, and functions as a switching transistor that controls a data voltage Vdata applied to the pixel driving circuit PDC.

[0224] The second thin film transistor TR2 includes an active layer A2 , a barrier layer 140 , a gate electrode G2 , a source electrode S2 , and a drain electrode D2 , and functions as a driving transistor that controls a driving voltage Vdd applied to the display element 710 .

[0225] A passivation layer 175 is disposed on the source electrodes S1 and S2, the drain electrodes D1 and D2, the data line DL, and the driving power line PL. The passivation layer 175 planarizes upper portions of the first and second thin film transistors TR1 and TR2 and protects the first and second thin film transistors TR1 and TR2.

[0226] The first electrode 711 of the display element 710 is disposed on the passivation layer 175 , and is connected to the source electrode S2 of the second thin film transistor TR2 through a sixth contact hole H6 formed in the passivation layer 175 .

[0227] The bank layer 750 is provided at an edge of the first electrode 711. The bank layer 750 defines a light emitting region of the display element 710.

[0228] The organic light-emitting layer 712 is provided on the first electrode 711, and the second electrode 713 is provided on the organic light-emitting layer 712. Thus, the display element 710 is completed. Figure 13 The display element 710 shown is an organic light emitting diode (OLED). Therefore, the display device 600 according to one embodiment of the present disclosure is an organic light emitting display device.

[0229] Figure 14 is a circuit diagram illustrating a pixel P of a display device 700 according to another embodiment of the present disclosure.

[0230] Figure 14 is an equivalent circuit diagram illustrating a pixel P of an organic light emitting display device.

[0231] Figure 14 The pixel P of the illustrated display device 700 includes an organic light emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0232] In the pixel P, signal lines DL, GL, PL, RL, and SCL for supplying signals to the pixel driving circuit PDC are provided.

[0233] The data voltage Vdata is supplied to the data line DL, the scan signal SS is supplied to the gate line GL, the driving voltage Vdd for driving the pixel is supplied to the driving power line PL, the reference voltage Vref is supplied to the reference line RL, and the sensing control signal SCS is supplied to the sensing control line SCL.

[0234] refer to Figure 14 , assuming that the gate line of the nth pixel P is "GL n The gate line of the (n-1)th pixel P adjacent to the nth pixel P is "GL n-1 ", the gate line "GL" of the (n-1)th pixel P n-1 ” is used as the sensing control line SCL of the n-th pixel P.

[0235] The pixel driving circuit PDC, for example, includes a first thin film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL, a second thin film transistor TR2 (driving transistor) for controlling the magnitude of the current output to the display element 710 according to the data voltage Vdata transmitted through the first thin film transistor TR1, and a third thin film transistor TR3 (reference transistor) for sensing the characteristics of the second thin film transistor TR2.

[0236] The first capacitor C1 is provided between the gate electrode of the second thin film transistor TR2 and the display element 710. The first capacitor C1 is referred to as a storage capacitor Cst.

[0237] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL to transfer the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2.

[0238] The third thin film transistor TR3 is connected to the first node n1 between the second thin film transistor TR2 and the display element 710 and the reference line RL, is turned on or off by the sensing control signal SCS, and senses the characteristics of the second thin film transistor TR2 as a driving transistor during a sensing period.

[0239] A second node n2 connected to the gate electrode of the second thin film transistor TR2 is connected to the first thin film transistor TR1. The first capacitor C1 is formed between the second node n2 and the first node n1.

[0240] When the first thin film transistor TR1 is turned on, a data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2. The data voltage Vdata is charged in the first capacitor C1 formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0241] When the second thin film transistor TR2 is turned on, a current is supplied to the display element 710 through the second thin film transistor TR2 according to a drive voltage Vdd for driving the pixel, and thus the display element 710 outputs light.

[0242] The display device 700 according to another embodiment of the disclosure can include at least one of the thin film transistors 100, 200, 300, 400, or 500 as illustrated in Figure 1 、 Figure 3 、 Figure 5 、 Figure 6 and Figure 7 .

[0243] Figure 15 is a circuit diagram illustrating a pixel of a display apparatus 800 according to still another embodiment of the disclosure.

[0244] Figure 15 The pixel P of the display apparatus 800 as illustrated in

[0245] The pixel drive circuit PDC includes thin film transistors TR1, TR2, TR3, and TR4.

[0246] In the pixel P, signal lines DL, EL, GL, PL, SCL, and RL for supplying a drive signal to the pixel drive circuit PDC are provided.

[0247] In comparison with the pixel P of Figure 14 , Figure 15 The pixel P of

[0248] In addition, in comparison with the pixel drive circuit PDC of Figure 14 , Figure 15The pixel driving circuit PDC further includes a fourth thin film transistor TR4 , which is a light emission control transistor for controlling the light emission timing of the display element 710 .

[0249] refer to Figure 15 , assuming that the gate line of the nth pixel P is "GL n The gate line of the (n-1)th pixel P adjacent to the nth pixel P is "GL n-1 ", the gate line "GL" of the (n-1)th pixel P n-1 ” is used as the sensing control line SCL of the n-th pixel P.

[0250] The first capacitor C1 is located between the gate electrode of the second thin film transistor TR2 and the display element 710. The second capacitor C2 is located between one terminal of the fourth thin film transistor TR4 to which the driving voltage Vdd is supplied and one electrode of the display element 710.

[0251] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL to transfer the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2.

[0252] The third thin film transistor TR3 is connected to the reference line RL, is turned on or off by the sensing control signal SCS, and senses characteristics of the second thin film transistor TR2 as a driving transistor during a sensing period.

[0253] The fourth thin film transistor TR4 transmits the driving voltage Vdd to the second thin film transistor TR2 or blocks the transmission of the driving voltage Vdd according to the emission control signal EM. When the fourth thin film transistor TR4 is turned on, current flows through the second thin film transistor TR2, so that the display element 710 outputs light.

[0254] A display device 800 according to another embodiment of the present disclosure may include: Figure 1 、 Figure 3 、 Figure 5 、 Figure 6 and Figure 7 At least one of the thin film transistors 100, 200, 300, 400 or 500 shown in FIG.

[0255] In addition to the above structure, the pixel driving circuit PDC according to another embodiment of the present disclosure may be formed in various structures. For example, the pixel driving circuit PDC may include five or more thin film transistors.

[0256] Figure 16 is a circuit diagram illustrating a pixel P of a display device 900 according to still another embodiment of the present disclosure.

[0257] Figure 16 The display device 900 is a liquid crystal display device.

[0258] Figure 16 The pixel P of the illustrated display device 900 includes a pixel driving circuit PDC and a liquid crystal capacitor Clc connected to the pixel driving circuit PDC. The liquid crystal capacitor Clc corresponds to a display element.

[0259] The pixel driving circuit PDC includes a thin film transistor TR connected to the gate line GL and the data line DL, and a storage capacitor Cst connected between the thin film transistor TR and the common electrode 372. A liquid crystal capacitor Clc is connected between the thin film transistor TR and the common electrode 372 in parallel with the storage capacitor Cst.

[0260] The voltage difference between the data signal supplied to the pixel electrode through the thin film transistor TR and the common voltage Vcom supplied to the common electrode 372 is charged into the liquid crystal capacitor Clc, and the liquid crystal capacitor Clc drives the liquid crystal according to the charged voltage to control the amount of light transmission. The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc.

[0261] A display device 900 according to yet another embodiment of the present disclosure may include Figure 1 、 Figure 3 、 Figure 5 、 Figure 6 and Figure 7 At least one of the thin film transistors 100, 200, 300, 400 or 500 shown in FIG.

[0262] According to the present disclosure, the following advantageous effects can be obtained.

[0263] According to one embodiment of the present disclosure, a high-resistance thin barrier layer made of an oxide semiconductor material is disposed on an active layer, thereby improving driving stability of a thin film transistor.

[0264] According to one embodiment of the present disclosure, a high-resistance thin barrier layer made of an oxide semiconductor material is provided on an active layer, whereby a threshold voltage variation of a thin film transistor can be minimized.

[0265] According to another embodiment of the present disclosure, a barrier layer made of an oxide semiconductor material having a high oxygen concentration is disposed on the active layer, thereby improving interface stability between the gate insulating layer and the active layer, and as a result, improving stability of the thin film transistor.

[0266] According to another embodiment of the present disclosure, even if an oxide semiconductor material having high mobility characteristics is used, the driving stability of a thin film transistor can be improved by providing a blocking layer on an active layer without using a new insulating layer or adding a new element.

[0267] According to another embodiment of the present disclosure, a thin film transistor including an active layer made of an oxide semiconductor material having high mobility characteristics can be manufactured without adding a process using a mask.

[0268] Since the display device according to one embodiment of the present disclosure includes the above-described thin film transistor, stable display performance can be exerted.

[0269] It is obvious to those skilled in the art that the above disclosure is not limited to the above embodiments and drawings, and that various substitutions, modifications, and variations may be made to the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the scope of the present disclosure is defined by the appended claims, and it is intended that all variations or modifications derived from the meaning, scope, and equivalents of the claims fall within the scope of the present disclosure.

Claims

1. A thin film transistor comprising: an active layer comprising an oxide semiconductor material; a barrier layer on the active layer; a gate insulating layer on the blocking layer; and a gate electrode on the gate insulating layer, wherein at least a portion of the gate electrode overlaps with at least a portion of the active layer, The barrier layer comprises an oxide semiconductor material, the resistivity of the barrier layer is greater than the resistivity of the active layer, and the thickness of the barrier layer is less than the thickness of the active layer, The mobility of the blocking layer is lower than that of the active layer, and the blocking layer has a 2cm 2 / V·s or less mobility, The carrier concentration of the blocking layer is lower than the carrier concentration of the active layer, The oxygen atomic concentration of the barrier layer is higher than the oxygen atomic concentration of the active layer, The barrier layer includes metal atoms and oxygen atoms, and the number of oxygen atoms in the barrier layer is 1.2 to 2.5 times the total number of metal atoms in the barrier layer.

2. The thin film transistor according to claim 1 , wherein the blocking layer comprises at least one of an IGZO (InGaZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, or a GO (GaO)-based oxide semiconductor material.

3. The thin film transistor according to claim 1, wherein the barrier layer has a thickness of 1.0×10 6 Resistivity of Ω·cm or more.

4. The thin film transistor according to claim 1, wherein the barrier layer has a thickness of 1.0×10 17 ea / cm 3 or smaller carrier concentration.

5. The thin film transistor according to claim 1, wherein the barrier layer has a thickness of 1 cm 2 / V·s to 2cm 2 / V·s mobility. The thin film transistor according to claim 1 , wherein the barrier layer has a thickness of 0.5 nm to 5 nm. The thin film transistor according to claim 1 , wherein the barrier layer has a thickness of 1 nm to 3 nm. 8 . The thin film transistor according to claim 1 , wherein the barrier layer covers an upper surface and side surfaces of the active layer. 9 . The thin film transistor according to claim 8 , wherein the barrier layer extends to the outside of the active layer. 10 . The thin film transistor according to claim 1 , wherein the barrier layer includes a first region overlapping with the gate electrode and a second region not overlapping with the gate electrode. The thin film transistor according to claim 10 , wherein a thickness of the first region is greater than a thickness of the second region. 12 . The thin film transistor according to claim 10 , wherein a thickness ratio of the first region to the second region (thickness of the first region:thickness of the second region) is 1:0.3 to 1:0.

9. 13 . The thin film transistor according to claim 10 , wherein the first region and the second region have the same thickness. 14 . The thin film transistor according to claim 1 , wherein the barrier layer is provided between the active layer and the gate insulating layer. The thin film transistor according to claim 1 , wherein the gate insulating layer is patterned.

16. The thin film transistor according to claim 1, wherein the active layer comprises: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer. 17 . The thin film transistor according to claim 16 , wherein the second oxide semiconductor layer comprises a FIZO (FeInZnO)-based oxide semiconductor material. 18 . The thin film transistor according to claim 16 , wherein the blocking layer is provided between the second oxide semiconductor layer and the gate insulating layer. The thin film transistor according to claim 18 , wherein the gate insulating layer is patterned. 20 . The thin film transistor according to claim 19 , wherein the gate insulating layer is patterned to correspond to the gate electrode. 21 . The thin film transistor according to claim 19 , wherein at least a portion of the blocking layer is removed in a region not overlapping with the gate insulating layer.

22. The thin film transistor according to claim 16, wherein the blocking layer is provided only on a channel portion.

23. A display device comprising the thin film transistor according to any one of claims 1 to 22.

24. A thin film transistor comprising: an active layer comprising an oxide semiconductor material; a barrier layer on the active layer, wherein the barrier layer is a different layer from the active layer; a gate insulating layer on the blocking layer; and a gate electrode on the gate insulating layer, wherein at least a portion of the gate electrode overlaps with at least a portion of the active layer, and The carrier concentration of the oxide semiconductor material contained in the blocking layer is lower than the carrier concentration of the oxide semiconductor material contained in the active layer, The mobility of the blocking layer is lower than that of the active layer, and the blocking layer has a 2cm 2 / V·s or less mobility, The oxygen atomic concentration of the oxide semiconductor material contained in the blocking layer is higher than the oxygen atomic concentration of the oxide semiconductor material contained in the active layer, The oxide semiconductor material included in the barrier layer includes metal atoms and oxygen atoms, and the number of oxygen atoms is 1.2 to 2.5 times the total number of metal atoms.

25. The thin film transistor according to claim 24, wherein the carrier concentration of the oxide semiconductor material contained in the blocking layer is 1.0×10 17 ea / cm 3 or smaller.

26. The thin film transistor according to claim 24, wherein the barrier layer is thinner than the active layer.

27. The thin film transistor according to claim 24, wherein the active layer comprises: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer. 28 . The thin film transistor according to claim 24 , wherein the barrier layer covers an upper surface and side surfaces of the active layer.

Images