Level shifter, gate drive circuit and display device

Abstract

The present disclosure relates to a level shifter, a gating driving circuit and a display device, and when m clock signals are used to output m gating signals, by controlling the signal waveform of the first clock signal among the m clock signals to be different from the signal waveform of the mth clock signal, an effect of reducing the characteristic difference between the gating signals and thus improving the image quality is provided.

Description

Technical Field

[0001] The present disclosure relates to a level shifter, a gate driving circuit and a display device. Background Art

[0002] With the advent of the information society, the demand for display devices for displaying images is growing. In order to meet such demand, various types of display devices such as liquid crystal display (LCD) devices, electroluminescent display (ELD) devices including quantum dot light-emitting display devices, and organic light-emitting display (e.g., OLED) devices have been developed and widely used recently.

[0003] Typically, a display device charges a capacitor in each of a plurality of sub-pixels arranged on a display panel and uses the charged capacitor for display driving. However, in such a typical display device, such a capacitor in each sub-pixel may be insufficiently charged, thereby causing image quality degradation.

[0004] In a typical display device, if the size of the non-display area of ​​the display panel can be reduced, the design freedom of the display device can be increased and the design quality can be improved. However, since various circuits and circuit elements are arranged in the non-display area of ​​the display panel, it is not easy to reduce the size of the non-display area of ​​the display panel in practice.

[0005] In addition, in the case of such a typical display device, insufficient charging time may cause image quality to deteriorate, and further, gate driving may malfunction due to differences in gate signal characteristics, thereby causing image quality to deteriorate. Summary of the invention

[0006] Embodiments of the present disclosure provide a level shifter, a gate driving circuit, and a display device capable of reducing a characteristic difference between gate signals and thus improving image quality.

[0007] Embodiments of the present disclosure provide a level shifter capable of variously controlling rising characteristics and falling characteristics of a clock signal, and a gate driving circuit and a display device using the level shifter.

[0008] Embodiments of the present disclosure provide a level shifter, a gate driving circuit, and a display device capable of reducing the size of a region in which a gate driving circuit is provided and reducing a characteristic difference between gate signals even when the gate driving circuit is embedded in a display panel as an embedded type.

[0009] According to aspects of the present disclosure, a display device is provided, comprising: a substrate; m gate lines, which are arranged on the substrate, wherein m is a natural number of 2 or greater; and a gate driving circuit, which is arranged on or connected to the substrate and can provide m gate signals to the m gate lines based on m input clock signals.

[0010] The gate driving circuit may include m output buffer circuits capable of outputting m gate signals based on the m clock signals, and a control circuit capable of controlling the m output buffer circuits.

[0011] Each of the m output buffer circuits may include a pull-up transistor and a pull-down transistor, and a point at which the pull-up transistor and the pull-down transistor are connected may be electrically connected to a corresponding gate line of the m gate lines.

[0012] All gate nodes of the respective pull-up transistors included in the m output buffer circuits may be electrically connected together, and all gate nodes of the respective pull-down transistors included in the m output buffer circuits may be electrically connected together.

[0013] A signal waveform of at least one clock signal among the m clock signals may be different from a signal waveform of another clock signal among the m clock signals.

[0014] The m gate signals may include a first gate signal having an on-level voltage duration at an earliest timing and an mth gate signal having an on-level voltage duration at a latest timing.

[0015] The m clock signals may include a first clock signal corresponding to the first strobe signal and an mth clock signal corresponding to the mth strobe signal.

[0016] The falling length of the first clock signal may be longer than the falling length of the mth clock signal. In this case, the difference between the falling length of the first selection signal and the falling length of the mth selection signal may be smaller than the difference between the falling length of the first clock signal and the falling length of the mth clock signal.

[0017] The rise length of the mth clock signal may be longer than the rise length of the first clock signal. In this case, the difference between the rise lengths of the first selection signal and the mth selection signal may be smaller than the difference between the rise lengths of the first clock signal and the mth clock signal.

[0018] The display device according to aspects of the present disclosure may further include a level shifter for outputting m clock signals according to the clock difference control signal.

[0019] In the display device according to aspects of the present disclosure, m may be 2 or 4.

[0020] According to aspects of the present disclosure, there is provided a gate driving circuit including m output buffer circuits capable of outputting m gate signals based on m clock signals and a control circuit capable of controlling the m output buffer circuits.

[0021] Each of the m output buffer circuits may include a pull-up transistor and a pull-down transistor, and a point at which the pull-up transistor and the pull-down transistor are connected may be electrically connected to a corresponding gate line of the m gate lines.

[0022] All gate nodes of the respective pull-up transistors included in the m output buffer circuits may be electrically connected.

[0023] All gate nodes of the respective pull-down transistors included in the m output buffer circuits may be electrically connected.

[0024] A signal waveform of at least one clock signal among the m clock signals may be different from a signal waveform of another clock signal.

[0025] According to aspects of the present disclosure, there is provided a level shifter including m clock output buffers for outputting m clock signals.

[0026] In the level shifter, m may be a natural number of 2 or more, and the m clock signals may include a first clock signal to an m-th clock signal.

[0027] A high-level voltage duration of the first clock signal and a high-level voltage duration of the second clock signal may partially overlap.

[0028] A signal waveform of a first clock signal among the m clock signals may be different from a signal waveform of an m-th clock signal.

[0029] The m clock output buffers may include a first clock output buffer for outputting a first clock signal and an m-th clock output buffer for outputting an m-th clock signal.

[0030] The first clock output buffer may include a first rising control circuit and a first falling control circuit, the first rising control circuit including N first rising control transistors (N is a natural number of 2 or greater) electrically connected between a high level voltage node and the first clock output terminal, and the first falling control circuit including N first falling control transistors electrically connected between a low level voltage node and the first clock output terminal.

[0031] The mth clock output buffer may include an mth rising control circuit and an mth falling control circuit, the mth rising control circuit including N mth rising control transistors electrically connected between a high level voltage node and the mth clock output terminal, and the mth falling control circuit including N mth falling control transistors electrically connected between a low level voltage node and the mth clock output terminal.

[0032] Respective turning on and off of N control transistors included in at least one of the first rising control circuit, the first falling control circuit, the mth rising control circuit, and the mth falling control circuit may be independently controlled.

[0033] The falling length of the first clock signal may be greater than the falling length of the mth clock signal. In this case, the number of turned-on falling control transistors among the N first falling control transistors may be less than the number of turned-on falling control transistors among the N mth falling control transistors.

[0034] The rising length of the mth clock signal may be greater than the rising length of the first clock signal. In this case, the number of turned-on rising control transistors among the N mth rising control transistors may be less than the number of turned-on rising control transistors among the N first rising control transistors.

[0035] According to an embodiment of the present disclosure, a level shifter, a gate driving circuit, and a display device capable of reducing a characteristic difference between gate signals and thus improving image quality may be provided.

[0036] According to an embodiment of the present disclosure, a level shifter capable of variously controlling rising characteristics and falling characteristics of a clock signal, and a gate driving circuit and a display device using the same can be provided.

[0037] According to an embodiment of the present disclosure, a level shifter, a gate driving circuit, and a display device can be provided that can reduce the size of an area in which the gate driving circuit is provided and reduce a characteristic difference between gate signals even when the gate driving circuit is embedded in a display panel as an embedded type. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of the present disclosure, illustrate various aspects of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0039] Figure 1 A system configuration of a display device according to aspects of the present disclosure is illustrated;

[0040] Figure 2A and Figure 2BAn equivalent circuit of a sub-pixel of a display device according to aspects of the present disclosure is illustrated;

[0041] Figure 3 An example system implementation of a display device according to aspects of the present disclosure is illustrated;

[0042] Figure 4A An example strobe signal output system of a display device according to aspects of the present disclosure is illustrated;

[0043] Figure 4B An example gate driving circuit of a display device according to aspects of the present disclosure is illustrated;

[0044] Figure 4C illustrates a clock signal and a voltage at a Q node in a display device according to aspects of the present disclosure;

[0045] Figure 4D The characteristic differences between the strobe signals in the display device according to aspects of the present disclosure are illustrated;

[0046] Figure 4E Compensation for a characteristic difference between gating signals in a display device according to aspects of the present disclosure is illustrated;

[0047] Figure 5 An example strobe signal output system of a display device according to aspects of the present disclosure is illustrated;

[0048] Fig. 6A and Figure 6B An example gate driving circuit of a display device according to aspects of the present disclosure is illustrated;

[0049] Figure 7 illustrates characteristic differences in display devices according to aspects of the present disclosure;

[0050] FIG. 8A to FIG. 8C A function of compensating for a characteristic difference between gating signals in a display device according to aspects of the present disclosure is illustrated;

[0051] Fig. 9 is a block diagram of a level shifter of a display device according to aspects of the present disclosure;

[0052] FIG. 10A to FIG. 10D is an example circuit illustrating a first clock output buffer of a level shifter of a display device according to aspects of the present disclosure;

[0053] FIG. 11A to FIG. 11D is an example circuit illustrating a second clock output buffer of a level shifter of a display device according to aspects of the present disclosure;

[0054] Fig.12is a detailed diagram of a level shifter for compensating for a difference in falling characteristics between gating signals in a display device according to aspects of the present disclosure;

[0055] Fig.13 Illustrated based on Fig.12 a falling length of the first clock signal of the number of first falling control transistors turned on among the N first falling control transistors of the level shifter;

[0056] Fig.14 is a detailed diagram of a level shifter for compensating for a falling characteristic difference and a rising characteristic difference between gating signals in a display device according to aspects of the present disclosure;

[0057] Fig.15 Illustrated based on Fig.14 a falling length of a first clock signal according to the number of turned-on falling control transistors among the N first falling control transistors of the level shifter and a rising length of a second clock signal according to the number of turned-on rising control transistors among the N second rising control transistors thereof;

[0058] Fig.16 An example strobe signal output system of a display device according to aspects of the present disclosure is illustrated;

[0059] Fig.17 Illustrated Fig.16 An example gate drive circuit in a gate signal output system;

[0060] Fig.18 Illustrated Fig.16 The characteristic difference between the strobe signals in the strobe signal output system;

[0061] Fig.19 Illustrated Fig.16 Compensation for characteristic differences between strobe signals in a strobe signal output system;

[0062] Fig. 20 yes Fig.16 A block diagram of a level shifter in a strobe signal output system;

[0063] Fig.21 yes Fig.19 Detailed diagram of a level shifter;

[0064] Fig. 22 Compensation for a characteristic difference between gating signals using a resistor in a display device according to aspects of the present disclosure is illustrated;

[0065] FIG. 23A to FIG. 23E A level shifter for controlling and outputting a clock signal through control of a resistor included in a display device according to aspects of the present disclosure is illustrated;

[0066] Fig.24 is a control signal illustrating a control signal for controlling a resistance level of a switch in a level shifter included in a display device according to aspects of the present disclosure;

[0067] Fig.25 The present invention illustrates various aspects of the present disclosure in a display device. Fig. 6A and Figure 6B Compensation effect for characteristic differences between gating signals in the case of a Q-node sharing structure; and

[0068] Fig.26 The present invention illustrates various aspects of the present disclosure in a display device. Fig.17 In the case of the Q-node sharing structure, there is a compensation effect on the difference in characteristics between the gating signals. DETAILED DESCRIPTION

[0069] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and even if shown in different drawings, the same reference numerals and symbols may be used to represent the same or similar components. In addition, in the following description of examples or embodiments of the present disclosure, when it is determined that the description may make the subject matter in some embodiments of the present disclosure unclear, the detailed description of the well-known functions and components combined in this article will be omitted. Unless used with the term "only", terms such as "including", "having", "including", "constituting", "composing" and "forming" used in this article are generally intended to allow the addition of other components. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0070] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence or quantity of the elements, etc., but is only used to distinguish the corresponding element from other elements.

[0071] When it is mentioned that a first element is "connected or coupled to" a second element, "contacts or overlaps" the second element, etc., it should be understood that the first element can not only be "directly connected or coupled to" the second element or "directly contact or overlaps" the second element, but also a third element can be "interposed" between the first element and the second element, or the first element and the second element can be "connected or coupled to", "contacts or overlaps" each other via a fourth element, etc. Here, the second element can be included in at least one of the two or more elements that are "connected or coupled to", "contacts or overlaps", etc., each other.

[0072] When time-relative terms such as "after", "subsequently", "next", "before" and the like are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, unless used with the terms "directly" or "immediately", these terms may be used to describe non-continuous or non-sequential processes or operations.

[0073] In addition, when referring to any size, relative size, etc., it should be considered that, even if no relevant description is specified, the numerical value for the element or feature, or the corresponding information (e.g., level, range, etc.) includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully includes all meanings of the term "may".

[0074] Figure 1 A system configuration of the display device 100 according to aspects of the present disclosure is illustrated.

[0075] Reference Figure 1 , a display device 100 according to aspects of the present disclosure includes a display panel 110 and a driving circuit for driving the display panel 110 .

[0076] The driving circuit may include a data driving circuit 120 , a gate driving circuit 130 , etc., and further include a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130 .

[0077] The display panel 110 may include a substrate SUB and signal lines such as a plurality of data lines DL, a plurality of gate lines GL, etc. disposed on the substrate SUB. The display panel 110 may include a plurality of sub-pixels SP connected to the plurality of gate lines GL and the plurality of data lines DL.

[0078] The display panel 110 may include a display area DA in which an image is displayed and a non-display area NDA in which an image is not displayed. In the display panel 110, a plurality of sub-pixels SP for displaying an image may be disposed in the display area DA, and the driving circuits 120, 130, and 140 may be electrically connected to or installed in the non-display area NDA. A pad portion connected to an integrated circuit or a printed circuit may be disposed in the non-display area NDA of the display panel 110.

[0079] The data driving circuit 120 is a circuit for driving a plurality of data lines DL, and may provide data signals to the plurality of data lines DL. The gate driving circuit 130 is a circuit for driving a plurality of gate lines GL, and may provide gate signals to the plurality of gate lines GL. The controller 140 may provide a data control signal DCS to the data driving circuit 120 to control the operation timing of the data driving circuit 120. The controller 140 may provide a gate control signal GCS to the gate driving circuit 130 to control the operation timing of the gate driving circuit 130.

[0080] The controller 140 starts a scanning operation according to the timing scheduled in each frame, converts image data input from other devices or other image providing sources (e.g., a host system) into a data signal form used in the data driving circuit 120 and then provides the converted image data Data to the data driving circuit 120, and loads the data to at least one pixel at a preconfigured time according to the scanning timing control.

[0081] In addition to input image data, the controller 140 may receive various types of timing signals including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, a clock signal CLK, etc. from other devices, networks, or systems (eg, the host system 150 ).

[0082] In order to control the data driving circuit 120 and the gate driving circuit 130, the controller 140 can receive one or more of the timing signals such as the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the input data enable signal DE, the clock signal CLK, etc., generate multiple types of control signals DCS and GCS and output the generated signals to the data driving circuit 120 and the gate driving circuit 130.

[0083] For example, in order to control the gate driving circuit 130 , the controller 140 may output various types of gate control signals GCS including a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like.

[0084] Furthermore, in order to control the data driving circuit 120 , the controller 140 may output various types of data control signals DCS including a source start pulse SSP, a source sampling clock SSC, a source output enable (SOE) signal, and the like.

[0085] The controller 140 may be implemented as a separate component from the data driving circuit 120 or integrated with the data driving circuit 120 and implemented in an integrated circuit.

[0086] The data driving circuit 120 may drive the plurality of data lines DL by receiving the image data Data from the controller 140 and providing the data voltages to the plurality of data lines DL. Here, the data driving circuit 120 may also be referred to as a source driving circuit.

[0087] The data driving circuit 120 may include one or more source driver integrated circuits SDIC.

[0088] Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter DAC, an output buffer, etc. In some cases, each source driver integrated circuit SDIC may also include an analog-to-digital converter ADC.

[0089] In some embodiments, each source driver circuit SDIC can be connected to the display panel 110 in a tape automated bonding (TAB) type, or connected to a conductive pad (e.g., a bonding pad) of the display panel 110 in a chip on glass (COG) type or a chip on panel (COP) type, or connected to the display panel 110 in a chip on film (COF) type.

[0090] The gate driving circuit 130 may output a gate signal of an on-level voltage or a gate signal of an off-level voltage according to the control of the controller 140. The gate driving circuit 130 may sequentially drive the plurality of gate lines GL by sequentially supplying the gate signal of an on-level voltage to the plurality of gate lines GL.

[0091] In some embodiments, the gate drive circuit 130 may be connected to the display panel 110 in a tape automated bonding (TAB) type, or connected to a conductive pad (e.g., a bonding pad) of the display panel 110 in a chip on glass (COG) type or a chip on panel (COP) type, or connected to the display panel 110 in a chip on film (COF) type. In another embodiment, the gate drive circuit 130 may be located in a non-display area NDA of the display panel 110 in a gate in panel (GIP) type. The gate drive circuit 130 may be disposed on or above the substrate SUB, or connected to the substrate SUB. That is, in the case of the GIP type, the gate drive circuit 130 may be disposed in the non-display area NDA of the substrate SUB. In the case of a chip on glass (COG) type, a chip on film (COF) type, etc., the gate drive circuit 130 may be connected to the substrate SUB.

[0092] At least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed not to overlap with the sub-pixels SP, or to overlap with one or more or all of the sub-pixels SP.

[0093] When a specific gate line is selectively driven by the gate driving circuit 130 , the data driving circuit 120 may convert the image data Data received from the controller 140 into a data voltage in an analog form and provide the converted data voltage to the plurality of data lines DL.

[0094] The data driving circuit 120 may be located on, but not limited to, only a portion (e.g., an upper portion or a lower portion) of the display panel 110. In some embodiments, the data driving circuit 120 may be located on, but not limited to, two portions (e.g., an upper portion and a lower portion) of the panel 110 or at least two of the four portions (e.g., an upper portion, a lower portion, a left side, and a right side) of the panel 110, depending on a driving scheme, a panel design scheme, etc.

[0095] The gate driving circuit 130 may be located on, but not limited to, only a portion (e.g., the left side or the right side) of the display panel 110. In some embodiments, the gate driving circuit 130 may be located on, but not limited to, two portions (e.g., the left side or the right side) of the panel 110 or at least two of the four portions (e.g., the upper portion, the lower portion, the left side, and the right side) of the panel 110, according to a driving scheme, a panel design scheme, etc.

[0096] The controller 140 may be a timing controller used in typical display technologies or a control device / apparatus capable of performing other control functions in addition to the typical functions of the timing controller. In some embodiments, the controller 140 may be one or more other control circuits different from the timing controller, or a circuit or component in the control device / apparatus. The controller 140 may be implemented using various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and / or a processor.

[0097] The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, or the like.

[0098] The controller 140 may send and receive signals to and from the data driving circuit 120 via one or more predetermined interfaces. In some embodiments, such interfaces may include a low voltage differential signaling (LVDS) interface, an EPI (Embedded Peripheral Point-to-Point Interface) interface, a serial peripheral interface (SPI), and the like.

[0099] The controller 140 may include a storage medium such as one or more registers.

[0100] The display device 100 according to various aspects of the present disclosure may be a display including a backlight unit such as a liquid crystal display device, or may be a self-luminous display such as an organic light emitting diode (OLED) display, a quantum dot (QD) display, a micro light emitting diode (M-LED) display, etc.

[0101] In the case where the display device 100 according to aspects of the present disclosure is an OLED display, each sub-pixel SP may include an OLED, wherein the OLED itself emits light as a light-emitting element. In the case where the display device 100 according to aspects of the present disclosure is a QD display, each sub-pixel SP may include a light-emitting element including quantum dots as self-luminous semiconductor crystals. In the case where the display device 100 according to aspects of the present disclosure is a micro-LED display, each sub-pixel SP may include a micro-LED, wherein the micro-OLED itself emits light and is based on an inorganic material as a light-emitting element.

[0102] Figure 2A and Figure 2B An example equivalent circuit for a sub-pixel SP of the display device 100 according to aspects of the present disclosure is illustrated.

[0103] Reference Figure 2A According to aspects of the present disclosure, each of a plurality of sub-pixels SP provided in the display panel 110 of the display device 100 may include a light emitting element ED, a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst.

[0104] Reference Figure 2A The light emitting element ED may include a pixel electrode PE and a common electrode CE, and include a light emitting layer EL located between the pixel electrode PE and the common electrode CE.

[0105] The pixel electrode PE of the light emitting element ED may be an electrode disposed in each sub-pixel SP, and the common electrode CE may be an electrode commonly disposed in all or some of the sub-pixels SP. Here, the pixel electrode PE may be an anode electrode, and the common electrode CE may be a cathode electrode. In another embodiment, the pixel electrode PE may be an anode electrode, and the common electrode CE may be a cathode electrode.

[0106] In one embodiment, the light emitting element ED may be an organic light emitting diode (OLED), a light emitting diode (LED), a quantum dot light emitting element, or the like.

[0107] The driving transistor DRT may be a transistor for driving the light emitting element ED, and may include a first node N1, a second node N2, a third node N3, and the like.

[0108] The first node N1 of the driving transistor DRT may be a gate node of the driving transistor DRT and may be electrically connected to a source node or a drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT may be a source node or a drain node of the driving transistor DRT. The second node N2 may be connected to the pixel electrode PE of the light emitting element ED. The third node N3 of the driving transistor DRT may be electrically connected to a driving voltage line DVL for providing a driving voltage EVDD.

[0109] The scanning transistor SCT may be controlled by a scanning signal SCAN as a kind of gate signal, and may be connected between the first node N1 of the driving transistor DRT and the data line DL. In other words, the scanning transistor SCT may be turned on or off according to the scanning signal SCAN provided by the scanning signal line SCL as a kind of gate line GL, and control the electrical connection between the data line DL and the first node N1 of the driving transistor DRT.

[0110] The scan transistor SCT may be turned on by a scan signal SCAN having an on-level voltage and transfer a data voltage Vdata provided through the data line DL to the first node of the driving transistor DRT.

[0111] In one embodiment, when the scan transistor SCT is an n-type transistor, the on-level voltage of the scan signal SCAN may be a high level voltage. In another embodiment, when the scan transistor SCT is a p-type transistor, the on-level voltage of the scan signal SCAN may be a low level voltage.

[0112] The storage capacitor Cst may be connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst may store an amount of charge corresponding to the voltage difference between the two terminals and maintain the voltage difference between the two terminals within a predetermined frame time. Therefore, the corresponding sub-pixel SP may emit light within a predetermined frame time.

[0113] Reference Figure 2B According to aspects of the present disclosure, each of the plurality of sub-pixels SP provided in the display panel 110 of the display device 100 may further include a sensing transistor SENT.

[0114] The sensing transistor SENT may be controlled by a sensing signal SENSE as a kind of gate signal, and may be connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL. In other words, the sensing transistor SENT may be turned on or off according to the sensing signal SENSE provided by the sensing signal line SENL as another kind of gate line GL, and controls the electrical connection between the reference voltage line RVL and the second node N2 of the driving transistor DRT.

[0115] The sensing transistor SENT may be turned on by the sensing signal SENSE having an on-level voltage and transfer the reference voltage Vref transmitted through the reference voltage line RVL to the second node of the driving transistor DRT.

[0116] In addition, the sensing transistor SENT may be turned on by the sensing signal SENSE having the on-level voltage and transmit the voltage at the second node N2 of the driving transistor DRT to the reference voltage line RVL.

[0117] In one embodiment, when the sensing transistor SENT is an n-type transistor, the on-level voltage of the sensing signal SENSE may be a high level voltage. In another embodiment, when the sensing transistor SENT is a p-type transistor, the on-level voltage of the sensing signal SENSE may be a low level voltage.

[0118] When driven to sense at least one characteristic value of the sub-pixel SP, the function of transmitting the voltage at the second node N2 of the driving transistor DRT to the reference voltage line RVL can be used by the sensing transistor SENT. In this case, the voltage transmitted to the reference voltage line RVL can be a voltage for calculating at least one characteristic value of the sub-pixel SP or a voltage in which at least one characteristic value of the sub-pixel SP is reflected.

[0119] Herein, at least one characteristic value of the subpixel SP may be a characteristic value of the driving transistor DRT or the light emitting element ED. The characteristic value of the driving transistor DRT may include a threshold voltage and / or mobility of the driving transistor DRT. The characteristic value of the light emitting element ED may include a threshold voltage of the light emitting element ED.

[0120] The driving transistor DRT, the scanning transistor SCT and the sensing transistor SENT may be n-type transistors, p-type transistors or a combination thereof. Herein, for ease of description, it is assumed that the driving transistor DRT, the scanning transistor SCT and the sensing transistor SENT are n-type transistors.

[0121] The storage capacitor Cst may be an external capacitor intentionally designed to be located outside the driving transistor DRT, rather than an internal capacitor such as a parasitic capacitor (eg, Cgs, Cgd) that may be formed between the gate node and the source node (or drain node) of the driving transistor DRT.

[0122] The scanning signal line SCL and the sensing signal line SENL may be different gate lines GL. In some embodiments, the scanning signal SCAN and the sensing signal SENSE may be separate gate signals, and the on-off timing of the scanning transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP may be independent. That is, the on-off timing of the scanning transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP may be the same as or different from each other.

[0123] In another embodiment, the scanning signal line SCL and the sensing signal line SENL may be the same gate line GL. That is, the gate node of the scanning transistor SCT and the gate node of the sensing transistor SENT in one sub-pixel SP may be connected to one gate line GL. In this embodiment, the scanning signal SCAN and the sensing signal SENSE may be the same gate signal, and the on-off timing of the scanning transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP may be the same.

[0124] It should be understood that Figure 2A and Figure 2B The sub-pixel structure shown in is merely an example of a possible sub-pixel structure for convenience of discussion, and the embodiments of the present disclosure may be implemented in any of various structures as required. For example, the sub-pixel SP may also include at least one transistor and / or at least one capacitor.

[0125] In addition, although the display device 100 has been described based on the assumption that the display device 100 is a self-luminous display device, Figure 2A and Figure 2B However, when the display device 100 is a liquid crystal display, each sub-pixel SP may include a transistor, a pixel electrode, etc.

[0126] Figure 3 An example system implementation of the display device 100 according to aspects of the present disclosure is illustrated.

[0127] Reference Figure 3 , the display panel 110 may include a display area DA in which an image is displayed and a non-display area NDA in which no image is displayed.

[0128] Reference Figure 3 When the data driving circuit 120 includes one or more source driver integrated circuits SDIC and is implemented in a chip on film (COF) type, each source driver integrated circuit SDIC may be mounted on a circuit film SF connected to the non-display area NDA of the display panel 110 .

[0129] Reference Figure 3, the gate driving circuit 130 may be implemented as a gate-in-panel (GIP) type. In this embodiment, the gate driving circuit 130 may be located in the non-display area NDA of the display panel 110. In another embodiment, Figure 3 Different from the illustration in FIG. 1 , the gate driving circuit 130 may be implemented in a chip on film (COF) type.

[0130] The display device 100 may include at least one source printed circuit board SPCB for circuit connection between one or more source driver integrated circuits SDIC and other devices, components, etc., and a control printed circuit board CPCB on which control elements and various types of electrical devices or elements are mounted.

[0131] The circuit film SF on which the source driver integrated circuit SDIC is mounted may be connected to at least one source printed circuit board SPCB. That is, one side of the circuit film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110 and the other side thereof may be electrically connected to the source printed circuit board SPCB.

[0132] The controller 140 and the power management integrated circuit PMIC 310 may be mounted on the control printed circuit board CPCB. The controller 140 may perform an overall control function related to the driving of the display panel 110 and the control operation of the data driving circuit 120 and the gate driving circuit 130. The power management integrated circuit 310 may provide various types of voltages or currents to the data driving circuit 120 and the gate driving circuit 130, or control various types of voltages or currents to be provided.

[0133] The circuit connection between the at least one source printed circuit board SPCB and the control printed circuit board CPCB may be performed by at least one connection cable CBL. The connection cable CBL may be, for example, a flexible printed circuit FPC, a flexible flat cable FFC, or the like.

[0134] At least one source printed circuit board SPCB and the control printed circuit board CPCB may be integrated and implemented as one printed circuit board.

[0135] The display device 100 according to aspects of the present disclosure may further include a level shifter 300 for adjusting a voltage level. In one embodiment, the level shifter 300 may be disposed on a control printed circuit board CPCB or a source printed circuit board SPCB.

[0136] In the display device 100 according to aspects of the present disclosure, the level shifter 300 may provide a signal required for gate driving to the gate driving circuit 130. In one embodiment, the level shifter 300 may provide a plurality of clock signals to the gate driving circuit 130. Therefore, the gate driving circuit 130 may provide a plurality of gate signals to a plurality of gate lines GL based on the plurality of clock signals input from the level shifter 300. The plurality of gate lines GL may carry the gate signals to the sub-pixels SP disposed in the display area DA of the substrate SUB.

[0137] Figure 4A An example strobe signal output system of the display device 100 according to aspects of the present disclosure is illustrated.

[0138] Reference Figure 4A , the level shifter 300 may output m clock signals (CLK1 to CLKm) to the gate driving circuit 130. The gate driving circuit 130 may generate m gate signals (VGATE1 to VGATEm) based on the m clock signals (CLK1 to CLKm), and output the generated gate signals (VGATE1 to VGATEm) to m gate lines (GL1 to GLm).

[0139] The m gate lines ( GL1 to GLm) may carry m gate signals ( VGATE1 to VGATEm) to the sub-pixels SP in the display area DA disposed on the substrate SUB.

[0140] For example, the m gate lines (GL1 to GLm) may be as follows: Figure 2A or Figure 2B The scan signal line SCL shown is connected to the gate node of the scan transistor SCT, and the m selection signals (VGATE1 to VGATEm) may be the scan signal SCAN applied to the gate node of the scan transistor SCT. The first selection signal VGATE1 among the m selection signals (VGATE1 to VGATEm) may be the scan signal SCAN applied to the corresponding gate node of the scan transistor SCT included in each of the sub-pixels SP disposed in the first sub-pixel row. The second selection signal VGATE2 among the m selection signals (VGATE1 to VGATEm) may be the scan signal SCAN applied to the corresponding gate node of the scan transistor SCT included in each of the sub-pixels SP disposed in the second sub-pixel row different from the first sub-pixel row.

[0141] In another example, the m gate lines (GL1 to GLm) may be as follows: Figure 2BThe sensing signal line SENL shown is connected to the gate node of the sensing transistor SENT, and the m selection signals (VGATE1 to VGATEm) may be the sensing signal SENSE applied to the gate node of the sensing transistor SENT. The first selection signal VGATE1 among the m selection signals (VGATE1 to VGATEm) may be the sensing signal SENSE applied to the corresponding gate node of the sensing transistor SENT included in each of the sub-pixels SP disposed in the first sub-pixel row. The second selection signal VGATE2 among the m selection signals (VGATE1 to VGATEm) may be the sensing signal SENSE applied to the corresponding gate node of the sensing transistor SENT included in each of the sub-pixels SP disposed in the second sub-pixel row different from the first sub-pixel row.

[0142] Figure 4B An example gate driving circuit 130 of a display device according to aspects of the present disclosure is illustrated.

[0143] Reference Figure 4B , the gate driving circuit 130 may include m output buffer circuits (GBUF1 to GBUFm) and a control circuit 400 capable of controlling the m output buffer circuits (GBUF1 to GBUFm), where m may be a natural number of 2 or greater.

[0144] The m output buffer circuits (GBUF1 to GBUFm) may receive m clock signals (CLK1 to CLKm) among a plurality of clock signals and output m gate signals (VGATE1 to VGATEm) among a plurality of gate signals to m gate lines (GL1 to GLm) among a plurality of gate lines GL.

[0145] Each of the m output buffer circuits (GBUF1 to GBUFm) may include a pull-up transistor Tu and a pull-down transistor Td.

[0146] In each of the m output buffer circuits (GBUF1 to GBUFm), a connection point of the pull-up transistor Tu and the pull-down transistor Td may be connected to a corresponding gate line among the m gate lines (GL1 to GLm).

[0147] The gate nodes of the respective pull-up transistors Tu included in the m output buffer circuits (GBUF1 to GBUFm) may be commonly connected to one Q-node Q in the control circuit 400. Thus, a structure in which the gate nodes of the respective pull-up transistors Tu included in the m output buffer circuits (GBUF1 to GBUFm) are commonly connected to one Q-node Q is referred to as a Q-node sharing structure.

[0148] When the gate driving circuit 130 is formed as a gate in panel (GIP) type and is designed to have a Q-node sharing structure, the size of the non-display area NDA in which the gate driving circuit 130 is disposed can be reduced. Here, the gate in panel type is also referred to as an embedded type.

[0149] In the Q-node sharing structure, corresponding pull-up transistors Tu included in the m output buffer circuits (GBUF1 to GBUFm) may be turned on or off simultaneously or almost simultaneously according to the voltage of one Q-node Q.

[0150] The gate nodes of the respective pull-down transistors Td included in the m output buffer circuits (GBUF1 to GBUFm) may be commonly connected to one QB node QB in the control circuit 400. Thus, a structure in which the gate nodes of the respective pull-down transistors Td included in the m output buffer circuits (GBUF1 to GBUFm) are commonly connected to one QB node QB is referred to as a QB node sharing structure.

[0151] In the QB node sharing structure, corresponding pull-down transistors Td included in the m output buffer circuits (GBUF1 to GBUFm) may be turned on or off simultaneously or almost simultaneously according to the voltage of one QB node QB.

[0152] Figure 4C The clock signals ( CLK1 to CLK4 ) and the voltage at the Q node in the display device 100 according to aspects of the present disclosure are illustrated. Figure 4D The characteristic differences between the strobe signals in the display device 100 according to aspects of the present disclosure are illustrated.

[0153] Figure 4C is a diagram illustrating the first to fourth clock signals ( CLK1 to CLK4 ) and the voltage at the Q node when m is 4.

[0154] The respective high-level voltage durations of the m clock signals (CLK1 to CLKm) are located at different times in time, and the respective on-level voltage durations (e.g., respective high-level voltage durations) of the m gate signals (VGATE1 to VGATEm) are located at different times. However, in order to explain the characteristics of the display device according to aspects of the present disclosure in terms of signal waveforms, Figure 4D , corresponding high-level voltage durations of the m clock signals (CLK1 to CLKm) are shifted at the same timing and displayed at the same timing, and corresponding on-level voltage durations (e.g., corresponding high-level voltage durations) of the m selection signals (VGATE1 to VGATEm) are shifted at the same timing and displayed at the same timing.

[0155] Reference Figure 4C and Figure 4D , the level shifter 300 can output m clock signals (CLK1 to CLKm) having equal signal waveforms. The gate drive circuit 130 can output m gate signals (VGATE1 to VGATEm) using m clock signals (CLK1 to CLKm) having equal signal waveforms. That is, the corresponding rising lengths of the m clock signals (CLK1 to CLKm) can be equal or different within a certain range. The corresponding falling lengths of the m clock signals (CLK1 to CLKm) can be equal or different within a certain range.

[0156] Reference Figure 4C In the display device 100 according to aspects of the present disclosure, the gate driving circuit 130 may perform overlap gate driving.

[0157] Reference Figure 4C When the gate driving circuit 130 performs overlapping gate driving, the corresponding high level voltage durations of the two clock signals may partially overlap. Therefore, the corresponding on-level voltage durations of the two gate signals corresponding to the continuous driving timing may partially overlap.

[0158] For example, refer to Figure 4C The on-level voltage duration of the first gate signal VGATE1 and the on-level voltage duration of the second gate signal VGATE2 may partially overlap. The on-level voltage duration of the second gate signal VGATE2 and the on-level voltage duration of the third gate signal VGATE3 may partially overlap.

[0159] The on-level voltage duration of the m gate signals ( VGATE1 , VGATE2 , . . . , VGATEm) may be a high-level voltage duration or a low-level voltage duration.

[0160] For example, refer to Figure 4C , the on-level voltage duration of the m gate signals (VGATE1, VGATE2, . . . , VGATEm) may have a time period of 2 H. The overlapping length of the corresponding on-level voltage durations of the two gate signals may be a period of 1 H.

[0161] Reference Figure 4D , the selected driving circuit 130 has a Q node sharing structure (such as Figure 4B ) and perform overlapping strobe drive (such as Figure 4C), the signal waveform of at least one of the m gate signals (VGATE1 to VGATEm) may be different from one or more signal waveforms of one or more other gate signals. Here, the signal waveform may include at least one of a rising length and a falling length.

[0162] Reference Figure 4D , the falling length of at least one of the m selection signals (VGATE1 to VGATEm) may be different from one or more falling lengths of one or more other selection signals. The rising length of at least one of the m selection signals (VGATE1 to VGATEm) may be different from one or more rising lengths of one or more other selection signals.

[0163] Reference Figure 4D , the m gate signals (VGATE1, VGATE2, . . . , VGATEm) output from the gate driving circuit 130 having a Q-node sharing structure may include a first gate signal VGATE1 having a conduction level voltage duration at the earliest timing, and an mth gate signal VGATEm having a conduction level voltage duration at the latest timing.

[0164] Reference Figure 4D , the m clock signals (CLK1 to CLKm) may include a first clock signal CLK1 corresponding to the first gate signal VGATE1 and an m-th clock signal CLKm corresponding to the m-th gate signal VGATEm.

[0165] Reference Figure 4D , among the first to m-th gate signals VGATE1 to VGATEm, the m-th gate signal VGATEm having the on-level voltage duration at the latest timing may have the worst falling characteristic. Therefore, the falling length of the m-th gate signal VGATEm having the on-level voltage duration at the latest timing becomes greater than the falling length of the first gate signal VGATE1 having the on-level voltage duration at the earliest timing.

[0166] Reference Figure 4D , the first enable signal VGATE1 having the on-level voltage duration at the earliest timing may have the worst rising characteristic. Therefore, the rising length of the first enable signal VGATE1 having the on-level voltage duration at the earliest timing becomes greater than the rising length of the mth enable signal VGATEm having the on-level voltage duration at the latest timing.

[0167] The fact that the rising length of the first selection signal VGATE1 is greater than the rising length of the mth selection signal VGATEm means that the rising characteristics between the selection signals (VGATE1 and VGATEm) are different, and the fact that the falling length of the mth selection signal VGATEm is greater than the falling length of the first selection signal VGATE1 means that the falling characteristics of the selection signals (VGATE1 and VGATEm) are different.

[0168] The characteristic differences (rising characteristic differences and falling characteristic differences) between the selection signals (VGATE1 to VGATEm) may cause malfunction of transistors (e.g., scanning transistors SCT and / or sensing transistors SENT) to which the selection signals (VGATE1 to VGATEm) are applied, which results in degradation of image quality.

[0169] In order to solve these problems, through the overlapped gating driving performed by the display device 100 according to various aspects of the present disclosure, a compensation scheme is provided for providing both the effect of improving the image quality by increasing the charging time that may be insufficiently charged in each sub-pixel and the effect of reducing the size of the frame area (non-display area NDA) of the display panel 110 through the Q-node sharing structure, and for reducing the characteristic difference between the gating signals that may be caused. Hereinafter, this will be described in detail.

[0170] Figure 4E Compensation for a characteristic difference between gating signals in the display device 100 according to aspects of the present disclosure is illustrated.

[0171] Reference Figure 4E The display device 100 according to aspects of the present disclosure may perform a clock signal control function in order to compensate for the reference Figure 4D The characteristic differences between the gating signals described above are as follows. Accordingly, the signal waveform of at least one of the m clock signals (CLK1 to CLKm) may be different from one or more signal waveforms of one or more other clock signals.

[0172] Reference Figure 4E , when the clock signal control function is performed to compensate for the characteristic difference between the gate signals in the display device 100, the falling length of the first clock signal CLK1 may become greater than the falling length of the mth clock signal CLKm.

[0173] Then, the difference between the falling length of the associated first gate signal VGATE1 and the falling length of the associated mth gate signal VGATEm may be small or very small, or smaller than the difference between the falling length of the first clock signal CLK1 and the falling length of the mth clock signal CLKm.

[0174] When the clock signal control function is performed to compensate for the characteristic difference between the gate signals in the display device 100 , the rising length of the mth clock signal CLKm may become greater than the rising length of the first clock signal CLK1 .

[0175] Then, the difference between the rising lengths of the first gate signal VGATE1 and the mth gate signal VGATEm may be small or very small, or smaller than the difference between the rising lengths of the first clock signal CLK1 and the mth clock signal CLKm.

[0176] The level shifter 300 may output m clock signals (CLK1 to CLKm) according to the clock difference control signal.

[0177] The level shifter 300 may include m clock output buffers for respectively outputting m clock signals (CLK1 to CLKm), where m may be a natural number of 2 or more.

[0178] The m clock signals (CLK1 to CLKm) may be first to m-th clock signals (CLK1 to CLKm).

[0179] Due to the overlapping gate driving, a high-level voltage duration of the first clock signal CLK1 and a high-level voltage duration of the second clock signal CLK2 may partially overlap.

[0180] The signal waveform of the first clock signal CLK1 among the m clock signals (CLK1 to CLKm) may be different from the signal waveform of the m-th clock signal CLKm. Here, the signal waveform may include a falling length and a rising length, and at least one of the falling length and the rising length of the signal waveform of the first clock signal CLK1 may be different from at least one of the falling length and the rising length of the signal waveform of the m-th clock signal CLKm.

[0181] The m clock output buffers ( CBUF1 to CBUFm) may include a first clock output buffer CBUF1 for outputting a first clock signal CLK1 and an m-th clock output buffer CBUFm for outputting an m-th clock signal CLKm.

[0182] The first clock output buffer CBUF1 may include a first rising control circuit and a first falling control circuit, the first rising control circuit including N (N is a natural number of 2 or greater) first rising control transistors electrically connected between a high-level voltage node and the first clock output terminal, and a first falling control circuit including N first falling control transistors electrically connected between a low-level voltage node and the first clock output terminal.

[0183] The mth clock output buffer CBUFm may include an mth rising control circuit and an mth falling control circuit, the mth rising control circuit including N mth rising control transistors electrically connected between a high level voltage node and the mth clock output terminal, and the mth falling control circuit including N mth falling control transistors electrically connected between a low level voltage node and the mth clock output terminal.

[0184] Respective turning on and / or off of N control transistors included in at least one of the first rising control circuit, the first falling control circuit, the mth rising control circuit, and the mth falling control circuit may be independently controlled.

[0185] The falling length of the first clock signal CLK1 may be greater than the falling length of the mth clock signal CLKm. In this case, the number of turned-on falling control transistors among the N first falling control transistors may be less than the number of turned-on falling control transistors among the N mth falling control transistors.

[0186] The rising length of the mth clock signal CLKm may be greater than that of the first clock signal CLK1. In this case, the number of turned-on rising control transistors among the N mth rising control transistors may be less than the number of turned-on rising control transistors among the N first rising control transistors.

[0187] The m clock output buffers (CBUF1 to CBUFm) included in the level shifter 300 will be referred to later. Fig. 9 A detailed description is given, where m is 2 as an example.

[0188] In the QB node sharing structure, the corresponding pull-down transistors Td included in the m output buffer circuits (GBUF1 to GBUFm) may be turned on or off simultaneously or almost simultaneously according to the voltage at one QB node QB. In the gate drive circuit 130, m is a value indicating the degree of sharing of the Q node Q, and may be the number of output buffer circuits (GBUF1 to GBUFm) that share one Q node Q.

[0189] For example, m may be 2 or 4. Hereinafter, compensation for the characteristic difference between the strobe signals when m is 2 will be described in more detail, and then, compensation for the characteristic difference between the strobe signals when m is 4 will be described in more detail.

[0190] Figure 5 An example strobe signal output system of the display device 100 according to aspects of the present disclosure is illustrated. Fig. 6A and Figure 6B An example gate driving circuit 130 of the display device 100 according to aspects of the present disclosure is illustrated.

[0191] Reference Figure 5 , Fig. 6A and Figure 6B , when m is 2, the two output buffer circuits (GBUF1 and GBUF2) share a Q-node Q.

[0192] When m is 2, the m clock signals (CLK1 to CLKm) include a first clock signal and a second clock signal (CLK1 and CLK2), and the m gate signals (VGATE1 to VGATEm) include a first gate signal and a second gate signal (VGATE1 and VGATE2).

[0193] Reference Figure 5 , Fig. 6A and Figure 6B , the level shifter 300 may output two clock signals (CLK1 and CLK2) among the plurality of clock signals. Here, the two clock signals (CLK1 and CLK2) may be a first clock signal CLK1 and a second clock signal CLK2.

[0194] Reference Figure 5 , Fig. 6A and Figure 6B , the gate driving circuit 130 can receive two clock signals (CLK1 and CLK2) and output two gate signals (VGATE1 and VGATE2). That is, the gate driving circuit 130 can receive the first clock signal CLK1 and output the first gate signal VGATE1 to the first gate line GL1, and receive the second clock signal CLK2 and output the second gate signal VGATE2 to the second gate line GL2.

[0195] Reference Fig. 6A The gate driving circuit 130 may include a first output buffer circuit GBUF1, a second output buffer circuit GBUF2, a control circuit 400 capable of controlling the first output buffer circuit GBUF1 and the second output buffer circuit GBUF2, and the like.

[0196] The first output buffer circuit GBUF1 may output a first gate signal VGATE1 to the first gate line GL1 through the first gate output terminal Ng1 in response to (based on) the first clock signal CLK1 input to the first clock input terminal Nc1 .

[0197] The second output buffer circuit GBUF2 may output a second gate signal VGATE2 to the second gate line GL2 through the second gate output terminal Ng2 in response to (based on) the second clock signal CLK2 input to the second clock input terminal Nc2.

[0198] The control circuit 400 may receive the start signal VST and the reset signal RST and control operations of the first output buffer circuit GBUF1 and the second output buffer circuit GBUF2 .

[0199] The first output buffer circuit GBUF1 may include a first pull-up transistor Tu1 and a first pull-down transistor Td1, the first pull-up transistor Tu1 being electrically connected between the first clock input terminal Nc1 and the first enable output terminal Ng1 and being controlled by the voltage in the Q node Q, and the first pull-down transistor Td1 being electrically connected between the first enable output terminal Ng1 and a base input terminal Ns to which a base voltage VSS1 is input and being controlled by the voltage at the QB node QB.

[0200] The second output buffer circuit GBUF2 may include a second pull-up transistor Tu2 and a second pull-down transistor Td2, the second pull-up transistor Tu2 being electrically connected between the second clock input terminal Nc2 and the second enable output terminal Ng2 and being controlled by the voltage in the Q node Q, and the second pull-down transistor Td2 being electrically connected between the second enable output terminal Ng2 and the base input terminal Ns and being controlled by the voltage of the QB node QB.

[0201] Reference Fig. 6A , a gate node of the first pull-up transistor Tu1 of the first output buffer circuit GBUF1 and a gate node of the second pull-up transistor Tu2 of the second output buffer circuit GBUF2 are electrically connected to the same Q-node Q.

[0202] By the voltage at the Q node Q, the first pull-up transistor Tu1 of the first output buffer circuit GBUF1 and the second pull-up transistor Tu2 of the second output buffer circuit GBUF2 may be turned on or off simultaneously or almost simultaneously.

[0203] A gate node of the first pull-down transistor Td1 of the first output buffer circuit GBUF1 and a gate node of the second pull-down transistor Td2 of the second output buffer circuit GBUF2 are electrically connected to the same QB node QB.

[0204] The first pull-down transistor Td1 of the first output buffer circuit GBUF1 and the second pull-down transistor Td2 of the second output buffer circuit GBUF2 may be turned on or off simultaneously or almost simultaneously according to the voltage at the shared QB node QB.

[0205] exist Figure 6B In the example of , when with Fig. 6A When compared with the example of , the first output buffer circuit GBUF1 may include a first additional pull-down transistor Td1a, and the second output buffer circuit GBUF2 may include a second additional pull-down transistor Td2a.

[0206] The first additional pull-down transistor Td1 a may be electrically connected between the first gate output terminal Ng1 and the base input terminal Ns and controlled by a voltage at another QB node QBa different from the QB node QB.

[0207] The second additional pull-down transistor Td2 a may be electrically connected between the second gate output terminal Ng2 and the base input terminal Ns and controlled by a voltage at another QB node QBa.

[0208] The first additional pull-down transistor Td1a and the first pull-down transistor Td1 may be controlled independently of each other. The second additional pull-down transistor Td2a and the second pull-down transistor Td2 may be controlled independently of each other.

[0209] The first additional pull-down transistor Td1a and the first pull-down transistor Td1 may be operated alternately. The second additional pull-down transistor Td2a and the second pull-down transistor Td2 may be operated alternately.

[0210] For example, the QB node QB to which the gate nodes of the first and second pull-down transistors Td1 and Td2 are commonly connected may be an odd-numbered QB node QB_O having a turn-on level voltage capable of turning on the first and second pull-down transistors Td1 and Td2 in odd-numbered timings.

[0211] For example, the QB node QBa to which the gate nodes of the first and second pull-down transistors Td1a and Td2a are commonly connected may be an even-numbered QB node QB_E having a turn-on level voltage capable of turning on the first and second pull-down transistors Td1a and Td2a in even-numbered timings.

[0212] Figure 7 The characteristic differences between the strobe signals in the display device 100 according to aspects of the present disclosure are illustrated.

[0213] Reference Figure 7 , the level shifter 300 may output a first clock signal CLK1 and a second clock signal CLK2 to the gate driving circuit 130. The gate driving circuit 130 may receive the first clock signal CLK1 and output an associated first gate signal VGATE1 to the first gate line GL1, and receive the second clock signal CLK2 and output an associated second gate signal VGATE2 to the second gate line GL2.

[0214] Figure 7 The first gate signal VGATE1 shown in FIG. 1 exhibits its on-level voltage duration, and Figure 7The second gate signal VGATE2 is shown to exhibit its on-level voltage duration.

[0215] Reference Figure 7 , the first clock signal CLK1 and the second clock signal CLK2 may have the same signal waveform. That is, the rising length CR1 of the first clock signal CLK1 and the rising length CR2 of the second clock signal CLK2 may be equal or approximately equal, or different within a certain range. The falling length CF1 of the first clock signal CLK1 and the falling length CR2 of the second clock signal CLK2 may be equal or approximately equal, or different within a certain range.

[0216] Among the two (m=2) gate signals (VGATE1 and VGATE2) output from the gate driving circuit 130 having a Q-node sharing structure, where m represents a sharing degree of 2, the first gate signal VGATE1 has an on-level voltage duration at the earliest timing, and the second gate signal VGATE2 has an on-level voltage duration at the latest timing.

[0217] According to the above-mentioned overlapping gate driving, the on-level voltage duration of the first gate signal VGATE1 and the on-level voltage duration of the second gate signal VGATE2 may partially overlap. For example, each of the on-level voltage duration of the first gate signal VGATE1 and the on-level voltage duration of the second gate signal VGATE2 may be a period of 2 horizontal times (H), and the second half (1H) of the on-level voltage duration of the first gate signal VGATE1 may overlap with the first half (1H) of the on-level voltage duration of the second gate signal VGATE2.

[0218] When the gate driving circuit 130 performs overlapping gate driving and has a Q node sharing structure (such as Fig. 6A and Figure 6B ), if the first clock signal CLK1 and the second clock signal CLK2 have equal signal waveforms according to a conventional scheme, the signal waveform of the first gate signal VGATE1 may become different from the signal waveform of the second gate signal VGATE2.

[0219] The generation of different signal waveforms between the first gate signal VGATE1 and the second gate signal VGATE2 indicates that there is a characteristic difference between the first gate signal VGATE1 and the second gate signal VGATE2.

[0220] The occurrence of the characteristic difference between the first gate signal VGATE1 and the second gate signal VGATE2 may mean that there is a rising characteristic difference between the first gate signal VGATE1 and the second gate signal VGATE2 or a falling characteristic difference between the first gate signal VGATE1 and the second gate signal VGATE2.

[0221] When the gate driving circuit 130 performs overlapping gate driving and has a Q node sharing structure (such as Fig. 6A and Figure 6B As shown), if the first clock signal CLK1 and the second clock signal CLK2 have equal signal waveforms according to the conventional scheme, the rising length R1 of the first selection signal VGATE1 may become greater than the rising length R2 of the second selection signal VGATE2, and the falling length F2 of the second selection signal VGATE2 may become greater than the falling length F1 of the first selection signal VGATE1.

[0222] The characteristic difference (rising characteristic difference and falling characteristic difference) between the selection signals (VGATE1 and VGATE2) may cause malfunction of transistors (e.g., scanning transistor SCT and / or sensing transistor SENT) to which the selection signals (VGATE1 and VGATE2) are applied, which may result in degradation of image quality.

[0223] In order to solve these problems, the display device 100 according to various aspects of the present disclosure may be provided with a function of compensating for the characteristic differences between the selection signals, and hereinafter, in some embodiments, the function for compensating for the characteristic differences between the selection signals in the display device 100 will be described in detail in conjunction with the accompanying drawings.

[0224] FIG. 8A to FIG. 8C A function of compensating for a characteristic difference between strobe signals in the display device 100 according to aspects of the present disclosure is illustrated.

[0225] Reference FIG. 8A to FIG. 8C In order to compensate for the characteristic difference between the selection signals, the level shifter 300 can control one or more of the rising characteristics and the falling characteristics of one or more of the first clock signal and the second clock signal (CLK1 and CLK2), thereby generating and outputting the updated first clock signal CLK1 and the updated second clock signal CLK2.

[0226] Then, the falling length CF1 of the first clock signal CLK1 and the falling length CF2 of the second clock signal CLK2 may be different, or the rising length CR1 of the first clock signal CLK1 and the rising length CR2 of the second clock signal CLK2 may be different.

[0227] Reference Fig. 8A, the level shifter 300 can make the first falling length CF1 of the first clock signal CLK1 greater than the second falling length CF2 of the second clock signal CLK2 through falling control. Fig. 8A The rising times of the first selection signal VGATE1 and the second selection signal VGATE2 are shown to be equal, but this is only for convenience of description, and in actual implementation, the first selection signal VGATE1 rises from a low level voltage to a high level voltage and falls from a high level voltage to a low level voltage at an earlier timing than the second selection signal VGATE2. In this case, through the falling control of the level shifter 300, the falling length CF1 of the first clock signal CLK1 as a basis for generating the first selection signal VGATE1 can become greater than the falling length CF2 of the second clock signal CLK2 as a basis for generating the second selection signal VGATE2. In other words, when the first gate signal VGATE1 is a gate signal applied to a gate line scanned at an earlier timing than the second gate signal VGATE2, in order to solve the situation that the falling length F2 of the second gate signal VGATE2 is relatively larger and the falling length F1 of the first gate signal VGATE1 is relatively smaller under the Q node sharing structure (difference in falling characteristics), the level shifter 300 may intentionally extend the falling length CF1 of the first clock signal CLK1 as a basis for generating the first gate signal VGATE1, thereby causing the updated falling length F1 of the first gate signal VGATE1 to be intentionally extended. Therefore, the extended falling length F1 of the first gate signal VGATE1 may be equal to or almost equal to the original falling length F2 of the second gate signal VGATE2.

[0228] Through the falling control of the level shifter 300 , the falling length F1 of the first gate signal VGATE1 and the falling length F2 of the second gate signal VGATE2 are equal or approximately equal, or are similar within a predetermined range.

[0229] Through the falling control of the level shifter 300, the difference between the falling length F1 of the first gate signal VGATE1 and the falling length F2 of the second gate signal VGATE2 is different from the case where the falling control is not performed (such as Figure 7 ) can be reduced compared to .

[0230] Through the falling control of the level shifter 300 , the difference between the falling lengths F1 and F2 of the first gate signal VGATE1 and VGATE2 may become smaller than the difference between the falling lengths CF1 and CF2 of the first clock signal CLK1 and CLK2 .

[0231] As a result, the difference in falling characteristics between the first gate signal and the second gate signal ( VGATE1 and VGATE2 ) can be compensated, so that image quality can be improved.

[0232] Reference Figure 8B , the level shifter 300 can make the second rising length CR2 of the second clock signal CLK2 greater than the first rising length CR1 of the first clock signal CLK1 through rising control.

[0233] Therefore, when the first gate signal VGATE1 is a gate signal that rises from a low level voltage to a high level voltage and falls from a high level voltage to a low level voltage at an earlier time than the second clock signal VGATE2, the updated rising length CR2 of the second clock signal CLK2 may become greater than the rising length CR1 of the first clock signal CLK1. In other words, when the first gate signal VGATE1 is a gate signal applied to a gate line scanned at an earlier timing than the second gate signal VGATE2, in order to solve the situation that the rising length R1 of the first gate signal VGATE1 is relatively larger and the rising length R2 of the second gate signal VGATE2 is relatively smaller under the Q-node sharing structure (difference in rising characteristics), the level shifter 300 may intentionally extend the rising length CR2 of the second clock signal CLK2 used as a basis for generating the second gate signal VGATE2, thereby causing the updated rising length R2 of the second gate signal VGATE2 to be intentionally extended. Therefore, the extended rising length R2 of the second gate signal VGATE2 may be equal to or almost equal to the original rising length R1 of the first gate signal VGATE1.

[0234] Through the rising control of the level shifter 300 , the rising length R1 of the first gate signal VGATE1 and the rising length R2 of the second gate signal VGATE2 may be equal or approximately equal, or similar within a predetermined range.

[0235] Through the rising control of the level shifter 300, the difference between the rising length R1 of the first gate signal VGATE1 and the rising length R2 of the second gate signal VGATE2 is different from the case where the rising control is not performed (such as Figure 7 ) can be reduced compared to .

[0236] Through the rising control of the level shifter 300 , a difference between the rising length R1 of the first gate signal VGATE1 and the rising length R2 of the second gate signal VGATE2 may become smaller than a difference between the rising length CR2 of the second clock signal CLK2 and the rising length CR1 of the first clock signal CLK1 .

[0237] As a result, the difference in rising characteristics between the first gate signal and the second gate signal ( VGATE1 and VGATE2 ) can be compensated, so that image quality can be improved.

[0238] Reference Figure 8C The level shifter 300 can make the first falling length CF1 of the first clock signal CLK1 greater than the second falling length CF2 of the second clock signal CLK2 through falling control, and make the second rising length CR2 of the second clock signal CLK2 greater than the first rising length CR1 of the first clock signal CLK1 through rising control.

[0239] Through rising and falling control of the level shifter 300 , a falling length CF1 of the first clock signal CLK1 may become greater than a falling length CF2 of the second clock signal CLK2 , and a rising length CR2 of the second clock signal CLK2 may become greater than a rising length CR1 of the first clock signal CLK1 .

[0240] Through the falling control and rising control of the level shifter 300, the falling length F1 of the first selection signal VGATE1 and the falling length F2 of the second selection signal VGATE2 can become equal or approximately equal, or similar within a predetermined range, and the rising length R1 of the first selection signal VGATE1 and the rising length R2 of the second selection signal VGATE2 can become equal or approximately equal, or similar within a predetermined range.

[0241] Through the falling control and rising control of the level shifter 300, the difference between the falling length F1 of the first gate signal VGATE1 and the falling length F2 of the second gate signal VGATE2 is different from the case where no falling control is performed (such as Figure 7 ) can be reduced, and the difference between the rising length R1 of the first selection signal VGATE1 and the rising length R2 of the second selection signal VGATE2 is smaller than that in the case where the rising control is not performed (such as Figure 7 ) can be reduced compared to .

[0242] Through the falling control and rising control of the level shifter 300, the difference between the falling length F1 of the first selection signal VGATE1 and the falling length F2 of the second selection signal VGATE2 can become smaller than the difference between the falling length CF1 of the first clock signal CLK1 and the falling length CF2 of the second clock signal CLK2, and the difference between the rising length R1 of the first selection signal VGATE1 and the rising length R2 of the second selection signal VGATE2 can become smaller than the difference between the rising length CR2 of the second clock signal CLK2 and the rising length CR1 of the first clock signal CLK1.

[0243] As a result, both the rising characteristic difference and the falling characteristic difference between the first gate signal and the second gate signal (VGATE1 and VGATE2) can be compensated, so that image quality can be significantly improved.

[0244] Fig. 9 is a block diagram of a level shifter 300 of the display device 100 according to aspects of the present disclosure.

[0245] As described above, the level shifter 300 may include m clock output buffers (CBUF1, CBUF2, ...). Fig. 9 , as an example, two clock output buffers (CBUF1 and CBUF2) capable of generating and outputting two clock signals (CLK1 and CLK2) will be discussed, where m is a natural number of 2 or greater.

[0246] Reference Fig. 9 The level shifter 300 may include a first clock output buffer CBUF1 for generating a first clock signal CLK1 and outputting the generated first clock signal CLK1 to a first clock output terminal Nclk1, and a second clock output buffer CBUF2 for generating a second clock signal CLK2 and outputting the generated second clock signal CLK2 to a second clock output terminal Nclk2.

[0247] The first clock output buffer CBUF1 may include a first rising control circuit RCC1 and a first falling control circuit FCC1 and may control at least one of rising and falling characteristics of the first clock signal CLK1 by controlling the first rising and falling control circuits RCC1 and FCC1 in response to a clock difference control signal CDCS[1:N].

[0248] The second clock output buffer CBUF2 may include a second rising control circuit RCC2 and a second falling control circuit FCC2, and may control at least one of rising and falling characteristics of the second clock signal CLK2 by controlling the second rising control circuit RCC2 and the second falling control circuit FCC2 in response to the clock difference control signal CDCS[1:N].

[0249] Here, the clock difference control signal CDCS[1:N] may be provided to the level shifter 300 by the power management integrated circuit 310 or the controller 140 .

[0250] FIG. 10A to FIG. 10D is an example circuit in the first clock output buffer CBUF1 of the level shifter 300 of the display device 100 according to aspects of the present disclosure, and FIG. 11A to FIG. 11Dis an example circuit in the second clock output buffer CBUF2 of the level shifter 300 of the display device 100 according to aspects of the present disclosure.

[0251] Reference FIG. 10A to FIG. 10D The first clock output buffer CBUF1 may include a first rising control circuit RCC1 and a first falling control circuit FCC1, the first rising control circuit RCC1 including N first rising control transistors (RCT1-1 to RCT1-N) electrically connected between a high-level voltage node Nhv applied with a high-level voltage HV and a first clock output terminal Nclk1, and the first falling control circuit FCC1 including N first falling control transistors (FCT1-1 to FCT1-N) electrically connected between a low-level voltage node Nlv applied with a low-level voltage LV and the first clock output terminal Nclk1, where N is a natural number of 2 or greater.

[0252] Reference FIG. 11A to FIG. 11D The second clock output buffer CBUF2 may include a second rising control circuit RCC2 and a second falling control circuit FCC2, the second rising control circuit RCC2 includes N second rising control transistors (RCT2-1 to RCT2-N) electrically connected between a high-level voltage node Nhv applied with a high-level voltage HV and the second clock output terminal Nclk2, and the second falling control circuit FCC2 includes N second falling control transistors (FCT2-1 to FCT2-N) electrically connected between a low-level voltage node Nlv applied with a low-level voltage LV and the second clock output terminal Nclk2.

[0253] Here, the high level voltage HV may correspond to the high level voltage of the clock signals (CLK1 and CLK2) and to the high level voltage (on level voltage) of the gate signals (VGATE1 and VGATE2). The low level voltage LV may correspond to the low level voltage of the clock signals (CLK1 and CLK2) and to the low level voltage (off level voltage) of the gate signals (VGATE1 and VGATE2).

[0254] Reference FIG. 10A to FIG. 11D , the corresponding turning on and / or off of N control transistors included in at least one of the first rising control circuit RCC1, the first falling control circuit FCC1, the second rising control circuit RCC2 and the second falling control circuit FCC2 can be independently controlled.

[0255] A cut-off level gating voltage may be applied to one or more of the corresponding gate nodes of the N control transistors included in at least one of the first rising control circuit RCC1, the first falling control circuit FCC1, the second rising control circuit RCC2, and the second falling control circuit FCC2. One or more of the N control transistors included in at least one of the first rising control circuit RCC1, the first falling control circuit FCC1, the second rising control circuit RCC2, and the second falling control circuit FCC2 may be cut off.

[0256] Reference FIG. 10A to FIG. 11D In response to the clock deviation control signal CDCS[1:N] input from the power management integrated circuit 310 or the controller 140, in the level shifter 300, one or more of the N control transistors included in at least one of the first rising control circuit RCC1, the first falling control circuit FCC1, the second rising control circuit RCC2 and the second falling control circuit FCC2 can be turned on, and all or some of the remaining control transistors except the turned-on control transistors can be turned off.

[0257] Reference Fig. 10A In the first clock output buffer CBUF1, all corresponding gate nodes of the N first rising control transistors (RCT1-1 to RCT1-N) can be electrically connected and commonly receive a first rising control signal RCS1, and all corresponding gate nodes of the N first falling control transistors (FCT1-1 to FCT1-N) can be electrically connected and commonly receive a first falling control signal FCS1. In this case, the N first rising control transistors (RCT1-1 to RCT1-N) can be turned on or off at the same time or substantially at the same time, and the N first falling control transistors (FCT1-1 to FCT1-N) can be turned on or off at the same time or substantially at the same time.

[0258] Reference Fig. 10B In the first clock output buffer CBUF1, all corresponding gate nodes of the N first rising control transistors (RCT1-1 to RCT1-N) can be electrically connected and receive a first rising control signal RCS1 in common, and the N first falling control signals FCS1[1:N] can be applied separately to the gate nodes of the N first falling control transistors (FCT1-1 to FCT1-N). In this case, the N first rising control transistors (RCT1-1 to RCT1-N) can be turned on or off at the same time or substantially at the same time, and the N first falling control transistors (FCT1-1 to FCT1-N) can be turned on and off independently.

[0259] Reference Fig. 10C, in the first clock output buffer CBUF1, N first rising control signals RCS1[1:N] may be applied individually to the gate nodes of the N first rising control transistors (RCT1-1 to RCT1-N), and all corresponding gate nodes of the N first falling control transistors (FCT1-1 to FCT1-N) may be electrically connected and receive one first falling control signal FCS1 in common. In this case, the N first rising control transistors (RCT1-1 to RCT1-N) may be turned on and off independently, and the N first falling control transistors (FCT1-1 to FCT1-N) may be turned on or off simultaneously or substantially simultaneously.

[0260] Reference Fig. 10D , in the first clock output buffer CBUF1, N first rising control signals RCS1[1:N] may be applied individually to the gate nodes of the N first rising control transistors (RCT1-1 to RCT1-N), and N first falling control signals FCS1[1:N] may be applied individually to the gate nodes of the N first falling control transistors (FCT1-1 to FCT1-N). In this case, the N first rising control transistors (RCT1-1 to RCT1-N) may be turned on and off independently, and the N first falling control transistors (FCT1-1 to FCT1-N) may be turned on and off independently.

[0261] Reference Fig.11A In the second clock output buffer CBUF2, all corresponding gate nodes of the N second rising control transistors (RCT2-1 to RCT2-N) can be electrically connected and commonly receive a second rising control signal RCS2, and all corresponding gate nodes of the N second falling control transistors (FCT2-1 to FCT2-N) can be electrically connected and commonly receive a second falling control signal FCS2. In this case, the N second rising control transistors (RCT2-1 to RCT2-N) can be turned on or off at the same time or substantially at the same time, and the N second falling control transistors (FCT2-1 to FCT2-N) can be turned on or off at the same time or substantially at the same time.

[0262] Reference Fig. 11BIn the second clock output buffer CBUF2, all corresponding gate nodes of the N second rising control transistors (RCT2-1 to RCT2-N) can be electrically connected and receive a second rising control signal RCS2 in common, and the N second falling control signals FCS2[1:N] can be applied separately to the gate nodes of the N second falling control transistors (FCT2-1 to FCT2-N). In this case, the N second rising control transistors (RCT2-1 to RCT2-N) can be turned on or off at the same time or substantially at the same time, and the N second falling control transistors (FCT2-1 to FCT2-N) can be turned on and off independently.

[0263] Reference Fig. 11C , in the second clock output buffer CBUF2, N second rising control signals RCS2[1:N] can be applied individually to the gate nodes of the N second rising control transistors (RCT2-1 to RCT2-N), and all corresponding gate nodes of the N second falling control transistors (FCT2-1 to FCT2-N) can be electrically connected and receive one second falling control signal FCS2 in common. In this case, the N second rising control transistors (RCT2-1 to RCT2-N) can be turned on and off independently, and the N second falling control transistors (FCT2-1 to FCT2-N) can be turned on or off simultaneously or substantially simultaneously.

[0264] Reference Fig.11D In the second clock output buffer CBUF2, N second rising control signals RCS2[1:N] can be applied individually to the gate nodes of the N second rising control transistors (RCT2-1 to RCT2-N), and N second falling control signals FCS2[1:N] can be applied individually to the gate nodes of the N second falling control transistors (FCT2-1 to FCT2-N). In this case, the N second rising control transistors (RCT2-1 to RCT2-N) can be turned on and off independently, and the N second falling control transistors (FCT2-1 to FCT2-N) can be turned on and off independently.

[0265] In some embodiments, by selectively combining FIG. 10A to FIG. 10D One of the four types of first clock output buffers CBUF1 shown and FIG. 11A to FIG. 11D A level shifter 300 is configured using one of the four types of second clock output buffers CBUF2 shown in FIG.

[0266] In the following, reference will be made to Fig.12 Description by Fig. 10B The first clock output buffer CBUF1 and Fig.11AThe second clock output buffer CBUF2 of the combination configuration level shifter 300, and will refer to Fig.14 Description by Fig. 10B The first clock output buffer CBUF1 and Fig. 11C The combination of the second clock output buffer CBUF2 configures the level shifter 300 .

[0267] Fig.12 is a detailed diagram of a level shifter 300 for compensating for a difference in falling characteristics between gating signals in a display device 100 according to aspects of the present disclosure. Fig.13 Illustrated based on Fig.12 The falling length CF1 of the first clock signal CLK1 is equal to the number of first falling control transistors that are turned on among the N first falling control transistors (FCT1 - 1 to FCT1 -N) of the level shifter 300 .

[0268] Reference Fig.12 In the case where the difference in falling characteristics between the selection signals is a major factor in image quality degradation, etc., the level shifter 300 may perform a control function of compensating for the difference in falling characteristics between the selection signals instead of performing a control function of compensating for the difference in rising characteristics between the selection signals.

[0269] Reference Fig.12 , the level shifter 300 can be composed of Fig. 10B The first clock output buffer CBUF1 and Fig.11A The combinatorial configuration of the second clock output buffer CBUF2.

[0270] Reference Fig.12 , the first clock output buffer CBUF1 included in the level shifter 300 may perform falling control of the first clock signal CLK1 and may not perform rising control of the first clock signal CLK1. In the first clock output buffer CBUF1 included in the level shifter 300, the N first falling control transistors (FCT1-1 to FCT1-N) included in the first falling control circuit FCC1 may be controlled to be turned on or off independently, and the N first rising control transistors (RCT1-1 to RCT1-N) included in the first rising control circuit RCC1 may be turned on or off simultaneously or almost simultaneously.

[0271] Reference Fig.12, the second clock output buffer CBUF2 included in the level shifter 300 may not perform falling and rising control of the second clock signal CLK2. In the second clock output buffer CBUF2 included in the level shifter 300, the N second rising control transistors (RCT2-1 to RCT2-N) included in the second rising control circuit RCC2 may be turned on or off at the same time or almost at the same time, and the N second falling control transistors (FCT2-1 to FCT2-N) included in the second falling control circuit FCC2 may be turned on or off at the same time or almost at the same time.

[0272] Reference Fig.12 , one to (N-1) first drop control transistors among the N first drop control transistors (FCT1-1 to FCT1-N) can be turned on by N first drop control signals FCS1[1:N], and all N second drop control transistors (FCT2-1 to FCT2-N) can be turned on by one second drop control signal FCS2.

[0273] A falling length CF1 of the first clock signal CLK1 output from the first clock output buffer CBUF1 may be greater than a falling length CF2 of the second clock signal CLK2 output from the second clock output buffer CBUF2 .

[0274] A difference between a falling length F1 of the associated first gate signal VGATE1 and a falling length F2 of the associated second gate signal VGATE2 may be smaller than a difference between a falling length CF1 of the first clock signal CLK1 and a falling length CF2 of the second clock signal CLK2 .

[0275] Reference Fig.12 When the falling length CF1 of the first clock signal CLK1 is greater than the falling length CF2 of the second clock signal CLK2, the number of the turned-on falling control transistors among the N first falling control transistors (FCT1-1 to FCT1-N) can be less than the number of the turned-on falling control transistors among the N second falling control transistors (FCT2-1 to FCT2-N).

[0276] Reference Fig.12 and Fig.13 In the first clock output buffer CBUF1 included in the level shifter 300, when the N first falling control transistors (FCT1-1 to FCT1-N) included in the first falling control circuit FCC1 are all turned on, the first clock signal CLK1 falls at the earliest timing. Therefore, the falling length CF1 of the first clock signal CLK1 can become the minimum. Fig.13, when all the N first falling control transistors (FCT1-1 to FCT1-N) included in the first falling control circuit FCC1 are turned on, the voltage of the first clock signal CLK1 can drop from the high level voltage to the low level voltage with almost no time delay. That is, when all the N first falling control transistors (FCT1-1 to FCT1-N) included in the first falling control circuit FCC1 are turned on, the falling length CF1 of the first clock signal CLK1 can become close to 0 (zero).

[0277] Reference Fig.12 and Fig.13 , in the first clock output buffer CBUF1 included in the level shifter 300, when one of the N first falling control transistors (FCT1-1 to FCT1-N) included in the first falling control circuit FCC1 is turned on, the first clock signal CLK1 falls at the latest timing. Therefore, the falling length CF1 of the first clock signal CLK1 can become maximum.

[0278] Fig.14 is a detailed diagram of a level shifter 300 for compensating for a falling characteristic difference and a rising characteristic difference between gating signals in a display device 100 according to aspects of the present disclosure. Fig.15 Illustrated based on Fig.14 The falling length CF1 of the first clock signal CLK1 is based on the number of first falling control transistors turned on among the N first falling control transistors (FCT1-1 to FCT1-N) of the level shifter 300, and the rising length CR2 of the second clock signal CLK2 is based on the number of second rising control transistors turned on among the N second rising control transistors (RCT2-1 to RCT2-N).

[0279] Reference Fig.14 When both the difference in falling characteristics and the difference in rising characteristics between the selection signals are main factors of image quality degradation, etc., the level shifter 300 can perform a control function of compensating for both the difference in falling characteristics and the difference in rising characteristics between the selection signals.

[0280] Reference Fig.14 , the level shifter 300 can be composed of Fig. 10B The first clock output buffer CBUF1 and Fig. 11C The combinatorial configuration of the second clock output buffer CBUF2.

[0281] Reference Fig.14, the first clock output buffer CBUF1 included in the level shifter 300 may perform falling control of the first clock signal CLK1 and may not perform rising control of the first clock signal CLK1. In the first clock output buffer CBUF1 included in the level shifter 300, the N first falling control transistors (FCT1-1 to FCT1-N) included in the first falling control circuit FCC1 may be controlled to be turned on or off independently, and the N first rising control transistors (RCT1-1 to RCT1-N) included in the first rising control circuit RCC1 may be turned on or off simultaneously or almost simultaneously.

[0282] Reference Fig.14 , the second clock output buffer CBUF2 included in the level shifter 300 may not perform falling control of the second clock signal CLK2 and may perform rising control of the second clock signal CLK2. In the second clock output buffer CBUF2 included in the level shifter 300, the N second rising control transistors (RCT2-1 to RCT2-N) included in the second rising control circuit RCC2 may be controlled to be turned on or off independently, and the N second falling control transistors (FCT2-1 to FCT2-N) included in the second falling control circuit FCC2 may be turned on or off simultaneously or almost simultaneously.

[0283] Reference Fig.14 , one to (N-1) first falling control transistors among the N first falling control transistors (FCT1-1 to FCT1-N) can be turned on by the N first falling control signals FCS1[1:N]. All the N second falling control transistors (FCT2-1 to FCT2-N) can be turned on by a second falling control signal FCS2.

[0284] A falling length CF1 of the first clock signal CLK1 output from the first clock output buffer CBUF1 may be greater than a falling length CF2 of the second clock signal CLK2 output from the second clock output buffer CBUF2 .

[0285] A difference between a falling length F1 of the associated first gate signal VGATE1 and a falling length F2 of the associated second gate signal VGATE2 may be smaller than a difference between a falling length CF1 of the first clock signal CLK1 and a falling length CF2 of the second clock signal CLK2 .

[0286] Reference Fig.14When the falling length CF1 of the first clock signal CLK1 is greater than the falling length CF2 of the second clock signal CLK2, the number of the turned-on falling control transistors among the N first falling control transistors (FCT1-1 to FCT1-N) can be less than the number of the turned-on falling control transistors among the N second falling control transistors (FCT2-1 to FCT2-N).

[0287] Reference Fig.14 , one to (N-1) second control transistors among the N second rising control transistors (RCT2-1 to RCT2-N) can be turned on by the N second rising control signals RCS2[1:N]. All the N first rising control transistors (RCT1-1 to RCT1-N) can be turned on by one first rising control signal RCS1.

[0288] A rising length CR2 of the second clock signal CLK2 output from the second clock output buffer CBUF2 may be greater than a rising length CR1 of the first clock signal CLK1 output from the first clock output buffer CBUF1 .

[0289] A difference between a rising length R1 of the associated first gate signal VGATE1 and a rising length R2 of the associated second gate signal VGATE2 may be smaller than a difference between a rising length CR1 of the first clock signal CLK1 and a rising length CR2 of the second clock signal CLK2 .

[0290] Reference Fig.14 When the rising length CR2 of the second clock signal CLK2 is greater than the rising length CR1 of the first clock signal CLK1, the number of the rising control transistors turned on among the N second rising control transistors (RCT2-1 to RCT2-N) can be less than the number of the rising control transistors turned on among the N first rising control transistors (RCT1-1 to RCT1-N).

[0291] Reference Fig.14 and Fig.15 In the first clock output buffer CBUF1 included in the level shifter 300, when all N first falling control transistors (FCT1-1 to FCT1-N) included in the first falling control circuit FCC1 are turned on, the first clock signal CLK1 falls at the earliest timing. Therefore, the falling length CF1 of the first clock signal CLK1 can become the minimum. Fig.15, when all N first falling control transistors (FCT1-1 to FCT1-N) included in the first falling control circuit FCC1 are turned on, the voltage of the first clock signal CLK1 can drop from a high level voltage to a low level voltage with almost no time delay. That is, when all N first falling control transistors (FCT1-1 to FCT1-N) included in the first falling control circuit FCC1 are turned on, the falling length CF1 of the first clock signal CLK1 can become close to 0 (zero).

[0292] Reference Fig.14 and Fig.15 , in the first clock output buffer CBUF1 included in the level shifter 300, when one of the N first falling control transistors (FCT1-1 to FCT1-N) included in the first falling control circuit FCC1 is turned on, the first clock signal CLK1 falls at the latest timing. Therefore, the falling length CF1 of the first clock signal CLK1 can become maximum.

[0293] Reference Fig.14 and Fig.15 In the second clock output buffer CBUF2 included in the level shifter 300, when all N second rise control transistors (RCT2-1 to RCT2-N) included in the second rise control circuit RCC2 are turned on, the second clock signal CLK2 rises at the earliest timing. Therefore, the rise length CR2 of the second clock signal CLK2 can become the minimum. Fig.15 , when all N second rising control transistors (RCT2-1 to RCT2-N) included in the second rising control circuit RCC2 are turned on, the voltage of the second clock signal CLK2 can rise from a low level voltage to a high level voltage with almost no time delay. That is, when all N second rising control transistors (RCT2-1 to RCT2-N) included in the second rising control circuit RCC2 are turned on, the rising length CR2 of the second clock signal CLK2 can become close to 0 (zero).

[0294] Reference Fig.14 and Fig.15 , in the second clock output buffer CBUF2 included in the level shifter 300, when one of the N second rise control transistors (RCT2-1 to RCT2-N) included in the second rise control circuit RCC2 is turned on, the second clock signal CLK2 rises at the latest timing. Therefore, the rise length CF2 of the second clock signal CLK2 can become maximum.

[0295] Fig.16 An example strobe signal output system of the display device 100 according to aspects of the present disclosure is illustrated. Fig.17 Illustrated Fig.16 An example gate driving circuit 130 in a gate signal output system.

[0296] Reference Fig.16 , when m is 4, four output buffer circuits (GBUF1 to GBUF4) can share one Q-node Q.

[0297] When m is 4, the four clock signals (CLK1 to CLK4) can be a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3 and a fourth clock signal CLK4, and the associated four selection signals (VGATE1 to VGATE4) can be a first selection signal VGATE1, a second selection signal VGATE2, a third selection signal VGATE3 and a fourth selection signal VGATE4.

[0298] Reference Fig.16 , the level shifter 300 may output four clock signals (CLK1 to CLK4) among the plurality of clock signals. Here, the four clock signals (CLK1 to CLK4) may be a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4.

[0299] Reference Fig.16 , the gate driving circuit 130 can receive four clock signals (CLK1 to CLK4) and output four gate signals (VGATE1 to VGATE4). That is, the gate driving circuit 130 can receive the first clock signal CLK1 and output the first gate signal VGATE1 to the first gate line GL1, receive the second clock signal CLK2 and output the second gate signal VGATE2 to the second gate line GL2, receive the third clock signal CLK3 and output the third gate signal VGATE3 to the third gate line GL3, and receive the fourth clock signal CLK4 and output the fourth gate signal VGATE4 to the fourth gate line GL4.

[0300] Reference Fig.17 , the gate driving circuit 130 may include first to fourth output buffer circuits (GBUF1 to GBUF4) and a control circuit 400 for controlling the first to fourth output buffer circuits (GBUF1 to GBUF4).

[0301] The first output buffer circuit GBUF1 may output a first gate signal VGATE1 to the first gate line GL1 through the first gate output terminal Ng1 in response to (based on) the first clock signal CLK1 input to the first clock input terminal Nc1 .

[0302] The first output buffer circuit GBUF1 may include a first pull-up transistor Tu1 electrically connected between the first clock input terminal Nc1 and the first enable output terminal Ng1 and controlled by the voltage in the Q node Q, and a first pull-down transistor Td1 electrically connected between the first enable output terminal Ng1 and a basic input terminal Ns input with a basic voltage VSS1 and controlled by the voltage of the QB node QB.

[0303] The second output buffer circuit GBUF2 may output a second gate signal VGATE2 to the second gate line GL2 through the second gate output terminal Ng2 in response to (based on) the second clock signal CLK2 input to the second clock input terminal Nc2.

[0304] The second output buffer circuit GBUF2 may include a second pull-up transistor Tu2 electrically connected between the second clock input terminal Nc2 and the second enable output terminal Ng2 and controlled by the voltage in the Q node Q, and a second pull-down transistor Td2 electrically connected between the second enable output terminal Ng2 and the base input terminal Ns and controlled by the voltage of the QB node QB.

[0305] The third output buffer circuit GBUF3 may output a third gate signal VGATE3 to the third gate line GL3 through the third gate output terminal Ng3 in response to (based on) the third clock signal CLK3 input to the third clock input terminal Nc3 .

[0306] The third output buffer circuit GBUF3 may include a third pull-up transistor Tu3 electrically connected between the third clock input terminal Nc3 and the third enable output terminal Ng3 and controlled by the voltage in the Q node Q, and a third pull-down transistor Td3 electrically connected between the third enable output terminal Ng3 and the base input terminal Ns and controlled by the voltage of the QB node QB.

[0307] The fourth output buffer circuit GBUF4 may output a fourth gate signal VGATE4 to the fourth gate line GL4 through the fourth gate output terminal Ng4 in response to (based on) the fourth clock signal CLK4 input to the fourth clock input terminal Nc4.

[0308] The fourth output buffer circuit GBUF4 may include a fourth pull-up transistor Tu4 electrically connected between the fourth clock input terminal Nc4 and the fourth selection output terminal Ng4 and controlled by the voltage in the Q node Q, and a fourth pull-down transistor Td4 electrically connected between the fourth selection output terminal Ng4 and the base input terminal Ns and controlled by the voltage of the QB node QB.

[0309] Fig.18 Illustrated Fig.16The characteristic difference between the selection signals in the selection signal output system (Q node sharing structure in the case of m=4) is shown. Fig.19 Illustrated for Fig.16 Compensation for characteristic differences between gate signals in a gate signal output system (Q-node sharing structure in the case of m=4).

[0310] Reference Fig.18 , when m is 4, the m clock signals (CLK1 to CLKm) may include a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3 and a fourth clock signal CLK4, and the m associated selection signals (VGATE1 to VGATEm) may include a first selection signal VGATE1, a second selection signal VGATE2, a third selection signal VGATE3 and a fourth selection signal VGATE4.

[0311] Reference Fig.18 , the level shifter 300 may output the first to fourth clock signals (CLK1 to CLK4), and the gate driving circuit 130 may output the first to fourth gate signals (VGATE1 to VGATE4) using the first to fourth clock signals (CLK1 to CLK4).

[0312] As described above, when a clock signal control function is not performed to compensate for a characteristic difference between gate signals, if the gate driving circuit 130 performs overlapping gate driving and has a Q-node sharing structure, a characteristic difference between gate signals may occur.

[0313] Not performing a clock signal control function to compensate for the characteristic difference between the strobe signals means that the first to fourth clock signals (CLK1 to CLK4) have equal signal waveforms. Configuring the first to fourth clock signals (CLK1 to CLK4) to have equal signal waveforms means that the first to fourth clock signals (CLK1 to CLK4) have the same rising characteristic (rising length) and falling characteristic (falling length).

[0314] Reference Fig.18, when m=4, assuming that the on-voltage level duration of the first selection signal VGATE1 is performed at the earliest timing and the on-voltage level duration of the fourth selection signal VGATE4 is performed at the latest timing among the first selection signal to the fourth selection signal (VGATE1 to VGATE4), the rising length R1 of the on-voltage level duration of the first selection signal VGATE1 among the first selection signal to the fourth selection signal (VGATE1 to VGATE4) is the largest. That is, the rising characteristic of the first selection signal VGATE1 among the first selection signal to the fourth selection signal (VGATE1 to VGATE4) is the worst.

[0315] The fourth selection signal VGATE4 has the largest drop length F4 in the on-voltage level duration among the first to fourth selection signals (VGATE1 to VGATE4). That is, the fourth selection signal VGATE4 has the worst drop characteristic among the first to fourth selection signals (VGATE1 to VGATE4).

[0316] Comparing the respective rising characteristics (rising lengths) of the first to fourth selection signals (VGATE1 to VGATE4), the first selection signal VGATE1 has the worst rising characteristic, and the degree of difference of the respective rising characteristics of the remaining selection signals may be in the order of the second selection signal VGATE2, the third selection signal VGATE3, and the fourth selection signal VGATE4. That is, the first selection signal VGATE1 may have the largest rising length R1, the second selection signal VGATE2 may have the second largest rising length R2, the third selection signal VGATE3 may have the third largest rising length R3, and the fourth selection signal VGATE4 may have the smallest rising length R4 (ie, R1>R2>R3>R4).

[0317] In this case, among the first to fourth selection signals (VGATE1 to VGATE4), although the first selection signal VGATE1 always has the largest rising length R1, the differences between the corresponding rising lengths (R2, R3, R4) of the second to fourth selection signals (VGATE2 to VGATE4) may vary differently.

[0318] Comparing the respective falling characteristics (falling lengths) of the first to fourth selection signals (VGATE1 to VGATE4), the fourth selection signal VGATE4 has the worst falling characteristic, and the respective falling characteristics of the remaining selection signals may be poor in the order of the third selection signal VGATE3, the second selection signal VGATE2, and the first selection signal VGATE1. That is, the fourth selection signal VGATE4 may have the largest falling length F4, the third selection signal VGATE3 may have the second largest falling length F3, the second selection signal VGATE2 may have the third largest falling length F2, and the first selection signal VGATE1 may have the smallest falling length F1 (i.e., F1). <F2<F3<F4)。

[0319] In this case, among the first to fourth selection signals (VGATE1 to VGATE4), although the fourth selection signal VGATE4 always has the largest falling length F4, the difference between the corresponding falling lengths (F1, F2, F3) of the first to third selection signals (VGATE1 to VGATE3) may vary differently.

[0320] In order to reduce the characteristic difference (rising characteristic difference, falling characteristic difference) between the first to fourth gate signals ( VGATE1 to VGATE4 ) as described above (ie, compensate for the characteristic difference between the gate signals), the level shifter 300 may perform a clock signal control function.

[0321] Reference Fig.19 In order to reduce the characteristic difference (falling characteristic difference) between the first to fourth selection signals (VGATE1 to VGATE4), the level shifter 300 can control the corresponding falling lengths (CF1, CF2 and CF3) of the first to third clock signals (CLK1 to CLK3) to become larger so as to allow the corresponding falling lengths (F1, F2 and F3) of the first to third selection signals (VGATE1 to VGATE3) to have a length similar to the falling length F4 of the fourth selection signal VGATE4 having the worst falling characteristic.

[0322] Reference Fig.19 , the on-level voltage duration of the first selection signal VGATE1 and the on-level voltage duration of the second selection signal VGATE2 may overlap, and the on-level voltage duration of the second selection signal VGATE2 and the on-level voltage duration of the third selection signal VGATE3 may overlap, and the on-level voltage duration of the third selection signal VGATE3 and the on-level voltage duration of the fourth selection signal VGATE4 may overlap.

[0323] Reference Fig.19 , the timing of the on-level voltage duration of the first gate signal VGATE1 may be earlier than the fourth gate signal VGATE4 which is the latest gate signal VGATEm (where m is 4). In this case, the falling length CF1 of the first clock signal CLK1 may be greater than the falling length CF4 of the fourth clock signal CLK4, or the rising length CR4 of the fourth clock signal CLK4 may be greater than the rising length CR1 of the first clock signal CLK1. Related discussions are given below.

[0324] Reference Fig.19 As long as the falling length CF4 of the fourth clock signal CLK4 is minimum, the difference between the corresponding falling lengths (CF1, CF2 and CF3) of the first to third clock signals (CLK1 to CLK3) may be allowed to vary.

[0325] Reference Fig.19 For example, the fourth clock signal CLK4 has the smallest falling length CF4, the third clock signal CLK3 has the second smallest falling length CF3, the second clock signal CLK2 has the third smallest falling length CF2, and the first clock signal CLK1 has the largest falling length CF1 (i.e., CF4 <CF3<CF2<CF1)。

[0326] Reference Fig.19 In order to reduce the characteristic difference (rising characteristic difference) between the first to fourth selection signals (VGATE1 to VGATE4), the level shifter 300 can control the corresponding rising lengths (CR2, CR3 and CR4) of the second to fourth clock signals (CLK2 to CLK4) to become larger so as to allow the corresponding rising lengths (R2, R3 and R4) of the second to fourth selection signals (VGATE2 to VGATE4) to have a length similar to the rising length R1 of the first selection signal VGATE1 having the worst rising characteristic.

[0327] Reference Fig.19 As long as the rising length CR1 of the first clock signal CLK1 is minimum, the difference between the corresponding first rising lengths (CR2, CR3 and CR4) of the second to fourth clock signals (CLK2 to CLK4) can be allowed to vary.

[0328] Reference Fig.19 For example, the first clock signal CLK1 has the smallest rise length CR1, the second clock signal CLK2 has the second smallest rise length CR2, the third clock signal CLK3 has the third smallest rise length CR3, and the fourth clock signal CLK4 has the largest rise length CR4 (ie, CR1 <CR2<CR3<CR4)。

[0329] Fig. 20 yes Fig.16 1 is a block diagram of a level shifter 300 in a selection signal output system. Fig.21 yes Fig.19 Detailed diagram of the level shifter 300 .

[0330] Reference Fig. 20 and Fig.21 , the level shifter 300 may output the first clock signal CLK1 , the second clock signal CLK2 , the third clock signal CLK3 , and the fourth clock signal CLK4 to the gate driving circuit 130 .

[0331] Reference Fig. 20 and Fig.21 , the level shifter 300 may include: a first clock output buffer CBUF1, which is used to generate a first clock signal CLK1 and output the generated first clock signal CLK1 to a first clock output terminal Nclk1; a second clock output buffer CBUF2, which is used to generate a second clock signal CLK2 and output the generated second clock signal CLK2 to a second clock output terminal Nclk2; a third clock output buffer CBUF3, which is used to generate a third clock signal CLK3 and output the generated third clock signal CLK3 to a third clock output terminal Nclk3; and a fourth clock output buffer CBUF4, which is used to generate a fourth clock signal CLK4 and output the generated fourth clock signal CLK4 to a fourth clock output terminal Nclk4.

[0332] Reference Fig.21 The first clock output buffer CBUF1 may include a first rising control circuit RCC1 and a first falling control circuit FCC1, the first rising control circuit RCC1 includes N first rising control transistors (RCT1-1 to RCT1-N) electrically connected between a high level voltage node Nhv and a first clock output terminal Nclk1, and the first falling control circuit FCC1 includes N first falling control transistors (FCT1-1 to FCT1-N) electrically connected between a low level voltage node Nlv and the first clock output terminal Nclk1, where N is a natural number of 2 or greater.

[0333] Reference Fig.21The second clock output buffer CBUF2 may include a second rising control circuit RCC2 and a second falling control circuit FCC2, the second rising control circuit RCC2 includes N second rising control transistors (RCT2-1 to RCT2-N) electrically connected between a high level voltage node Nhv and the second clock output terminal Nclk2, and the second falling control circuit FCC2 includes N second falling control transistors (FCT2-1 to FCT2-N) electrically connected between a low level voltage node Nlv and the second clock output terminal Nclk2.

[0334] Reference Fig.21 The third clock output buffer CBUF3 may include a third rising control circuit RCC3 and a third falling control circuit FCC3, the third rising control circuit RCC3 including N third rising control transistors (RCT3-1 to RCT3-N) electrically connected between the high level voltage node Nhv and the third clock output terminal Nclk3, and the third falling control circuit FCC3 including N third falling control transistors (FCT3-1 to FCT3-N) electrically connected between the low level voltage node Nlv and the third clock output terminal Nclk3.

[0335] Reference Fig.21 The fourth clock output buffer CBUF4 may include a fourth rising control circuit RCC4 and a fourth falling control circuit FCC4, the fourth rising control circuit RCC4 including N fourth rising control transistors (RCT4-1 to RCT4-N) electrically connected between the high level voltage node Nhv and the fourth clock output terminal Nclk4, and the fourth falling control circuit FCC4 including N fourth falling control transistors (FCT4-1 to FCT4-N) electrically connected between the low level voltage node Nlv and the fourth clock output terminal Nclk4.

[0336] The corresponding turn-on and / or turn-off of N control transistors included in at least one of the first rising control circuit RCC1, the first falling control circuit FCC1, the second rising control circuit RCC2, the second falling control circuit FCC2, the third rising control circuit RCC3, the third falling control circuit FCC3, the fourth rising control circuit RCC4 and the fourth falling control circuit FCC4 can be independently controlled.

[0337] Reference Fig.21In the first clock output buffer CBUF1, the corresponding conduction or / and cutoff of the N first rising control transistors (RCT1-1 to RCT1-N) can be individually controlled by the N first rising control signals RCS1[1:N], and the corresponding conduction or / and cutoff of the N first falling control transistors (FCT1-1 to FCT1-N) can be individually controlled by the N first falling control signals FCS1[1:N].

[0338] Reference Fig.21 In the second clock output buffer CBUF2, the corresponding conduction or / and cutoff of the N second rising control transistors (RCT2-1 to RCT2-N) can be individually controlled by the N second rising control signals RCS2[1:N], and the corresponding conduction or / and cutoff of the N second falling control transistors (FCT2-1 to FCT2-N) can be individually controlled by the N second falling control signals FCS2[1:N].

[0339] Reference Fig.21 In the third clock output buffer CBUF3, the corresponding conduction or / and cutoff of the N third rising control transistors (RCT3-1 to RCT3-N) can be individually controlled by the N third rising control signals RCS3[1:N], and the corresponding conduction or / and cutoff of the N third falling control transistors (FCT3-1 to FCT3-N) can be individually controlled by the N third falling control signals FCS3[1:N].

[0340] Reference Fig.21 In the fourth clock output buffer CBUF4, the corresponding conduction or / and cutoff of the N fourth rising control transistors (RCT4-1 to RCT4-N) can be individually controlled by the N fourth rising control signals RCS4[1:N], and the corresponding conduction or / and cutoff of the N fourth falling control transistors (FCT4-1 to FCT4-N) can be individually controlled by the N fourth falling control signals FCS4[1:N].

[0341] Reference Fig.21 When the falling length CF1 of the first clock signal CLK1 is greater than the falling length CF4 of the fourth clock signal CLK4, the number of the turned-on falling control transistors among the N first falling control transistors (FCT1-1 to FCT1-N) can be less than the number of the turned-on falling control transistors among the N fourth falling control transistors (FCT4-1 to FCT4-N).

[0342] Reference Fig.21When the rising length CR4 of the fourth clock signal CLK4 is greater than the rising length CR1 of the first clock signal CLK1, the number of the turned-on rising control transistors among the N fourth rising control transistors (RCT4-1 to RCT4-N) can be less than the number of the turned-on rising control transistors among the N first rising control transistors (RCT1-1 to RCT1-N).

[0343] Fig. 22 Compensation for a characteristic difference between gating signals using at least one resistor ( r1 , r2 ) in the display device 100 according to aspects of the present disclosure is illustrated.

[0344] Reference Fig. 22 According to various aspects of the present disclosure, the display device 100 may include: a printed circuit board PCB, which is configured to output a first reference clock signal REF_CLK1 to a first reference clock output terminal Nr1 and a second reference clock signal REF_CLK2 to a second reference clock output terminal Nr2; a first resistor r1, which is connected between the first reference clock output terminal Nr1 and the gate drive circuit 130; and a second resistor r2, which is connected between the second reference clock output terminal Nr2 and the gate drive circuit 130.

[0345] Reference Fig. 22 , the first reference clock signal REF_CLK1 and the second reference clock signal REF_CLK2 are uncontrolled clock signals, and their respective rising lengths and falling lengths may correspond to each other.

[0346] The first resistor r1 and the second resistor r2 may have different resistance values. For example, the resistance value of the first resistor r1 may be greater than the resistance value of the second resistor r2. As the resistance value of the first resistor r1 increases, the rising length and the falling length of the first clock signal CLK1 may become larger. As the resistance value of the first resistor r1 decreases, the rising length and the falling length of the first clock signal CLK1 may become smaller.

[0347] The first clock signal CLK1 may be a signal when the first reference clock signal REF_CLK1 passes through the first resistor r1 and then enters the gate driving circuit 130. The second clock signal CLK2 may be a signal when the second reference clock signal REF_CLK2 passes through the second resistor r2 and then enters the gate driving circuit 130.

[0348] FIG. 23A to FIG. 23D The level shifter 300 that controls and outputs at least one clock signal ( CLK1 , CLK2 ) through control of a resistor according to aspects of the present disclosure is illustrated and included in the display device 100 .

[0349] Reference Fig.23A , the level shifter 300 may provide m clock signals (CLK1 to CLKm) to the gate driving circuit 130. The level shifter 300 may be mounted on a printed circuit board PCB or connected to the printed circuit board PCB.

[0350] The m clock signals (CLK1 to CLKm) may include a first clock signal CLK1 and a second clock signal CLK2.

[0351] The level shifter 300 may include a first sourcing pin Psrc1 , a first sink pin Psnk1 , a second sourcing pin Psrc2 , and a second sink pin Psnk2 .

[0352] The level shifter 300 may include a first high level switch S1H between the first source pin Psrc1 and a node to which a high level voltage HV is applied, and a first low level switch S1L between the first sink pin Psnk1 and a node to which a low level voltage LV is applied.

[0353] The level shifter 300 may include a second high level switch S2H between the second source pin Psrc2 and a node to which the high level voltage HV is applied, and a second low level switch S2L between the second sink pin Psnk2 and a node to which the low level voltage LV is applied.

[0354] The level shifter 300 may further include control logic 2300 for outputting control signals (CS1H, CS1L, CS2H, and CS2L) to control respective switching operations of the first high level switch S1H, the first low level switch S1L, the second high level switch S2H, and the second low level switch S2L.

[0355] When the first high level switch S1H is turned on, the first clock signal CLK1 may rise to a high level voltage HV, and when the first low level switch S1L is turned on, the first clock signal CLK1 may fall to a low level voltage LV.

[0356] When the second high level switch S2H is turned on, the second clock signal CLK2 may rise to the high level voltage HV, and when the second low level switch S2L is turned on, the second clock signal CLK2 may fall to the low level voltage LV.

[0357] Each of the first high level switch S1H, the first low level switch S1L, the second high level switch S2H and the second low level switch S2L described in this article can be implemented using a transistor, and the corresponding control signals (CS1H, CS1L, CS2H and CS2L) of the first high level switch S1H, the first low level switch S1L, the second high level switch S2H and the second low level switch S2L can be voltages applied to the gate nodes of the transistors.

[0358] The printed circuit board PCB may include a first rising control resistor Rtr1, a first falling control resistor Rtf1, a second rising control resistor Rtr2, and a second falling control resistor Rtf2, and include a first output node Nout1 from which the first clock signal CLK1 is output to the gate drive circuit 130 and a second output node Nout2 from which the second clock signal CLK2 is output to the gate drive circuit 130.

[0359] The first rising control resistor Rtr1 may be electrically connected between the first source pin Psrc1 and the first output node Nout1. The first falling control resistor Rtf1 may be electrically connected between the first sink pin Psnk1 and the first output node Nout1.

[0360] The second rising control resistor Rtr2 may be electrically connected between the second source pin Psrc2 and the second output node Nout2. The second falling control resistor Rtf2 may be electrically connected between the second sink pin Psnk2 and the second output node Nout2.

[0361] The first capacitor C1 may be connected between the first output node Nout1 and the ground GND, and the second capacitor C2 may be connected between the second output node Nout2 and the ground GND.

[0362] In order to make the falling length CF1 of the first clock signal CLK1 greater than the falling length CF2 of the second clock signal CLK2 , the resistance value of the first falling control resistor Rtf1 may be set to a value greater than the resistance value of the second falling control resistor Rtf2 .

[0363] In order for the rising length CR2 of the second clock signal CLK2 to become greater than the rising length CR1 of the first clock signal CLK1 , the resistance value of the second rising control resistor Rtr2 may be set to a value greater than the resistance value of the first rising control resistor Rtr1 .

[0364] Reference Fig. 23B , the level shifter 300 may include a first clock signal output pin Pclk1 and a second clock signal output pin Pclk2.

[0365] The level shifter 300 may include a first high level switch S1H between the first clock signal output pin Pclk1 and a node to which a high level voltage HV is applied, and a first low level switch S1L between the first clock signal output pin Pclk1 and a node to which a low level voltage LV is applied.

[0366] The level shifter 300 may include a second high level switch S2H between the second clock signal output pin Pclk2 and a node to which the high level voltage HV is applied, and a second low level switch S2L between the second clock signal output pin Pclk2 and a node to which the low level voltage LV is applied.

[0367] The level shifter 300 may further include a control logic 2300 for outputting control signals (CS1H, CS1L, CS2H, and CS2L) to control respective switching operations of the first high level switch S1H, the first low level switch S1L, the second high level switch S2H, and the second low level switch S2L.

[0368] When the first high level switch S1H is turned on, the first clock signal CLK1 may rise to a high level voltage HV, and when the first low level switch S1L is turned on, the first clock signal CLK1 may fall to a low level voltage LV.

[0369] When the second high level switch S2H is turned on, the second clock signal CLK2 may rise to the high level voltage HV, and when the second low level switch S2L is turned on, the second clock signal CLK2 may fall to the low level voltage LV.

[0370] The printed circuit board PCB may include a first rising control resistor Rtr1 , a first falling control resistor Rtf1 , a second rising control resistor Rtr2 , and a second falling control resistor Rtf2 .

[0371] The printed circuit board PCB may include a first output node Nout1 from which a first clock signal CLK1 is output to the gate driving circuit 130 , and a second output node Nout2 from which a second clock signal CLK2 is output to the gate driving circuit 130 .

[0372] The printed circuit board PCB may include a first rising control diode Dr1 and a first falling control diode Df1 for allowing current to flow in opposite directions to each other. The printed circuit board PCB may include a second rising control diode Dr2 and a second falling control diode Df2 for allowing current to flow in opposite directions to each other.

[0373] The first rising control diode Dr1 and the first rising control resistor Rtr1 may be connected in series between the first clock signal output pin Pclk1 and the first output node Nout1. The first falling control diode Df1 and the first falling control resistor Rtf1 may be connected in series between the first clock signal output pin Pclk1 and the first output node Nout1.

[0374] The second rising control diode Dr2 and the second rising control resistor Rtr2 may be connected in series between the second clock signal output pin Pclk2 and the second output node Nout2. The second falling control diode Df2 and the second falling control resistor Rtf2 may be connected in series between the second clock signal output pin Pclk2 and the second output node Nout2.

[0375] The first capacitor C1 may be connected between the first output node Nout1 and the ground GND, and the second capacitor C2 may be connected between the second output node Nout2 and the ground GND.

[0376] In order to make the falling length CF1 of the first clock signal CLK1 greater than the falling length CF2 of the second clock signal CLK2 , the resistance value of the first falling control resistor Rtf1 may be set to a value greater than the resistance value of the second falling control resistor Rtf2 .

[0377] In order for the rising length CR2 of the second clock signal CLK2 to become greater than the rising length CR1 of the first clock signal CLK1 , the resistance value of the second rising control resistor Rtr2 may be set to a value greater than the resistance value of the first rising control resistor Rtr1 .

[0378] Reference Fig.23C The level shifter 300 may include a first clock signal output pin Pclk1 and a second clock signal output pin Pclk2, and include a first rising setting pin Pr1, a first falling setting pin Pf1, a second rising setting pin Pr2, and a second falling setting pin Pf2.

[0379] The level shifter 300 may include a first high level switch S1H between the first clock signal output pin Pclk1 and a node to which a high level voltage HV is applied, and a first low level switch S1L between the first clock signal output pin Pclk1 and a node to which a low level voltage LV is applied.

[0380] The level shifter 300 may include a second high level switch S2H between the second clock signal output pin Pclk2 and a node to which the high level voltage HV is applied, and a second low level switch S2L between the second clock signal output pin Pclk2 and a node to which the low level voltage LV is applied.

[0381] The level shifter 300 may further include control logic 2300 for outputting control signals (CS1H, CS1L, CS2H, and CS2L) to control respective switching operations of the first high level switch S1H, the first low level switch S1L, the second high level switch S2H, and the second low level switch S2L.

[0382] When the first high level switch S1H is turned on, the first clock signal CLK1 may rise to a high level voltage HV, and when the first low level switch S1L is turned on, the first clock signal CLK1 may fall to a low level voltage LV.

[0383] When the second high level switch S2H is turned on, the second clock signal CLK2 may rise to the high level voltage HV, and when the second low level switch S2L is turned on, the second clock signal CLK2 may fall to the low level voltage LV.

[0384] Reference Fig.23C The printed circuit board PCB may include a first rising control resistor Rtr1, a first falling control resistor Rtf1, a second rising control resistor Rtr2, and a second falling control resistor Rtf2.

[0385] The first rising control resistor Rtr1 may be electrically connected between the first rising setting pin Pr1 and the ground GND. The first falling control resistor Rtf1 may be electrically connected between the first falling setting pin Pf1 and the ground GND.

[0386] The second rising control resistor Rtr2 may be electrically connected between the second rising setting pin Pr2 and the ground GND. The second falling control resistor Rtf2 may be electrically connected between the second falling setting pin Pf2 and the ground GND.

[0387] Reference Fig.23C The level shifter 300 may further include a setting logic 2310 for detecting a resistance value of a first rising control resistor Rtr1 through a first rising setting pin Pr1, detecting a resistance value of a first falling control resistor Rtf1 through a first falling setting pin Pf1, detecting a resistance value of a second rising control resistor Rtr2 through a second rising setting pin Pr2, and detecting a resistance value of a second falling control resistor Rtf2 through a second falling setting pin Pf2.

[0388] For example, the setting logic 2310 may provide a current having a known current value to the first rising setting pin Pr1, thereafter measure a voltage value at the first rising setting pin Pr1 and then obtain the resistance value of the first rising control resistor Rtr1 by dividing the measured voltage value by the known current value. In this way, the resistance values ​​of the first falling control resistor Rtf1, the second rising control resistor Rtr2, and the second falling control resistor Rtf2 may also be obtained.

[0389] The setting logic 2310 may provide resistance control information regarding the obtained resistance value to the control logic 2300 .

[0390] The control logic 2300 may control the level of the resistance value (on-resistance when turned on) of each of the first high level switch S1H, the first low level switch S1L, the second high level switch S2H, and the second low level switch S2L using the resistance control information.

[0391] In order to make the falling length CF1 of the first clock signal CLK1 greater than the falling length CF2 of the second clock signal CLK2 , the resistance value of the first low level switch S1L may be set to a value greater than the resistance value of the second low level switch S2L.

[0392] In order to make the rising length CR2 of the second clock signal CLK2 become greater than the rising length CR1 of the first clock signal CLK1 , the resistance value of the second high level switch S2H may be set to a value greater than the resistance value of the first high level switch S1H.

[0393] Reference Fig.23D The level shifter 300 may include a first clock signal output pin Pclk1 and a second clock signal output pin Pclk2, and include a control clock port Pc and a control data port Pd.

[0394] Reference Fig.23D The level shifter 300 may include a first high-level switch S1H between the first clock signal output pin Pclk1 and a node to which a high-level voltage HV is applied, and a first low-level switch S1L between the first clock signal output pin Pclk1 and a node to which a low-level voltage LV is applied.

[0395] The level shifter 300 may include a second high level switch S2H between the second clock signal output pin Pclk2 and a node to which the high level voltage HV is applied, and a second low level switch S2L between the second clock signal output pin Pclk2 and a node to which the low level voltage LV is applied.

[0396] The level shifter 300 may further include control logic 2300 for outputting control signals (CS1H, CS1L, CS2H, and CS2L) to control respective switching operations of the first high level switch S1H, the first low level switch S1L, the second high level switch S2H, and the second low level switch S2L.

[0397] When the first high level switch S1H is turned on, the first clock signal CLK1 may rise to a high level voltage HV, and when the first low level switch S1L is turned on, the first clock signal CLK1 may fall to a low level voltage LV.

[0398] The level shifter 300 may receive a control clock signal SCL from the controller 140 through a control clock port Pc, and receive control data SDA for controlling respective signal waveforms of the first and second clock signals ( CLK1 and CLK2 ) from the controller 140 through a control data port Pd.

[0399] The level shifter 300 may further include a setting logic 2310 for detecting a setting value using a control clock signal SCL and control data SDA, and providing predefined resistance control information corresponding to the detected setting value to the control logic 2300. The setting logic 2310 may be implemented using a register.

[0400] Reference Fig.23D For example, the setting logic 2310 can identify the voltage level of the control data SDA for each falling timing (or rising timing) of the control clock signal SCL, obtain a bit stream (11100111) as a setting value by comparing the identified voltage level with a reference voltage level to observe whether the identified voltage level is greater than or less than the reference voltage level or the degree to which the identified voltage level is greater than or less than the reference voltage level, and derive control information corresponding to the obtained setting value using a correspondence table between a predefined setting value and resistance control information.

[0401] The setting logic 2310 may provide resistance control information regarding the obtained resistance value to the control logic 2300 .

[0402] The control logic 2300 may control the level of the resistance value (on-resistance when turned on) of each of the first high level switch S1H, the first low level switch S1L, the second high level switch S2H, and the second low level switch S2L using the resistance control information.

[0403] In order to make the falling length CF1 of the first clock signal CLK1 greater than the falling length CF2 of the second clock signal CLK2 , the resistance value of the first low level switch S1L may be set to a value greater than the resistance value of the second low level switch S2L.

[0404] In order to make the rising length CR2 of the second clock signal CLK2 become greater than the rising length CR1 of the first clock signal CLK1 , the resistance value of the second high level switch S2H may be set to a value greater than the resistance value of the first high level switch S1H.

[0405] Reference Fig.23E The level shifter 300 may include a first clock signal output pin Pclk1 and a second clock signal output pin Pclk2, and include a control clock port Pc and a control data port Pd.

[0406] Reference Fig.23E , the level shifter 300 may include a first rising control resistor Rtr1, a first falling control resistor Rtf1, a second rising control resistor Rtr2, and a second falling control resistor Rtf2.

[0407] The level shifter 300 may include a first high level switch S1H, a first low level switch S1L, a second high level switch S2H, and a second low level switch S2L.

[0408] The first high level switch S1H and the first rising control resistor Rtr1 may be connected in series between the first clock signal output pin Pclk1 and a node to which the high level voltage HV is applied. The first low level switch S1L and the first falling control resistor Rtf1 may be connected in series between the first clock signal output pin Pclk1 and a node to which the low level voltage LV is applied.

[0409] The second high level switch S2H and the second rising control resistor Rtr2 may be connected in series between the second clock signal output pin Pclk2 and a node to which the high level voltage HV is applied. The second low level switch S2L and the second falling control resistor Rtf2 may be connected in series between the second clock signal output pin Pclk2 and a node to which the low level voltage LV is applied.

[0410] The level shifter 300 may further include control logic 2300 for outputting control signals (CS1H, CS1L, CS2H, and CS2L) to control respective switching operations of the first high level switch S1H, the first low level switch S1L, the second high level switch S2H, and the second low level switch S2L.

[0411] When the first high level switch S1H is turned on, the first clock signal CLK1 may rise to a high level voltage HV, and when the first low level switch S1L is turned on, the first clock signal CLK1 may fall to a low level voltage LV.

[0412] The level shifter 300 may receive a control clock signal SCL from the controller 140 through a control clock port Pc, and receive control data SDA for controlling respective signal waveforms of the first and second clock signals ( CLK1 and CLK2 ) from the controller 140 through a control data port Pd.

[0413] The level shifter 300 may further include a setting logic 2310 for detecting a setting value using a control clock signal SCL and control data SDA, and providing predefined resistance control information corresponding to the detected setting value to the control logic 2300. The setting logic 2310 may be implemented using a register.

[0414] Reference Fig.23D For example, the setting logic 2310 can identify the voltage level of the control data SDA for each falling timing (or rising timing) of the control clock signal SCL, obtain a bit stream (11100111) as a setting value by comparing the identified voltage level with the reference voltage level to observe whether the identified voltage level is greater than or less than the reference voltage level or the degree to which the identified voltage level is greater than or less than the reference voltage level, and derive control information corresponding to the obtained setting value using a correspondence table between predefined setting values ​​and resistance control information.

[0415] The setting logic 2310 may control the respective resistance values ​​of the first rising control resistor Rtr1 , the first falling control resistor Rtf1 , the second rising control resistor Rtr2 , and the second falling control resistor Rtf2 based on the control information using a software tool.

[0416] In order to make the falling length CF1 of the first clock signal CLK1 greater than the falling length CF2 of the second clock signal CLK2 , the resistance value of the first falling control resistor Rtf1 may be set to a value greater than the resistance value of the second falling control resistor Rtf2 .

[0417] In order for the rising length CR2 of the second clock signal CLK2 to become greater than the rising length CR1 of the first clock signal CLK1 , the resistance value of the second rising control resistor Rtr2 may be set to a value greater than the resistance value of the first rising control resistor Rtr1 .

[0418] In addition, the corresponding resistance values ​​of the first rising control resistor Rtr1, the first falling control resistor Rtf1, the second rising control resistor Rtr2 and the second falling control resistor Rtf2 can be the corresponding resistance values ​​(on-resistance when turned on) of the first high level switch S1H, the first low level switch S1L, the second high level switch S2H and the second low level switch S2L, respectively.

[0419] In this case, the setting logic 2300 may control the level of a resistance value (on-resistance when turned on) of each of the first high level switch S1H, the first low level switch S1L, the second high level switch S2H, and the second low level switch S2L.

[0420] In order to make the falling length CF1 of the first clock signal CLK1 greater than the falling length CF2 of the second clock signal CLK2 , the resistance value of the first low level switch S1L may be set to a value greater than the resistance value of the second low level switch S2L.

[0421] In order to make the rising length CR2 of the second clock signal CLK2 become greater than the rising length CR1 of the first clock signal CLK1 , the resistance value of the second high level switch S2H may be set to a value greater than the resistance value of the first high level switch S1H.

[0422] Controls included in Fig.23C , Fig.23D and Fig.23E The method of controlling the level of the resistance value (on-resistance when turned on) of at least one of the first high-level switch S1H, the first low-level switch S1L, the second high-level switch S2H and the second low-level switch (S1H) in the level shifter 300 may include a method of controlling the number of turned-on switches in parallel switches and a method of controlling the voltage of a control signal.

[0423] The method of adjusting the number of on switches in the parallel switch is as follows.

[0424] like FIG. 10A to FIG. 10D , FIG. 11A to FIG. 11D , Fig.12 , Fig.14 and Fig.21 As shown, when a switch is configured, it is necessary to use multiple sub-switches connected in parallel (for example, RCT1-1 to RCT1-N) to adjust the resistance value, and the resistance value of the switch can be controlled by adjusting the number of turned-on switches in the multiple sub-switches connected in parallel.

[0425] The method of controlling the voltage of the control signal is a method of controlling the voltage of the control signal (CS1H, CS1L, CS2H and CS2L) that controls the on and / or off of the switch. Fig.24 Describe in more detail.

[0426] Fig.24 is a diagram illustrating a control signal CS for controlling resistance levels of switches ( S1H, S1L, S2H, and S2L) included in the level shifter 300 in the display device 100 according to aspects of the present disclosure.

[0427] Reference Fig.24, the voltage change of the control signal (the corresponding signal of the control signal (CS1H, CS1L, CS2H and CS2L)) can be controlled to facilitate the control of the control signal included in Fig.23C , Fig.23D and Fig.23E The level of the resistance value (on-resistance when turned on) of at least one switch among the first high-level switch S1H, the first low-level switch S1L, the second high-level switch S2H and the second low-level switch S2L in the level shifter.

[0428] In order to make the falling length CF1 of the clock signal CLK1 longer, the following discussion is made by taking controlling the resistance value of the first low-level switch S1L as an example.

[0429] The control logic 2300 may switch the voltage of the control signal CS1L applied to the first low level switch S1L from the off voltage Voff to the on voltage Von so as to turn on the first low level switch S1L.

[0430] To increase the resistance value of the first low level switch S1L, when switching the voltage of the control signal CS1L from the off voltage Voff to the on voltage Von, the control logic 2300 may switch from the off voltage Voff to the on voltage Von at a relatively reduced speed.

[0431] like Fig.24 As shown, as the voltage of the control signal CS1L applied to the first low-level switch S1L slowly switches from the cut-off voltage Voff to the on-voltage Von (ie, as Fig.24 The slope of the curve becomes gentler), the current through the first low-level switch S1L flows more slowly, which produces an effect equivalent to an increase in the resistance value of the first low-level switch S1L.

[0432] Fig.25 The present invention illustrates the application of the display device 100 according to various aspects of the present disclosure. Fig. 6A and Figure 6B The effect of compensating for the characteristic difference between the selection signals when the Q node is shared in the structure.

[0433] Fig.25 Graphs showing the first gate signal VGATE1 , the second gate signal VGATE2 , and the Q-node voltage before and after applying the characteristic difference compensation control between the gate signals in the case of m=2 are shown.

[0434] Reference Fig.25, before the characteristic difference compensation control between the gate signals is applied, the falling characteristics of the first gate signal and the second gate signal (VGATE1 and VGATE2) are as follows. In this case, the falling length represents the difference between the time when the voltage level reaches 90% of the voltage value before the falling and the time when the voltage level reaches 10% of the voltage value before the falling.

[0435] Reference Fig.25 , before the characteristic difference compensation control between the gate signals is applied, the falling length of the first gate signal VGATE1 is 1.64 μs, and the falling length of the second gate signal VGATE2 is 2.08 μs.

[0436] Reference Fig.25 , before the characteristic difference compensation control between the gate signals is applied, the difference in falling length (falling difference) between the first gate signal VGATE1 and the second gate signal VGATE2 is 0.44 μs (=2.08-1.61).

[0437] Note that, in the effect verification simulation, when the characteristic difference compensation control between the strobe signals was applied, only the fall control for allowing the fall length CF1 of the first clock signal CLK1 to become larger was applied.

[0438] Reference Fig.25 , the falling characteristics of the first gate signal VGATE1 after the characteristic difference compensation control between the gate signals is applied are as follows. Through the falling process of the first gate signal VGATE1, when measured in terms of the falling length, the difference between the time when the voltage level reaches 90% of the voltage value before the falling and the time when the voltage level reaches 10% of the voltage value before the falling is expressed as 1.94μs extended from 1.64μs measured before the characteristic difference compensation control is applied.

[0439] Reference Fig.25 , the falling characteristics of the second gate signal VGATE2 after the characteristic difference compensation control between the gate signals is applied are as follows. Through the falling process of the second gate signal VGATE2, when measured in terms of the falling length, the difference between the time when the voltage level reaches 90% of the voltage value before the falling and the time when the voltage level reaches 10% of the voltage value before the falling is expressed as 2.08μs.

[0440] Reference Fig.25 , after the characteristic difference compensation control between the gate signals is applied, the difference in falling length (falling difference) between the first gate signal VGATE1 and the second gate signal VGATE2 is 0.14 μs (=2.08-1.94). This value is significantly reduced compared to 0.44 μs, which is the difference between the falling lengths before the characteristic difference compensation control between the gate signals is applied.

[0441] Therefore, the difference in falling characteristics between the first gate signal VGATE1 and the second gate signal VGATE2 may be reduced through falling control of the first clock signal CLK1 .

[0442] Fig.26 The present invention illustrates the application of the display device 100 according to various aspects of the present disclosure. Fig.17 The effect of the function of compensating for the characteristic difference between the selection signals in the Q-node sharing structure (m=4).

[0443] Fig.26 Graphs showing first to fourth gate signals ( VGATE1 to VGATE4 ) and the Q-node voltage before and after applying characteristic difference compensation control between gate signals in a case where m=4 are shown.

[0444] Reference Fig.26 , before the characteristic difference compensation control between the gate signals is applied, the falling characteristics of the first to fourth gate signals (VGATE1 to VGATE4) are as follows. In this case, the falling length represents the difference between the time when the voltage level reaches 90% of the voltage value before the falling and the time when the voltage level reaches 10% of the voltage value before the falling.

[0445] Reference Fig.26 , before the characteristic difference compensation control between the gate signals is applied, the falling length of the first gate signal VGATE1 is 1.91 μs. The falling length of the second gate signal VGATE2 is 1.83 μs. The falling length of the third gate signal VGATE3 is 2.17 μs. The falling length of the fourth gate signal VGATE4 is 2.42 μs.

[0446] Reference Fig.26 , before the characteristic difference compensation control between the gate signals is applied, the maximum difference in falling length (maximum falling difference) between the first to fourth gate signals (VGATE1 to VGATE4) is 0.59 μs (=2.42-1.83).

[0447] It should be noted that in the effect verification simulation, when the characteristic difference compensation control between the selection signals is applied, the fall control is applied to allow: the fall length CF1 of the first clock signal CLK1 to become the largest; the fall length CF2 of the second clock signal CLK2 to become the second largest; and the fall length CF3 of the third clock signal CLK3 is smaller than the fall length CF2 of the second clock signal CLK2.

[0448] Reference Fig.26, after applying the characteristic difference compensation control between the gate signals, the falling characteristics of the first to fourth gate signals ( VGATE1 to VGATE4 ) are as follows.

[0449] Reference Fig.26 , after applying the characteristic difference compensation control between the gate signals, the falling length of the first gate signal VGATE1 is 2.06 μs. The falling length of the second gate signal VGATE2 is 1.96 μs. The falling length of the third gate signal VGATE3 is 1.99 μs. The falling length of the fourth gate signal VGATE4 is 2.36 μs.

[0450] Reference Fig.26 , after the characteristic difference compensation control between the gate signals is applied, the maximum difference in the falling lengths (maximum falling difference) between the first gate signal to the fourth gate signal (VGATE1 to VGATE4) is 0.40 μs (=2.36-1.96). This value is significantly reduced compared to 0.59 μs, which is the difference value between the falling lengths before the characteristic difference compensation control between the gate signals is applied.

[0451] Therefore, the difference in falling characteristics between the first to fourth gate signals ( VGATE1 to VGATE4 ) may be reduced through falling control of the first to fourth clock signals ( CLK1 to CLK4 ).

[0452] According to the embodiments described herein, the level shifter 300 , the gate driving circuit 130 , and the display device 100 capable of reducing a characteristic difference between gate signals to thereby improve image quality may be provided.

[0453] According to the embodiments described herein, the level shifter 300 capable of variously controlling rising and falling characteristics of a clock signal, and the gate driving circuit 130 and the display device 100 using the level shifter 300 may be provided.

[0454] According to the embodiments described herein, a level shifter 300 , a gate driving circuit 130 , and a display device 100 capable of reducing the size of a region in which a gate driving circuit is provided and reducing a characteristic difference between gate signals even when the gate driving circuit is embedded in a display panel as an embedded type may be provided.

[0455] The above description is to enable those skilled in the art to implement and use the technical ideas of the present invention, and is provided in the context of specific applications and their requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. The above description and accompanying drawings provide examples of the technical ideas of the present invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of the present invention. Therefore, the scope of the present invention is not limited to the embodiments shown, but is in accordance with the widest scope consistent with the claims. The scope of protection of the present invention should be interpreted based on the attached claims, and all technical ideas within their equivalent scope should be understood to be included in the scope of protection of the present invention.

[0456] CROSS-REFERENCE TO RELATED APPLICATIONS

[0457] This application claims the benefit of priority of Korean Patent Application No. 10-2020-0183863 filed in the Korean Intellectual Property Office on December 24, 2020, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display device, comprising: substrate; m gate lines, the m gate lines being arranged on the substrate, wherein m is a natural number of 2 or more; and a gate drive circuit, the gate drive circuit being disposed on the substrate or connected to the substrate and being capable of providing m gate signals to the m gate lines based on m input clock signals, The gate drive circuit includes m output buffer circuits capable of outputting the m gate signals based on the m clock signals, and a control circuit capable of controlling the m output buffer circuits. wherein each of the m output buffer circuits comprises a pull-up transistor and a pull-down transistor, and a point at which the pull-up transistor and the pull-down transistor are connected is electrically connected to a corresponding gate line among the m gate lines, wherein all gate nodes of the respective pull-up transistors included in the m output buffer circuits are electrically connected together, and all gate nodes of the respective pull-down transistors included in the m output buffer circuits are electrically connected together, wherein the signal waveform of at least one of the m clock signals is different from the signal waveform of one or more other clock signals of the m clock signals, and The signal waveform includes a falling length and a rising length.

2. The display device according to claim 1, wherein: The m strobe signals include a first strobe signal having a conduction level voltage duration at the earliest timing and an mth strobe signal having a conduction level voltage duration at the latest timing, The m clock signals include a first clock signal corresponding to the first selection signal and an mth clock signal corresponding to the mth selection signal, and The falling length of the first clock signal is greater than the falling length of the mth clock signal.

3. The display device according to claim 2, wherein: A difference between a falling length of the first strobe signal and a falling length of the m-th strobe signal is smaller than a difference between a falling length of the first clock signal and a falling length of the m-th clock signal.

4. The display device according to claim 1, wherein: The m strobe signals include a first strobe signal having a conduction level voltage duration at the earliest timing and an mth strobe signal having a conduction level voltage duration at the latest timing, The m clock signals include a first clock signal corresponding to the first selection signal and an mth clock signal corresponding to the mth selection signal, and The rising length of the mth clock signal is greater than the rising length of the first clock signal.

5. The display device according to claim 4, wherein: A difference between a rising length of the first selection signal and a rising length of the m-th selection signal is smaller than a difference between a rising length of the first clock signal and a rising length of the m-th clock signal.

6. The display device according to claim 1, wherein: When m is 2, the m clock signals include a first clock signal and a second clock signal, and the m selection signals include a first selection signal and a second selection signal, The gate drive circuit is capable of outputting the first gate signal to the first gate line according to the first clock signal, and outputting the second gate signal to the second gate line according to the second clock signal. wherein the on-level voltage duration of the first selection signal overlaps with the on-level voltage duration of the second selection signal, and the on-level voltage duration of the first selection signal is located at an earlier timing than the on-level voltage duration of the second selection signal, and The falling length of the first clock signal is greater than the falling length of the second clock signal, and / or the rising length of the second clock signal is greater than the rising length of the first clock signal.

7. The display device according to claim 6, wherein: The gate drive circuit comprises: a first output buffer circuit capable of outputting the first strobe signal to the first strobe line through a first strobe output terminal in response to the first clock signal input to a first clock input terminal; a second output buffer circuit capable of outputting the second gate signal to the second gate line through a second gate output terminal in response to the second clock signal input to a second clock input terminal; and a control circuit capable of controlling the first output buffer circuit and the second output buffer circuit, wherein the first output buffer circuit comprises a first pull-up transistor and a first pull-down transistor, the first pull-up transistor being electrically connected between the first clock input terminal and the first gate output terminal and being controlled by a voltage at a Q node, the first pull-down transistor being electrically connected between the first gate output terminal and a basic input terminal to which a basic voltage is input and being controlled by a voltage at a QB node, and The second output buffer circuit includes a second pull-up transistor and a second pull-down transistor, the second pull-up transistor is electrically connected between the second clock input terminal and the second enable output terminal and is controlled by the voltage at the Q node, and the second pull-down transistor is electrically connected between the second enable output terminal and the base input terminal and is controlled by the voltage at the QB node.

8. The display device according to claim 7, wherein: The first output buffer circuit further includes a first additional pull-down transistor electrically connected between the first gate output terminal and the base input terminal and controlled by a voltage at another QB node different from the QB node, wherein the second output buffer circuit further comprises a second additional pull-down transistor electrically connected between the second selection output terminal and the base input terminal and controlled by the voltage at the other QB node, and The first pull-down transistor and the first additional pull-down transistor are operated alternately, and the second pull-down transistor and the second additional pull-down transistor are operated alternately.

9. The display device according to claim 6, further comprising a level shifter for outputting the first clock signal and the second clock signal to the gate driving circuit, in, The level shifter comprises: a first clock output buffer configured to generate the first clock signal and output the generated first clock signal to a first clock output terminal; and a second clock output buffer configured to generate the second clock signal and output the generated second clock signal to a second clock output terminal, wherein the first clock output buffer comprises a first rising control circuit and a first falling control circuit, the first rising control circuit comprises N first rising control transistors electrically connected between a high level voltage node and the first clock output terminal, wherein N is a natural number of 2 or greater, and the first falling control circuit comprises N first falling control transistors electrically connected between a low level voltage node and the first clock output terminal, wherein the second clock output buffer comprises a second rising control circuit and a second falling control circuit, the second rising control circuit comprises N second rising control transistors electrically connected between the high level voltage node and the second clock output terminal, wherein N is a natural number of 2 or greater, and the second falling control circuit comprises N second falling control transistors electrically connected between the low level voltage node and the second clock output terminal, and Wherein, respective on and off of N control transistors included in at least one of the first rising control circuit, the first falling control circuit, the second rising control circuit, and the second falling control circuit are independently controlled.

10. The display device according to claim 9, wherein: The falling length of the first clock signal is greater than the falling length of the second clock signal, and The number of the turned-on falling control transistors among the N first falling control transistors is less than the number of the turned-on falling control transistors among the N second falling control transistors.

11. The display device according to claim 9, wherein: The rising length of the second clock signal is greater than the rising length of the first clock signal, and Among them, the number of the turned-on rising control transistors among the N second rising control transistors is less than the number of the turned-on rising control transistors among the N first rising control transistors.

12. The display device according to claim 1, further comprising a level shifter and a printed circuit board, wherein the level shifter is used to provide the m clock signals to the gate drive circuit, and the level shifter is connected to or mounted on the printed circuit board. in, The m clock signals include a first clock signal and a second clock signal, The level shifter includes a first signal source pin, a first signal sink pin, a second signal source pin, and a second signal sink pin. The printed circuit board includes a first rising control resistor, a first falling control resistor, a second rising control resistor, a second falling control resistor, a first output node and a second output node, wherein the first clock signal is output from the first output node to the gate drive circuit, and the second clock signal is output from the second output node to the gate drive circuit. wherein the first rising control resistor is electrically connected between the first source pin and the first output node, and the first falling control resistor is electrically connected between the first sink pin and the first output node, and The second rising control resistor is electrically connected between the second source pin and the second output node, and the second falling control resistor is electrically connected between the second sink pin and the second output node.

13. The display device according to claim 1, further comprising a level shifter and a printed circuit board, wherein the level shifter is used to provide the m clock signals to the gate drive circuit, and the level shifter is connected to or mounted on the printed circuit board. in, The m clock signals include a first clock signal and a second clock signal, Wherein, the level shifter comprises a first clock signal output pin and a second clock signal output pin, wherein the printed circuit board includes a first rising control resistor, a first falling control resistor, a second rising control resistor, a second falling control resistor, a first output node, a second output node, a first rising control diode and a first falling control diode, and a second rising control diode and a second falling control diode, wherein the first clock signal is output from the first output node to the gate drive circuit, the second clock signal is output from the second output node to the gate drive circuit, the first rising control diode and the first falling control diode are used to allow current to flow in opposite directions to each other, and the second rising control diode and the second falling control diode are used to allow current to flow in opposite directions to each other, wherein the first rising control diode and the first rising control resistor are connected in series between the first clock signal output pin and the first output node, and the first falling control diode and the first falling control resistor are connected in series between the first clock signal output pin and the first output node, and Wherein, the second rising control diode and the second rising control resistor are connected in series between the second clock signal output pin and the second output node, and the second falling control diode and the second falling control resistor are connected in series between the second clock signal output pin and the second output node.

14. The display device according to claim 1, further comprising a level shifter and a printed circuit board, wherein the level shifter is used to provide the m clock signals to the gate drive circuit, and the level shifter is connected to or mounted on the printed circuit board. in, The m clock signals include a first clock signal and a second clock signal, The level shifter includes a first clock signal output pin, a second clock signal output pin, a first rising setting pin, a first falling setting pin, a second rising setting pin, and a second falling setting pin. Wherein, the printed circuit board includes a first rising control resistor, a first falling control resistor, a second rising control resistor and a second falling control resistor, wherein the first rising control resistor is electrically connected between the first rising setting pin and ground, and the first falling control resistor is electrically connected between the first falling setting pin and the ground, and Wherein, the second rising control resistor is electrically connected between the second rising setting pin and the ground, and the second falling control resistor is electrically connected between the second falling setting pin and the ground.

15. The display device according to claim 1, further comprising a level shifter for providing the m clock signals to the gate drive circuit and a controller for controlling the gate drive circuit, in, The m clock signals include a first clock signal and a second clock signal, The level shifter comprises a first clock signal output pin, a second clock signal output pin, a control clock port and a control data port, and The level shifter is capable of receiving a control clock signal from the controller through the control clock port, and receiving control data for controlling a signal waveform of each of the first clock signal and the second clock signal from the controller through the control data port.

16. The display device according to claim 1, further comprising a level shifter for providing the m clock signals to the gate driving circuit, in, The m clock signals include a first clock signal and a second clock signal, The level shifter includes a first clock signal output pin, a second clock signal output pin, a first high-level switch between the first clock signal output pin and a node to which a high-level voltage is applied, a first low-level switch between the first clock signal output pin and a node to which a low-level voltage is applied, a second high-level switch between the second clock signal output pin and a node to which the high-level voltage is applied, and a second low-level switch between the second clock signal output pin and a node to which the low-level voltage is applied, and The level shifter controls the level of on-resistance of each of the first high-level switch, the first low-level switch, the second high-level switch, and the second low-level switch to change the waveforms of the first clock signal and the second clock signal.

17. The display device according to claim 16, wherein: In order to make the falling length of the first clock signal become longer than the falling length of the second clock signal, the on-resistance of the first low-level switch is set to a value larger than the on-resistance of the second low-level switch, and In order to make the rising length of the second clock signal become longer than the rising length of the first clock signal, the on-resistance of the second high-level switch is set to a value larger than the on-resistance of the first high-level switch.

18. A gate drive circuit, the gate drive circuit comprising: m output buffer circuits, the m output buffer circuits being capable of outputting m strobe signals based on m clock signals; as well as a control circuit capable of controlling the m output buffer circuits, wherein each of the m output buffer circuits comprises a pull-up transistor and a pull-down transistor, and a point at which the pull-up transistor and the pull-down transistor are connected is electrically connected to a corresponding gate line among the m gate lines, all gate nodes of the respective pull-up transistors included in the m output buffer circuits are electrically connected together, and all gate nodes of the respective pull-down transistors included in the m output buffer circuits are electrically connected together, wherein the signal waveform of at least one clock signal among the m clock signals is different from the signal waveform of one or more other clock signals, and The signal waveform includes a falling length and a rising length.

19. The gate drive circuit according to claim 18, wherein: The m strobe signals include a first strobe signal having a conduction level voltage duration at the earliest timing and an mth strobe signal having a conduction level voltage duration at the latest timing, The m clock signals include a first clock signal corresponding to the first selection signal and an mth clock signal corresponding to the mth selection signal, and The falling length of the first clock signal is greater than the falling length of the mth clock signal.

20. The gate driving circuit according to claim 19, wherein: A difference between a falling length of the first strobe signal and a falling length of the m-th strobe signal is smaller than a difference between a falling length of the first clock signal and a falling length of the m-th clock signal.

21. A level shifter, the level shifter comprising: m clock output buffers, the m clock output buffers are used to output m clock signals, wherein m is a natural number of 2 or greater, The m clock signals include the first clock signal to the mth clock signal. Among the first clock signal to the mth clock signal, the high level voltage duration of the first clock signal and the high level voltage duration of the second clock signal partially overlap, wherein the signal waveform of the first clock signal among the m clock signals is different from the signal waveform of one or more other clock signals among the m clock signals, and The signal waveform includes a falling length and a rising length.

22. The level shifter according to claim 21, wherein: A falling length of the first clock signal among the m clock signals is greater than a falling length of the mth clock signal.

23. A level shifter for outputting a clock signal including a first clock signal and a second clock signal, the level shifter comprising: a first clock signal output pin, a second clock signal output pin, a first high-level switch between the first clock signal output pin and a node to which a high-level voltage is applied, a first low-level switch between the first clock signal output pin and a node to which a low-level voltage is applied, a second high-level switch between the second clock signal output pin and a node to which the high-level voltage is applied, and a second low-level switch between the second clock signal output pin and a node to which the low-level voltage is applied, wherein the level shifter controls the level of on-resistance of each of the first high-level switch, the first low-level switch, the second high-level switch, and the second low-level switch to change the waveforms of the first clock signal and the second clock signal so that the signal waveform of the first clock signal is different from the signal waveform of the second clock signal, and The signal waveform includes a falling length and a rising length.

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