Light emitting display device and multi-screen light emitting display device including the same

Abstract

A light emitting display apparatus includes a display area configured to include a plurality of pixels disposed in first through mth horizontal lines parallel to a first direction over a first substrate; a plurality of gate lines disposed at the first through mth horizontal lines of the display area parallel to the first direction; a plurality of gate control lines disposed between the plurality of pixels along a second direction crossing the first direction; and a gate driver circuit including first through mth stage circuit units disposed in the display area and selectively coupled to the plurality of gate lines and the plurality of gate control lines, wherein the first through mth stage circuit units each include a plurality of branch circuits disposed apart along the first direction between the plurality of pixels and selectively coupled to the plurality of gate control lines, and a branch network selectively coupled to the plurality of branch circuits, and wherein the branch network of the first stage circuit unit and the branch network of the mth stage circuit unit are disposed between two adjacent pixels along the second direction.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0189778, filed on December 31, 2020, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a light-emitting display device and a multi-screen display device including the light-emitting display device. Background Technology

[0004] Emitting light display devices are installed in household appliances or electronic devices, such as televisions (TVs), monitors, laptops, smartphones, tablet PCs, electronic tablets, wearable devices, smartwatches, portable information devices, navigation devices, and vehicle control displays, as screens for displaying images.

[0005] The light-emitting display device includes a light-emitting display panel, which includes a plurality of pixels, each pixel including a thin-film transistor (TFT) connected to a data line and a gate line, a data driving circuit that provides a data voltage to the data line, and a gate driving circuit that provides a gate signal to the gate line.

[0006] Recently, in the process of manufacturing each pixel of a TFT, the gate driving circuit is embedded in the non-display area of ​​the display panel. Light-emitting display devices with a gate in panel (GIP) structure are being used to simplify the configuration of circuit components, reduce manufacturing costs, and reduce bezel width.

[0007] The gate drive circuit with a GIP structure includes multiple stages for providing gate signals to multiple gate lines. These stages operate independently based on signals provided through multiple gate shift clock lines and gate start signal lines disposed in the light-emitting display panel.

[0008] A light-emitting display panel including a gate drive circuit with a GIP structure includes a bezel area due to the gate drive circuit being located in a non-display area. Related light-emitting display devices require a bezel or a mechanism for covering the bezel area of ​​the light-emitting display panel.

[0009] Recently, multi-screen display devices that achieve large screens by arranging display devices in a grid pattern have been commercialized.

[0010] However, in multi-screen display devices of related technologies, boundary portions, such as seams, are formed between adjacent light-emitting display devices due to the bezel area or the bezel of each of the multiple light-emitting display devices. When an image is displayed on the entire screen of a multi-screen light-emitting display device, the boundary portions may cause the image to appear broken (or discontinuous), thus potentially reducing the viewer's immersion in the image. Summary of the Invention

[0011] Therefore, this disclosure aims to provide a light-emitting display device and a multi-screen display device including the light-emitting display device, which substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0012] One aspect of this disclosure is to provide a light-emitting display device with zero bezel width and a multi-screen display device including the light-emitting display device.

[0013] Another aspect of this disclosure aims to provide a light-emitting display device with zero bezel width and to prevent operational defects in the gate drive circuit, as well as a multi-screen display device including the display device.

[0014] Another aspect of this disclosure aims to provide a light-emitting display device that improves the brightness uniformity of the display area, and a multi-screen display device including the display device.

[0015] Other advantages and features of this disclosure will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art upon examination of the following, or may be learned from practice of this disclosure.

[0016] The objectives and other advantages of this disclosure can be realized and obtained through the written description and its claims, as well as the structures particularly pointed out in the drawings.

[0017] To achieve these and other advantages and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a light-emitting display device includes: a display area configured to include a plurality of pixels disposed above a first substrate in a first to m-th horizontal line parallel to a first direction; a plurality of gate lines disposed in the first to m-th horizontal line of the display area parallel to the first direction; a plurality of gate control lines disposed between the plurality of pixels along a second direction intersecting the first direction; and a gate driving circuit including first to m-th level circuit components disposed in the display area and selectively coupled to the plurality of gate lines and the plurality of gate control lines, wherein each of the first to m-th level circuit components includes: a plurality of branch circuits separately disposed along the first direction between the plurality of pixels and selectively coupled to the plurality of gate control lines, and a branch network selectively coupled to the plurality of branch circuits; and the branch network of the first-level circuit component and the branch network of the m-th level circuit component are each disposed between two adjacent pixels along the second direction.

[0018] In another aspect of this disclosure, a multi-screen display device includes: a plurality of display devices disposed along at least one of a first direction and a second direction intersecting the first direction, each of the plurality of display devices including a light-emitting display device, the light-emitting display device including: a display area configured to include a plurality of pixels disposed above a first substrate along a first to m-th horizontal line parallel to the first direction; a plurality of gate lines disposed at the first to m-th horizontal line of the display area parallel to the first direction; a plurality of gate control lines disposed between the plurality of pixels along the second direction; and a gate driving circuit including a first to m-th level circuit components disposed in the display area and selectively coupled to the plurality of gate lines and the plurality of gate control lines, wherein each of the first to m-th level circuit components includes: a plurality of branch circuits disposed separately between the plurality of pixels along the first direction and selectively coupled to the plurality of gate control lines, and a branch network selectively coupled to the plurality of branch circuits; and the branch network of the first level circuit component and the branch network of the m-th level circuit component are each disposed between two adjacent pixels along the second direction.

[0019] Some embodiments of this disclosure may provide a light-emitting display device and a multi-screen display device including the same, having a zero-bezel width.

[0020] Some embodiments of this disclosure provide a light-emitting display device and a multi-screen display device including the same, having a zero bezel width, and wherein operational defects of the gate drive circuitry are prevented.

[0021] Some embodiments of this disclosure provide a light-emitting display device and a multi-screen display device including the same, wherein the brightness uniformity of the display area is improved.

[0022] Some embodiments of this disclosure provide a light-emitting display device and a multi-screen display device including the same, which displays an image without a sense of discontinuity when displaying an image across the entire screen. Attached Figure Description

[0023] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0024] Figure 1 This is a plan view illustrating a light-emitting display device according to an embodiment of the present disclosure.

[0025] Figure 2A It is a diagram. Figure 1 The illustration shows a pixel according to an embodiment of the present disclosure.

[0026] Figure 2B It is a diagram. Figure 1 The illustration shows a pixel according to another embodiment of the present disclosure.

[0027] Figure 2C It is a diagram. Figure 1 The illustration shows a pixel according to another embodiment of the present disclosure.

[0028] Figure 3 yes Figure 1 An enlarged view of area "A" shown.

[0029] Figure 4 It is a diagram. Figure 1 and Figure 3 The equivalent circuit diagram of one pixel is shown.

[0030] Figure 5 This is an illustration of the rear surface of a light-emitting display device according to an embodiment of the present disclosure.

[0031] Figure 6 It is a diagram. Figure 5 The diagram shows the second pad, third pad, and connector portion of the vegan solder pad.

[0032] Figure 7 yes Figure 6 A magnified view of region "B" in the image.

[0033] Figure 8 This is a diagram illustrating the arrangement of the gate drive circuit and the common electrode connection portion according to an embodiment of the present disclosure.

[0034] Figure 9 It is a diagram. Figure 8 The circuit diagram of the i-th level circuit component is shown.

[0035] Figure 10 It is a diagram. Figure 9 The electrical connections of the node control circuit, the first inverter circuit, the second inverter circuit, and the first sensing control circuit shown are illustrated.

[0036] Figure 11 It is a diagram. Figure 9 The noise reduction circuit, output buffer circuit, and second sensing circuit shown are each independent circuit diagrams.

[0037] Figure 12 It is along Figure 5 The cross-sectional view of the line I-I' shown.

[0038] Figure 13 yes Figure 12 An enlarged view of area "C" shown.

[0039] Figure 14 It is along Figure 5 The cross-sectional view of line II-II' shown.

[0040] Figure 15 yes Figure 14 A magnified view of area "D" shown.

[0041] Figure 16 It is along Figure 3 The cross-sectional view of line III-III' shown.

[0042] Figure 17 This is an illustration of a second substrate of a light-emitting display device according to another embodiment of the present disclosure.

[0043] Figure 18 along Figure 17 The cross-sectional view of the straight line IV-IV' shown.

[0044] Figure 19 This is an illustration of a multi-screen display device according to an embodiment of the present disclosure.

[0045] Figure 20 It is along Figure 19 The cross-sectional view of the straight line V-V' shown in the figure. Detailed Implementation

[0046] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of known functions or configurations relating to this document will be omitted where it is determined that such detailed descriptions unnecessarily obscure the spirit of the inventive concept. The described process steps and / or order of operations are exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as is known in the art, except for steps and / or operations that must occur in a particular order. Similar reference numerals designate similar elements throughout the text. The names of the various elements used in the following explanation have been chosen solely for convenience of writing this specification, and they may therefore differ from those used in actual products.

[0047] The advantages and features of this disclosure, as well as its implementation methods, will become clear from the following embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of this disclosure to those skilled in the art.

[0048] The shapes, dimensions, scales, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore, embodiments of this disclosure are not limited to the details illustrated. Similar reference numerals throughout the text refer to similar elements. In the following description, detailed descriptions of related known functions or configurations will be omitted where it is determined that such descriptions unnecessarily obscure the focus of this disclosure. Where terms such as “comprising,” “having,” and “including” are used as described in this specification, another component may be added unless “only” is used. Singular terms may include plural forms unless otherwise stated.

[0049] When interpreting a component, even without an explicit description, the component is interpreted as including a tolerance range.

[0050] In describing positional relationships, for example, when the positional relationship between two components is described as "above", "over", "below", or "near", one or more other components may be positioned between the two components, unless more restrictive terms such as "only" or "directly" are used.

[0051] In describing temporal relationships, such as when time sequence is described as, for example, “after,” “following,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “only,” “immediately,” or “directly” are used.

[0052] It should be understood that although the terms “first,” “second,” etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from others. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0053] In describing the elements of this disclosure, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are used only to distinguish the corresponding elements from other elements, and the corresponding elements are not limited by these terms in their nature, order, or priority. It is to be understood that when an element or layer is referred to as being "on" or "coupled" to another element or layer, it may be directly on or directly coupled to that other element or layer, or there may be intermediate elements or layers. Furthermore, it should be understood that when an element is disposed on or below another element, this may indicate a situation where the elements are disposed in direct contact with each other, but it may also indicate a situation where the elements are disposed without direct contact with each other.

[0054] The term "at least one" should be understood to include any and all combinations of one or more of the related listed elements. For example, "at least one of the first element, the second element, and the third element" means a combination of all elements derived from two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0055] As used herein, the term "surround" includes at least partially surrounding and completely surrounding one or more of the relevant elements. Similarly, as used herein, the term "cover" includes at least partially covering and completely covering one or more of the relevant elements.

[0056] Features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may interoperate and be technically driven in various ways, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0057] In the following, embodiments of this content will be described in detail with reference to the accompanying drawings. In the elements for which reference numerals are added in the various drawings, similar reference numerals may refer to similar elements even if the same elements are shown in other drawings. Furthermore, for ease of description, the scale of each element shown in the accompanying drawings differs from the actual scale, and therefore, is not limited to the scale shown in the drawings.

[0058] Figure 1This is a plan view illustrating a light-emitting display device according to an embodiment of the present disclosure.

[0059] Reference Figure 1 According to the embodiments of the present disclosure, the light-emitting display device (or light-emitting display panel) 10 may include a first substrate 100, the first substrate 100 including a display area AA, a plurality of pixels P in the display area AA of the first substrate 100, a first pad portion 110 and a gate driving circuit 150 in the display area AA.

[0060] The first substrate 100 may be referred to as a first substrate, a base substrate, or a pixel array substrate. For example, the first substrate 100 may be a glass substrate, or it may be a bendable or flexible thin glass substrate or a plastic substrate.

[0061] The display area AA of the first substrate 100 can be an area for displaying an image and can be referred to as an active portion, active region, display portion, or display screen. The size of the display area AA can be the same as or substantially the same as that of the first substrate 100 (or the light-emitting display device or display panel). For example, the size of the display area AA can be the same as the total size of the first surface of the first substrate 100. Therefore, the display area AA can be implemented (or disposed) on the entire front surface of the first substrate. Therefore, the first substrate 100 may not include an opaque non-display area disposed along the peripheral portion (or edge portion) of the first surface to surround all display areas AA. Therefore, the entire front surface of the light-emitting display device can realize the display area AA.

[0062] The end (or outermost portion) of the display area AA may overlap or substantially align with the outer surface OS of the first substrate 100. For example, relative to the thickness direction Z of the light-emitting display device, the side surface (or end line) of the display area AA may be substantially aligned with a vertical extension line extending perpendicularly from the outer surface OS of the first substrate 100. The side surface of the display area AA may not be subject to a separate mechanical device and may only be adjacent to ambient air. For example, all side surfaces of the display area AA may be provided as structures that directly contact the air without being surrounded by a separate mechanism. Therefore, the outer surface OS of the first substrate 100 corresponding to the end of the display area AA may be surrounded only by air (or adjacent ambient air), and thus, the light-emitting display device according to embodiments of the present disclosure may have an air-frame structure or a non-frame structure (or a zero-frame structure), wherein the end (or side surface) of the display area AA is surrounded by air rather than an opaque non-display area.

[0063] Multiple pixels P can be arranged (or disposed) in the display area AA of the first substrate 100 to have a first interval D1 along the first direction X and the second direction Y. For example, the first direction X can be transverse (or arranged) and intersect or cross the second direction Y. The first direction X can be the width direction, horizontal direction or first length direction (e.g., the length direction of the width direction) of the first substrate 100 or the light-emitting display device.

[0064] Each of the plurality of pixels P can be implemented on a plurality of pixel regions defined on a display area AA of the first substrate 100. Each of the plurality of pixels P can have a first length L1 and a second length L2 parallel to a first direction X and a second length L2 parallel to a second direction Y. The first length L1 can be the same as the second length L2 or the first interval D1. The first length L1 and the second length L2 can be the same as the first interval D1. Therefore, the plurality of pixels (or pixel regions) P can all have the same size.

[0065] Within the tolerance range of the manufacturing process, two pixels P that are adjacent to each other along the first direction X and the second direction Y can have the same first interval D1. The first interval D1 can be the distance (or pixel pitch) between two adjacent pixels P. For example, the first length L1 or the second length L2 of pixel P can be called the pixel pitch. For example, the first interval D1 can be the distance (or length) between the center portions of two adjacent pixels P. For example, the first interval (or pixel pitch) D1 can be the shortest distance (or shortest length) between the center portions of two adjacent pixels P.

[0066] Each of the plurality of pixels P according to embodiments of the present disclosure may include a circuit layer comprising a pixel circuit implemented in a pixel region of the first substrate 100, and a light-emitting device layer disposed on and coupled to the circuit layer. The pixel circuit outputs a data current corresponding to the data signal in response to a data signal and a scan signal provided from a pixel driving line disposed in the pixel region. The light-emitting device layer may include a light-emitting layer that emits light through the data current provided from the pixel circuit. The pixel driving line, the pixel circuit, and the light-emitting device layer will be described below.

[0067] Multiple pixels P can be divided (or classified) into outermost pixels Po and inner pixels (or inner pixels) Pi.

[0068] The outermost pixel Po can be the pixel closest to the outer surface OS of the first substrate 100 among multiple pixels P.

[0069] The second interval D2 between the center portion of each outermost pixel Po and the outer surface OS of the first substrate 100 can be half or less than the first interval D1. For example, the second interval D2 can be the distance (or length) between the center portion of the outermost pixel Po and the outer surface OS of the first substrate 100. For example, the second interval D2 can be the shortest distance (or shortest length) between the center portion of the outermost pixel Po and the outer surface OS of the first substrate 100.

[0070] When the second pitch D2 is greater than half of the first pitch D1, the size of the first substrate 100 can be larger than the display area AA by the difference between half of the first pitch D1 and the second pitch D2. Therefore, the area between the end of the outermost pixel Po and the outer surface OS of the first substrate 100 can be configured as a non-display area surrounding all display areas AA. For example, when the second pitch D2 is greater than half of the first pitch D1, the first substrate 100 may have to include a border area based on the non-display area surrounding all display areas AA. On the other hand, when the second pitch D2 is equal to or less than half of the first pitch D1, the end of each outermost pixel Po can be aligned (or set) with the outer surface OS of the first substrate 100, or the end can be aligned (or set) with the outer surface OS of the first substrate 100. A portion of the display area AA can be aligned (or set) with the outer surface OS of the first substrate 100. Therefore, the display area AA can be implemented (or set) on the entire front surface of the first substrate 100.

[0071] An inner pixel Pi can be a pixel other than the outermost pixel Po among a plurality of pixels P, or it can be a pixel surrounded by the outermost pixel Po among a plurality of pixels P. An inner pixel (or second pixel) Pi can be implemented with a different configuration or structure than the outermost pixel (or first pixel) Po.

[0072] The first pad portion 110 may be a first pad portion or a front pad portion. The first pad portion 110 may include a plurality of first pads to receive data signals, gate control signals, pixel driving power supplies, reference voltages, and pixel common voltages from the driving circuit portion.

[0073] The first pad portion 110 can be included within the outermost pixel Po located at a first peripheral portion of the first surface of the first substrate 100, parallel to the first direction X. That is, the first substrate 100 may include at least one of a plurality of first pads within the outermost pixel Po located at the first peripheral portion of the first surface of the first substrate 100. Therefore, the plurality of first pads can be disposed or included within the display area AA, and thus, a non-display area (or border area) based on the first pad portion 110 may not be formed or may not be present on the first substrate 100. Therefore, the outermost pixel (or first pixel) Po may include the first pad portion 110, and thus can be implemented with a different configuration or structure than the pixel (or second pixel) Pi located within the first pad portion 110.

[0074] For example, when the first pad portion 110 is not disposed within the outermost pixel Po and is disposed between the outermost pixel Po and the outer surface OS of the first substrate 100, the first substrate 100 may include a non-display area (or a non-display portion) corresponding to the area where the first pad portion 110 is disposed. Due to the non-display area, the second interval D2 between the outermost pixel Po and the outer surface OS of the first substrate 100 may be greater than half of the first interval D1. Therefore, not all of the first substrate 100 may be implemented as a display area AA, and a separate border (or separate structure) may be needed to cover the non-display area. On the other hand, according to embodiments of this disclosure, the first pad portion 110 may be disposed between the outermost pixel Po and the outer surface OS of the first substrate 100 to be included within the outermost pixel Po. Therefore, a display area (or border area) not based on the first pad portion 110 may not be formed or may not be between the outermost pixel Po and the outer surface OS of the first substrate 100.

[0075] The first pad portion 110 according to an embodiment of the present disclosure may include a plurality of pixel driving power pads, a plurality of data pads, a plurality of reference voltage pads and a plurality of pixel common voltage pads, but the embodiments disclosed herein are not limited thereto.

[0076] A gate driving circuit 150 may be disposed in the display area AA to provide a scan signal (or gate signal) to a pixel P disposed on the first substrate 100. The gate driving circuit 150 may simultaneously provide a scan signal to the disposed pixel P on a horizontal line parallel to the first direction X. For example, the gate driving circuit 150 may provide at least one scan signal to a pixel P disposed on a horizontal line via at least one gate line GL.

[0077] The gate driving circuit 150 according to an embodiment of the present disclosure can be implemented using a shift register that includes multiple stages of circuit components. That is, the light-emitting display device according to an embodiment of the present disclosure may include a shift register disposed in the display area AA of the first substrate 100 to provide a scan signal to the pixel P.

[0078] Figure 2A It is a diagram. Figure 1 The illustration shows a pixel according to an embodiment of the present disclosure. Figure 2B It is a diagram. Figure 1 The illustration shown is of a pixel according to another embodiment of the present disclosure. Figure 2C It is a diagram. Figure 1 The illustration shows a pixel according to another embodiment of the present disclosure.

[0079] Reference Figure 1 and Figure 2A According to embodiments of the present disclosure, a pixel (or unit pixel) P may include first to fourth sub-pixels SP1 to SP4.

[0080] The first sub-pixel SP1 can be set in the first sub-pixel region of pixel region PA, the second sub-pixel SP2 can be set in the second sub-pixel region of pixel region PA, the third sub-pixel SP3 can be set in the third sub-pixel region of pixel region PA, and the fourth sub-pixel SP4 can be set in the fourth sub-pixel region of pixel region PA.

[0081] According to embodiments of the present disclosure, the first to fourth sub-pixels SP1 to SP4 can be arranged in a 2×2 configuration or a quadrilateral structure. Each of the first to fourth sub-pixels SP1 to SP4 may include multiple emission regions EA1 to EA4 and multiple circuit regions CA1 to CA4. For example, emission regions EA1 to EA4 may be referred to as aperture regions, aperture portions, or emission portions.

[0082] The emission regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 can have a uniform quadrilateral structure to form a square shape with the same size (or the same area). According to embodiments of this disclosure, each of the emission regions EA1 to EA4 with a uniform quadrilateral structure can be positioned near the center portion CP of the pixel P within the corresponding sub-pixel region to have a smaller size than each of them. The four equally divided regions of pixel P can also be concentrated at the center portion CP of pixel P. According to another embodiment of this disclosure, each of the emission regions EA1 to EA4 with a uniform quadrilateral structure can be located at the center portion CP of the corresponding sub-pixel region, thus having a smaller size than each of the four equally divided regions of pixel P.

[0083] Reference Figure 1 and Figure 2B According to another embodiment of the present disclosure, each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform quadrilateral structure with different sizes. For example, each of the emission regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform quadrilateral structure with different sizes.

[0084] The size of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quadrilateral structure can be set based on resolution, emission efficiency, or image quality. According to another embodiment of this disclosure, when the emission regions EA1 to EA4 have a non-uniform quadrilateral structure, among the emission regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the emission region EA4 of the fourth sub-pixel SP4 and the emission region EA3 of the third sub-pixel SP3 can have the smallest size, and the emission region EA3 of the third sub-pixel SP3 can have the largest size. For example, each of the emission regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quadrilateral structure can be arranged to be concentrated around (or near) the central portion CP of pixel P.

[0085] Reference Figure 1 and Figure 2C According to another embodiment of this disclosure, each of the first to fourth sub-pixels SP1 to SP4 may have a 1×4 form or a uniform stripe structure. For example, the emission regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may have a 1×4 form or a uniform stripe structure.

[0086] The emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, which have uniform stripe structures, can all have a rectangular shape, including a short side parallel to the first direction X and a long side parallel to the second direction Y.

[0087] According to embodiments of this disclosure, each of the emission regions EA1 to EA4 having a uniform stripe structure can be configured to be closer to the central portion CP of the pixel P within the corresponding sub-pixel region, having a smaller size than each of them. Alternatively, the four equally divided regions of the pixel P can be configured to be concentrated in the central portion of the pixel P.

[0088] According to another embodiment of the present disclosure, each of the emission regions EA1 to EA4 having a uniform stripe structure can be disposed at the center portion CP of the corresponding sub-pixel region to have a size smaller than that of each of the four equally divided regions.

[0089] According to another embodiment of this disclosure, each of the emission regions EA1 to EA4 having a uniform stripe structure can be disposed in the entire corresponding sub-pixel region to have the same size as each of the four equally divided regions of pixel P.

[0090] Alternatively, each of the emission regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform stripe structure with different sizes. According to embodiments of the present disclosure, when the emission regions EA1 to EA4 have a non-uniform stripe structure, among the emission regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the emission region EA4 of the fourth sub-pixel SP4 and the light-emitting region EA3 of the third sub-pixel SP3 may have the smallest size, and the light-emitting region EA3 of the third sub-pixel SP3 may have the largest size, but embodiments of the present disclosure are not limited thereto.

[0091] Reference Figure 2A and 2B The circuit regions CA1 to CA4 of each of the first to fourth sub-pixels SP1 to SP4 can be disposed around (or near) the corresponding emission regions EA1 to EA4. Each of the circuit regions CA1 to CA4 may include pixel circuitry and pixel driving lines for emitting the corresponding sub-pixels of the first to fourth sub-pixels SP1 to SP4. For example, the circuit regions CA1 to CA4 may be referred to as non-light-emitting regions, non-aperture regions, non-light-emitting portions, non-aperture portions, or peripheral portions.

[0092] Alternatively, to increase the aperture ratio of sub-pixels SP1 to SP4 corresponding to the sizes of emission regions EA1 to EA4, or to reduce the pixel pitch D1 as the resolution of pixel P increases, the emission regions EA1 to EA4 to the fourth sub-pixels SP1 to SP4 can extend to the circuit regions CA1 to CA4 to overlap with some or all of the circuit regions CA1 to CA4. For example, since the emission regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 have a top emission structure, each of the emission regions EA1 to EA4 can be arranged to overlap with the corresponding circuit region of the circuit regions CA1 to CA4. In this case, each of the emission regions EA1 to EA4 can have a size equal to or larger than the corresponding circuit regions CA1 to CA4.

[0093] exist Figures 2A to 2CIn this configuration, the first sub-pixel SP1 can be configured to emit light of a first color, the second sub-pixel SP2 can be configured to emit light of a second color, the third sub-pixel SP3 can be configured to emit light of a third color, and the fourth sub-pixel SP4 can be configured to emit light of a fourth color. For example, each of the first to fourth colors can be different. As one embodiment, the first color can be red, the second color can be blue, the third color can be white, and the fourth color can be green. As another embodiment, some of the first to fourth colors can be the same. For example, the first color can be red, the second color can be first green, the third color can be second green, and the fourth color can be blue.

[0094] Optionally, the white sub-pixels used to emit white light from the first to fourth sub-pixels SP1 to SP4, which have a uniform or non-uniform stripe structure, can be omitted.

[0095] Figure 3 yes Figure 1 An enlarged view of area "A" shown. Figure 4 It is a diagram. Figure 1 and Figure 3 The equivalent circuit diagram of one pixel is shown.

[0096] Reference Figure 1 , Figure 3 and Figure 4 According to an embodiment of the present disclosure, the first substrate 100 may include pixel driving lines DL, GL, PL, CVL, RL and GCL, a plurality of pixels P, a common electrode CE, a plurality of common electrode connection portions CECP and a first pad portion 110.

[0097] In a diagram, where another reference number or letter is provided in parentheses after a previous one, it means that the number and / or letter in parentheses represents the general category or group of the item, and the first number preceding it is a specific example of that item within that group. For example, Figure 3 The indication of PG1 (PG) indicates that the first pad group PG1 is a specific item within the wide pad group PG. Similarly, in Figure 5 In the figure, the symbol 150m (150) indicates that each of circuits 1501, 1502, ..., 1511, 1512 is a drive circuit within a broad group of drive circuits 150. Similar meanings apply to similar symbols in the figure, and these are provided as examples to illustrate the meaning.

[0098] In a similar way, the legend below a particular graphic provides a general group, followed by a colon, and then a list of items within that group, as shown in the figure. For example, Figure 1The symbols P: Po, Pi below indicate that P is a general group of pixels, and Po and Pi are specific items within that pixel group P. Furthermore, in Figure 3 Below, the symbols DL:DLo and DLe and GL:GLo and GLe indicate that each of these is a specific item within the general group for the data line DL and the gate line GL, respectively. Similar meanings apply to similar symbols in the figure, and these are provided as examples to illustrate their meaning.

[0099] The pixel drive lines DL, GL, PL, CVL, RL, and GCL may include multiple data lines DL, multiple gate lines GL, multiple pixel drive power lines PL, multiple pixel common voltage lines CVL, multiple reference voltage lines RL, and gate control lines GCL.

[0100] Multiple data lines DL can extend relatively long along the second direction Y and can be arranged spaced apart from each other at predetermined or selected intervals along the first direction X in the display area AA of the first substrate 100. For example, odd-numbered data lines DLo can be disposed at the first peripheral portion of each of the multiple pixel areas PA arranged along the second direction Y on the first substrate 100, and even-numbered data lines DLe can be disposed at the second peripheral portion of each of the multiple pixel areas PA arranged along the second direction Y on the first substrate 100, but the embodiments disclosed herein are not limited thereto.

[0101] Multiple gate lines GL can extend relatively long along a first direction X and can be spaced apart from each other at predetermined or selected intervals along a second direction Y in the display area AA of the first substrate 100. For example, each of the multiple gate lines GL can be disposed at each of the first to m-th horizontal lines in the display area AA parallel to the first direction X. For example, the odd-numbered gate lines GLo can be disposed in the third peripheral portion of each of the multiple pixel areas PA disposed on the first substrate 100 along the first direction X. The even-numbered gate lines GLe can be disposed in the fourth peripheral portion along the length of each pixel area PA of the multiple pixel areas PA disposed on the first substrate 100 along the first direction X, but the embodiments of this disclosure are not limited thereto.

[0102] Multiple pixel driving power lines PL can extend relatively long along the second direction Y and can be spaced apart from each other at predetermined or selected intervals along the first direction X in the display area AA of the first substrate 100. For example, among the multiple pixel driving power lines PL, odd-numbered pixel driving power lines PL can be disposed in the first peripheral portion of the odd-numbered pixel area PA with respect to the first direction X, and even-numbered pixel driving power lines PL can be disposed in the first peripheral portion of the odd-numbered pixel area PA. The power lines PL can be disposed in the second peripheral portion of the even-numbered pixel area PA with respect to the first direction X, but the embodiments of this disclosure are not limited thereto.

[0103] Two adjacent pixel driving power lines PL in a plurality of pixel driving power lines PL can be coupled to a plurality of power sharing lines PSL disposed in each pixel region PA arranged along the second direction Y. For example, the plurality of pixel driving power lines PL can be electrically coupled to each other through the plurality of power sharing lines PSL, and therefore can have a trapezoidal structure or a mesh structure. The plurality of pixel driving power lines PL can have a trapezoidal structure or a mesh structure, so the voltage drop (IR drop) of the pixel driving power supply caused by the line resistance of each of the plurality of pixel driving power lines PL can be prevented, minimized or reduced. Therefore, the light-emitting display device according to the embodiments of the present disclosure can prevent or minimize or reduce the image quality degradation caused by the deviation of the pixel driving power supply provided to each pixel P arranged in the display region AA.

[0104] Each power line PSL in the multiple power sharing lines PSL can branch from the adjacent pixel driving power line PL parallel to the first direction X and can be located in the middle region of each pixel region PA, but the embodiments of this disclosure are not limited thereto.

[0105] Multiple pixel common voltage lines (CVLs) can extend relatively long along the second direction Y and can be spaced apart from each other at predetermined or selected intervals along the first direction X in the display area AA of the first substrate 100. For example, each of the multiple pixel common voltage lines (CVLs) can be located in the first peripheral portion of the even-numbered pixel area PA with respect to the first direction X.

[0106] Multiple reference voltage lines RL can extend relatively long along the second direction Y and can be arranged at predetermined or selected intervals along the first direction X in the display area AA of the first substrate 100. The reference voltage lines RL can be arranged in the central region of each pixel area PA arranged along the second direction Y.

[0107] Each of the multiple reference voltage lines RL can be shared by two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) along the first direction X in each pixel region PA. For this purpose, each of the multiple reference voltage lines RL may include a reference branch RDL. The reference branch RDL may branch (or protrude) along the first direction X in each pixel region PA to two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) and may be electrically connected to the two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)).

[0108] Each of the multiple gate control lines GCLs can extend along the second direction Y and can be spaced apart from each other at predetermined or selected intervals along the first direction X in the display area AA of the first substrate 100. For example, as shown in the figure, each of the multiple gate control lines GCLs can be disposed at the boundary region with respect to the first direction X between multiple pixel areas PA or between two adjacent pixel areas PA.

[0109] Each of the plurality of pixels P may include at least three sub-pixels. For example, each of the plurality of pixels P may include first to fourth sub-pixels SP1 to SP4.

[0110] Each of the first to fourth sub-pixels SP1 to SP4 may include a pixel circuit PC and a light-emitting device layer.

[0111] According to embodiments of the present disclosure, the pixel circuit PC can be disposed in the circuit region of the pixel region PA and can be coupled to the adjacent gate line GLo or GLe, the adjacent data line DLo or GLe, and the pixel driving power line PL. For example, the pixel circuit PC disposed in the first sub-pixel SP1 can be coupled to the odd-numbered data line DLo and the odd-numbered gate line GLo; the pixel circuit PC disposed in the second sub-pixel SP2 can be coupled to the even-numbered data line GLe and the odd-numbered gate line GLo; the pixel circuit PC disposed in the third sub-pixel SP3 can be coupled to the odd-numbered data line GLe and the even-numbered gate line GLe; and the pixel circuit PC disposed in the third sub-pixel SP3 and the fourth sub-pixel SP4 can be coupled to the even-numbered data line GLe and the even-numbered gate line GLe.

[0112] The pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can sample the data signal provided from the corresponding data line DLo or DLe in response to the scan signal provided from the corresponding gate line GLo or GLe, and can control the current flowing from the pixel drive power line PL to the light-emitting device layer based on the sampled data signal.

[0113] The pixel circuit PC according to embodiments of the present disclosure may include a first switching thin-film transistor Tsw1, a second switching thin-film transistor Tsw2, a driving thin-film transistor Tdr, and a storage capacitor Cst; however, embodiments of the present disclosure are not limited thereto. In the following description, the thin-film transistor may be referred to as a TFT.

[0114] The first switch TFT Tsw1 may include a gate electrode coupled to the corresponding gate line GL (GLo or GLe), a first source / drain electrode coupled to the corresponding data line DL (DLo or DLe), and a second source / drain electrode coupled to the corresponding data line DL (DLo or DLe). The gate node n1 of the driving TFT Tdr is also present. The first switch TFT Tsw1 can be turned on by a scan signal provided through the corresponding gate line GL (GLo or GLe), and data signals provided through the corresponding data line DL (DLo or DLe) can be transmitted to the gate electrode n1 of the first switch TFT. The driving TFT Tdr is also present.

[0115] The second switch TFT Tsw2 may include a gate electrode connected to the corresponding gate line GL (GLo or GLe), a first source / drain electrode connected to the source node n2 of the driving TFT Tdr, and a second source / drain electrode connected to the source node n2 of the driving TFT Tdr. A corresponding reference voltage line RL is also included. The second switch TFT Tsw2 can be turned on by a scan signal provided through the corresponding gate line GL (GLo or GLe), and a reference voltage provided through the corresponding reference line RL can be transmitted to the source node n2 of the driving TFT Tdr. For example, the second switch TFT Tsw2 can be turned on simultaneously with the first switch TFT Tsw1.

[0116] A storage capacitor Cst can be formed between the gate node n1 and the source node n2 of the driving TFT Tdr. According to embodiments of this disclosure, the storage capacitor Cst may include a first capacitor electrode coupled to the gate node n1 of the driving TFT Tdr, a second capacitor electrode coupled to the source node n2 of the driving TFT Tdr, and a dielectric layer formed in the overlapping region between the first and second capacitor electrodes. The storage capacitor Cst can be charged with the differential voltage between the gate node n1 and the source node n2 of the driving TFT Tdr, and then the driving TFT Tdr can be turned on or off based on its charging voltage.

[0117] The driving TFT Tdr may include a gate electrode (or gate node n1) commonly coupled to the second source / drain electrode of the first switching TFT Tsw1 and the first capacitor electrode of the storage capacitor Cst. The first source / drain electrode (or source node n2) is commonly coupled to the first source / drain electrode of the second switching thin-film transistor Tsw2, the second capacitor electrode of the storage capacitor Cst, and the pixel electrode PE of the light-emitting device layer, as well as the second source / drain electrode PE. The drain electrode (or drain node) is coupled to the corresponding pixel driving power line PL. The driving TFT Tdr can be turned on based on the voltage of the storage capacitor Cst and the amount of current flowing from the pixel driving power line PL to the light-emitting device layer can be controlled.

[0118] The light-emitting device layer can be disposed in the emission region EA of the pixel region PA and electrically coupled to the pixel circuit PC.

[0119] According to embodiments of this disclosure, the light-emitting device layer may be a pixel electrode PE electrically connected to a pixel circuit PC, a common electrode CE electrically connected to a pixel common voltage line CVL, and a self-emissive device ED inserted between these electrodes. The pixel electrode PE and the common electrode CE are also mentioned.

[0120] The pixel electrode PE can be referred to as the anode electrode, reflective electrode, lower electrode, anode, or first electrode of a self-emissive device ED.

[0121] The pixel electrode PE can overlap with the emitter region EA of each of the multiple sub-pixels SP. The pixel electrode PE can be patterned into an island shape and disposed in each sub-pixel SP, and can be electrically coupled to the first source / drain electrode of the driving TFT Tdr of the corresponding pixel circuit PC. One side of the pixel electrode PE can extend from the emitter region EA of the sub-pixel region to the first source / drain electrode of the driving TFT Tdr disposed in the circuit region CA, and can be electrically coupled to the first source / drain electrode of the driving TFT Tdr. The driving TFT Tdr is driven through a contact hole disposed in a planarization layer above the driving TFT Tdr.

[0122] A self-emissive device (ED) can be disposed on top of and in direct contact with the pixel electrode (PE). The ED can be a common layer or a common device layer, which are collectively formed in each of multiple sub-pixels (SPs) so as not to be distinguished by sub-pixel SP units. The ED can respond to the current flowing between the pixel electrode (PE) and the common electrode (CE) to emit white or blue light.

[0123] A common electrode CE can be disposed above the display area AA of the first substrate 100 and can be electrically coupled to the self-emissive device ED of each of the plurality of pixels P. For example, the common electrode CE can be disposed in the remaining display area AA of the first substrate 100, excluding the first pad portion 110 of the first substrate 100.

[0124] Each of the plurality of common electrode connection portions CECP can be disposed between a plurality of pixels P that overlap with a plurality of pixel common voltage lines CVL, and the common electrode CE can be electrically coupled to each of the plurality of pixel common voltage lines CVL. With respect to the first direction X and the second direction Y, each of the plurality of common electrode connection portions CECP according to embodiments of the present disclosure can be electrically coupled to each of the plurality of pixel common voltage lines CVL at a portion therebetween. Two adjacent pixels P can be electrically connected to a portion of the common electrode CE, thus the common electrode CE can be electrically connected to each of the plurality of pixel common voltage lines CVL. For example, the common electrode CE can be coupled to each of the plurality of common electrode connection portions CECP via a side contact structure corresponding to the undercut structure.

[0125] Relative to the first direction X and the second direction Y, each of the plurality of common electrode connection portions CECP can be disposed in the portion between two pixel groups to electrically couple the common electrode CE to each of the plurality of pixel common voltage lines CVL. Therefore, the voltage drop (IR drop) of the pixel common voltage caused by the surface resistance of the common electrode CE can be prevented, minimized, or reduced. Thus, the light-emitting display device according to embodiments of the present disclosure can prevent, minimize, or reduce image quality degradation caused by deviations in the pixel common voltage supplied to each pixel P arranged in the display area AA.

[0126] The first pad portion 110 may be disposed on a first peripheral portion of the first surface of the first substrate 100, parallel to the first direction X. The first pad portion 110 may also be disposed on a third peripheral portion of each outermost pixel region PAo. Regarding the second direction Y, the end of the first pad portion 110 may overlap with or be aligned with the end of each outermost pixel region PAo. Therefore, the first pad portion 110 may be included (or disposed) in each outermost pixel region PAo disposed on the first peripheral portion of the first substrate 100, thus, a non-display area (or border area) may not be formed or may not be present in the first substrate 100 based on the first pad portion 110.

[0127] The first pad portion 110 may include a plurality of first pads arranged parallel to each other along a first direction X at a first peripheral portion of the first substrate 100. The plurality of first pads may be divided (or classified) into a first data pad DP1, a first gate pad GP1, a first pixel drive power pad PPP1, a first reference voltage pad RVP1, and a first pixel common voltage pad CVP1.

[0128] Each first data pad DP1 can be individually (or in a one-to-one relationship) coupled to one side of each of the multiple data lines DLo and DLe located on the first substrate 100.

[0129] Each first gate pad GP1 can be individually (or in a one-to-one relationship) coupled to one side of each gate control line GCL disposed on the first substrate 100. According to this embodiment, the first gate pad GP1 can be divided (or classified) into a first start signal pad, a plurality of first shift clock pads, a plurality of first carry clock pads, at least one first gate drive power supply pad, and at least one first gate common power supply pad. According to embodiments of this disclosure, the first gate pad GP1 can be further divided (or classified) into a first forward drive signal pad, a first reverse drive signal pad, a first external sensing line selection signal pad, a first external sensing reset signal pad, and a first external sensing control signal pad.

[0130] Each first pixel drive voltage pad PPP1 can be individually (or in a one-to-one relationship) coupled to one side of each of the multiple pixel drive power lines PL disposed on the first substrate 100.

[0131] Each first reference voltage pad RVP1 can be individually (or in a one-to-one relationship) coupled to one side of each of the multiple reference voltage lines RL disposed on the first substrate 100.

[0132] Each first pixel common voltage pad CVP1 can be individually (or in a one-to-one relationship) coupled to one side of each of the multiple pixel common voltage lines CVL disposed on the first substrate 100.

[0133] According to embodiments of the present disclosure, a first pad portion 110 may include a first pixel drive power pad PPP1, a first data pad DP1, a first reference voltage pad RVP1, a first gate pad GP1, a first pixel common voltage pad CVP1, a first data pad DP1, a first reference voltage pad RVP1, a first data pad DP1, and a first pixel drive power pad PPP1 X along a first direction. Each of a plurality of pad groups PG can be coupled to two adjacent pixels P arranged along the first direction X. For example, the plurality of pad groups PG may include a first pad group PG1, which includes a first pixel drive power pad PPP1, a first data pad DP1, a first reference voltage pad RVP1, a first data pad DP1, and a first gate pad GP1 continuously disposed along the first direction X in an odd number of pixel regions PA, and a second pad group PG2 including a first pixel common voltage pad CVP1. Figure 1In the first pixel region PA, a first data pad DP1, a first reference voltage pad RVP1, a first data pad DP1 and a first pixel drive power pad PPP1 are continuously disposed along the first direction X.

[0134] The first substrate 100 according to an embodiment of this disclosure may further include multiple secondary voltage lines (SVLs) and multiple secondary line connection portions (SLCPs). For example, the secondary voltage lines may be referred to as additional voltage lines or auxiliary voltage lines, etc. For example, the secondary line connection portions may be referred to as additional line connection portions or auxiliary line connection portions, etc.

[0135] Each of the multiple secondary voltage lines SVL can extend relatively long along the second direction Y and can be arranged adjacent to a corresponding pixel common voltage line CVL among the multiple pixel common voltage lines CVL. For example, a secondary voltage line SVL can be arranged parallel to a pixel common voltage line CVL, with a gate control line GCL located between them.

[0136] Each of the multiple secondary voltage lines SVL according to embodiments of the present disclosure can be electrically connected to an adjacent pixel common voltage line CVL but not electrically connected to a pixel common voltage pad CVP1, and can be provided with a pixel common voltage via adjacent pixel common voltage lines CVL. For this purpose, the first substrate 100 according to embodiments of the present disclosure may further include a plurality of line connection patterns LCP that electrically connect adjacent pixel common voltage lines CVL and secondary voltage lines SVL.

[0137] Each of the plurality of line connection patterns LCP can be disposed on the first substrate 100 such that the line connection pattern LCP and adjacent pixel common voltage lines CVL and secondary voltage lines SVL intersect or overlap each other, and adjacent pixel common voltage lines CVL and secondary voltage lines SVL can be electrically coupled by using a jumper structure. For example, one side of each of the plurality of line connection patterns LCP can be electrically coupled to a portion of the secondary voltage line SVL through a first line contact hole formed on an insulating layer above the secondary voltage line SVL, while on the other side, each of the plurality of line connection patterns LCP can be electrically coupled to a portion of the pixel common voltage line CVL through a second line contact hole formed on an insulating layer above the pixel common voltage line CVL.

[0138] Each of the plurality of secondary line connection portions (SLCPs) can electrically couple a common electrode CE to each of the plurality of secondary voltage lines (SVLs) between a plurality of pixels P overlapping with each of the plurality of secondary voltage lines (SVLs). Regarding the second direction Y, each of the plurality of secondary line connection portions (SLCPs) according to embodiments of the present disclosure can be electrically coupled to each of the plurality of secondary voltage lines (SVLs) at a portion between two adjacent pixels P, and can be electrically coupled to a portion of the common electrode CE, thus electrically coupling the common electrode CE to each of the plurality of secondary voltage lines (SVLs). Therefore, the common electrode CE can be additionally coupled to each of the plurality of secondary voltage lines (SVLs) through the secondary line connection portions (SLCPs). Therefore, the light-emitting display device according to embodiments of the present disclosure can prevent or minimize or reduce image quality degradation caused by deviations in the pixel common voltage supplied to each pixel P arranged in the display area AA. Furthermore, in the light-emitting display device according to embodiments of the present disclosure, although no additional pixel common voltage pad CVP is provided (or formed) connected to each of the plurality of secondary voltage lines SVL, the pixel common voltage can be provided to each of the plurality of secondary voltage lines SVL through each pixel common voltage line CVL and the plurality of line connection patterns LCP.

[0139] According to embodiments of this disclosure, a plurality of secondary line connection portions (SLCPs) can be implemented or formed in a structure symmetrical with respect to the gate control line (GCL) to each of a plurality of common electrode connection portions (CECPs). For example, with respect to the first direction X, adjacent common electrode connection portions (CECPs) and secondary line connection portions (SLCPs) can be implemented or formed in a structure symmetrical with respect to the boundary portion between two adjacent pixels P along the first direction X. Therefore, each of the plurality of pixels P disposed in the display area AA may include at least one of the common electrode connection portion (CECP) and the secondary line connection portion (SLCP). For example, each of the pixels P disposed in each of the first pixel column and the last pixel column parallel to the second direction Y may include only the secondary line connection portion (SLCP). Furthermore, each pixel P disposed in pixel columns other than the first pixel column and the last pixel column may include the common electrode connection portion (CECP) and the secondary line connection portion (SLCP).

[0140] Figure 5 This is an illustration of the rear surface of a light-emitting display device according to an embodiment of the present disclosure. Figure 6 It is a diagram. Figure 5 The diagram shows the second pad, third pad, and interconnect lines of the vegan solder pad. Figure 7 yes Figure 6 A magnified view of region "B" in the image. Figures 5 to 7 It shows in Figures 1 to 4 An embodiment of the light-emitting display device shown is provided with a wiring substrate.

[0141] Reference Figure 3 , Figures 5 to 7 The light-emitting display device according to the embodiments of the present disclosure may include a first substrate 100, a second substrate 200, a bonding member 300 and a wiring portion 400.

[0142] The first substrate 100 may be referred to as a display substrate, pixel array substrate, upper substrate, front substrate, or base substrate. The first substrate 100 may be a glass substrate, a thin glass substrate, or a plastic substrate, and may be bendable or flexible.

[0143] The first substrate 100 may include a gate driving circuit 150, a first pad portion 110, and a plurality of pixels P. Figure 1 And the substrate 100 of the display area AA shown in Figure 2. With Figures 1 to 4 Since they are identical, their repeated descriptions can be omitted.

[0144] The second substrate 200 may be referred to as a wiring substrate, circuit substrate, link substrate, lower substrate, rear substrate, or link glass. The second substrate 200 may be a glass substrate, or a bendable or flexible thin glass substrate or plastic substrate. For example, the second substrate 200 may comprise the same material as the first substrate 100. The dimensions of the second substrate 200 may be the same as or substantially the same as the first substrate 100, but embodiments of this disclosure are not limited thereto. For example, the dimensions of the second substrate 200 may be smaller than the dimensions of the first substrate 100. For example, the second substrate 200 may be configured to have the same dimensions as the first substrate 100 to maintain or ensure the rigidity 100 of the first substrate.

[0145] The second substrate 200 may include a second pad portion 210, at least one third pad portion 230, and a connection line portion 250.

[0146] The second pad portion 210 may be disposed at a peripheral portion (or a first peripheral portion) of the rear surface 200b of the second substrate 200, overlapping with the first pad portion 110 disposed on the front surface of the first substrate 100.

[0147] The second pad portion 210 may include a plurality of second pads disposed parallel to the first direction X at the first peripheral portion of the second substrate 200.

[0148] According to embodiments of the present disclosure, a plurality of second pads can be divided (or classified) into a plurality of second pixel driving power pads PPP2 that overlap with a first pixel driving power pad PPP1, and a plurality of second data pads DP2 that overlap with a first pixel driving power pad PPP1. A first data pad DP1, a plurality of second reference voltage pads RVP2 that overlap with a first reference voltage pad RVP1, a plurality of second gate pads GP2 that overlap with a first gate pad GP1, and a plurality of second pixel common voltage pads CVP2 that overlap with a first reference voltage pad RVP1. A first pixel common voltage pad CVP1. According to embodiments of the present disclosure, a plurality of second gate pads GP2 can be divided (or classified) into a second start signal pad, a plurality of second shift clock pads, a plurality of second carry clock pads, at least one second gate driving power pad, and at least one second gate common power pad.

[0149] According to embodiments of the present disclosure, a plurality of second gate pads GP2 can be divided (or classified) into a second forward drive signal pad, a second reverse drive signal pad, a second external sense line select signal pad, a second external sense reset signal pad, and a second external sense control signal pad. The plurality of second pads according to embodiments of the present disclosure can be arranged along a first direction X in an order equal to (or matching) that of the first pads arranged in the first pad portion 210. For example, the second pad portion 210 may include a second pixel drive power pad PPP2, a second data pad DP2, a second reference voltage pad RVP2, a second gate pad GP2, a second pixel common voltage pad CVP2 along the first direction X, a second data pad DP2, a second reference voltage pad RVP2, a second data pad DP2, and a second pixel drive power pad PPP2. Each of the plurality of pad groups PG can be connected to two adjacent pixels P arranged along the first direction X. For example, each of the plurality of pad groups PG may include a first pad group PG1 including a second pixel drive power pad PPP2, a second data pad DP2, a second reference pad RVP2, a second data pad DP2, and a second gate pad GP2 arranged continuously along the first direction X in an odd-numbered pixel region PA, and a second pad group PG2 including a second pixel common voltage pad CVP2. The second data pad DP2, the second reference voltage pad RVP2, the second data pad DP2, and the second pixel drive power pad PPP2 are arranged continuously along the first direction X in an even-numbered pixel region PA. At least one third pad portion 230 may be disposed on the rear surface 200b of the second substrate 200. For example, at least one third pad portion 230 may be disposed in a central portion adjacent to a first peripheral portion of the rear surface 200b of the second substrate 200.

[0150] At least one third pad portion 230 according to an embodiment of the present disclosure may include a plurality of third pads (or input pads) arranged at intervals along a first direction X. The plurality of third pads may include a third pixel drive power pad PPP3, a third data pad DP3, a third reference voltage pad RVP3, a third gate pad GP3, and at least one third pixel common voltage pad CVP3.

[0151] At least one third pad portion 230 may include a first region (or a central region) containing a third pixel drive power pad PPP3 and a third data pad DP3, a second region (or a region) including a third gate pad GP3, and a third region (or other region) including at least one third pixel common voltage pad CVP3. For example, at least one third pad portion 230 may also include a first dummy region disposed between the first region and the second region and including a plurality of dummy pads, and a second dummy region disposed between the first region and the second region. The third region includes a plurality of dummy pads. For example, the third pixel drive power pad PPP3, the third data pad DP3, and the third reference voltage pad RVP3 disposed in the first region of at least one third pad portion 230 may be arranged in parallel in the same (matching) order as the arrangement order of the second pixel drive power pad PPP2, the second data pad DP2, and the second reference voltage pad RVP2 disposed in the second pad portion 210.

[0152] The third gate pad GP3 may be disposed in parallel in the second region of at least one third pad portion 230 to have a predetermined or selected interval along the first direction X.

[0153] According to embodiments of the present disclosure, the third gate pad GP3 can be divided (or classified) into a third start signal pad, a plurality of third shift clock pads, a plurality of third carry clock pads, at least one third gate drive power supply pad, and at least one third gate common power supply pad. The plurality of third gate pads GP3 according to embodiments of the present disclosure can be further divided (or classified) into a third forward drive signal pad, a third reverse drive signal pad, a third external sense line select signal pad, a third external sense reset signal pad, and a third external sense control signal pad.

[0154] A connector portion 250 may be disposed between a second pad portion and at least one third pad portion 230. The connector portion 250 may include multiple connectors that connect the second pads of the second pad portion 210 to the third pad portions, respectively. The pads of at least one third pad portion 230 are individually (or in a one-to-one relationship).

[0155] According to embodiments of the present disclosure, the multiple link lines can be divided (or classified) into data link line 251, gate link line 253, pixel drive power link line 255, pixel common power link line 257 and reference voltage link line 259.

[0156] Data link line 251 can be configured to electrically connect (or couple) the second data pad DP2 to the third data pad DP3 in a one-to-one relationship. Gate connection line 253 can be configured to electrically connect (or couple) the second gate pad GP2 to the third gate pad GP3 in a one-to-one relationship. Pixel drive power connection line 255 can be configured to electrically connect (or couple) the second pixel drive power pad PPP2 to the third pixel drive power pad PPP3 in a one-to-one relationship. Pixel common power connection line 257 can be configured to electrically connect (or couple) each second pixel drive power pad PPP2 to at least one third pixel common voltage pad CVP3. Reference voltage connection line 259 can be configured to electrically connect (or couple) the second reference voltage pad RVP2 to the third reference voltage pad RVP3 in a one-to-one relationship.

[0157] According to embodiments of the present disclosure, the third gate connection line 253 can be divided (or classified) into a start signal connection line 253a, multiple shift clock connection lines 253b, at least one gate drive power supply connection line 253c, and at least one gate common power supply link line. The multiple gate connection lines 253 can be further divided (or classified) into connection lines for a third positive drive signal pad, a third reverse drive signal, a third external sense line selection signal, a third external sense reset signal, and a third external sense control signal.

[0158] The connection portion 250 according to an embodiment of the present disclosure may further include a plurality of gate control signal transmission lines 254.

[0159] The gate control signal transmission line 254 can selectively connect (or couple) the gate link line 253 to the third gate pad GP3 disposed in at least one third pad portion 230.

[0160] Gate control signal transmission lines 254 can be electrically connected (or coupled) to third gate pads GP3, and can bypass one side of at least one third pad portion 230, and can be selectively connected (or coupled) to gate connection lines 253. For example, gate control signal transmission lines 254 and gate connection lines 253 can be disposed on different layers on the rear surface 200b of the second substrate 200, and the other side link line 253 of each gate can be electrically connected (or coupled) to the corresponding gate control signal transmission line through a link contact hole. Optionally, the other side of each gate connection line 253 can pass through the area between two adjacent third pads, without overlapping with the third pads disposed in at least one third pad portion 230, and can be selectively connected (or coupled) to the third pad. In this case, the gate control signal provided to the gate connection line 253 can be maintained at the original voltage level without changing (or altering) based on the signal provided to the third pad.

[0161] According to embodiments of the present disclosure, the pixel common power connection line 257 may include a first common connection line 257a, a second common connection line 257b, and multiple third common connection lines 257c.

[0162] The first common link line 257a may be commonly connected (or coupled) to at least one third pixel common power pad CPP3 disposed in at least one third pad portion 230. For example, the first common link line 257a may be disposed at a corner of the back surface 200b of a second substrate 200.

[0163] The first common connection line 257a may be disposed or formed on the rear surface 200b of the second substrate 200 between the second pad portion 210 and at least one third pad portion 230 to have a relatively wide size (or area), such that the drop in pixel common power supply voltage applied thereto is reduced or minimized. The size of the first common connection line 257a according to embodiments of the present disclosure may gradually increase in a direction from one side to the other. For example, the size of the first common connection line 257a may gradually increase in a direction from at least one third pad portion 230 to the outer surface OS of the second substrate 200.

[0164] In the first common connection line 257a according to an embodiment of the present disclosure, its side adjacent to the third pad portion 230 can be jointly connected (or coupled) to at least one third pad portion 230 disposed on at least one third pixel common power pad CPP3, and its other side adjacent to the second pad portion 210 can overlap with the second common connection line 257b. For example, the first common connection line 257a can be disposed on the rear surface 200b of the second substrate 200 together with the data connection line 251 or the gate connection line 253.

[0165] The second common connection line 257b may be disposed at a first peripheral portion of the rear surface 200b of the second substrate 200 to overlap with the first peripheral portion of the first substrate 100 and adjacent to the second pad portion 210. The second common connection line 257b according to an embodiment of the present disclosure may be arranged parallel to a first direction X to face all pads disposed at the second pad portion 210. For example, the second common connection line 257b may be strip-shaped with a relatively wide dimension (or area) to reduce or minimize the voltage drop of the pixel common voltage applied to the pixel common power connection line 257.

[0166] The second common connection line 257b may overlap with each of the plurality of pixel drive power connection lines 255, the plurality of data connection lines 251, and the plurality of gate connection lines 253. For example, the data connection line 251 may be disposed above the gate connection line 253 and the second common connection line 257b may be disposed above the pixel drive power connection line 255. Furthermore, the pixel drive power connection line 255 may be disposed together with the data connection line 251 on the gate connection line 253.

[0167] One side of the second common connection line 257b can be electrically connected (or coupled) to the other side of the first common connection line 257a through the connection contact hole 257h.

[0168] Each of the plurality of third common link lines 257c can be commonly connected to the second common link line 257b and can be commonly connected (or coupled) to each of the second pixel common power pads CVP2. According to embodiments of this disclosure, each of the plurality of third common link lines 257c can extend (or protrude) from the other side of the second common link line 257b in a direction toward the plurality of second pixel common power pads CVP2 disposed thereon, and can be electrically connected (or coupled) to a corresponding second pixel common power pad in the plurality of second pixel common power pads CVP2. For example, each of the plurality of third common link lines 257c can be formed together with the second common link line 257b. Furthermore, the plurality of third common link lines 257c and the second common link line 257b can be formed together with the pads of the second pad portion 210.

[0169] The second substrate 200 can be coupled (or connected) to the second surface of the first substrate 100 using a coupling member 300. The coupling member 300 can be inserted between the first substrate 100 and the second substrate 200. Therefore, the first substrate bonding member 300 can bond the substrate 100 and the second substrate 200 to each other.

[0170] The wiring portion 400 can be configured to surround the outer surface OS of the first substrate 100 and the outer surface OS of the second substrate 200. For example, the wiring portion 400 can be configured at each of the outer surface OS of the first substrate 100 (or a surface) as OS1a and the outer surface OS of the second substrate 200 as OS1b. For example, the wiring portion 400 can be referred to as a side wiring portion, edge wiring portion, side wiring portion, edge wiring portion, printed line portion, printed wiring portion, or wiring portion, etc.

[0171] According to embodiments of the present disclosure, the wiring portion 400 may include multiple wirings disposed at each of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200.

[0172] Each of the plurality of wirings 410 can be formed around the first pad portion 110, the first outer surface OS1a of the first substrate 100, the first outer surface OS1b of the second substrate 200, and the second pad portion 210, and can be electrically connected (or coupled) to the first pad portion 110 and the second pad portion 210 in a one-to-one relationship. According to an embodiment of this disclosure, each of the plurality of wirings 410 can be formed by a printing process using conductive paste. According to another embodiment of this disclosure, each of the plurality of wirings 410 can be formed by a transfer process in which a conductive paste pattern is transferred to a transfer pad made of a flexible material and the conductive paste pattern transferred to the transfer pad is transferred to the wiring portion 400. For example, the conductive paste can be Ag paste, but embodiments of this disclosure are not limited thereto.

[0173] Each of the multiple traces 410 can be electrically connected (or coupled) to each of the first pad 111 of the first pad portion 110 and the second pad 211 of the second pad portion 210 in a one-to-one relationship. For example, each of the multiple traces 410 can be spaced apart from each other along a first direction X.

[0174] According to embodiments of the present disclosure, the multiple wirings 410 can be divided (classified) into multiple pixel power supply wirings 411, multiple data wirings 413, multiple reference voltage wirings 415, multiple gate wirings 417, and multiple pixel common voltage wirings 419.

[0175] Multiple pixel power lines 411 can be electrically connected (or coupled) one-to-one to multiple first pixel drive power pads PPP1 of the first pad section 110 and multiple second pixel drive power pads PPP2 of the second pad section 210.

[0176] Multiple data routing lines 413 can be electrically connected in a one-to-one relationship to multiple first data pads DP1 of the first pad section 110 and multiple second data pads DP2 of the second pad section 210.

[0177] Multiple reference voltage wirings 415 can be electrically connected (or coupled) in a one-to-one relationship to multiple first reference voltage pads RVP1 of the first pad portion 110 and multiple second reference voltage pads RVP2 of the second pad portion 210.

[0178] Multiple data routing lines 417 can be electrically connected in a one-to-one relationship to multiple first gate pads GP1 of the first pad portion 110 and multiple second gate pads GP2 of the second pad portion 210.

[0179] Multiple pixel common voltage wirings 419 can be electrically connected (or coupled) to multiple first pixel common voltage pads CVP1 of the first pad portion 110 and multiple second pixel common voltage pads CVP2 of the second pad portion 210. This is a one-to-one relationship.

[0180] The light-emitting display device according to embodiments of the present disclosure may further include a driving circuit section 500.

[0181] The driving circuit section 500 can drive (or emit light) the pixel P disposed on the first substrate 100 based on digital video data and timing synchronization signals provided from the display driving system, so as to allow the display area AA to display an image corresponding to the image. The driving circuit section 500 can be connected (or coupled) to at least one third pad section 230 disposed on the rear surface 200b of the second substrate 200, and can output data signals, gate control signals, and driving power supplies for driving (or emitting light) the pixel P disposed on the first substrate 100 to at least one third pad section 230.

[0182] The drive circuit component 500 according to an embodiment of the present disclosure may include a flexible circuit film 510, a drive integrated circuit (IC) 530, a printed circuit board (PCB) 550, a timing controller 570, and a power supply circuit 590.

[0183] The flexible circuit film 510 can be connected (or coupled) to at least one third pad portion 230 disposed on the rear surface 200b of the second substrate 200.

[0184] The driver IC 530 can be mounted on the flexible circuit film 510. The driver IC 530 can receive sub-pixel data and data control signals provided from the timing controller 570, and convert the sub-pixel data into analog data signals based on the data control signals, and provide the analog data signals to the corresponding data lines DL. The data signals can be provided through the flexible circuit film 510 to the corresponding third data pad DP3 in at least one third pad portion 230.

[0185] The driver IC 530 can sense the feature values ​​of the driving TFTs disposed in the sub-pixels SP through multiple reference voltage lines RL (or pixel sensing lines) disposed on the substrate 100, generate raw sensing data corresponding to the sensing value of each sub-pixel, and provide the raw sensing data of each sub-pixel to the timing controller 570.

[0186] PCB 550 can be attached to the other peripheral portion of flexible circuit film 510. PCB 550 can transmit signals and power between components in drive circuit section 500.

[0187] The timing controller 570 can be mounted on PCB 550 and can receive digital video data and timing synchronization signals from the display driver system via a user connector located on PCB 550. Alternatively, the timing controller 570 may not be mounted on PCB 550. PCB 550 can be implemented in the display driver system or mounted on a separate control board connected between PCB 550 and the display driver system.

[0188] The timing controller 570 can align digital video data based on timing synchronization signals to generate pixel data that matches the pixel arrangement structure set in the display area AA, and can provide the generated pixel data to the driver IC 530.

[0189] The timing controller 570 can generate each of a data control signal and a gate control signal based on a timing synchronization signal, control the drive timing of the driver IC 530 based on the data control signal, and control the drive timing 150 of the gate drive circuit based on the gate control signal. For example, the timing synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a master clock (or dot clock).

[0190] The data control signal according to embodiments of this disclosure may include a source start pulse, a source shift clock, and a source output signal, etc. The data control signal can be provided to the driver IC 530 through the flexible circuit film 510.

[0191] The gate control signal according to embodiments of this disclosure may include a start signal (or gate start pulse), a plurality of scan clocks whose phases are sequentially shifted, and a plurality of carry clocks whose phases are sequentially shifted. The gate control signal may also include a forward drive signal and a reverse drive signal, etc. The gate control signal may also include an external sense line selection signal, an external sense reset signal, and an external sense control signal. The gate control signal may be provided to the gate drive circuit 150 110 and the gate control line GCL via a flexible circuit film 510, at least one third pad portion 230, a connection portion 250, a second pad portion 210, a wiring portion 400, and a first pad portion.

[0192] The timing controller 570 can drive each of the driver IC 530 and the gate driver circuit 150 based on an external sensing mode during a predetermined or selected external sensing cycle, generating compensation data for each sub-pixel to compensate for characteristic variations of the driven TFT. It modulates each sub-pixel based on the raw sensing data provided from the driver IC 530 and modulates the pixel data of each sub-pixel based on the generated compensation data. For example, for each external sensing period corresponding to a blank period (or vertical blank period) of the vertical synchronization signal, the timing controller 570 can drive each of the driver IC 530 and the gate driver circuit 150 based on an external sensing mode. For example, the external sensing mode can be set in real-time or periodically during the power-on process of the display device, the power-off process of the display device, the power-off process after the display device has been driven for a long time, or a frame set periodically.

[0193] According to embodiments of the present disclosure, the timing controller 570 can store raw sensing data of each sub-pixel provided by the driver IC 530 in a storage circuit based on an external sensing mode. Furthermore, in display mode, the timing controller 570 can correct the pixel data to be provided to each sub-pixel based on the raw sensing data stored in the storage circuit, and can provide the corrected pixel data to the driver IC 530. Here, the raw sensing data of each sub-pixel may include information about the sequential changes of each driving TFT and self-emissive device disposed in the respective sub-pixel. Therefore, in external sensing mode, the timing controller 570 can sense the characteristic values ​​(e.g., threshold voltage or mobility) of the driving TFTs disposed in each sub-pixel, and based on this, can correct the pixel data to be provided to each sub-pixel, thereby minimizing or preventing image quality degradation caused by deviations in the characteristic values ​​of the driving TFTs of multiple sub-pixels. The external sensing method of the display device is a technique well-known to those skilled in the art and will not be described further here. For example, the display device according to embodiments of this disclosure can sense the feature values ​​of the driving TFTs set in each sub-pixel P based on the sensing modes disclosed in Korean Patent Publications No. 10-2016-0093179, 10-2017-0054654 or 10-2018-0002099.

[0194] Power supply circuit 590 can be mounted on PCB 550 and can generate various power supply voltages required to display an image on pixel P by providing the generated power supply voltage to the corresponding circuits using an externally supplied input power supply. For example, power supply circuit 590 can generate and output the required logic source voltage for each of drive timing controller 570 and driver IC 530, multiple reference gamma voltages supplied to driver IC 530, and at least one gate drive power supply and at least one gate common power supply required to drive gate drive circuit 150. Additionally, power supply circuit 590 can generate and output pixel drive power supply and pixel common voltage, but embodiments of this disclosure are not limited thereto. For example, driver IC 530 can generate and output pixel drive power supply and pixel common voltage based on multiple reference gamma voltages.

[0195] Figure 8 This is a diagram showing the arrangement of the gate drive circuit and the common electrode connection portion according to an embodiment of the present disclosure.

[0196] Reference Figure 8 According to another embodiment of this disclosure, the gate driving circuit 150 can be implemented (or embedded) within the display area AA of the first substrate 100. The gate driving circuit 150 can generate scan signals based on the provided gate control signals, the first pad portion 110, and the gate control line GCL, and sequentially provide scan signals to multiple gate lines GL.

[0197] The gate control line GCL can extend a long distance along the second direction Y and can be spaced apart from each other at a predetermined or selected interval along the first direction X in the display area AA of the first substrate 100. For example, the gate control line GCL can be disposed between at least one or more pixels P along the first direction X.

[0198] According to an embodiment of the present disclosure, the gate drive circuit 150 can be implemented using a shift register comprising multiple stages of circuitry 1501 to 150m, where m is an integer of 2 or greater.

[0199] Each of the multiple stage circuit sections 1501 to 150m can be individually disposed on each horizontal line on the first surface of the first substrate 100 along the first direction X, and can be independently connected (or coupled) to each other along the second direction Y. Each of the multiple stage circuit sections 1501 to 150m can generate a scan signal in a predetermined or selected order in response to a gate control signal provided through the first pad section 110 and the gate control line GCL, and can provide the scan signal to the corresponding gate line GL.

[0200] Each of the multiple stage circuit portions 1501 to 150m according to embodiments of the present disclosure may include multiple branch circuits 1511 to 151n and a branch network 153. The multiple branch circuits 1511 to 151n may be distributed along a first direction X among multiple pixels P and selectively coupled to multiple gate control lines GCL. It should be understood that "distributed arrangement" means distributed in one or more directions. Dispersion can be regular intervals. For example, as... Figure 8 As shown, the branch circuits 1511 to 151n of the stage circuit section 1501 are distributed at regular intervals along the X-axis in the outermost pixel Po. As another example, the branch circuits 1511 of the stage circuit section 1501 to 150m are distributed at regular intervals along the Y-axis in the outermost pixel Po.

[0201] Each of the plurality of branch circuits 1511 to 151n may be separated from and arranged therein on the horizontal lines HL1 to HLm of the first substrate 100 in the first direction X. Each of the plurality of branch circuits 1511 to 151n may be disposed in a circuit region between two adjacent pixels P or may be disposed in a circuit region between at least two adjacent pixels P on the horizontal lines HL1 to HLm of the first substrate 100, but embodiments of the present disclosure are not limited thereto. For example, each of the plurality of branch circuits 1511 to 151n may include at least one thin-film transistor (TFT) (or branch TFT) and may be disposed between at least two pixels P (or pixel regions) in one of them. The horizontal lines HL1 to HLm of the first substrate 100 in the first direction X.

[0202] Multiple branch circuits 1511 to 151n can be selectively connected (or coupled) to the gate control line GCL via branch network 153, and can be electrically connected (or coupled) to each other via branch network 153. The multiple branch circuits 1511 to 151n can generate scan signals based on the gate control signal provided via the gate control line GCL and the voltage of branch network 153, and can provide the scan signals to the corresponding gate lines GL. It should be understood that "selective connection" means that one element can be coupled to or separated from another element via an intermediate selective element. For example, the first branch network BN1 is selectively connected to the first branch circuit 1511 of the first circuit section 1501 via a switch, such as... Figure 8 As shown. When the switch is closed, the first branch network BN1 is coupled to the first branch circuit 1511, and when the switch is open, the first branch network BN1 is decoupled from the first branch circuit 1511.

[0203] Each of the plurality of branch circuits 1511 to 151n may include at least one TFT (or branch TFT) of a plurality of TFTs constituting a primary circuit portion of the stage circuit portions 1501 to 150m. Any one of the plurality of branch circuits 1511 to 151n may include a pull-up TFT connected to (or coupled to) the gate line GL. Another branch circuit of the plurality of branch circuits 1511 to 151n may include a pull-down TFT connected to (or coupled to) the gate line GL.

[0204] Branch network 153 can be set at each horizontal line HL1 to HLm of the first substrate 100 and multiple branch circuits 1511 to 151n can be electrically coupled to each other.

[0205] The branch network 153 set in each of the first to m-th level circuit sections 1501 to 150m can be divided (or classified) into first to m-th branch networks BN1 to BNm. For example, m can be a natural number or four or more natural numbers.

[0206] According to embodiments of this disclosure, the first to m-th branch networks BN1 to BNm may include multiple control node lines and multiple network lines.

[0207] Multiple control node lines can be set at each horizontal line HL1 to HLm of the first substrate 100, and can be selectively coupled to multiple branch circuits 1511 to 151n in a horizontal line HL1 to HLm.

[0208] Multiple network lines can be selectively coupled to a gate control line GCL disposed on the first substrate 100, and can be selectively connected (or coupled) to multiple branch circuits 1511 to 151n. For example, the multiple network lines can transmit gate control signals provided from the gate control line GCL to the corresponding branch circuits 1511 to 151n, and can transmit signals between multiple branch circuits 1511 to 151n.

[0209] Each of the first branch networks BN1 to BNm adjacent to the outer surface of the first substrate 100 can be disposed between the emission regions of the inner pixel Pi and the outermost pixel Po. For example, in the outermost pixel Po, when the region between the emission region and the outer surface of the first substrate 100 is called the peripheral region of the horizontal line, and the region between the emission region and the inner pixel Pi is called the inner peripheral region of the horizontal line, each of the first branch networks BN1 and BNm can be disposed in the inner peripheral region instead of the peripheral region of the outermost pixel Po. Therefore, driving defects may occur due to the increased capacitance between the common electrode and each of the first branch networks BN1 and BNm occurring in the peripheral region of the outermost pixel Po.

[0210] According to embodiments of this disclosure, each of the branch network BN1 of the first-level circuit portion 1501 and the branch network BNm of the m-th level circuit portion 150m can be disposed between two adjacent pixels Po and Pi along the second direction Y. For example, the branch network BN1 of the first-level circuit portion 1501 can be disposed between the first horizontal line HL1 and the second horizontal line HL2, while the branch network BNm of the m-th level circuit portion 150m can be disposed between the (m-1)-th horizontal line and the m-th horizontal line HLm.

[0211] According to embodiments of this disclosure, branch networks BN1 to BNm can be located between the 4n-3 (where n is a natural number and 4n is equal to or less than m) horizontal lines HL4n-3 and HL4n-2. This includes horizontal line HL4n-2 and the area between the 4n-1 horizontal line HL4n-1 and the 4n horizontal line HL4n. For example, the area between the 4n-3 horizontal line HL4n-3 and the 4n-2 horizontal line HL4n-2, and the area between the 4n-1 horizontal line HL4n-1 and the 1st to 4n horizontal lines HL4n. The m-th horizontal lines HL1 to HLm can be defined as the arrangement area of ​​the branch network. Furthermore, the area between the 4n-2 horizontal line HL4n-2 and the 4n-1 horizontal line HL4n-1 of the first to m-th horizontal lines HL1 to HLm can be defined as the non-arrangement area of ​​the branch network.

[0212] According to one embodiment of the present invention, the branch networks BN2k-1 (where k is a natural number, and 2k is equal to or less than m) of the 2k-1th branch network BN2k and the branch networks BN1 to BNm of the 2k-1th branch network BN2k can be arranged between the 2k-1th horizontal line HL2k-1 and the 2kth horizontal line HL2k. For example, relative to the second direction Y, when each pixel P is divided into an upper region (or one region, or a first region) and a lower region (or another region, or a second region), the first branch network (or odd branch network) BN2k-1 arranged in the 2k-1th horizontal line HL2k-1 (or odd horizontal line) HL2k-1 can be arranged in the lower region of each pixel P, and the second branch network (or even branch network) BN2k arranged in the 2kth horizontal line (or even horizontal line) HL2k can be arranged in the upper region of each pixel P. Therefore, the 2k-1th branch network BN2k-1 and the 2kth branch network BN2k can be arranged or configured to be symmetrical about the boundary portion of two adjacent pixels P along the second direction Y.

[0213] According to embodiments of this disclosure, the common electrode connection portion CECP can be disposed in the region of each pixel P where no branch networks BN1 to BNm are disposed. For example, relative to the second direction Y, when branch networks BN1 to BNm are disposed in the upper region of pixel P, the common electrode connection portion CECP can be disposed in the lower region of pixel P. On the other hand, relative to the second direction Y, when branch networks BN1 to BNm are disposed in the lower region of pixel P, the common electrode connection portion CECP can be disposed in the upper region of pixel P. For example, relative to the second direction Y, when each of the first to mth horizontal lines HL1 to HLm is divided into an upper region (or one region, or a first region) and a lower region (or another region, or a second region), branch networks BN1 to BNm can be disposed in one of the upper region and the lower region, and the common electrode connection portion CECP can be disposed in the other of the upper region and the lower region.

[0214] According to embodiments of this disclosure, the common electrode connection portion CECP arranged in the 2k-1th horizontal line HL2k-1 of the first to m-th horizontal lines HL1 to HLm can be arranged in the upper region of pixel P, and the common electrode connection portion CECP provided in the 2kth horizontal line HL2k can be provided in the lower region of pixel P. For example, relative to the second direction Y, the common electrode connection portion CECP-2 provided in the 4n-2th horizontal line HL4n and the common electrode connection portion CECP provided in the 4n-1th horizontal line HL4n-1 can be provided between the 4n-2th horizontal line HL4n-2 and the 4n-1th horizontal line HL4n-1. On the other hand, relative to the second direction Y, a common electrode connection portion (CECP) may not be provided between the 2k-1th horizontal line HL2k-1 and the 2kth horizontal line HL2k, where branch networks BN1 to BNm are not provided. For example, the region between the 4n-2nd horizontal line HL4n-2 and the 4n-1st horizontal line HL4n-1 of the first to mth horizontal lines HL1 to HLm can be defined as the arrangement region of the common electrode connection portion (CECP). Furthermore, each horizontal line HL1 to HLm in the region between the 4n-3rd horizontal line HL4n-3 and the 4n-2nd horizontal line HL4n-2, and the region between the 4n-1st horizontal line HL4n-1 and the 4nth horizontal line HL4n, can be defined as a non-arrangement region of the common electrode connection portion (CECP).

[0215] According to embodiments of this disclosure, the common electrode connection portion CECP may not be provided in each of the first horizontal line HL1 and the m-th horizontal line HLm, in order to simplify the structure of the outermost pixel Po provided in each. The first to m-th horizontal lines HL1 to HLm are the first horizontal line HL1 and the m-th horizontal line HLm, but embodiments of this disclosure are not limited thereto.

[0216] According to embodiments of this disclosure, the secondary line connection portion SLCP can be arranged parallel to the common electrode connection portion CECP. For example, with respect to the first direction X, adjacent common electrode connection portions CECP and secondary line connection portions SLCP can be implemented or formed in a structure symmetrical with respect to the boundary portion between two adjacent pixels P in the first direction X.

[0217] According to one embodiment of this disclosure, since the gate driving circuit 150 is disposed in the display area AA of the first substrate 100, the second interval D2 between the center portion of the outermost pixel area PAo and the outer surface OS, and the first spacing (or pixel spacing) D1 of the first substrate 100, can be half or less than the first spacing (or pixel spacing) D1 between adjacent pixel areas PA. For example, when the gate driving circuit 150 is not disposed in the display area AA of the first substrate 100 but in the peripheral portion of the first substrate 100, the second interval D2 can be half or less than the first interval D1. Therefore, in the light-emitting display device according to the embodiment of the present invention, the gate driving circuit 150 can be disposed in the display area AA of the first substrate 100, and thus, the second interval D2 can be implemented as half or less than the first interval D1.

[0218] Furthermore, according to this embodiment of the present disclosure, each pixel common voltage line CVL disposed in each pixel P along the second direction Y can be electrically connected (or coupled) to the common electrode via a common electrode connection portion CECP and a common electrode. A second line connection portion SLCP is also present in each pixel P. Therefore, the pixel common voltage applied to each pixel P can be uniform, thereby preventing or minimizing image quality degradation or brightness non-uniformity caused by region-based non-uniformity. The pixel common voltage is applied to each pixel P.

[0219] Figure 9 It is a diagram. Figure 8 The circuit diagram of the i-th level circuit component is shown.

[0220] Reference Figure 3 , 8 According to embodiments of the present disclosure, the i-th stage circuit portion 150i can output two scan signals SSi and SSi+1, a carry signal CSi, and a gate control line GCL disposed above the first substrate 100 in response to a gate control signal provided by the first pad portion 110.

[0221] According to embodiments of this disclosure, the gate control signal may include a start signal Vst, multiple shift clocks including multiple scan clocks sCLK and multiple carry clocks cCLK, first to third gate drive power supplies GVdd1, GVdd2 and GVdd3, and a first to third gate common power supply supplying power to GVss1, GVss2 and GVss3. In this case, the gate control line GCL may include a start signal line, multiple scan clock lines, multiple carry clock lines, first to third gate drive power supply lines, and a first to third gate common power supply line.

[0222] The gate control signal according to embodiments of the present disclosure may include first to j-th carry clocks and first to j-th scan clocks. For example, j may be 4, but embodiments of the present disclosure are not limited thereto and may be 6, 8, or 10 or more even numbers.

[0223] When the gate control signal includes the first to fourth carry clocks, the first carry clock can be applied to the 4n-3 level (where n is a natural number and 4n is less than m) level circuit section, the second carry clock can be applied to the 4n-2 level circuit section, the third carry clock can be applied to the 4n-1 level circuit section, and the fourth carry clock can be applied to the 4n level circuit section. When the gate control signal includes the first to fourth scan clocks, the first and second scan clocks can be applied to the odd-numbered level circuit sections, and the third and fourth scan clocks can be applied to the even-numbered level circuit sections.

[0224] Furthermore, the gate control signal according to embodiments of this disclosure may also include a forward drive signal FWS and a reverse drive signal BWS. In this case, the gate control line GCL may also include a forward drive signal line and a reverse drive signal line.

[0225] According to embodiments of this disclosure, the gate control signal may further include an external sensing line selection signal Slss, an external sensing reset signal Sirst, and an external sensing control signal Scs for external sensing mode. In this case, the gate control line GCL may further include an external sensing selection signal line, an external sensing reset signal line, and an external sensing control signal line.

[0226] According to embodiments of this disclosure, the i-th stage circuit portion 150i may include the i-th branch network BNi, the node control circuit NCC, the first inverter circuit IC1, the second inverter circuit IC2, the node reset circuit NRC, and the output buffer circuit OBC.

[0227] The i-th branch network BNi can be used to form a circuit connection between the node control circuit NCC, the first inverter circuit IC1, the second inverter circuit IC2, the node reset circuit NRC, and the output buffer circuit OBC, and can be selectively connected to the gate control line GCL.

[0228] The i-th branch network BNi can be selectively coupled to the gate control line GCL. According to embodiments of this disclosure, the i-th branch network BNi may include first to third control node lines Q, QBo, and QBe, as well as multiple network lines NL.

[0229] Each of the first to third control node lines Q, QBo, and QBe can be located at the upper edge (or lower edge) of each pixel region arranged on the i-th horizontal line of the first substrate 100. The first to third control node lines Q, QBo, and QBe can be arranged parallel to the first direction X or the gate line GL. For example, each of the first to third control node lines Q, QBo, and QBe can be configured to be adjacent to the gate line GL.

[0230] Multiple network lines NL can be selectively coupled to the gate control line GCL and can be selectively coupled to the first to third control node lines Q, QBo, and QBe. Furthermore, multiple network lines NL can be selectively coupled between circuits constituting stage circuit section 150i.

[0231] The node control circuit NCC can be implemented to control the voltage of each of the first to third control node lines Q, QBo and QBe.

[0232] According to embodiments of the present disclosure, the node control circuit NCC can be coupled to each of the first to third control node lines Q, QBo, and QBe via multiple network lines NL, and can be implemented to control the voltage of each. The first to third control node lines Q, QBo, and QBe respond to a start signal Vst, a reset signal Vrst, and a first gate drive power supply GVdd1 provided via the multiple network lines NL. As an embodiment, the start signal Vst can be the (i-2)th carry signal output from the (i-2)th stage circuit section. The reset signal Vrst can be the (i+2)th carry signal output from the (i+2)th stage circuit section.

[0233] According to another embodiment of this disclosure, the node control circuit NCC can be coupled to each of the first to third control node lines Q, QBo, and QBe via multiple network lines NL, and can control the voltage of each of the first to third control node lines Q, QBo, and QBe. The circuit is responsive to the start signal Vst, reset signal Vrst, forward drive signal FWS, reverse drive signal BWS, and first gate drive power supply GVdd1 transmitted through the multiple network lines NL to the third control node lines Q, QBo, and QBe.

[0234] As an example, when the forward drive signal FWS has a high voltage level (or a high potential voltage level), the reverse drive signal BWS may have a low voltage level (or a low potential voltage level), and when the forward drive signal FWS has a low voltage level (or a low potential voltage level), the reverse drive signal BWS may have a high voltage level (or a high potential voltage level). For example, when the forward drive signal FWS has a high voltage level, the gate drive circuit 150 may provide a scan signal from the first gate line to the last gate line based on a forward scan drive, and when the reverse drive signal BWS has a high voltage level, the gate drive circuit 150 may provide a scan signal from the last gate line to the first gate line based on a reverse scan drive. Here, the high voltage level may be referred to as a first voltage level, a high potential voltage level, a gate turn-on voltage level, or a transistor turn-on voltage level, while the low voltage level may be referred to as a second voltage level, a low potential voltage level, a gate turn-off voltage level, or a transistor turn-off voltage level.

[0235] The first inverter circuit IC1 can control or discharge the voltage of the second control node line QBo based on the voltage of the first control node line Q provided through multiple network lines NL. According to an embodiment of this disclosure, the first inverting circuit IC1 can be coupled to the second gate drive power supply GVdd2, the first control node line Q, the second control node line QBo, the first gate common power supply GVss1, and the second gate common power supply. GVss2 is powered through multiple network lines NL. In response to the voltages of the second gate common power supply GVss2 and the first control node line Q, the first inverting circuit IC1 can provide the first gate common power supply GVss1 to the second control node line QBo to discharge the voltage of the second control node line QBo.

[0236] The second inverter circuit IC2 can control or discharge the voltage of the third control node line QBe based on the voltage of the first control node line Q provided through multiple network lines NL. According to an embodiment of this disclosure, the second inverter circuit IC2 can be coupled to the third gate drive power supply GVdd3, the first control node line Q, the third control node line QBe, the first gate common power supply GVss1, and the second gate common power supply. GVss2 is powered through multiple network lines NL. In response to the voltages of the third gate common power supply GVss3 and the first control node line Q, the second inverter circuit IC2 can provide the first gate common power supply GVss1 to the third control node line QBe to discharge the voltage of the third control node line QBe.

[0237] The second gate drive power supply GVdd2 and the third gate drive power supply GVdd3 can have inverse (or opposite) voltage levels. For example, when the second gate drive power supply GVdd2 has a high voltage level, the third gate drive power supply GVdd3 can have a low voltage level, and when the second gate drive power supply GVdd2 has a low voltage level, the third gate drive power supply GVdd3 can have a high voltage level.

[0238] The second gate common power supply GVss2 and the first gate common power supply GVss1 can have the same voltage level or different voltage levels.

[0239] The node reset circuit NRC can maintain the voltage level of each of the second control node line QBo and the third control node line QBe, while the voltage of the first control node line Q has a high voltage level.

[0240] According to embodiments of the present disclosure, the node reset circuit NRC can simultaneously reset the voltage of the second control node line QBo and the voltage of the third control node line QBe in response to a reset signal Vrst provided by a start signal Vst and a reset signal Vrst. Multiple network lines NL. As one embodiment, the node reset circuit NRC can provide a first gate common power supply GVss1 to the second control node line QBo and the third control node line QBe in response to the start signal Vst and the reset signal Vrst, thereby maintaining the second control node line QBo and the third control node line QBe at the voltage level of the first gate common power supply GVss1.

[0241] According to another embodiment of this disclosure, the node reset circuit NRC can respond to a start signal Vst, a reset signal Vrst, a forward drive signal FWS, and a reverse drive signal BWS provided through multiple network lines NL. As one embodiment, the node reset circuit NRC can respond to the start signal Vst, the reset signal Vrst, the forward drive signal FWS, providing a first gate common power supply GVss1 to the second control node line QBo and the third control node line QBe, and the reverse drive signal BWS, thus maintaining each of the second control node line QBo and the third control node line QBe at the voltage level of the first gate common power supply GVss1.

[0242] The output buffer circuit OBC can be implemented to sequentially output two scan signals with gate on-voltage levels or sequentially output two scan signals with gate off-voltage levels in response to the voltage of each of the first to third control node lines. Q, QBo, and QBe are based on the carry clock cCLK, scan clock sCLK, first gate common power supply GVss1, and third gate common power supply GVss3 provided through multiple network lines NL.

[0243] When the voltage of the first control node line Q is high and the voltage of each of the second and third control node lines QBo and QBe is low, the output buffer circuit OBC according to an embodiment of the present disclosure can output each of the i-th carry signal CSi corresponding to the carry clock cCLK, the i-th scan signal SSi corresponding to the odd scan clock sCLKo, and the (i+1)-th scan signal SSi+1 corresponding to the even scan clock sCLKe. As an embodiment, the i-th carry signal CSi can be provided as a start signal Vst to the (i+2)-th stage circuit section, the i-th scan signal SSi can be provided to the odd gate line GLo (or the i-th gate line GLi), and the (i+1)-th scan signal SSi+1 can be provided to the even gate line GLe (or the (i+1)-th gate line GLi+1).

[0244] When the voltage of each of the first and third control node lines Q and QBe is low and the voltage of the second control node line QBo is high, the output buffer circuit OBC according to the embodiment of the present disclosure can output each of the i-th scan signal SSi and the (i+1)-th scan signal SSi+1, each scan signal having a gate cutoff voltage level corresponding to the voltage level of the third gate common power supply GVss3, and can output the i-th carry signal CSi with the gate, the cutoff voltage level corresponding to the voltage level of the first gate common power supply GVss1.

[0245] When the voltage of each of the first and second control node lines Q and QBo is low and the voltage of the third control node line QBe is high, the output buffer circuit OBC according to an embodiment of the present disclosure can output each of the i-th scan signal SSi and the (i+1)-th scan signal SSi+1, each scan signal having a gate cutoff voltage level corresponding to the voltage level of the third gate common power supply GVss3, and can output the i-th carry signal CSi with the gate, the cutoff voltage level corresponding to the voltage level of the first gate common power supply GVss1.

[0246] According to embodiments of the present disclosure, the output buffer circuit OBC can be disposed in the central region of the i-th horizontal line parallel to the first direction X. For example, when the output buffer circuit OBC is disposed adjacent to one end (or the other end of the first direction X), due to the line resistance of the horizontal line, the voltage level of the scan signal may decrease in the direction from one end of the gate line to the other end. Therefore, to prevent this problem, the output buffer circuit OBC should be disposed in the central region of the i-th horizontal line parallel to the first direction X. However, embodiments of the present disclosure are not limited to this and can be disposed on one side or the other side of the horizontal line. When the total length of the gate line is short, the i-th horizontal line...

[0247] The first to third gate common power supplies GVss1, GVss2 and GVss3 can have the same voltage level or different voltage levels.

[0248] According to embodiments of the present disclosure, the i-th stage circuit portion 150i may further include a fourth control node line Qm, a first sensing control circuit SCC1, and a second sensing control circuit SCC2.

[0249] The fourth control node line Qm can be electrically connected between the first sensing control circuit SCC1 and the second sensing control circuit SCC2. The fourth control node line Qm can be included in the i-th branch network BNi and can be electrically connected between the first sensing control circuit SCC1 and the second sensing control circuit SCC2 through multiple network lines NL.

[0250] The first sensing control circuit SCC1 can be implemented in response to the i-th carry signal CSi, the external sensing line selection signal Slss, the external sensing control signal Scs, the external sensing reset signal Sirst, and the first gate drive power supply GVdd1 provided through the i-th branch network BNi. As an embodiment, the first sensing control circuit SCC1 can charge the first gate drive power supply GVdd1 into the fourth control node line Qm in response to the i-th carry signal CSi with a high voltage level and the external sensing line selection signal Slss with a high voltage level. Then, the voltage of the first control node line Q can be controlled in response to the voltage charged into the fourth control node line Qm, providing the external sensing control signal Scs period with a high voltage level and the first gate drive power supply GVdd1 during the early stage of vertical blanking. Therefore, the output buffer circuit OBC can output the i-th carry signal CSi corresponding to the carry clock cCLK, the i-th scan signal SSi corresponding to the odd scan clock sCLKo, and the (i+1)-th scan signal SSi+1 corresponding to the following. The even-numbered scan clock sCLKe during the vertical blanking period is based on the voltage of the first control node line Q.

[0251] Furthermore, the first sensing control circuit SCC1 can release the voltage of the first control node line Q in response to an external sensing reset signal Srst provided by the i-th branch network BNi. As an embodiment, the first sensing control circuit SCC1 can provide a first gate common power supply GVss1 to the first control node line Q in response to an external sensing reset signal Srst with a high level to reset or initialize the voltage of the first control node line Q. This voltage level is provided later in the vertical blanking period.

[0252] The second sensing control circuit SCC2 can be implemented to release the voltage of each of the second control node lines QBo and QBe in response to the voltage of the fourth control node line Qm and the provided external sensing control signal Scs. The i-th branch network BNi. As an embodiment, the second sensing control circuit SCC2 can provide a first gate common voltage GVss1 to each of the second control node lines QBo and QBe to simultaneously discharge both the second control node lines QBo and QBe, in response to the voltage of the fourth control node line Qm having a high voltage level and the external sensing control signal Scs having a high voltage level.

[0253] Figure 10 It is a diagram. Figure 9 The electrical connections of the node control circuit, the first inverter circuit, the second inverter circuit, and the first sensing control circuit shown are illustrated.

[0254] Reference Figure 9 and Figure 10 According to embodiments of the present disclosure, the node control circuit NCC may include first to fourth node control circuits NCC1 to NCC4.

[0255] In forward scan drive, the first node control circuit NCC1 can, in response to a high-voltage start signal Vst and a high-voltage forward drive signal FWS, charge the first control node line Q with the high voltage level of the forward drive signal FWS. Furthermore, in reverse scan drive, the first node control circuit NCC1 can electrically connect a low-voltage forward drive signal line to the first control node line Q to discharge the voltage charged into the first control node line Q to a low level. The voltage level is responsive to the high-voltage start signal Vst and the low-voltage forward drive signal FWS.

[0256] The first node control circuit NCC1 according to an embodiment of the present disclosure may include first to third TFTs T1 to T3.

[0257] The first TFT T1 can output a positive drive signal FWS to the first connection node Nc1 in response to a start signal Vst. For example, the first TFT T1 can be turned on based on a start signal Vst with a high voltage level and can output a positive drive signal FWS provided through a positive drive signal line to the first connection node Nc1.

[0258] In response to the start signal Vst, the second TFT T2 can electrically connect the first connection node Nc1 to the first control node line Q. For example, the second TFT T2 can be turned on based on the start signal Vst with a high voltage level and can output the positive drive signal FWS provided by the first TFT T1 and the first connection node Nc1 to the first control node line Q.

[0259] The third TFT T3 can respond to the voltage of the first control node line Q by providing a first gate drive power supply GVdd1 to the first connection node Nc1 via the first gate drive power supply line. For example, the third TFT T3 can be turned on based on the voltage of the first control node line Q having a high voltage level and can transmit the first gate drive power supply GVdd1 to the first connection node Nc1 between the first TFT T1 and the second TFT T2, thereby preventing voltage leakage. For example, the third thin-film transistor T3 can increase the voltage difference between the gate voltage of the second thin-film transistor T2 and the voltage of the first connection node Nc1 to turn off the already turned-off second thin-film transistor T2. On the start-up signal Vst having a low voltage level, the voltage drop of the first control node line Q can therefore be prevented by the turned-off second TFT T2, thereby stably maintaining the voltage of the first control node line Q.

[0260] In the reverse scan drive, the second node control circuit NCC2 can, in response to a high-level reset signal Vrst and a high-level reverse drive signal BWS, charge the first control node line Q with a high voltage level. Conversely, in the forward scan drive, the second node control circuit NCC2 can electrically connect a low-level reverse drive signal line to the first control node line Q to discharge the voltage charged into the first control node line Q to a low level. The voltage level is responsive to the high-level reset signal Vrst and the low-level reverse drive signal BWS.

[0261] The second node control circuit NCC2 according to an embodiment of the present disclosure may include a fourth TFT T4 and a fifth TFT T5.

[0262] The fourth TFT T4 can output a reverse drive signal BWS in response to a reset signal Vrst. For example, the fourth TFT T4 can be turned on based on a reset signal Vrst with a high voltage level and can output the reverse drive signal BWS provided through the reverse drive signal line to the second connection node Nc2.

[0263] The fifth TFT T5 can electrically connect the second connection node Nc2 to the first control node line Q in response to the reset signal Vrst. For example, the fifth TFT T5 can be turned on based on the reset signal Vrst with a high voltage level and can output the reverse drive signal BWS provided through the fourth TFT T4 and the second connection node Nc2 to the first control node line.

[0264] The second connection node Nc2 between the fourth TFT T4 and the fifth TFT T5 can be electrically connected to the first connection node Nc1. Therefore, the third TFT T3 of the first node control circuit NCC1 can provide the first gate drive power supply GVdd1, supplied via the first gate drive power line, to the second connection node Nc2. Thus, the third thin-film transistor T3 of the first node control circuit NCC1 can increase the voltage difference between the gate voltage of the fifth thin-film transistor T5 of the second node control circuit NCC2 and the voltage of the second connection node Nc2, thereby completely turning off the fifth thin-film transistor. Based on the fact that T5, with its low-voltage reset signal Vrst, is already off, the voltage drop (or leakage current) of the first control node line Q can be prevented by the off fifth TFT T5, thereby stabilizing the voltage of the first control node line Q.

[0265] The third node control circuit NCC3 can discharge the voltage of the first control node line Q in response to the voltage of the second control node line QBo. For example, the third node control circuit NCC3 can form a current path between the first control node line Q and the first gate common power supply line based on the high voltage level of the second control node line QBo to discharge the voltage of the first control node.

[0266] The third node control circuit NCC3 according to embodiments of this disclosure may include a sixth TFT T6 and a seventh TFT T7.

[0267] The sixth TFT T6 can provide the second connection node Nc2 with a first gate common power supply GVss1 supplied via the first gate common power supply line in response to the voltage of the second control node line QBo. For example, the sixth TFT T6 can be turned on based on a high voltage level of the second control node line QBo and can electrically connect the second connection node Nc2 to the first gate common power supply line.

[0268] The seventh TFT T7 can electrically connect the second connection node Nc2 to the first control node line Q in response to the voltage of the second control node line QBo. For example, the seventh TFT T7 can be turned on based on a high voltage level of the second control node line QBo and can electrically connect the second connection node Nc2 to the first control node line Q.

[0269] The seventh thin-film transistor T7 can be turned off based on the low voltage level of the second control node line QBo, and the voltage difference between the gate voltage of the turned-off seventh thin-film transistor T7 and the voltage of the second connection node Nc2 can be based on the first gate drive power supply GVdd1 provided to the second connection node Nc2 by the third TFT T3 through the first node control circuit NCC1. Therefore, the seventh TFT T7 can be completely turned off based on the low voltage level of the second control node line QBo, and thus turned off based on the first gate drive power supply GVdd1 provided to the second connection node Nc2. Therefore, voltage leakage (or current leakage) through the voltage drop of the third node control circuit NCC3 to the first control node line Q can be prevented because the seventh TFT T7 is completely turned off, thereby stably maintaining the voltage of the first control node line Q.

[0270] The fourth node control circuit NCC4 can discharge the voltage of the first control node line Q in response to the voltage of the third control node line QBe. For example, the fourth node control circuit NCC4 can form a current path between the first control node line Q and the first gate common power supply line based on the high voltage level of the third control node line QBe, so as to discharge the voltage of the first control node line Q to the first gate common power supply line.

[0271] The fourth node control circuit NCC4 according to embodiments of this disclosure may include an eighth TFT T8 and a ninth TFT T9.

[0272] The eighth TFT T8 can supply the first gate common power supply GVss1, which is supplied through the first gate common power supply line, to the second connection node Nc2 in response to the voltage of the third control node line QBe. For example, the eighth TFT T8 can be turned on based on a high voltage level of the third control node line QBe and can electrically connect the second connection node Nc2 to the first gate common power supply line.

[0273] The ninth TFT T9 can electrically connect the second connection node Nc2 to the first control node line Q in response to the voltage of the third control node line QBe. For example, the ninth TFT T9 can be turned on based on a high voltage level of the third control node line QBe and can electrically connect the second connection node Nc2 to the first control node line Q.

[0274] The ninth TFT T9 can be turned off based on the low voltage level of the third control node line QBe, and the voltage difference between the gate voltage of the turned-off ninth TFT T9 and the voltage of the second connection node Nc2 can be based on the first gate drive power supply GVdd1 provided to the second connection node Nc2 by the third TFT T3 through the first node control circuit NCC1. Therefore, the ninth TFT T9 can be completely turned off based on the low voltage level of the third control node line QBe, thus being cut off based on the first gate drive power supply GVdd1 provided to the second connection node Nc2. Therefore, since the ninth TFT T9 is completely turned off, voltage leakage (or current leakage) through the voltage drop (or current leakage) of the first control node line Q via the fourth node control circuit NCC4 can be prevented, thereby stably maintaining the voltage of the first control node line Q.

[0275] The first inverter circuit IC1 can discharge the voltage of the second control node line QBo in response to the voltage of the first control node line Q and the second gate drive power GVdd2. For example, the first inverter circuit IC1 can form a current path between the second control node line QBo and the first gate common power line based on the high voltage level of the first control node line QBo, to discharge the voltage of the second control node line QBo to the first gate common power line.

[0276] According to embodiments of the present disclosure, the first inverter circuit IC1 may include tenth to thirteenth TFTs T10 to T13 and a first capacitor C1.

[0277] The tenth TFT T10 can be turned on or off based on the second gate drive power supply GVdd2, and can output the second gate drive power supply GVdd2, which has a high voltage level when turned on, to the first internal node Ni1. According to an embodiment of this disclosure, the tenth TFT T10 can be diode-connected between the second gate drive power supply GVdd2 and the first internal node Ni1.

[0278] The eleventh TFT T11 can be turned on or off based on the voltage of the first control node line Q, and when turned on, it can discharge the voltage of the first internal node Ni1 to the second gate common power line.

[0279] The twelfth TFT T12 can be turned on or off based on the voltage of the first internal node Ni1, and when turned on, it can provide the second gate drive power supply GVdd2 to the second control node line QBo.

[0280] The thirteenth TFT T13 can be turned on or off according to the voltage of the first control node line Q. When it is turned on, it can provide the voltage of the second control node line QBo to the first gate common power supply line.

[0281] The first capacitor C1 can be formed between the first internal node Ni1 and the nodes (or the second control node line QBo) between the twelfth TFT T12 and the thirteenth TFT T13. For example, the first capacitor C1 can allow bootstrapping in the first internal node Ni1 based on voltage changes in the second gate drive power GVdd2. Therefore, when the voltage level of the second gate drive power GVdd2 changes, the voltage of the first internal node Ni1 may change due to the voltage change in the second gate drive power GVdd2, which is due to the bootstrapping caused by the coupling of the first capacitor C1 and the second gate drive power GVdd2, thereby further enhancing the output characteristics of the twelfth TFT T12.

[0282] The second inverter circuit IC2 can discharge the voltage of the third control node line QBe in response to the voltage of the first control node line Q and the third gate drive power GVdd3. For example, the second inverter circuit IC2 can form a current path between the third control node line QBe and the first gate common power line based on the high voltage level of the first control node line QBe, thereby discharging the voltage of the third control node line QBe to the first gate common power line.

[0283] The second inverter circuit IC2 according to an embodiment of the present disclosure may include fourteenth to seventeenth TFTs T14 to T17 and a second capacitor C2.

[0284] The fourteenth TFT T14 can be turned on or off based on the third gate drive power supply GVdd3, and can output the third gate drive power supply GVdd3, which has a high voltage level when turned on, to the second internal node Ni2. According to an embodiment of this disclosure, the fourteenth TFT T14 can be diode-connected between the third gate drive power supply GVdd3 and the second internal node Ni2.

[0285] The fifteenth TFT T15 can be turned on or off based on the voltage of the first control node line Q, and when turned on, it can discharge the voltage of the second internal node Ni2 to the second gate common power supply line.

[0286] The sixteenth TFT T16 can be turned on or off based on the voltage of the second internal node Ni2, and when turned on, it can provide the third gate drive power supply GVdd3 to the third control node line QBe.

[0287] The seventeenth TFT T17 can be turned on or off according to the voltage of the first control node line Q. When it is turned on, it can provide the voltage of the third control node line QBe to the first gate common power supply line.

[0288] The second capacitor C2 can be formed between the second internal node Ni2 and the nodes (or the third control node line QBe) between the sixteenth TFT T16 and the seventeenth TFT T17. For example, based on the voltage change of the third gate drive power supply GVdd3, the second capacitor C2 can allow bootstrapping to occur in the second internal node Ni2. Therefore, when the voltage level of the third gate drive power supply GVdd3 changes, the voltage of the second internal node Ni2 may further change with the voltage change of the third gate drive power supply GVdd3 due to the bootstrapping caused by the coupling of the second capacitor C2 and the third gate drive power GVdd3, thereby further enhancing the output characteristics of the sixteenth TFT T16.

[0289] The first sensing control circuit SCC1 can be implemented in response to the i-th carry signal CSi, the external sensing line selection signal Slss, the external sensing control signal Scs, the external sensing reset signal Srst, and the first gate drive power supply GVdd1.

[0290] According to an embodiment of this disclosure, the first sensing control circuit SCC1 may include a fifth node control circuit NCC5 and a sixth node control circuit NCC6.

[0291] The fifth node control circuit NCC5 can respond to the i-th carry signal CSi, the external sensing line selection signal Slss, the external sensing control signal Scs, and the first gate drive power supply GVdd1.

[0292] The fifth node control circuit NCC5 according to an embodiment of this disclosure may include the thirty-third to thirty-seventh TFTs T33 to T37 and the third capacitor C3.

[0293] The 33rd TFT T33 can output the i-th carry signal CSi to the third connection node Nc3 in response to an external sensing line selection signal Slss provided together with the start signal Vst. For example, the 33rd TFT T33 can be turned on based on the external sensing line selection signal Slss having a high voltage level and can output the i-th carry signal CSi to the third connection node Nc3.

[0294] The 34th TFT T34 can electrically connect the third connection node Nc3 to the fourth control node line Qm in response to an external sensing line selection signal Slss. For example, the 34th TFT T34 can be turned on based on the external sensing line selection signal Slss with a high voltage level and can provide the i-th carry signal CSi provided through the 33rd TFT T33 and the third connection node Nc3 to the fourth control node line Qm. The third connection node Nc3 can be a connection line between the 33rd TFT T33 and the 34th TFT T34.

[0295] The 35th TFT T35 can provide a first gate drive power supply GVdd1 to the third connection node Nc3 in response to the voltage of the fourth control node line Qm. For example, the 35th TFT T35 can be turned on based on the voltage of the fourth control node line Qm having a high voltage level and can provide the first gate drive power supply GVdd1 to the third connection node Nc3, thereby preventing voltage leakage. The fourth control node line Qm. For example, the 35th thin-film transistor T35 can increase the voltage difference between the gate voltage of the 34th thin-film transistor T34 and the voltage of the third connection node Nc3, thereby completely turning off the 34th thin-film transistor T34, which is turned off based on the external sensing line selection signal Slss having a low voltage level. This prevents the voltage drop (or current leakage) of the fourth control node line Qm by the turned-off 34th TFT T34, thus stabilizing the voltage of the fourth control node line Qm.

[0296] The thirty-sixth TFT T36 can output a first gate drive power GVdd1 to the thirty-seventh TFT T37 in response to the voltage of the fourth control node line Qm. For example, the thirty-sixth TFT T36 can be turned on based on the voltage of the fourth control node line Qm having a high voltage level and can provide the first gate drive power supply GVdd1 to the thirty-seventh TFT T37.

[0297] The 37th TFT T37 can electrically connect the 36th TFT T36 to the first control node line Q in response to an external sensing control signal Scs. For example, the 37th TFT T37 can be turned on based on an external sensing control signal Scs with a high voltage level, and the first gate drive power supply GVdd1 provided by the 36th TFT T36 can be supplied to the first control node line Q to charge the first control node line Q with the voltage level of the first gate drive power supply GVdd1.

[0298] A third capacitor C3 can be formed between the fourth control node line Qm and the first gate drive power line and can store the voltage difference between the fourth control node line Qm and the first gate drive power line. For example, the first electrode of the third capacitor C3 can be electrically connected to the fourth control node line Qm, which is connected to the gate electrode of the thirty-fifth TFT T35 and the gate electrode of the thirty-sixth TFT T36, and the second electrode of the third capacitor C3 can be electrically connected to the first gate drive power line. Depending on the conduction of the thirty-third, thirty-fourth, and thirty-fifth TFTs T33 to T35, and when the thirty-third, thirty-fourth, and thirty-fifth TFTs T33 to T35 are turned off, the third capacitor C3 can use the stored voltage to maintain the voltage of the fourth control node line Qm at a high voltage level. For example, the third capacitor C3 can maintain the voltage of the fourth control node line Qm at a high voltage level during a horizontal cycle by using the stored voltage.

[0299] The sixth node control circuit NCC6 can release the voltage of the first control node line Q in response to an external sensed reset signal Srst. As an example, the sixth node control circuit NCC6 can provide a first gate common power supply GVss1 to the first control node line Q in response to an external sensed reset signal Srst with a high voltage level, thereby resetting or initializing the voltage of the first control node line Q.

[0300] The sixth node control circuit NCC6 according to an embodiment of this disclosure may include the thirty-eighth TFT T38 and the thirty-ninth TFT T39.

[0301] The 38th TFT T38 can supply the first gate common power supply GVss1, which is supplied through the first gate common power supply line, to the second connection node Nc2 in response to an external sensed reset signal Srst. For example, the 38th TFT T38 can be turned on based on an external sensed reset signal Srst with a high voltage level and can output the first gate common power supply GVss1 to the second connection node Nc2.

[0302] The 39th TFT T39 can electrically connect the second connection node Nc2 to the first control node line Q in response to an external sensed reset signal Srst. For example, the 39th TFT T39 can be turned on based on an external sensed reset signal Srst with a high voltage level and can provide a first gate common power supply GVss1, provided through the 38th TFT T38 and the second connection node Nc2, to the first control node line Q.

[0303] The second connection node Nc2 between the thirty-eighth TFT T38 and the thirty-ninth TFT T39 can be electrically connected to the first connection node Nc1. Therefore, the first gate drive power supply GVdd1 can be provided to the second connection node Nc2 via the third TFT T3 of the first node control circuit NCC1. Thus, the third thin-film transistor T3 of the first node control circuit NCC1 can increase the voltage difference between the gate voltage of the thirty-ninth thin-film transistor T39 of the sixth node control circuit NCC6 and the voltage of the second connection node Nc2, thereby completely turning off the circuit. The thirty-ninth TFT T39 has already been turned off based on the external sensed reset signal Srst with a low voltage level, therefore, the voltage drop (or current leakage) of the first control node line Q can be prevented by turning off the thirty-ninth TFT T39, thereby stably maintaining the voltage of the first control node line Q.

[0304] Figure 11 It is a diagram. Figure 9 The noise reduction circuit, output buffer circuit, and second sensing circuit shown are each independent circuit diagrams.

[0305] Reference Figure 9 and Figure 11 According to an embodiment of the present disclosure, the node reset circuit NRC can maintain the voltage level of each of the second control node line QBo and the third control node line QBe, while the voltage of the first control node line Q has a high voltage level.

[0306] The node reset circuit NRC according to embodiments of this disclosure may include eighteenth to twenty-third TFTs T18 to T23.

[0307] The eighteenth TFT T18 can electrically connect the fourth connection node Nc4 to the positive drive signal line in response to the start signal Vst and the positive drive signal FWS. As an example, the eighteenth TFT T18 can be turned on based on the start signal Vst with a high voltage level and can provide the positive drive signal FWS to the fourth connection node Nc4.

[0308] The nineteenth TFT T19 can electrically connect the second control node line QBo to the first gate common power supply line in response to the voltage of the fourth connection node Nc4. As an embodiment, the nineteenth thin-film transistor T19 can be turned on based on the voltage of the fourth connection node Nc4 and can form a current path between the second control node line QBo and the first gate common power supply line to release the voltage of the second control node. The node line QBo is connected to the first gate common power supply line, thereby resetting the voltage of the second control node line QBo to the voltage level of the first gate common power supply GVss1.

[0309] In response to the voltage of the second control node line QBo, the twentieth TFT T20 can electrically connect the fourth connection node Nc4 to the first gate common power supply line. As an embodiment, the twentieth thin-film transistor T20 can be turned on based on a high voltage level of the second control node line QBo, and can form a current path between the fourth connection node Nc4 and the first gate common power supply line to release the voltage of the control node line QBo. The fourth connection node Nc4 is connected to the first gate common power supply line, thereby resetting the voltage of the fourth connection node Nc4 to the voltage level of the first gate common power supply GVss1. Accordingly, when the voltage of the second control node line QBo is high, the twentieth thin-film transistor T20 can reset the voltage of the fourth connection node Nc4 to the voltage level of the first gate common power supply GVss1 to turn off the nineteenth thin-film transistor T19, thereby preventing the voltage of the second control node line QBo from discharging to the first gate common power supply line through the nineteenth TFT T19.

[0310] The 21st TFT T21 can electrically connect the fourth connection node Nc4 to the reverse drive signal line in response to the reset signal Vrst and the reverse drive signal BWS. As an example, the 21st TFT T21 can be turned on based on the reset signal Vrst having a high voltage level and can provide the fourth connection node Nc4 with the reverse drive signal BWS having a high voltage level.

[0311] The 22nd TFT T22 can electrically connect the third control node line QBe to the first gate common power supply line in response to the voltage of the fourth connection node Nc4. As an embodiment, the 22nd TFT T22 can be turned on based on the voltage of the fourth connection node Nc4, and a current path can be formed between the third control node line QBe and the first gate common power supply line to release the voltage of the connection node Nc4. The third control node line QBe is connected to the first gate common power supply line, thereby resetting the voltage of the third control node line QBe to the voltage level of the first gate common power supply GVss1.

[0312] The 23rd TFT T23 can electrically connect the fourth connection node Nc4 to the first gate common power supply line in response to the voltage of the third control node line QBe. As an embodiment, the 23rd TFT T23 can be turned on based on a high voltage level of the third control node line QBe and can form a current path between the fourth connection node Nc4 and the first gate common power supply line to release the voltage. Connecting the voltage of the fourth connection node Nc4 to the first gate common power supply line resets the voltage of the fourth connection node Nc4 to the voltage level of the first gate common power supply GVss1. Accordingly, when the voltage of the third control node line QBe is high, the 23rd TFT T23 can reset the voltage of the fourth connection node Nc4 to the voltage level of the first gate common power supply GVss1 to turn off the 22nd TFT T22, thereby preventing the voltage of the third control node line QBe from discharging to the first gate common power supply line through the 22nd TFT T22.

[0313] The nineteenth TFT T19 and the twenty-second TFT T22 can be turned on or off simultaneously based on the voltage of the fourth connection node Nc4.

[0314] As one embodiment, in the forward scan drive of the gate drive circuit 150, the nineteenth thin-film transistor T19 and the twenty-second thin-film transistor T22 can be simultaneously turned on based on the high level of the forward drive signal FWS provided to the fourth connection node Nc4. The eighteenth TFT T18 is turned on based on the start signal Vst with a high voltage level and can be simultaneously turned off based on the first gate common power supply GVss1 provided to the fourth connection node Nc4. The twentieth TFT T20 is turned on based on the high level of the voltage level of the second control node line QBo and can be simultaneously turned off based on the first gate common power supply GVss1 provided to the fourth connection node Nc4 through the twenty-third TFT T23. The line QBe is turned on based on the high voltage level of the third control node.

[0315] In another embodiment, during the reverse scan drive of the gate drive circuit 150, the nineteenth thin-film transistor T19 and the twenty-second thin-film transistor T22 can be simultaneously turned on based on the high level of the reverse drive signal BWS provided to the fourth connection node Nc4. The twenty-first TFT T21 can be turned on based on the reset signal Vrst with a high voltage level and can be simultaneously turned off based on the high voltage level of the third control node line QBe, provided to the fourth connection node Nc4 by the first gate common power supply GVss1 via the twenty-third TFT T23; or it can be simultaneously turned off based on the high voltage level of the control node line QBo, provided to the fourth connection node Nc4 by the twenty twentieth TFT T20.

[0316] The output buffer circuit OBC can receive the carry clock cCLK, the odd scan clock sCLKo, the even scan clock sCLKe, the first gate common power supply GVss1, the second gate common power supply GVss2, and the third gate common power supply GVss3, and can output the i-th scan signal SSi, the (i+1)-th scan signal SSi+1, and the i-th carry signal CSi based on the carry clock cCLK, the scan clock sCLK, and the third gate common power supply GVss3, in response to the voltage of each of the first to third control node lines Q, QBo, and QBe. For example, when the voltage of the first control node line Q is high, the output buffer circuit OBC can output the i-th carry signal CSi corresponding to the carry clock cCLK, the i-th scan signal SSi corresponding to the odd scan clock sCLKo, and the (i+1)-th scan signal SSi+1 corresponding to the even scan clock sCLKe.

[0317] The output buffer circuit OBC according to embodiments of the present disclosure may include first to third output buffer circuits OBC1 to OBC3.

[0318] The first output buffer circuit OBC1 can output the i-th scan signal SSiQ, QBo, and QBe based on the voltage level of either the odd scan clock sCLKo or the voltage level of the third gate common power supply GVss3, according to the voltage of each of the first to third control node lines.

[0319] The first output buffer circuit OBC1 according to an embodiment of the present disclosure may include TFTs 24 to 26 (T24 to T26) and a coupling capacitor Cc.

[0320] The 24th TFT T24 (or the first pull-up TFT) can transmit the odd scan clock sCLKo to the i-th gate line GLi through the first output node No1 based on the voltage of the first control node line Q. For example, the 24th TFT T24 may include a gate electrode connected to the first control node line Q, a first source / drain electrode connected to the first output node No1, and a second source / drain electrode line connected to the odd scan clock.

[0321] The 25th TFT T25 (or the odd-numbered first pull-down TFT) can transmit the third gate common power supply GVss3 to the i-th gate line GLi through the first output node No1 based on the voltage of the second control node line QBo. For example, the 25th TFT T25 may include a gate electrode connected to the second control node line QBo, a first source / drain electrode connected to the first output node No1, and a second source / drain electrode connected to the third gate common power supply line.

[0322] The 26th TFT T26 (or even the first pull-down TFT) can transmit the third gate common power supply GVss3 to the i-th gate line GLi through the first output node No1 based on the voltage of the third control node line QBe. For example, the 26th TFT T26 may include a gate electrode connected to the third control node line QBe, a first source / drain electrode connected to the first output node No1, and a second source / drain electrode connected to the third gate common power supply line.

[0323] A coupling capacitor Cc can be formed between the first control node line Q and the first output node No1. For example, the coupling capacitor Cc can be the parasitic capacitance between the gate of the twenty-fourth thin-film transistor T24 and the first output node No1. Based on the phase shift (or change) of the odd scan clock sCLKo, the coupling capacitor Cc can allow bootstrapping to occur in the first control node line Q. Therefore, when the odd scan clock sCLKo transitions from a low voltage level to a high voltage level, the voltage of the first control node line Q can be boosted to a higher voltage by the high voltage level of the odd scan clock. The clock sCLKo is based on bootstrapping caused by the coupling capacitor Cc and the odd scan clock sCLKo with a high voltage level. For example, when an odd-numbered scan clock sCLKo with a high voltage level is provided to the second source / drain electrode of the 24th TFT T24, the voltage of the first control node line Q is pre-charged to a higher voltage level. The positive drive signal FWS of the first node control circuit NCC1 can be boosted to a higher voltage. Therefore, the 24th TFT T24 can be fully turned on and can provide an odd-numbered scan clock sCLKo with a high voltage level as the i-th scan signal SSi. The i-th gate line GLi passes through the first output node No1 and the turned-on 24th TFT T24 without voltage loss.

[0324] The second output buffer circuit OBC2 can output a scan signal SSi+1 with an even-numbered scan clock sCLKe or the voltage level of the third gate common power supply GVss3, based on the voltage of each of the first to third gate common power supplies GVss3. The third control node lines are Q, QBo, and QBe.

[0325] The second output buffer circuit OBC2 according to an embodiment of this disclosure may include TFTs 27 to 29 (T27 to T29).

[0326] The 27th TFT T27 (or the second pull-up TFT) can transmit the even-numbered scan clock sCLKe to the (i+1)th gate line GLi+1Q via the second output node No2 based on the voltage of the first control node line. For example, the 27th TFT T27 may include a gate electrode connected to the first control node line Q, a first source / drain electrode connected to the second output node No2, and a second source / drain electrode connected to the even-numbered scan clock line. The 27th TFT T27 can be turned on based on the bootstrap voltage of the first control node line Q, and therefore can transmit the even-numbered scan clock sCLKe with a high voltage level provided by the even-numbered scan clock line as the (i+1)th scan signal SSi+1 to the (i+1)th gate line GLi+1 via the second output node No2 without voltage loss.

[0327] The 28th TFT T28 (or the odd-numbered second pull-down TFT) can transmit the third gate common power supply GVss3 to the (i+1)th gate line GLi+1QBo through the second output node No2 based on the voltage of the second control node line. For example, the 28th thin-film transistor T28 may include a gate electrode connected to the second control node line QBo, a first source / drain electrode connected to the second output node No2, and a second source / drain electrode connected to the third gate common power supply line.

[0328] The 29th TFT T29 (or the even-numbered second pull-down TFT) can transmit the third gate common power supply GVss3 to the (i+1)th gate line GLi+1QBe through the second output node No2 based on the voltage of the third control node line. For example, the 29th thin-film transistor T29 may include a gate connected to the third control node line QBe, a first source / drain electrode connected to the second output node No2, and a second source / drain electrode connected to the third gate common power supply line.

[0329] The third output buffer circuit OBC3 can output the i-th carry signal CSi and QBe based on the voltage level of each of the first to third control node lines Q and QBo, with a carry clock cCLK or a first gate common power supply GVss1.

[0330] The third output buffer circuit OBC3 according to embodiments of the present disclosure may include the thirtieth to the thirty-second TFTs T30 to T32.

[0331] The thirtieth TFT T30 (or the third pull-up TFT) can output a carry clock cCLK as the i-th carry signal CSi through the third output node No3 based on the voltage of the first control node line Q. For example, the thirtieth TFT T30 may include a gate electrode connected to the first control node line Q, a first source / drain electrode connected to the third output node No3, and a second source / drain electrode connected to the carry clock line. The thirtieth TFT T30 can be turned on based on the bootstrap voltage of the first control node line Q and can output a carry clock cCLK with a high voltage level as the i-th carry signal CSi, which has a high voltage level and no voltage loss through the carry clock line and through the third output node No3.

[0332] The 31st TFT T31 (or the odd-numbered third pull-down TFT) can output the first gate common power supply GVss1 as the i-th carry signal CSi through the third output node No3 based on the voltage of the second control node line QBo. For example, the 31st thin-film transistor T31 may include a gate electrode connected to the second control node line QBo, a first source / drain electrode connected to the third output node No3, and a second source / drain electrode connected to the first gate common power supply line.

[0333] The 32nd TFT T32 (or even the 3rd pull-down TFT) can output the first gate common power supply GVss1 as the i-th carry signal CSi through the third output node No3 based on the voltage of the third control node line QBe. For example, the 32nd TFT T32 may include a gate electrode connected to the third control node line QBe, a first source / drain electrode connected to the third output node No3, and a second source / drain electrode connected to the first gate common power supply line.

[0334] Alternatively, the coupling capacitor Cc can be formed between the first control node line Q and the third output node No3. Furthermore, the coupling capacitor Cc can be formed in at least one of the regions between the first control node line Q and the first output node No1, between the first control node line Q and the second output node No2, and between the first control node line Q and the third output node No3.

[0335] The second sensing control circuit SCC2 can be implemented to discharge the voltage of each of the second control node lines QBo and the third control node line QBe in response to the voltage of the fourth control node line Qm and the external sensing control signal Scs.

[0336] The second sensing control circuit SCC2 according to an embodiment of the present disclosure may include a first node discharge circuit NDC1 and a second node discharge circuit NDC2.

[0337] The first node discharge circuit NDC1 can discharge the voltage of the second control node line QBo in response to the voltage of the fourth control node line Qm and the externally sensed control signal Scs. As an example, the first node discharge circuit NDC1 can respond to the voltage of the fourth control node line Qm having a high voltage level and a high voltage level, thereby discharging the voltage of the second control node line QBo to the first gate common power supply line or resetting the voltage of the second control node line QBo to the first gate common power supply GVss1.

[0338] The first node discharge circuit NDC1 according to an embodiment of this disclosure may include the fortieth TFT T40 and the forty-first TFT T41.

[0339] The fortieth TFT T40 can transfer the first gate common power supply GVss1 to the forty-first TFT T41 in response to the voltage of the fourth control node line Qm. As an example, the fortieth thin-film transistor T40 can be turned on based on the high voltage level of the fourth control node line Qm, and a current path can be formed between the forty-first thin-film transistor T41 and the first gate common power supply GVss1.

[0340] In response to an external sensing control signal Scs, the forty-first TFT T41 can electrically connect the second control node line QBo to the fortieth TFT T40. As an example, the forty-first thin-film transistor T41 can be turned on based on the external sensing control signal Scs with a high voltage level and can form a current path between the second control node line QBo and the fortieth thin-film transistor T40. With the fortieth TFT T40 turned on based on a high voltage level of the fourth control node line Qm, the forty-first TFT T41 can be turned on based on the external sensing control signal Scs with a high voltage level. Therefore, as shown, the voltage of the second control node line QBo can be discharged to the first gate common power line through each of the forty-first TFT T41 and the fortieth TFT T40, or can be reset to the first gate common power supply GVss1.

[0341] The second node discharge circuit NDC2 can discharge the voltage of the third control node line QBe in response to the voltage of the fourth control node line Qm and the externally sensed control signal Scs. As an example, the second node discharge circuit NDC2 can respond to the voltage of the fourth control node line Qm having a high voltage level and a high voltage level, thereby discharging the voltage of the third control node line QBe to the first gate common power supply line or resetting the voltage of the third control node line QBe to the first gate common power supply GVss1.

[0342] The second node discharge circuit NDC2 according to an embodiment of this disclosure may include a forty-second TFT T42 and a forty-third TFT T43.

[0343] The forty-second TFT T42 can transfer the first gate common power supply GVss1 to the forty-third TFT T43 in response to the voltage of the fourth control node line Qm. As an example, the forty-second TFT T42 can be turned on based on a high voltage level of the fourth control node line Qm and can form a current path between the forty-third TFT T43 and the first gate common power supply GVss1.

[0344] In response to an external sensing control signal Scs, the forty-third TFT T43 can electrically connect the third control node line QBe to the forty-second TFT T42. As an example, the forty-third thin-film transistor T43 can be turned on based on an external sensing control signal Scs with a high voltage level and can form a current path between the third control node line QBe and the forty-second thin-film transistor T42. With the forty-second TFT T42 turned on based on a high voltage level of the fourth control node line Qm, the forty-third TFT T43 can be turned on based on the external sensing control signal Scs with a high voltage level. Therefore, the voltage of the third control node line QBe can be discharged to the first gate common power supply line or reset to the first gate common power supply GVss1 through the forty-third thin-film transistor T43 and the forty-second thin-film transistor T42, respectively.

[0345] Alternatively, the second sensing control circuit SCC2 can be omitted along with the first sensing control circuit SCC1. That is, each of the first sensing control circuit SCC1 and the second sensing control circuit SCC2 can be a circuit for sensing the feature value of the driving TFT disposed in the sub-pixel of the pixel based on the external sensing mode of the pixel, and when the pixel is not driven in the external sensing mode, each of the first sensing control circuit SCC1 and the second sensing control circuit SCC2 may be an undesirable component and therefore may be omitted.

[0346] Figure 10 and 11 The first to forty-third TFTs T1 to T43 shown can be arranged dispersedly (or separately, or distributed along a horizontal line of the display area AA) and can be connected to each other through the i-th branch network BNi. Therefore, they can be configured... Figure 8The plurality of branch circuits 1511 to 151n shown. For example, each stage circuit portion 1501 to 150m may include first to nth (where n is 43) branch circuits 1511 to 151n, wherein one of the first to forty-third TFTs T1 to T43 is arranged or provided, but embodiments of the present disclosure are not limited thereto, and each of the plurality of branch circuits 1511 to 151n may be implemented with at least one of the first to forty-third TFTs T1 to T43 based on the number of pixels arranged on a horizontal line.

[0347] In addition, Figures 9 to 11 In the stage circuit section 150i shown, when the first switch TFT Tsw1 and the second switch TFT Tsw2 are set... Figure 1 When the pixel circuit PC of each of the multiple sub-pixels SP1 to SP4 shown is in the pixel circuit, Figure 4 The scan signals shown are turned on based on different first and second scan signals. The i-th scan signal SSi can be used as the first gate line through the odd-numbered gate line GLo, and the (i+1)-th scan signal SSi+1 can be used as the first scan signal through the even-numbered gate line GLe. Therefore, Figures 9 to 11 The output buffer circuit OBC of the stage circuit section 150i shown is not limited to this. Figures 9 to 11 It may also include a fourth output buffer circuit and a fifth output buffer circuit.

[0348] The fourth output buffer circuit can be implemented to output a second scan signal to the second gate line of the odd-numbered gate line GLo, and the fifth output buffer circuit can be implemented to output a second scan signal to the second gate line of the even-numbered gate line GLe.

[0349] According to embodiments of this disclosure, the fourth output buffer circuit can output the i-th second scan signal based on the voltage level of the second scan odd-numbered scan clock or the voltage level of the third gate common power supply GVss3. The first to third control node lines Q, QBo, and QBe. Besides the fourth output buffer circuit outputting the i-th second scan signal based on the second scan odd-numbered scan clock, the fourth output buffer circuit may include... Figure 11 The three TFTs of the first output buffer circuit OBC1 shown are basically the same, so their repeated descriptions are omitted.

[0350] According to an embodiment of this disclosure, the fifth output buffer circuit can output a second scan signal (i+1) based on a voltage level having a second scan even-numbered scan clock or a voltage level having a third gate common power supply GVss3. Each of the first to third control node lines Q, QBo, and QBe. In addition to the fifth output buffer circuit outputting the second scan signal based on a second scan even-numbered scan clock, the fifth output buffer circuit may include three TFTs substantially identical to the second output buffer circuit OBC2, as shown in the figure. (Refer to...) Figure 11 Therefore, its repeated description is omitted.

[0351] exist Figures 9 to 11 In the i-th stage circuit section 150i shown, the odd-numbered scan clock sCLKo can be referred to as the first scan odd-numbered scan clock, and the even-numbered scan clock sCLKe can be referred to as the first scan even-numbered scan clock. For example, the first scan clock and the second scan clock can have the same phase or different phases. Furthermore, the first scan clock and the second scan clock can have the same clock width or different clock widths.

[0352] exist Figures 9 to 11 In the i-th stage circuit section 150i shown, each of the third control node line QBe, the fourth node control circuit NCC4 which controls the voltage of the third control node line QBe, the second node discharge circuit NDC2, and the second output buffer circuit OBC2 can be omitted, depending on the driving mode (or method) of the gate drive circuit 150.

[0353] Figure 12 It is along Figure 5 The cross-sectional view of the line I-I' shown. Figure 13 yes Figure 12 An enlarged view of area "C" shown. Figure 14 It is along Figure 5 The cross-sectional view of line II-II' shown. Figure 15 yes Figure 14 A magnified view of area "D" shown.

[0354] Reference Figure 5 and Figures 12 to 15 The light-emitting display device according to the embodiments of the present disclosure may include a first substrate 100, a second substrate 200, a bonding member 300 and a wiring portion 400.

[0355] According to embodiments of the present disclosure, the first substrate 100 may include a circuit layer 101, a planarization layer 102, a light-emitting device layer (EDL), a dam 103, and a first pad portion 110.

[0356] The circuit layer 101 may be disposed above the first substrate 100. The circuit layer 101 may be referred to as a pixel array layer or a TFT array layer.

[0357] The circuit layer 101 according to embodiments of the present disclosure may include a buffer layer 101a and a circuit array layer 101b.

[0358] The buffer layer 101a prevents materials such as hydrogen contained in the first substrate 100 from diffusing to the circuit array layer 101b during the high-temperature processes of manufacturing TFTs. Furthermore, the buffer layer 101a prevents external water or moisture from penetrating the light-emitting device layer (EDL). The buffer layer 101a according to embodiments of this disclosure may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or multiples thereof, but embodiments of this disclosure are not limited thereto. For example, the buffer layer 101a may include a first buffer layer BL1 comprising SiNx and disposed on the first substrate 100, and a second buffer layer BL2 comprising SiOx and disposed on the first buffer layer BL1.

[0359] The circuit array layer 101b may include a pixel circuit PC, which includes a driving TFT Tdr in each of a plurality of pixel regions PA disposed above the buffer layer 101a.

[0360] The driving TFT Tdr disposed in the circuit area of ​​each pixel region PA may include an active layer ACT, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer 101c, a first source / drain electrode SD1, a second source / drain electrode SD2, and a passivation layer 101d.

[0361] An active layer ACT can be disposed on the buffer layer 101a in each pixel region PA. The active layer ACT may include a channel region overlapping with the gate electrode GE, and a first source / drain region and a second source / drain region parallel to each other between adjacent channel regions. The active layer ACT can be conductive during conduction, and therefore can serve as a bridging wire for a jumper structure that directly connects lines in the display area AA or electrically connects lines on different layers.

[0362] The gate insulating layer GI can be disposed on the channel region of the active layer ACT. The gate insulating layer GI can insulate the active layer ACT from the gate electrode GE.

[0363] The gate electrode GE can be disposed on the gate insulating layer GI and connected to the gate line. The gate electrode GE can overlap with the channel region of the active layer ACT, with the gate insulating layer GI located therebetween.

[0364] An interlayer insulating layer 101c may be disposed at the first substrate 100 to cover the gate electrode GE and the active layer ACT. The interlayer insulating layer 101c may electrically insulate (or isolate) the gate electrode GE and the source / drain electrodes SD1 and SD2.

[0365] The first source / drain electrode SD1 can be disposed on the interlayer insulating layer 101c overlapping the first source / drain region of the active layer ACT, and can be electrically connected to the first source / drain region of the active layer ACT through the first source / drain region. A drain contact hole is disposed in the interlayer insulating layer 101c. For example, the first source / drain electrode SD1 can be the source electrode for driving the TFT Tdr, and the first source / drain region of the active layer ACT can be the source region.

[0366] The second source / drain electrode SD2 can be disposed on the interlayer insulating layer 101c overlapping the second source / drain region of the active layer ACT, and can be electrically connected to the second source / drain region of the active layer ACT through the second source / drain region. A drain contact hole is disposed in the interlayer insulating layer 101c. For example, the second source / drain electrode SD2 can be the drain electrode for driving the TFT Tdr, and the second source / drain region of the active layer ACT can be the drain region.

[0367] The passivation layer 101d can be disposed above the first substrate 100 to cover the pixel circuit PC including the driving TFT Tdr.

[0368] According to embodiments of this disclosure, when the interlayer insulating layer 101c is not disposed on the peripheral portion of the first substrate 100, the passivation layer 101d disposed on the peripheral portion of the first substrate 100 can directly contact the buffer layer 101a. For example, the passivation layer 101d can be referred to as a protective layer, circuit protective layer, insulating layer, circuit insulating layer, etc. For example, the passivation layer 101d can be formed of an inorganic insulating material, but embodiments of this disclosure are not limited thereto.

[0369] Each of the first and second switching TFTs Tsw1 and Tsw2 that constitute the pixel circuit PC can be formed with a driving TFT Tdr, therefore a detailed description of them is omitted.

[0370] According to an embodiment of the present disclosure, the circuit layer 101 may further include a lower metal layer BML disposed between the first substrate 100 and the buffer layer 101a.

[0371] The lower metal layer (BML) may also include a light-blocking pattern (or light-blocking layer) LSP disposed below (or beneath) the active layer ACT of each of the TFTs Tdr, Tsw1, and Tsw2 constituting the pixel circuit PC.

[0372] A light-blocking pattern LSP can be disposed in an island-like configuration between the first substrate 100 and the active layer ACT. The light-blocking pattern LSP can block light incident on the active layer ACT through the first substrate 100, thereby preventing or minimizing threshold voltage variations in each TFT caused by external light. Optionally, the light-blocking pattern LSP can be electrically connected to the first source / drain electrode SD1 of the corresponding TFT, thereby serving as the lower gate electrode of the corresponding TFT. In this case, characteristic variations in each TFT can be minimized, reduced, or prevented due to light and threshold voltage variations in each TFT caused by bias voltage.

[0373] The lower metal layer BML can be used as a line for gate lines GL, data lines DL, pixel drive power lines PL, pixel common voltage lines CVL, and reference voltage lines RL arranged parallel to each other. For example, the lower metal layer BML can be used as a line (or metal layer) 100 arranged in a second direction Y parallel to the pixel drive lines DL, GL, PL, CVL, RL, and GCL arranged on the first substrate.

[0374] Planarization layer 102 may be disposed above first substrate 100 and may provide a flat surface above circuit layer 101. Planarization layer 102 may cover circuit layer 101, which includes driving TFTs Tdr disposed at each of a plurality of pixel regions PA. Planarization layer 102 according to embodiments of the present disclosure may be formed of organic insulating material, but embodiments of the present disclosure are not limited thereto. Planarization layer 102 according to embodiments of the present disclosure may be formed to cover the remaining circuit layer 101 except for the peripheral portion of passivation layer 101d disposed at first substrate 100. For example, planarization layer 102 may be disposed between passivation layer 101d and light-emitting device layer EDL or disposed below light-emitting device layer EDL.

[0375] The light-emitting device layer (EDL) can be disposed above the planarization layer 102. According to embodiments of this disclosure, the light-emitting device layer (EDL) may include a pixel electrode (PE), a self-emissive device (ED), and a common electrode (CE).

[0376] The pixel electrode PE can be referred to as the anode electrode, reflective electrode, lower electrode, anode, or first electrode of a self-emissive device ED.

[0377] A pixel electrode PE can be disposed on the planarization layer 102, overlapping the emission region EA of each of the plurality of sub-pixels SP in the first substrate 100. The pixel electrode PE can be patterned as an island and disposed in each sub-pixel SP, and can be electrically coupled to the first source / drain electrode SD1 of the driving TFT Tdr of the corresponding pixel circuit PC. For example, one side of the pixel electrode PE can extend onto the first source / drain electrode SD1 of the driving TFT Tdr, and can be electrically coupled to the first source / drain electrode SD1 of the driving TFT Tdr through a provided electrode contact hole ECH. In the planarization layer 102...

[0378] The pixel electrode PE can include a metallic material with low work function and good reflection efficiency.

[0379] According to embodiments of the present disclosure, the pixel electrode PE may have a bilayer structure including a first pixel electrode layer (or a first metal layer) PEL1 and a second pixel electrode layer (or a second metal layer) PEL2. The first pixel electrode layer PEL1 and the second pixel electrode layer PEL2 may be deposited sequentially on top of the planarization layer 102 and then patterned simultaneously, but embodiments of the present disclosure are not limited thereto.

[0380] The first pixel electrode layer PEL1 can be disposed above the planarization layer 102. The second pixel electrode layer PEL2 can be disposed (or stacked) on the first pixel electrode layer PEL1. For example, the first pixel electrode layer PEL1 can serve as an adhesive layer corresponding to the planarization layer 102 and can serve as a secondary electrode of the self-emissive device ED. In addition, it can include indium tin oxide (ITO) or indium zinc oxide (IZO), but the embodiments of this disclosure are not limited thereto. For example, the second pixel electrode layer PEL2 can serve as a reflector and can perform the function of reducing the resistance of the pixel electrode PE. In addition, it can include a material selected from aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti), and Mo-Ti alloy (MoTi), but the embodiments of this disclosure are not limited thereto. For example, the pixel electrode PE according to the embodiments of this disclosure can be formed as a two-layer structure of ITO / MoTi or IZO / MoTi.

[0381] According to another embodiment of the present invention, the pixel electrode PE can have a three-layer structure, including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 on the first pixel electrode layer PEL1, and a third pixel electrode layer (or a third metal layer) PEL3 located on the second pixel electrode layer PEL2. The third pixel electrode layer PEL3 can serve as an electrode of a self-emissive device ED and can include ITO or IZO. For example, according to another embodiment of the present disclosure, the pixel electrode PE can be formed as a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO.

[0382] According to another embodiment of the present invention, the pixel electrode PE may have a four-layer structure, including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 on the first pixel electrode layer PEL1, a third pixel electrode layer (or a third pixel electrode metal layer) PEL3 on the second pixel electrode layer PEL2, and a fourth pixel electrode layer (or a fourth metal layer) on the third pixel electrode layer PEL3.

[0383] In the four-layer pixel electrode PE structure, the first pixel electrode layer can serve as an adhesive layer corresponding to the planarization layer 102, and can also serve as a sub-electrode of the self-emissive device ED. Furthermore, it may include one or more ITO, Mo, and MoTi materials. The second pixel electrode layer can reduce the resistance of the pixel electrode PE and may include Cu. The third pixel electrode layer can serve as a reflector and may include one or more materials selected from Al, Ag, Mo, Ti, and MoTi. The fourth pixel electrode layer can serve as an electrode of the self-emissive device ED and may include ITO or IZO. For example, according to another embodiment of this disclosure, the pixel electrode PE can be formed as a four-layer structure of ITO / Cu / MoTi / ITO.

[0384] According to another embodiment of the present invention, the pixel electrode PE may have a five-layer structure, including a first pixel electrode layer made of ITO, a second pixel electrode layer made of MoTi, a third pixel electrode layer made of ITO, a fourth pixel electrode layer, and an electrode layer made of Ag. The fifth pixel electrode layer is ITO.

[0385] The self-emissive device ED can be disposed on the first substrate 100. The self-emissive device ED can be formed on the pixel electrode PE and can directly contact the pixel electrode PE. The pixel electrode PE can be disposed below (or beneath) the self-emissive device ED. For example, the pixel electrode PE can be disposed between the planarization layer 102 and the self-emissive device ED.

[0386] The self-emissive device ED according to embodiments of the present disclosure may be a common layer formed in each of a plurality of sub-pixels SP so as not to be distinguished by sub-pixel SP units. The self-emissive device ED may respond to current flowing between the pixel electrode PE and the common electrode CE to emit white light (or blue light). The self-emissive device ED according to embodiments of the present disclosure may include an organic light-emitting device, or may include a stacked or combined structure of organic light-emitting devices and quantum dot light-emitting devices. For example, the self-emissive device ED according to another embodiment of the present disclosure may include an organic light-emitting layer, or may include a stacked or combined structure of an organic light-emitting layer and a quantum dot light-emitting layer.

[0387] The organic light-emitting device according to embodiments of this disclosure may include two or more organic light-emitting components for emitting white light (or blue light). For example, the organic light-emitting device may include a first organic light-emitting portion and a second organic light-emitting portion for emitting white light based on a combination of a first light and a second light. For example, the first organic light-emitting portion may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer. The second organic light-emitting portion may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer for emitting a second light. It combines with the first light from the first organic light-emitting portion to generate white light.

[0388] The organic light-emitting device according to embodiments of this disclosure may further include at least one or more functional layers for improving luminous efficiency and / or lifetime. For example, the functional layers may be disposed above and / or below the light-emitting layer.

[0389] A common electrode CE can be disposed above the display area AA of the first substrate 100 and can be electrically coupled to the self-emissive device ED of each of the plurality of pixels P. For example, the common electrode CE can be disposed in the remaining display area AA of the first substrate 100, excluding the first pad portion 110 of the first substrate 100.

[0390] The common electrode CE can be referred to as the cathode electrode, transparent electrode, upper electrode, cathode, or second electrode of the self-emissive device ED. The common electrode CE can be formed on the self-emissive device ED and can directly contact the self-emissive device ED or can electrically and directly contact the self-emissive device ED. The common electrode CE may include a transparent conductive material that transmits light emitted from the self-emissive device ED.

[0391] The common electrode CE according to embodiments of this disclosure can be formed as a single-layer or multi-layer structure, comprising at least one material selected from graphene and a transparent conductive material with a high work function. For example, the common electrode CE may comprise a metal oxide such as ITO or IZO, or may comprise a combination of oxides and metals such as ZnO:Al or SnO2:Sb.

[0392] Furthermore, the light-emitting device layer (EDL) may also include a capping layer disposed above the common electrode (CE). The capping layer can be disposed above the common electrode (CE) and the light emission efficiency can be improved by adjusting the refractive index of the light emitted from the light-emitting device layer (EDL).

[0393] A dam 103 may be disposed above the planarization layer 102 to define (e.g., laterally surround) a pixel region PA above the first substrate 100. The dam 103 may be disposed above the planarization layer 102 to cover the peripheral portion of the pixel electrode PE. The dam 103 may define (e.g., laterally surround) an emission region EA (or opening portion) of each of the plurality of sub-pixels SP and may electrically isolate the pixel electrodes PE disposed in adjacent sub-pixels SP. The dam 103 may be formed to cover the electrode contact hole ECH disposed in each of the plurality of pixel regions PA. The dam 103 may be covered by a self-emissive device ED of the light-emitting device layer EDL. For example, the self-emissive device ED may be disposed above the dam 103 and above the pixel electrode PE of each of the plurality of sub-pixels SP.

[0394] According to embodiments of the present disclosure, the dam 103 may be a transparent dam comprising a transparent material or a black dam comprising black pigment (or an opaque dam).

[0395] The first pad portion 110 may be disposed at a peripheral portion of the first substrate 100 and may be electrically coupled to the pixel driving lines DL, GL, PL, CVL, RL and GCL in a one-to-one relationship.

[0396] According to embodiments of the present disclosure, the first pad portion 110 may include a plurality of first pads 111. The plurality of first pads 111 may be divided (or classified) into a first data pad DP1, a first gate pad GP1, a first pixel drive power pad PPP1, a first reference voltage pad RVP1, and a first pixel common voltage pad CVP1, as shown in the reference... Figure 3 and Figure 4 The descriptions are as described, therefore repeated descriptions are omitted.

[0397] Each of the plurality of first pads 111 can be electrically coupled to a corresponding line 101c and a buffer layer 101a of pixel drive lines DL, GL, PL, CVL, RL, and GCL through a pad contact hole PCH passing through the passivation layer 101d and the interlayer insulating layer. Each of the plurality of first pads 111 according to an embodiment of the present disclosure may include the same material as the pixel electrode PE and may be formed together with the pixel electrode PE. According to another embodiment of the present disclosure, each of the plurality of first pads 111 may include the same material as the source / drain electrodes of the TFT and may be formed together with the source / drain electrodes of the TFT.

[0398] The light-emitting display device or the first substrate 100 according to the embodiments of this disclosure may further include a device isolation portion 104, a dam portion 105, and an encapsulation layer 106.

[0399] Reference Figure 12 , 14According to embodiments of the present disclosure, the device isolation portion 104 may be disposed on the peripheral portion of the first substrate 100 or the peripheral portion of the outermost pixel. For example, the outermost pixel disposed on the peripheral portion of the first substrate 100 may include the device isolation portion 104, and thus may be implemented to have a different configuration or structure than the inner pixels. In the following description, the device isolation portion 104 may be referred to as isolation portion 104.

[0400] The isolation portion 104 can be implemented to isolate (or disconnect) the self-emissive device ED. The isolation portion 104 can be implemented to prevent water or moisture from penetrating in the lateral direction of the first substrate 100, thereby preventing the self-emissive device ED from deteriorating due to lateral penetration of water or moisture. The isolation portion 104 can isolate (or disconnect) the self-emissive device ED of the light-emitting device layer EDL at least once near the dam portion 105, thus preventing lateral penetration of water or moisture. For example, the isolation portion 104 can be an isolation region, isolation line, disconnection region, or disconnection line of the self-emissive device ED.

[0401] The isolation portion 104 can be implemented on the interlayer insulating layer 101c in the first substrate 100 to surround the display area AA. For example, the isolation portion 104 can be implemented in a closed loop shape on the interlayer insulating layer 101c to surround the display area AA in one dimension.

[0402] The isolation portion 104 according to embodiments of the present disclosure may include a plurality of device isolation patterns 104a to 104d disposed above an interlayer insulating layer 101c in the outermost pixel. For example, the isolation portion 104 may include first to third device isolation patterns 104a, 104b, and 104c implemented parallel to each other to have a closed-loop shape. In the following description, the device isolation pattern may be referred to as an isolation pattern.

[0403] Each of the first to third isolation patterns 104a, 104b and 104c according to embodiments of the present disclosure may include a first trench structure TS1, a metal pattern layer MPL and a second trench structure TS2.

[0404] The first trench structure TS1 can be implemented by a passivation layer 101d. The first trench structure TS1 can be formed by a patterning process performed on the passivation layer 101d located at the outermost pixel. For example, the first trench structure TS1 can be formed by a patterning process performed on the passivation layer 101d using an etching process. For example, the first trench structure TS1 can be referred to as a first isolation structure, a first tapered structure, etc.

[0405] The side surface (or side surface) of the first groove structure TS1 according to an embodiment of the present disclosure can be implemented as an inclined structure or a conical structure. For example, the cross-sectional surface of the first groove structure TS1 cut along the width direction can have a trapezoidal cross-sectional structure, wherein the upper side is narrower than the lower side.

[0406] A metal patterned layer (MPL) can be disposed above the first trench structure TS1. The MPL can have at least two layers identical to the pixel electrode PE. For example, the MPL may include a first metal layer formed together with the first pixel electrode layer PEL1 of the pixel electrode PE and directly contacting the top surface of the first trench structure TS1, and a second metal layer formed together with the first pixel electrode layer PEL1 of the pixel electrode PE and directly contacting the top surface of the first trench structure TS1. A second pixel electrode layer PEL2 of the pixel electrode PE is formed and disposed (or stacked) above the first metal layer. For example, in the MPL, the first metal layer may be ITO material, and the second metal layer may be molybdenum-titanium alloy (MoTi), but the embodiments of this disclosure are not limited thereto.

[0407] The metal patterned layer MPL can have a width wider than the top surface of the first trench structure TS1. The side surfaces of the metal patterned layer MPL can be implemented with an inclined structure or a conical structure. For example, the cross-section of the metal patterned layer MPL taken along the width direction can have a cross-sectional structure with the same trapezoidal shape as the first trench structure TS1. Regarding the width direction, each of the outer peripheral portions on one side and the other side of the metal patterned layer MPL can protrude beyond the outer side of the side surface of the first trench structure TS1.

[0408] The side surface of the first groove structure TS1 may have an undercut structure relative to the metal pattern layer MPL. For example, the boundary portion between the first groove structure TS1 and the metal pattern layer MPL, or the upper side surface (or upper surface) of the first groove structure TS1, may have an undercut structure relative to the metal pattern layer MPL. Therefore, the metal pattern layer MPL may have an eaves structure relative to the first groove structure TS1. It should be understood that "eaves structure" includes the meaning of overhanging portions. For example, as shown in the figure. Refer to Figure 15 The metal pattern layer MPL extends (e.g., beyond) the upper surface and sidewalls of the first trench structure TS1 at its left and right ends along the Y-axis direction.

[0409] The second trench structure TS2 can be disposed above the metal pattern layer MPL. For example, the second trench structure TS2 can be referred to as a second isolation structure, a second conical structure, etc.

[0410] The second trench structure TS2 may include an organic insulating material. The second trench structure TS2 according to embodiments of this disclosure may include the same material as the embankment 103, but embodiments of this disclosure are not limited thereto.

[0411] The lower surface of the second trench structure TS2 can have the same width as the top surface of the metal pattern layer MPL. In the second trench structure TS2, the upper surface can have the same width as the lower surface or a narrower width. For example, the side surfaces of the second trench structure TS2 can be implemented as an inclined structure or a conical structure.

[0412] As described above, the isolation portion 104, including the first to third isolation patterns 104a, 104b, and 104c, can isolate (or disconnect) the self-emitting device ED, or can isolate (or disconnect) the self-emitting device ED and the common electrode CE. For example, the self-emitting device ED formed (or deposited) above the isolation portion 104 can be automatically isolated (or disconnected) during the deposition process performed through the undercut structure (or overhang structure) of each of the first to third isolations. Patterns 104a, 104b, and 104c do not require separate isolation processes. Therefore, the self-emitting device ED can include an isolation region isolated by the isolation portion 104.

[0413] According to embodiments of this disclosure, the deposition material of the self-emissive device ED made of organic light-emitting devices can be linear, and therefore, it can be omitted from deposition on the side surface of the first trench structure TS1 covered by the organic light-emitting devices. The metal patterning layer MPL is based on the undercut structure (or overhang structure) of each of the first to third isolation patterns 104a, 104b, and 104c. Therefore, the self-emissive device ED formed (or deposited) over the isolation portion 104 can be between the first trench structure TS1 and the first to third isolation patterns 104a, 104b, 104b, 104b, 104b, 104b, and 104c. Therefore, during the deposition process, the self-emissive device ED can be automatically isolated (or disconnected) by the first to third isolation patterns 104a, 104b, and 104c of the isolation portion 104, and thus, the separate patterning process (or disconnection) of the self-emissive device ED can be omitted. Therefore, the self-emissive device ED disposed above the first substrate 100 can be isolated (or disconnected) at the peripheral portion of the first substrate 100, thus the lateral water permeation path of the first substrate 100 can be blocked by the first substrate. This is achieved through the third isolation patterns 104a, 104b, and 104c to the isolation portion 104.

[0414] Optionally, when performing a deposition-based deposition process, the common electrode CE disposed above the self-emitting device ED can be automatically isolated (or disconnected) by the first to third isolation patterns 104a, 104b and 104c of the isolation portion 104, or when performing a deposition-based deposition process, island-shaped self-emitting devices EDi and the first to third isolation patterns 104a, 104b and 104c of the isolation portion 104 can be formed around all the isolated self-emitting devices EDi.

[0415] Reference Figure 12 , 14 According to embodiments of the present disclosure, the dam portion 105 can be disposed on the peripheral portion of the first substrate 100 or the peripheral portion of the outermost pixel. For example, the outermost pixel disposed on the peripheral portion of the first substrate 100 may also include the dam portion 105, and thus can be implemented to have a different configuration or structure than the inner pixels.

[0416] The dam 105 can be disposed on the circuit layer 101 of the peripheral portion of the first substrate 100 or the peripheral portion of the outermost pixel to have a closed loop shape. For example, the dam 105 can be disposed above the passivation layer 101d of the circuit layer 101 to have a closed loop shape surrounding the display area AA. The dam 105 can prevent the encapsulation layer 106 disposed above the first substrate 100 to cover the display area AA from diffusing or overflowing.

[0417] The dam portion 105 can be disposed between two adjacent isolation patterns among the plurality of isolation patterns 104a, 104b, and 104c. For example, the dam portion 105 can be implemented as a closed loop shape to surround the first isolation pattern 104a and can be implemented to be surrounded by the second and third isolation patterns 104b and 104c. For example, the dam portion 105 can be disposed between the first isolation pattern 104a and the second isolation pattern 104b of the isolation portion 104.

[0418] The dam section 105 according to an embodiment of this disclosure may include the same material as the planarization layer 102. The dam section 105 may have the same height (or thickness) as the planarization layer 102, or it may have a height higher than the planarization layer 102. For example, the height (or thickness) of the dam section 105 may be twice the height (or thickness) of the planarization layer 102.

[0419] According to another embodiment of this disclosure, the dam section 105 may include a first dam pattern (or lower dam) 105a and a second dam pattern (or upper dam) 105b formed of the same material as the planarization layer 102, stacked on the first dam pattern 105a and comprising the same material as the dike 103. The first dam pattern 105a may have the same height (or thickness) as the planarization layer 102, or it may have a height greater than the planarization layer 102. For example, the height (or thickness) of the first dam pattern 105a may be twice the height (or thickness) of the planarization layer 102.

[0420] Reference Figures 12 to 15 According to embodiments of the present disclosure, the encapsulation layer 106 can be disposed on the remaining portion of the first substrate 100 except for the outermost portion including the first pad portion 110, and can be implemented to cover the light emitting device layer EDL. For example, the encapsulation layer 106 can be implemented to surround all front and side surfaces of the light emitting device layer EDL, thereby preventing oxygen or water (or moisture) from penetrating into the light emitting device layer EDL, thereby improving the reliability of the light emitting device layer EDL from oxygen or water (or moisture).

[0421] According to embodiments of the present disclosure, the encapsulation layer 106 may include first to third encapsulation layers 106a to 106c.

[0422] A first encapsulation layer 106a can be implemented to prevent oxygen or water from penetrating into the light-emitting device layer EDL. The first encapsulation layer 106a can be disposed above the common electrode CE and can surround the light-emitting device layer EDL. Therefore, all front and side surfaces of the light-emitting device layer EDL can be surrounded by the first encapsulation layer 106a. The first encapsulation layer 106a according to embodiments of this disclosure may include an inorganic insulating material.

[0423] When the self-emitting device ED and the common electrode CE are isolated by the isolation portion 104, the first encapsulation layer 106a can be isolated by the isolation portion 104 around the isolation surface (or disconnected surface) of the self-emitting device ED and the common electrode CE. For example, the first encapsulation layer 106a can fill (or bury) the isolation space between the self-emitting device ED and the common electrode CE, which is formed by the isolation structure (or undercut structure) of the isolation portion 104. The portion 104 seals or completely surrounds the isolation portion 104, thus completely surrounding or covering each of the isolated self-emitting device ED and the common electrode CE, thereby fundamentally (or completely) preventing lateral penetration of water (or moisture).

[0424] The second encapsulation layer 106b may be implemented on the first encapsulation layer 106a to have a thickness relatively thicker than the first encapsulation layer 106a. The second encapsulation layer 106b may have a thickness sufficient to completely cover the first encapsulation layer 106a or to cover particles (or undesirable materials or undesirable structural elements) on the first encapsulation layer 106a. Due to its relatively thick thickness, the second encapsulation layer 106b may extend to the peripheral portion of the first substrate 100, but the extension of the second encapsulation layer 106b may be blocked by a dam 105. The second encapsulation layer 106b may be referred to as a particle cover layer. The second encapsulation layer 106b according to embodiments of this disclosure may include an organic insulating material or a liquid organic insulating material.

[0425] A third encapsulation layer 106c can be implemented to primarily prevent oxygen or water from penetrating into the light-emitting diode layer (EDL). The third encapsulation layer 106c can be implemented around all the second encapsulation layers 106b disposed on the inner side of the dam 105 and the first encapsulation layer 106a disposed on the outer side of the dam 105. According to embodiments of the present disclosure, the third encapsulation layer 106c may include the same or different inorganic insulating material as the first encapsulation layer 106a.

[0426] According to embodiments of the present disclosure, the light-emitting display device or the first substrate 100 may further include a first edge region MA1, a second edge region MA2, and a dam region DA.

[0427] The first edge region MA1 can be disposed between the emission region EA of the outermost pixel Po and the dam 105. The first edge region MA1 can be configured to provide a reliability margin between the outermost pixel Po and the dam 105 based on the reliability tolerance of the light-emitting device layer EDL caused by water or moisture or lateral seepage of moisture in the emission region EA. Therefore, the dam 105 can be implemented to be spaced apart from the end of the emission region EA by a first width of the first edge region MA1 relative to the first direction X.

[0428] A second edge region MA2 can be disposed between the outer surface OS of the first substrate 100 and the dam 105. The second edge region MA2 can be configured to have a second width portion 105 between the outer surface OS of the first substrate 100 and the dam, based on a reliability margin of the light-emitting device layer EDL caused by lateral water penetration or moisture. Therefore, the dam 105 can be implemented to separate the second edge region MA2 from the outer surface OS of the first substrate 100 by a second width relative to the first direction X. For example, the second edge region MA2 can be a region including a first pad portion 110 and second and third isolation patterns 104b and 104c.

[0429] The dam area DA can be located between the first edge region MA1 and the second edge region MA2. The dam area DA can be configured to have a third width corresponding to the width of the lowest bottom surface (or bottom surface) of the dam section 105. For example, the dam area DA can be the region that includes the dam section 105.

[0430] Regarding the first direction X, the width of each of the first edge region MA1, the second edge region MA2, and the dam region DA can be implemented such that the second interval D2 between the center portion of the outermost pixel and the outer pixel, and the surface OS of the first substrate 100, is half or less of the pixel pitch (first interval D1) between two adjacent pixel regions PA.

[0431] Refer again Figures 12 to 14 According to embodiments of the present disclosure, the light-emitting display device or the first substrate 100 may further include a wavelength conversion layer 107 disposed above the encapsulation layer 106.

[0432] The wavelength conversion layer 107 can convert the wavelength of light incident on each pixel region PA from its emission region. For example, the wavelength conversion layer 107 can convert white light (or blue light) incident on the emission region into light of the color corresponding to the sub-pixel SP, or it can transmit only light of the color corresponding to the sub-pixel SP. For example, the wavelength conversion layer 107 may include at least one of a wavelength conversion component and a color filter layer.

[0433] The wavelength conversion layer 107 according to embodiments of the present disclosure may include a plurality of wavelength conversion components 107a and a protective layer 107b.

[0434] Multiple wavelength conversion components 107a may be disposed on an encapsulation layer 106, which is disposed at the emission region EA of each of the multiple sub-pixels SP. For example, each of the multiple wavelength conversion components 107a may be implemented to have the same or wider size as the emission region EA of each sub-pixel SP.

[0435] According to embodiments of the present disclosure, multiple wavelength conversion components 107a can be divided (or classified) into red light filters that convert white light to red light, green light filters that convert white light to green light, and blue light filters. For example, a red light filter (or a first filter) can be disposed above the encapsulation layer 106 in the emission region EA of the red sub-pixel SP, a green light filter (or a second filter) can be disposed above the encapsulation layer 106 located in the emission region EA of the green sub-pixel SP, and a blue filter (or a third filter) can be disposed above the encapsulation layer 106 in the emission region EA of the blue sub-pixel SP.

[0436] According to another embodiment of this disclosure, a plurality of wavelength conversion components 107a may be disposed above the encapsulation layer 106 of each sub-pixel SP. For example, each of the plurality of wavelength conversion components 107a may be disposed above the encapsulation layer 106 to overlap the entire corresponding sub-pixel SP.

[0437] According to another embodiment of this disclosure, multiple wavelength conversion members 107a can be implemented to overlap each other at an encapsulation layer 106 that overlaps with a circuit region CA (or non-emitting region) in addition to the emitting region EA of each sub-pixel. For example, two or more wavelength conversion members 107a of different colors are disposed at the encapsulation layer 106, overlapping with the circuit region CA (or non-emitting region) in addition to the emitting region EA of each sub-pixel SP. The two or more wavelength conversion members 107a disposed at the encapsulation layer 106 that overlap with the circuit region CA (or non-emitting region) can function as a light-blocking pattern to prevent color mixing between adjacent sub-pixels SP or adjacent pixels P.

[0438] The protective layer 107b may be implemented to cover the wavelength conversion member 107a and provide a flat surface above the wavelength conversion member 107a. The protective layer 107b may be configured to cover both the wavelength conversion member 107a and an encapsulation layer 106 without the wavelength conversion member 107a. The protective layer 107b according to embodiments of this disclosure may include an organic insulating material. Alternatively, the protective layer 107b may also include an absorbent material for adsorbing water and / or oxygen.

[0439] Optionally, the wavelength conversion layer 107 according to another embodiment of this disclosure may include two or more layers of wavelength conversion members 107a disposed above the encapsulation layer 106, overlapping the circuit area CA (or non-emitting area) other than the emitting area EA. Each sub-pixel SP. The two or more layers of wavelength conversion members 107a may function as a light-blocking pattern.

[0440] Alternatively, the wavelength conversion layer 107 can be a sheet-like wavelength conversion sheet and can be disposed above the encapsulation layer 106. In this case, the wavelength conversion sheet (or quantum dot sheet) may include a wavelength conversion member 107a disposed between a pair of thin films. For example, when the wavelength conversion layer 107 includes quantum dots that re-emit colored light disposed in the sub-pixel, the light-emitting device layer EDL of the sub-pixel SP can be implemented to emit white or blue light.

[0441] Reference Figures 12 to 14 The light-emitting display device or the first substrate 100 according to the embodiments of this disclosure may further include a functional film 108.

[0442] The functional film 108 may be disposed above the wavelength conversion layer 107. For example, the functional film 108 may be coupled to the wavelength conversion layer 107 via a transparent adhesive member. The functional film 108 according to embodiments of the present disclosure may include an anti-reflective layer (or anti-reflective film), a blocking layer (or blocking film), a touch sensing layer, and an optical path control layer (or optical path control film).

[0443] The anti-reflection layer may include a circular polarization layer (or circular polarization film) that prevents external light reflected by the TFT and / or the pixel drive lines disposed on the substrate 10 from propagating to the outside.

[0444] The barrier layer may include a material with low water permeability (e.g., a polymer material) and may primarily prevent the penetration of water or oxygen.

[0445] The touch sensing layer may include a touch electrode layer based on mutual capacitance or self-capacitance methods, and touch data corresponding to the user's touch can be output through the touch electrode layer.

[0446] The optical path control layer can include a stacked structure of alternating high-refractive-index and low-refractive-index layers, and can change the path of light incident from each pixel P to minimize or reduce viewpoint-based color shift.

[0447] Reference Figures 12 to 14 The light-emitting display device or the first substrate 100 according to the embodiments of this disclosure may further include a side sealing member 109.

[0448] Side seal 109 may be formed between the first substrate 100 and the functional film 108 and may cover all side surfaces of the circuit layer 101 and the wavelength conversion layer 107. For example, side seal 109 may cover all lateral surfaces. The surface of each of the circuit layer 101 and the wavelength conversion layer 107 is exposed to the outside of the display device between the functional film 108 and the first substrate 100. In addition, side seal 109 may cover a portion of the trace portion 400. Side seal 109 may prevent lateral light leakage caused by light propagating from the interior of the wavelength conversion layer 107 to its outer surface and light emitted by itself. Each sub-pixel SP has a light-emitting device ED. In particular, the side seal member 109 overlapping with the first pad portion 110 of the first substrate 100 may prevent or minimize or reduce the reflection of external light caused by the first pad 111 provided in the first pad portion 110.

[0449] Optionally, the side seal 109 may also include an absorbent material for adsorbing water and / or oxygen.

[0450] The light-emitting display device or first substrate 100 according to embodiments of the present disclosure may further include a first chamfer 100c disposed at the corner between the first surface 100a and the outer surface OS. The first chamfer 100c can reduce or minimize damage to the corner of the first substrate 100 caused by physical impacts applied from the outside, and can prevent the wiring portion 400 from being disconnected due to the corner of the first substrate 100. For example, the first chamfer 100c may have a 45-degree angle, but embodiments of the present disclosure are not limited thereto. The first chamfer 100c can be implemented by using a chamfering process using a cutting wheel, a polishing wheel, a laser, etc. Therefore, each outer surface of the pad electrode 111 configured to contact the first pad portion 110 of the first chamfer 100c may include an inclined surface, which is inclined at an angle corresponding to the angle of the first chamfer 100c by removing or polishing the angle corresponding to the first chamfer 100c. The portion is removed together with the corner of the first substrate 100 by the chamfering process. For example, when the first chamfer 100c is formed at a 45-degree angle between the outer surface OS and the first surface 100a of the first substrate 100, the outer surface (or one end) 110 of the pad electrode 111 of the first pad portion can be formed at a 45-degree angle.

[0451] Reference Figures 5 to 7 , Figure 12 and Figure 14 The second substrate 200 according to embodiments of the present disclosure may include, as referenced Figure 5 and Figure 6 The second pad portion 210, at least one third pad portion 230, and the connecting line portion 250 are therefore omitted or can be briefly described again.

[0452] The second substrate 200 according to an embodiment of the present disclosure may include a metal pattern layer and an insulating layer that insulates the metal pattern layer.

[0453] The metal patterned layer (or conductive patterned layer) may include multiple metal layers. According to embodiments of this disclosure, the metal patterned layer may include a first metal layer 201, a second metal layer 203, and a third metal layer 205. The insulating layer may include multiple insulating layers. For example, the insulating layer may include a first insulating layer 202, a second insulating layer 204, and a third insulating layer 206. The insulating layer may be referred to as a back insulating layer or a patterned insulating layer.

[0454] The first metal layer 201 may be implemented on the rear surface 200b of the second substrate 200. The first metal layer 201 according to embodiments of the present disclosure may include a first metal pattern. For example, the first metal layer 201 may be referred to as a first link layer or link layer.

[0455] The first metal pattern according to an embodiment of the present disclosure may have a two-layer structure of Cu and MoTi (Cu / MoTi). The first metal pattern may be used as a connecting line of the connecting line portion 250, therefore, its repeated description may be omitted.

[0456] The first insulating layer 202 may be applied over the rear surface 200b of the second substrate 200 to cover the first metal layer 201. The first insulating layer 202 according to embodiments of the present disclosure may include an inorganic insulating material.

[0457] The second metal layer 203 may be implemented over the first insulating layer 202. The second metal layer 203 according to embodiments of this disclosure may include a second metal pattern. For example, the second metal layer 203 may be referred to as a second link layer, patch layer, or bridging layer.

[0458] The second metal pattern according to embodiments of the present disclosure may have a Cu / MoTi dual-layer structure. The second metal pattern may be used as multiple gate connections for multiple interconnects in the interconnect portion 250, but embodiments of the present disclosure are not limited thereto. For example, the second metal layer 203 may be used as a jumper (or bridging wire) for electrically connecting interconnects formed on different layers of different metal materials in the interconnect portion 250.

[0459] Optionally, the connecting lines (e.g., multiple first connecting lines) located at the second metal layer 203 can be modified to be located at the first metal layer 201, and the connecting lines (e.g., multiple second connecting lines) can be located at the first metal layer 201. Alternatively, the connecting lines located at the first metal layer 201 can be modified to be located at the second metal layer 203.

[0460] The second insulating layer 204 may be applied over the rear surface 200b of the second substrate 200 to cover the second metal layer 203. The second insulating layer 204 according to embodiments of the present disclosure may include an inorganic insulating material.

[0461] The third metal layer 205 may be implemented over the second insulating layer 204. The third metal layer 205 according to embodiments of the present disclosure may include a third metal pattern. For example, the third metal layer 205 may be referred to as a third link layer or a pad electrode layer.

[0462] The third metal pattern according to embodiments of this disclosure may have a stacked structure of at least two materials selected from ITO (or IZO), Mo, Ti, and MoTi. For example, the third metal pattern may have a three-layer structure of any one of ITO / Mo / ITO, ITO / MoTi / ITO, IZO / Mo / ITO, or IZO / MoTi / ITO. The third metal pattern may be used as a pad 211 of the second pad portion 210. For example, the pad 211 of the second pad portion 210 formed by the third metal layer 205 may be electrically coupled to the first metal layer 201 via pad contacts to form holes at the first insulating layer 202 and the second insulating layer 204.

[0463] The third insulating layer 206 may be applied over the rear surface 200b of the second substrate 200 to cover the third metal layer 205. The third insulating layer 206 according to embodiments of the present disclosure may include an organic material. For example, the third insulating layer 206 may include an insulating material such as photoacrylic acid. The third insulating layer 206 may cover the third metal layer 205 to prevent the third metal layer 205 from being exposed. The third insulating layer 206 may be referred to as an organic insulating layer, protective layer, back protective layer, organic protective layer, back coating, or back cover layer.

[0464] Each of the plurality of second pads 211 disposed at the second pad portion 210 can be electrically coupled to a second substrate 200 of a connection line portion 250 made of a first metal layer 201 or a second metal layer 203, via second pad contact holes disposed at the first insulating layer 202 and the second insulating layer 204. For example, a second data pad can be electrically coupled to one end of a data link line 251 via second pad contact holes disposed at the first insulating layer 202 and the second insulating layer 204. (First insulating layer 202 and second insulating layer 204)

[0465] Reference Figure 5 , Figure 12 and Figure 14 According to embodiments of the present disclosure, the connecting member 300 can be disposed between the first substrate 100 and the second substrate 200. The first substrate 100 and the second substrate 200 can be connected to each other by the connecting member 300 in the following ways. According to embodiments of the present disclosure, the connecting member 300 can be a transparent adhesive member or a double-sided tape including optically transparent adhesive (OCA), optically transparent resin (OCR), or pressure-sensitive adhesive (PSA). According to another embodiment of the present disclosure, the connecting member 300 can include glass fiber.

[0466] According to embodiments of the present disclosure, the connecting member 300 can be disposed throughout the space between the first substrate 100 and the second substrate 200. For example, all the second surfaces 100b of the first substrate 100 can be connected to one surface of all the connecting members 300, and all the front surfaces 200a of the second substrate 200 can be connected to all the other surfaces of the connecting members 300.

[0467] According to another embodiment of this disclosure, the bonding member 300 may be disposed in a patterned structure between the first substrate 100 and the second substrate 200. For example, the bonding member 300 may have a line pattern structure or a grid pattern structure. The grid pattern structure may also include a curved portion that discharges air bubbles that appear between the first substrate 100 and the second substrate 200 during the bonding of the first substrate 100 to the second substrate 200 to the outside.

[0468] Reference Figure 5 and Figures 12 to 14 According to embodiments of the present disclosure, the wiring portion 400 may include a plurality of wirings 410, which electrically connect the first pad 111 of the first pad portion 110 to the second pad 211 of the second pad portion 210, and may be referenced above. Figure 4 The described multiple wirings are identical to 410. (And...) Figure 5 Since they are the same, their repeated descriptions are omitted.

[0469] The light-emitting display device or wiring portion 400 according to embodiments of the present disclosure may further include an edge coating 430.

[0470] An edge coating 430 may be applied to cover wiring portions 400. An edge coating 430 may be applied to cover multiple wirings 410. For example, the edge coating 430 may be an edge protection layer or an edge insulation layer.

[0471] According to embodiments of the present disclosure, the edge coating 430 can be implemented to cover the entirety of the first peripheral portion and the first outer surface OS1a of the first substrate 100 and the first peripheral portion and the first outer surface OS1b of the second substrate 200, as well as multiple wirings 410. The edge coating 430 can prevent corrosion of each of the multiple wirings 410, including metallic material, or electrical short circuits between the multiple wirings 410. Furthermore, the edge coating layer 430 can prevent or minimize or reduce the reflection of external light caused by the multiple wirings 410 and the first pad 111 of the first pad portion 110. As one embodiment, the edge coating 430 can include a light-blocking material, which includes black ink. As another embodiment, the edge coating 430 can cover (or configure) the outermost surface (or sidewall) of the display device (or display panel), and therefore can include an impact-absorbing material (or substance) or a ductile material to prevent damage to the outer surface OS of each of the first substrate 100 and the second substrate 200. As another embodiment, the edge coating 430 can include a mixture of light-blocking material and impact-absorbing material.

[0472] According to an embodiment of the present disclosure, the edge coating 430 may be formed as an outer surface OS surrounding each of the first and second substrates 100 and 200, on which the wiring portion 400 is disposed.

[0473] According to another embodiment of this disclosure, such as Figure 5 , 12 As shown in Figure 14, the edge coating 430 can be formed as an outer surface OS surrounding all other outer surfaces OS of each of the first and second substrates 100 and 200, as well as an outer surface OS on which the wiring portion 400 is located. For example, the edge coating 430 can be formed as an outer surface OS surrounding each of the first and second substrates 100 and 200. In this case, one outer surface OS (or first outer surface) of each of the first substrates 100 and 200. The first and second substrates 100 and 200 can be surrounded by multiple wirings 410 and the edge coating 430. The second substrates 100 and 200 can be surrounded only by the edge coating 430. For example, the first outer surface of each of the first substrate 100 and the second substrate 200 can include multiple wirings 410 and the edge coating 430, and the second to fourth outer surfaces of each of the first and second substrates 100 and 200, in addition to the first outer surface, can include only the edge coating 430.

[0474] According to one embodiment of the present invention, when multiple traces 410 and a covering layer 430 disposed on a first outer surface are referred to as a first sidewall structure, and when the covering layer 430 is disposed on a second to fourth outer surface, the surface is referred to as a second sidewall structure. The first sidewall structure and the second sidewall structure can have different thicknesses (or widths). For example, the thickness (or width) of the second sidewall structure can be thinner or narrower than the thickness (or width) of the first sidewall structure than the thickness of the multiple traces 410.

[0475] Figure 16 It is along Figure 3 The cross-sectional view of line III-III' shown is for illustration. Figure 3 The diagram shows the common electrode connection and the secondary wire connection. In the description... Figure 16 In, with Figure 3 Components that are identical or corresponding to each other will be omitted or will be briefly given below.

[0476] Reference Figure 3 , 12 According to embodiments of the present disclosure, each of the plurality of common electrode connection portions CECP can be disposed in a first electrode connection region ECA1 between a plurality of pixels P that overlap with a plurality of pixel common voltage lines CVL, and the common electrode CE can be electrically connected to each of the plurality of pixel common voltage lines CVL.

[0477] Each of the multiple common electrode connection portions of CECP may include a first electrode connection pattern ECP1, a groove GRV, a second electrode connection pattern ECP2, and a connection groove CT.

[0478] Regarding the first direction X, the first electrode connection pattern ECP1 can be disposed on the circuit layer 101, which is disposed at the first electrode connection region ECA1 between multiple pixels P, and can be electrically connected (or coupled) to each of the multiple pixels. The pixel common voltage line CVL passes through the first via VH1.

[0479] According to an embodiment of this disclosure, the first electrode connection pattern ECP1 can extend relatively long along a first direction X and can be disposed on the interlayer insulating layer 101c of the circuit layer 101 to intersect or overlap with the corresponding pixel common voltage line CVL. A first via VH1 can be formed at the interlayer insulating layer 101c, which is disposed in the overlapping region between the first electrode connection pattern ECP1 and the pixel common voltage line CVL. The first electrode connection pattern ECP1 can be covered by a passivation layer 101d.

[0480] According to an embodiment of this disclosure, the first electrode connection pattern ECP1 can be formed together with the source / drain electrodes of the TFT disposed at the pixel. According to another embodiment of this disclosure, the first electrode connection pattern ECP1 may include a metal line layer directly connected to the pixel common voltage line CVL through a first via VH1, and a cover metal layer that only covers a portion of the metal line layer. The cover metal layer (or cladding layer) can prevent corrosion of the metal line layer.

[0481] The groove GRV can be formed to expose the top surface of the circuit layer 101 disposed at the first electrode connection region ECA1. The groove GRV can expose the passivation layer 101d of the circuit layer 101 disposed at the first electrode connection region ECA1. For example, the groove GRV can be formed by patterning the portion of the planarization layer 102 covering the circuit layer 101 located at the first electrode connection region ECA1.

[0482] The second electrode connection pattern ECP2 can be disposed at the periphery (or near) of the groove GRV and the groove GRV so as to be electrically connected (or coupled) to the first electrode connection pattern ECP1.

[0483] According to an embodiment of the present disclosure, the second electrode connection pattern ECP2 can be disposed above the planarization layer 102 above the pixel common voltage line CVL and the passivation layer 101d, and can be electrically connected (or coupled) to the first electrode connection pattern ECP1 through the first via VH1 formed at the passivation layer 101d above the first electrode connection pattern ECP1.

[0484] According to an embodiment of the present disclosure, the second electrode connection pattern ECP2 can be formed together with the pixel electrode PE disposed at the pixel.

[0485] According to another embodiment, the second electrode connection pattern ECP2 may consist only of metallic materials that are not damaged or corroded by the patterning or trenching processes that form the connection trench CT. For example, the second electrode connection pattern ECP2 may include a first metal line pattern MLP1 directly connected (or coupled) to the first electrode connection pattern ECP1 through a second via VH2, and a second metal line pattern MLP2 stacked on the first metal. For example, the first metal line pattern MLP1 may include indium tin oxide (ITO), and the second metal line pattern MLP2 may include molybdenum titanium alloy (MoTi). For example, when the pixel electrode PE is formed as a five-layer structure, including a first pixel electrode layer containing ITO, a second pixel electrode layer containing MoTi, a third pixel electrode layer containing ITO, a fourth pixel electrode layer containing silver (Ag), and a fifth pixel electrode layer containing ITO, the second electrode connection pattern ECP2 may consist only of the first to fifth pixel electrode layers PE, excluding the third to fifth pixel electrode layers.

[0486] The connection trench CT can be formed by a patterning process performed on the passivation layer 101d covering the outer portion of the first electrode connection pattern ECP1. For example, the connection trench CT can be formed by a patterning process performed on the pixel electrode PE and the second electrode connection pattern ECP2, followed by a patterning process on the passivation layer 101d. That is, the connection trench CT can be formed by the same patterning process as the first trench structure material used to form or provide the isolation portion 104 at the outermost pixel, therefore its description will be omitted or simply repeated.

[0487] According to embodiments of the present disclosure, the connection trench CT can be formed to expose a passivation layer 101d covering the peripheral portion of the first electrode connection pattern ECP1. The connection trench CT can be a side surface of the passivation layer 101d disposed between the end of the second electrode connection pattern ECP2 and the peripheral portion of the first electrode connection pattern ECP1. For example, the connection trench CT can have an inclined structure or a positive conical structure, but embodiments of the present disclosure are not limited thereto. Therefore, the connection trench CT can be an undercut region between the end of the second electrode connection pattern ECP2 and the peripheral portion of the first electrode connection pattern ECP1.

[0488] The second electrode connection pattern ECP2 may protrude to the outer side of the side surface of the connecting groove CT and may overlap with or directly face the peripheral portion of the first electrode connection pattern ECP1. The second electrode connection pattern ECP2 may include a protruding tip PT that protrudes to the outer side of the side surface of the connecting groove CT and faces the first electrode connection pattern ECP1. Therefore, the end (or protruding tip PT) of each of the first metal wire pattern MLP1 and the second metal wire pattern MLP2 of the second electrode connection pattern ECP2 may have an overhang structure relative to the connecting groove CT. For example, the protruding tip PT of the second electrode connection pattern ECP2 may be an overhang structure material corresponding to the connecting groove CT. It should be understood that "overhang structure" includes the meaning of an overhang portion. For example, the ends of the first metal wire pattern MLP1 and the second metal wire pattern MLP2 extend (e.g., extend beyond) the upper surface and lateral sidewalls of the connecting groove CT in the X-axis direction, such as... Figure 16 As shown.

[0489] The second electrode connection pattern ECP2 can be directly electrically connected to the common electrode CE based on a side contact method. For example, the deposition material of the self-emissive device ED can be linear, and therefore can be deposited on the top surface (or upper surface) of the second electrode connection pattern ECP2, but not on the side surface and the bottom surface (or lower surface) of the second electrode connection pattern ECP2. Therefore, the side and bottom surfaces of the second electrode connection pattern ECP2 can be exposed without being covered by the self-emissive device ED. For example, the side surface of the first metal wire pattern MLP1 and the side and bottom surface of the second metal wire pattern MLP2 of the second electrode connection pattern ECP2 can be exposed without being covered by the self-emissive device ED.

[0490] The second electrode connection pattern ECP2 can isolate (or disconnect) the self-emissive device ED disposed above the first electrode connection area ECA1. For example, the deposition material of the self-emissive device ED may not be deposited on the side surface of the connection groove CT that is closed (or covered) by the protruding tip PT of the second electrode connection pattern ECP2, and thus can be isolated (or disconnected) in the undercut region of the connection groove CT. Furthermore, the deposition material of the self-emissive device ED deposited on the peripheral portion of the first electrode connection pattern ECP1 can be closed (or covered) by the protruding tip PT of the second electrode connection pattern ECP2, and can be separated from the protruding tip PT of the second electrode connection pattern ECP2 on the side surface of the connection groove CT. Therefore, the portion of the first electrode connection pattern ECP1 that overlaps with or is obscured (or covered) by the protruding tip PT of the second electrode connection pattern ECP2 may not be covered by the deposition material of the self-emissive device ED and may be exposed.

[0491] The common electrode CE can be formed above the top surface of the self-emissive device ED and deposited above the side and bottom surfaces of the second electrode connection pattern ECP2. Therefore, it can be electrically connected (or coupled) to the second electrode connection pattern ECP2 via a side contact method. For example, the common electrode CE can be formed by physical deposition or chemical deposition processes, in which case the common electrode material can be deposited on the self-emissive device ED and can penetrate into the undercut region. It can also be deposited above the side and bottom surfaces of the second electrode connection pattern ECP2 via a connecting trench CT. Therefore, the common electrode CE can be electrically connected (or coupled) to the side surface of the first metal line pattern MLP1 and the side and bottom surface of the second metal line pattern MLP2 of the second electrode connection pattern ECP2. Thus, even without a process for forming separate contact holes or separate contact structure materials, the common electrode CE can be electrically connected (or coupled) to the pixel common voltage line CVL via the common electrode connection portion CECP.

[0492] The common electrode CE can be formed continuously in the undercut region through the connecting groove CT without being isolated or disconnected, and thus can be formed to completely surround the self-emitting device ED. According to embodiments of this disclosure, the common electrode CE can penetrate the undercut region through the connecting groove CT and can cover the side surface of the connecting groove CT, the exposed and covered portion of the first electrode connection pattern ECP1, the protruding tip PT of the second electrode connection pattern ECP2, and the self-emitting device ED isolated above the first electrode connection pattern ECP1. Therefore, the common electrode CE can be electrically connected (or coupled) to a portion of the first electrode connection pattern ECP1 at the undercut region between the protruding tip PT of the second electrode connection pattern ECP2 and the first electrode connection pattern ECP1. Therefore, the common electrode CE can be directly electrically connected (or coupled) to the protruding tip PT of the second electrode connection pattern ECP2 and can be directly connected (or coupled) to the first electrode connection pattern ECP1, thus increasing the contact area between the common electrode CE and the common electrode connection portion CECP.

[0493] Each of the multiple common electrode connection portions (CECPs) can be surrounded and planarized by an encapsulation layer 106. For example, a first encapsulation layer 106a of the encapsulation layer 106 can be disposed above the common electrode CE to surround or cover the common electrode CE. A second encapsulation layer 106b of the encapsulation layer 106 can be disposed above the first encapsulation layer 106a and can provide a flat surface on the first encapsulation layer 106a. Therefore, the area overlapping with the groove GRV formed at each of the multiple common electrode connection portions (CECPs) can be planarized by the second encapsulation layer 106b. The second encapsulation layer 106b can be covered by a third encapsulation layer 106c.

[0494] Each of the plurality of secondary line connection portions SLCPs according to embodiments of the present disclosure may be disposed at a second electrode connection region ECA2 between a plurality of pixels P that overlap with a plurality of secondary voltage lines SVL respectively, and may be electrically connected to a common electrode CE connected to each of the plurality of secondary voltage lines SVL.

[0495] Each of the plurality of secondary line connection portions SLCP may include a first electrode connection pattern ECP1, a groove GRV, a second electrode connection pattern ECP2, and a connection groove CT. Except that each of the plurality of secondary line connection portions SLCP electrically connects the common electrode CE to a corresponding secondary voltage line in one of the plurality of secondary voltage lines SVL in the second electrode connection region ECA1 parallel to the first electrode connection region ECA1, the plurality of secondary line connection portions SLCP may be substantially identical to each of the plurality of common electrode connection portions CECP; therefore, the same reference numerals refer to the same elements and their repeated descriptions are omitted.

[0496] As described above, in the light-emitting display device according to this embodiment, each pixel common voltage line CVL in each pixel P of the display area AA can be electrically connected to a common electrode through a common electrode connection portion CECP and a common electrode connection portion SLCP. Therefore, the pixel common voltage applied to each pixel P can be uniform, thereby preventing or minimizing the degradation of image quality or brightness uniformity caused by region-based non-uniformity. (or deviation) is applied to the pixel common voltage of each pixel P.

[0497] Figure 17 This is an illustration of a second substrate of a light-emitting display device according to another embodiment of the present disclosure. Figure 18 along Figure 17 The cross-sectional view of the straight line IV-IV' shown. Figure 17 and 18 This shows how the above references can be modified. Figure 17 and 18 An embodiment implemented using the pixel driving power supply structure of the described light-emitting display device. (Refer to...) Figures 1 to 16 Therefore, in the following text, repeated descriptions of components other than the supply structure of the pixel drive power supply and its related components are omitted or will be briefly given below.

[0498] Reference Figure 17 and 18 According to another embodiment of the present disclosure, the light-emitting display device may further include a secondary pad portion 130, a second secondary pad portion 270, multiple secondary pixel driving power connection lines 275, and a secondary wiring portion 450. For example, the second secondary pad portion may be referred to as an additional pad portion or an auxiliary pad portion, etc. For example, the secondary pixel driving power connection lines may be referred to as additional pixel driving power connection lines or auxiliary pixel driving power connection lines, etc. For example, the secondary wiring portion may be referred to as an additional wiring portion or an auxiliary wiring portion, etc.

[0499] The first sub-pad portion 130 may include a plurality of outermost pixels Po, which are disposed on a second peripheral portion (or another peripheral portion) parallel to the first peripheral portion (or one peripheral portion) on the first surface. First substrate 100.

[0500] According to embodiments of the present disclosure, the first sub-pad portion 130 may include a plurality of first sub-pixel drive power pads (or first sub-pads) SPP1.

[0501] Each of the plurality of first pixel drive power pads SPP1 can be individually (or in a one-to-one relationship) connected (or coupled) to the other end of the corresponding pixel drive power line PL of the plurality of pixel drive power lines, which is disposed above the first substrate 100. Except for the fact that each of the plurality of first pixel drive power pads SPP1 is connected (or coupled) to the other end of the corresponding pixel drive power line PL of the plurality of pixel drive power lines PL, as shown in the figure, each of the plurality of first pixel drive power pads SPP1 can be implemented or formed with the same structure as each of the plurality of first pixel drive power pads PPP1, therefore, repeated descriptions of them are omitted.

[0502] The second pad portion 270 may be located at another peripheral portion (or second rear peripheral portion) of the rear surface 200b of the second substrate 200, overlapping the first pad portion 130 located above the front surface of the first substrate 100.

[0503] The second pad portion 270 according to an embodiment of the present disclosure may include a plurality of second pixel drive power pads (or second pads) SPP2.

[0504] Each of the plurality of secondary pixel driving power pads SPP2 may be disposed on another peripheral portion of the rear surface 200b of the second substrate 200, overlapping with the corresponding first pixel driving power pad SPP1 of the plurality of primary pixel driving power pads. SPP1 is disposed above the front surface of the first substrate 100. Apart from each of the plurality of secondary pixel driving power pads SPP2 being disposed on the second rear peripheral portion of the second substrate 200, each power pad SPP2 of the plurality of secondary pixel driving power pads may be implemented or formed with the same structure as each of the plurality of secondary pixel driving power pads PPP2, therefore, a detailed description of them is omitted.

[0505] Multiple subpixel driving power connection lines (or secondary connection lines) 275 can be disposed above the rear surface 200b of the second substrate 200 and can electrically connect (or couple) the third pad portion 250 to the second pad portion 270. The multiple subpixel driving power connection lines 275 can individually (or in a one-to-one relationship) connect (or couple) each third pixel driving power pad of the third pad portion 250 to the corresponding second pixel driving power pad SPP2. Except for the electrical connection (or coupling) of the third pixel driving power pad to the second pixel driving power pad SPP2, the subpixel driving power connection lines 275 can be the same as the pixel driving power connection lines 255; therefore, their repeated description is omitted.

[0506] The secondary wiring portion 450 can be configured to surround the first substrate 100 with a second outer surface OS2a parallel to the first outer surface OS1a and a second outer surface OS2b parallel to the first outer surface OS1b. The second substrate 200 can individually (or in a one-to-one relationship) connect (or couple) the first pixel drive power pad SPP1 to the second pixel drive power pad SPP2.

[0507] The secondary wiring portion 450 according to embodiments of the present disclosure may include a plurality of secondary pixel power wirings (or secondary wirings) 451.

[0508] Each of the multiple sub-pixel power traces 451 can be configured to surround the second outer surface OS2a of the first substrate 100 and the second outer surface OS2b of the second substrate 200, and can individually (or in a one-to-one relationship) connect (or couple) the first pixel drive power pad SPP1 to the second pixel drive power pad SPP2. Except that each of the multiple sub-pixel power traces 451 is configured to surround the second outer surface OS2a of the first substrate 100 and the second outer surface OS2b of the second substrate 200, each of the multiple sub-pixel power traces surrounds the second outer surface OS2a of the first substrate 100. 451 can be the same as pixel power traces 411, therefore its description is omitted.

[0509] According to embodiments of this disclosure, the pixel driving power supplied from the driving circuit portion to the third pixel driving power pad of the third pad portion 250 can be provided to one side of each pixel driving power line PL via the pixel. The driving power connection line 255, the second pixel driving power pad PPP2, the pixel power wiring 411, and the first pixel driving power pad PPP1 can also be provided to the other side of each pixel driving power line PL simultaneously. The sub-pixel driving power connection line 275, the second pixel driving power pad SPP2, the sub-pixel power wiring 451, and the first pixel driving power pad SPP1 are also included.

[0510] The light-emitting display device according to another embodiment of the present disclosure may further include a pixel driving power common line 280 disposed at a second rear peripheral portion of the second substrate 200.

[0511] A pixel driving power common line (or secondary common line) 280 may be disposed at the second rear peripheral portion of the second substrate 200 adjacent to the secondary pad portion 270. According to embodiments of the present disclosure, the pixel driving power common line 280 may be arranged parallel to the first direction X and may be connected to each secondary pixel driving power pad SPP2. For example, the pixel driving power common line 280 may have a strip with a relatively wide dimension (or area) to minimize or reduce the voltage drop of the pixel driving power. For example, the pixel driving power common line 280 may be formed together with the second common connection line 257b of the pixel common power connection line 257.

[0512] According to an embodiment of this disclosure, the pixel driving power common line 280 may include a plurality of protruding lines, which are electrically connected (or coupled) to the secondary pixel driving power pads SPP2. For example, each secondary pixel driving power pad SPP2 may be a protruding line protruding from the pixel driving power common line 280.

[0513] The pixel driving power common line 280 can overlap with the end of the sub-pixel driving power connection line 275 and can be connected to the end of the sub-pixel driving power connection line 275 through a common line contact hole 281. Therefore, the pixel driving power supplied from the driving circuit section to the third pixel driving power pad of the third pad section 250 can be supplied to one side of each pixel driving power line PL, the second pixel driving power pad PPP2, the pixel power wiring 411, and the first pixel driving power pad PPP1 through the pixel driving power connection line 255. At the same time, it can be supplied to the other side of each pixel driving power line PL, the line 275, the pixel driving power common line 280, the second pixel driving power pad SPP2, the sub-pixel power wiring 451, and the first pixel driving power pad SPP1 through the second pixel driving power connection line.

[0514] In the light-emitting display device according to this embodiment, the pixel driving power supply can be simultaneously supplied to one side and the other side of each pixel driving power supply line PL based on a double-fed scheme. Therefore, the voltage drop can be better prevented, reduced, or minimized due to the line resistance of the pixel driving power supply line PL. Thus, the light-emitting display device according to this embodiment can better prevent, reduce, or minimize image quality defects caused by deviations in the pixel driving power supply supplied to each pixel P disposed in the display area AA.

[0515] See the diagram. (Refer to the diagram.) Figure 17The illustration shows a dual-feed configuration corresponding to a pixel driving power supply, but the embodiments disclosed herein are not limited to this. The reference voltage provided to each pixel can also be simultaneously provided to one side and the other side of each reference voltage line based on the dual-feed configuration, and the pixel common voltage provided to each pixel can also be simultaneously provided to one side and the other side of each pixel common voltage line based on the dual-feed configuration. A dual-feed configuration corresponding to at least one of the reference voltage and the pixel common voltage can be implemented or formed with the same structure as the dual-feed configuration corresponding to the pixel driving power supply, and therefore will not be described further.

[0516] Figure 19 This is a diagram illustrating a multi-screen display device according to an embodiment of the present disclosure. Figure 20 It is along Figure 19 The cross-sectional view shown is taken from line V-V'. Figure 19 and 20 It shows that according to Figures 1 to 18 The illustrated multi-screen display device is a tiled implementation of a light-emitting display device according to another embodiment of the present disclosure.

[0517] Reference Figure 19 and 20 According to embodiments of the present disclosure, a multi-screen display device (or splicing light-emitting display device) may include multiple display devices DM1 to DM4.

[0518] Multiple display devices DM1 to DM4 can each display a separate image or can display an image separately. Each of the multiple display devices DM1 to DM4 can include Figure 1 And the light-emitting display device according to an embodiment of the present disclosure shown in FIG2. Figures 1 to 18 Since they are the same, their repeated descriptions will be omitted or briefly given.

[0519] Multiple display devices DM1 to DM4 can be tiled on a separate tile frame so that their side surfaces are in contact with each other. For example, multiple display devices DM1 to DM4 can be tiled in an N×M configuration to achieve a multi-screen display device with a large screen. For example, N is a positive integer greater than 1 and M is a positive integer greater than 2, but the embodiments of this disclosure are not limited to this. For example, N is a positive integer greater than 2 and M is a positive integer of 1 or greater.

[0520] Each of the plurality of display devices DM1 to DM4 may not include a border area (or non-display portion) surrounding all display areas AA of the displayed image, and may have an air border structure in which the display areas AA are surrounded by air. For example, in each of the plurality of display devices DM1 to DM4, the entire first surface of the first substrate 100 may be implemented as the display area AA.

[0521] According to embodiments of this disclosure, in each of the plurality of display devices DM1 to DM4, the second interval D2 between the central portion CP of the outermost pixel Po and the outermost surface VL of the first substrate 100 can be implemented as half or less of the first interval D1 (or pixel pitch) between adjacent pixels. Therefore, in two adjacent display devices DM1 to DM4 coupled (or in contact) to each other on their side surfaces based on lateral coupling, the area PAo of the interval “D2+D2” between adjacent outermost pixels can be equal to or less than the first interval D1 between the two adjacent pixels. (Refer to...) Figure 20 In the first and third display devices DM1 and DM3 coupled (or in contact) with each other on their side surfaces along the second direction Y, the interval “D2+D2” between the center portions CP of the outermost pixels Po of the first display device DM1 and the center portions CP of the outermost pixels Po of the third display device DM3 can be equal to or less than the first interval D1 (or pixel pitch) between two adjacent pixels set at each of the first and third display devices DM1 and DM3.

[0522] Therefore, the interval "D2+D2" between the central portions CP of the outermost pixels Po of two adjacent display devices DM1 to DM4 coupled (or in contact) to each other on their side surfaces along the first direction X and the second direction Y can be set equally or less than the first interval D1 between two adjacent pixels in each display device DM1 to DM4. Thus, there will be no seams or boundary portions between two adjacent display devices DM1 to DM4, and no dark areas will be caused by the boundary portions between display devices DM1 to DM4. As a result, images displayed on a multi-screen display device with multiple display devices DM1, DM2, DM3, and DM4 tiled in an N×M pattern can be displayed continuously without the feeling of discontinuity (or discontinuity) at the boundary portions between the multiple display devices DM1, DM2, DM3, and DM4.

[0523] exist Figure 19 and 20The diagram shows multiple display devices DM1 to DM4 tiled in a 2×2 configuration. However, embodiments of this disclosure are not limited to this; the multiple display devices DM1 to DM4 can be tiled in a 2×2 configuration, or in an x×1, 1×y, or x×y configuration. For example, in the x×1 configuration, x can be a natural number greater than or equal to 2; in the 1×y configuration, y can be a natural number greater than or equal to 2; and in the x×y configuration, x and y can be natural numbers greater than or equal to 2 and can be equal to or different from each other. For example, in the x×y configuration, x can be a natural number greater than or equal to 2 and can be equal to y, or x and y can be natural numbers greater than or equal to 2 and y greater than or less than x. As described above, when the display area AA of each of the multiple display devices DM1 to DM4 is a screen and displays an image, the multi-screen display device according to embodiments of this disclosure can display uninterrupted images, and DM1 to DM4 are continuous at the boundary portions between the multiple display devices DM1 to DM4. Therefore, the immersive experience for viewers viewing images displayed by the multi-screen display device can be enhanced.

[0524] The following describes a light-emitting display device according to embodiments of the present disclosure and a multi-screen display device including the light-emitting display device.

[0525] The light-emitting display device according to this disclosure may include: a display area configured to include a plurality of pixels disposed on a first to m-th horizontal line parallel to a first direction above a first substrate; a plurality of gate lines disposed on the first to m-th horizontal lines of the display area parallel to the first direction; a plurality of gate control lines disposed between a plurality of pixels along a second direction intersecting the first direction; and a gate driving circuit including first to m-th level circuit components disposed in the display area and selectively coupled to the plurality of gate lines and the plurality of gate control lines, wherein each of the first to m-th level circuit components includes: a plurality of branch circuits, a branch network separately disposed between the plurality of pixels along the first direction and selectively coupled to the plurality of gate control lines and selectively coupled to the plurality of branch circuits, and wherein the branch network of the first level circuit unit and the branch network of the m-th level circuit unit are disposed between two adjacent pixels along the second direction.

[0526] According to some embodiments of this disclosure, the branch network of the first-level circuit unit may be disposed between the first and second horizontal lines, and the branch network of the m-th level circuit unit may be disposed in the (m-1)-m horizontal lines.

[0527] According to some embodiments of this disclosure, the branch networks of the first to m level circuit components can be divided into first to m level branch networks. The 2k-1 level branch network and the 2k level branch network of the first to m level branch networks can each be set between the 2k-1 level line and the 2k level line, where k is a natural number and 2k is less than or equal to m.

[0528] According to some embodiments of this disclosure, the region between the 4n-2nd and 4n-1st horizontal lines of the first to mth horizontal lines can be the non-set region of the branch network, and n is a natural number and 4n is less than m.

[0529] According to some embodiments of this disclosure, the light-emitting display device may further include: a plurality of pixel common voltage lines disposed parallel to the second direction and along the first direction between the plurality of pixels; a common electrode disposed above the display area; and a plurality of common voltage connection portions electrically coupling the plurality of pixel common voltage lines to the common electrode.

[0530] According to some embodiments of this disclosure, the first to the mth horizontal lines can each be divided into a first region and a second region relative to the second direction, the branch network can be disposed in one of the first region and the second region, and the common voltage connection can be disposed in the other region of the first region and the second region.

[0531] According to some embodiments of this disclosure, the common electrode connection portion located at the 2k-1th horizontal line of the first to m horizontal lines may be located in the first region, and the common electrode connection portion located at the 2kth horizontal line of the first to m horizontal lines may be located in the second region.

[0532] According to some embodiments of this disclosure, the region between the (4n-3)th and (4n-2)th horizontal lines of the first to m-th horizontal lines can be the setting region of the branch network and the non-setting region of the common electrode connection part; the region between the (4n-2)th and (4n-1)th horizontal lines of the first to m-th horizontal lines can be the non-setting region of the branch network and the setting region of the common electrode connection part; the region between the (4n-1)th and (4n)th horizontal lines of the first to m-th horizontal lines can be the setting region of the branch network and the non-setting region of the common electrode connection part; n is a natural number, and 4n is less than or equal to m.

[0533] According to some embodiments of this disclosure, each of the plurality of common voltage connections may include: a first electrode connection pattern electrically coupled to the pixel common voltage line; a passivation layer covering the first electrode connection pattern; a second electrode connection pattern disposed above the passivation layer and electrically coupled to the first electrode connection pattern; and a connection trench including an undercut region formed by removing the passivation layer between the end of the second electrode connection pattern and the first electrode connection pattern, wherein the common electrode is electrically connected to the rear surface and bottom surface of the end of the second electrode connection pattern.

[0534] According to some embodiments of this disclosure, the end of the second electrode connection pattern may have an eave structure relative to the connection groove, and the common electrode may be electrically coupled to the first electrode connection pattern at the undercut region.

[0535] According to some embodiments of this disclosure, the light-emitting display device may further include: a plurality of secondary voltage lines arranged parallel to the plurality of pixel common voltage lines, with the plurality of gate control lines each therebetween; a line connection pattern electrically coupling adjacent pixel common voltage lines and secondary voltage lines; and a plurality of secondary line connection portions arranged parallel to the plurality of common voltage connection portions to electrically couple the plurality of secondary voltage lines to the common electrode.

[0536] According to some embodiments of this disclosure, the light-emitting display device may further include: a first pad portion disposed at a peripheral portion of the first substrate; a second substrate coupled to a rear surface of the first substrate via a coupling element; a second pad portion disposed on the rear surface of the second substrate to overlap the first pad portion; a third pad portion disposed on the rear surface of the first substrate and electrically coupled to the second pad portion; a driving circuit portion coupled to the third pad portion; and a routing portion disposed on the first outer surface of each of the first substrate and the second substrate and electrically coupled to the first pad portion and the second pad portion.

[0537] According to some embodiments of this disclosure, the light-emitting display device may further include: a first-level pad portion disposed at other peripheral portions parallel to one peripheral portion of the first substrate; a second-level pad portion disposed on the rear surface of the second substrate to overlap the first-level pad and electrically coupled to the third pad portion; and a secondary routing portion disposed on the second outer surface parallel to the first outer surface of the first substrate and the second substrate and electrically coupled to the first-level pad portion and the second-level pad portion.

[0538] According to some embodiments of this disclosure, the light-emitting display device may further include a plurality of pixel driving power lines disposed at the display area of ​​the first substrate and coupled to each of the plurality of pixels, a portion of each of the plurality of pixel driving power lines being electrically coupled to the first pad portion, and another portion of each of the plurality of pixel driving power lines being electrically coupled to the first primary pad portion.

[0539] According to some embodiments of this disclosure, the driving circuit component can supply pixel driving power to the third pad portion, and the pixel driving power can be supplied to a portion of each of the plurality of pixel driving power lines through the third pad portion, the second pad portion, the secondary selection portion, and the first pad portion, and can be supplied to another portion of each of the plurality of pixel driving power lines through the third pad portion, the second secondary pad portion, the secondary selection portion, and the first primary pad portion.

[0540] According to some embodiments of this disclosure, the light-emitting display device may further include a plurality of secondary link lines disposed on the rear surface of the second substrate and electrically coupled between the third pad portion and the second secondary pad portion.

[0541] According to some embodiments of this disclosure, the light-emitting display device may further include: a second common line disposed on the rear surface of the second substrate and electrically coupled to the second secondary pad portion; and a plurality of secondary link lines disposed on the rear surface of the second substrate and electrically coupled between the third pad portion and the secondary common line.

[0542] According to some embodiments of this disclosure, the size of the display area may be equal to the size of the first substrate, or the distance between the center of the outermost pixel of the plurality of pixels and the outer surface of the first substrate may be half or less of the pixel pitch, and the pixel pitch may be the distance between the centers of two adjacent pixels.

[0543] A multi-screen display device according to some embodiments of the present disclosure includes: a plurality of display devices disposed along at least one of a first direction and a second direction intersecting the first direction, each of the plurality of display devices including a light-emitting display device. The light-emitting display device according to the present disclosure includes: a display area configured to include a plurality of pixels disposed above a first substrate along a first to m-th horizontal line parallel to the first direction; a plurality of gate lines disposed along the first to m-th horizontal line of the display area parallel to the first direction; a plurality of gate control lines disposed between the plurality of pixels along a second direction intersecting the first direction; and a gate driving circuit including first to m-th level circuit components disposed in the display area and selectively coupled to the plurality of gate lines and the plurality of gate control lines. Each of the first to m-th level circuit components includes: a plurality of branch circuits, a branch network separately disposed along the first direction between the plurality of pixels and selectively coupled to the plurality of gate control lines and selectively coupled to the plurality of branch circuits, and wherein the branch network of the first-level circuit unit and the branch network of the m-th level circuit unit may be disposed between two adjacent pixels along the second direction.

[0544] According to some embodiments of this disclosure, in a first display device and a second display device that are adjacent to each other along at least one of the first direction or the second direction, the distance between the center of the outermost pixel of the first display device and the center of the outermost pixel of the second display device may be less than or equal to the pixel pitch, and the pixel pitch may be the distance between the center of pixels that are adjacent to each other along at least one of the first direction or the second direction.

[0545] The display device according to some embodiments of this disclosure can be applied to all electronic devices including display panels. For example, the display device according to this disclosure can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, electronic organizers, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop personal computers (PCs), laptops, netbooks, workstations, navigation devices, car navigation devices, automotive display devices, automotive equipment, theater equipment, theater display devices, televisions, wallpaper display devices, signage devices, game consoles, laptops, monitors, cameras, video cameras, home appliances, etc.

[0546] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from the spirit and scope of the invention. Therefore, it is intended that this disclosure cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A light emitting display apparatus comprising: a display area configured to include a plurality of pixels disposed in first through mth horizontal lines parallel to a first direction over a first substrate; a plurality of gate lines disposed at the first through mth horizontal lines of the display area parallel to the first direction; a plurality of gate control lines disposed between the plurality of pixels along a second direction crossing the first direction; and a gate driver circuit including first through mth stage circuit units disposed in the display area and selectively coupled to the plurality of gate lines and the plurality of gate control lines, wherein the first through mth stage circuit units each include: a plurality of branch circuits disposed between the plurality of pixels along the first direction and selectively coupled to the plurality of gate control lines, and a branch network selectively coupled to the plurality of branch circuits, and wherein the branch network of the first stage circuit unit and the branch network of the mth stage circuit unit are disposed between two adjacent pixels along the second direction, and wherein one or more of the plurality of gate control lines are disposed between two adjacent pixels along the first direction, wherein an area between a 4n-2th horizontal line and a 4n-1th horizontal line of the first through mth horizontal lines is a non-disposed area of the branch network, and wherein n is a natural number and 4n is less than m.

2. The light emitting display apparatus of claim 1, wherein the branch network of the first stage circuit unit is disposed between the first and second horizontal lines, and wherein the branch network of the mth stage circuit unit is disposed in the m-1th and mth horizontal lines.

3. The light emitting display apparatus of claim 1, wherein the branch network of each of the first through mth stage circuit units is divided into first through mth branch networks, wherein a 2k-1th branch network and a 2kth branch network of the first through mth branch networks are each disposed between a 2k-1th horizontal line and a 2kth horizontal line, and wherein k is a natural number and 2k is less than or equal to m.

4. The light emitting display apparatus of claim 1, further comprising: a plurality of pixel common voltage lines disposed parallel to the second direction and between the plurality of pixels along the first direction; a common electrode disposed over the display area; and a plurality of common voltage connection portions electrically coupling the plurality of pixel common voltage lines and respectively coupled to the common electrode.

5. The light emitting display apparatus of claim 4, wherein the plurality of common voltage connection portions are disposed at the non-disposed area of the branch network.

6. The light emitting display apparatus of claim 4, wherein each of the first through mth horizontal lines is divided into a first area and a second area with respect to the second direction, wherein the branch network is disposed at one of the first area and the second area, and wherein the common voltage connection portion is disposed at the other of the first area and the second area.

7. The light emitting display apparatus of claim 6, wherein the common electrode connection portion disposed at a 2k-1th horizontal line of the first through mth horizontal lines is disposed at the first area, and wherein the common electrode connection portion disposed at a 2kth horizontal line of the first through mth horizontal lines is disposed at the second area. ​ The common electrode connection portion disposed at the 2kth horizontal line among the first to mth horizontal lines is disposed at a second region.

8. The light emitting display device of claim 7, wherein a region between the 4n-3rd horizontal line and the 4n-2nd horizontal line among the first to mth horizontal lines is a disposed region of the branch network and a non-disposed region of the common electrode connection portion, wherein a region between the 4n-2nd horizontal line and the 4n-1st horizontal line among the first to mth horizontal lines is a disposed region of the common electrode connection portion; wherein a region between the 4n-1st horizontal line and the 4nth horizontal line among the first to mth horizontal lines is a disposed region of the branch network and a non-disposed region of the common electrode connection portion.

9. The light emitting display device of claim 6, wherein each of the plurality of common voltage connection portions comprises: a first electrode connection pattern electrically coupled to the pixel common voltage line; a passivation layer covering the first electrode connection pattern; a second electrode connection pattern disposed over the passivation layer and electrically coupled to the first electrode connection pattern; and a connection trench including an undercut region formed by removing the passivation layer between an end of the second electrode connection pattern and the first electrode connection pattern, and the common electrode is electrically coupled to a back surface and a bottom surface of the end of the second electrode pattern.

10. The light emitting display device of claim 9, wherein the end of the second electrode connection pattern has a eave structure with respect to the connection trench, and wherein the common electrode is electrically coupled to the first electrode connection pattern at the undercut region.

11. The light emitting display device of claim 5, further comprising: a plurality of secondary voltage lines disposed parallel to the plurality of pixel common voltage lines with the plurality of gate control lines each therebetween; a line connection pattern electrically coupling adjacent pixel common voltage lines and secondary voltage lines; and a plurality of secondary line connection portions disposed parallel to the plurality of common voltage connection portions to electrically couple the plurality of secondary voltage lines each to the common electrode.

12. The light emitting display device of claim 1, further comprising: a first pad portion disposed at one peripheral portion of the first substrate; a second substrate coupled to a back surface of the first substrate by a coupling element; a second pad portion disposed at a back surface of the second substrate to overlap the first pad portion; a third pad portion disposed at a back surface of the first substrate and electrically coupled to the second pad portion; a driving circuit portion coupled to the third pad portion; and a routing portion disposed at each of first outer surfaces of the first substrate and the second substrate and electrically coupled to the first pad portion and the second pad portion.

13. The light emitting display device of claim 12, further comprising: a first secondary pad portion disposed at another peripheral portion parallel to the one peripheral portion of the first substrate; a second secondary pad portion disposed at a back surface of the second substrate to overlap the first secondary pad and electrically coupled to the third pad portion; and a routing portion disposed at each of first outer surfaces of the first substrate and the second substrate and electrically coupled to the first pad portion and the second pad portion. ​ ​ a secondary routing portion provided at a second outer surface parallel to the first outer surface of each of the first substrate and the second substrate and electrically coupled to the first secondary pad portion and the second secondary pad portion.

14. The light emitting display device according to claim 13, further comprising a plurality of pixel driving power supply lines provided at a display region of the first substrate and coupled to each of the plurality of pixels, wherein a portion of each of the plurality of pixel driving power supply lines is electrically coupled to the first pad portion, and wherein another portion of each of the plurality of pixel driving power supply lines is electrically coupled to the first secondary pad portion.

15. The light emitting display device according to claim 14, wherein the driving circuit portion supplies a pixel driving power to the third pad portion, and wherein the pixel driving power is supplied to a portion of each of the plurality of pixel driving power supply lines through the third pad portion, the second pad portion, the routing portion, and the first pad portion, and to another portion of each of the plurality of pixel driving power supply lines through the third pad portion, the second secondary pad portion, the secondary routing portion, and the first secondary pad portion.

16. The light emitting display device according to claim 14, further comprising a plurality of secondary link lines provided at a rear surface of the second substrate and electrically coupled between the third pad portion and the second secondary pad portion.

17. The light emitting display device according to claim 14, further comprising: a secondary common line provided at a rear surface of the second substrate and electrically coupled to the second secondary pad portion; and a plurality of secondary link lines provided at a rear surface of the second substrate and electrically coupled between the third pad portion and the secondary common line.

18. The light emitting display device according to any one of claims 1 to 17, wherein a size of the display region is equal to a size of the first substrate, or wherein a distance between a center portion of an outermost pixel of the plurality of pixels and an outer surface of the first substrate is half or less of a pixel pitch, and wherein the pixel pitch is a distance between center portions of two pixels adjacent to each other.

19. A multi-screen display device comprising: a plurality of display devices provided along at least one of a first direction and a second direction intersecting the first direction, wherein each of the plurality of display devices comprises the display device according to any one of claims 1 to 17.

20. The multi-screen display device according to claim 19, wherein in first and second display devices adjacent along at least one of the first direction or the second direction, a distance between a center portion of an outermost pixel of the first display device and a center portion of an outermost pixel of the second display device is less than or equal to a pixel pitch, and wherein the pixel pitch is a distance between center portions of adjacent pixels along at least one of the first direction or the second direction.

21. The multi-screen display device according to claim 19 or 20, wherein the first display device and the second display device are provided in a same plane, and wherein the first display device and the second display device are provided in different planes.

Images