Brightness compensator and display system including the same

Abstract

Brightness compensators and display systems including brightness compensators are provided. The brightness compensator includes a memory device and a brightness compensation circuit. The memory device stores a plurality of brightness compensation data and provides first brightness compensation data and second brightness compensation data among the plurality of brightness compensation data in response to a frame rate dimming on signal. The first brightness compensation data corresponds to a first frame rate. The second brightness compensation data corresponds to a second frame rate. The plurality of brightness compensation data is used to compensate brightness of at least one region operating at a plurality of frame rates. The frame rate dimming on signal indicates a time interval during which a frame rate of the at least one region is gradually changed. The brightness compensation circuit generates third brightness compensation data in response to the frame rate dimming on signal, the first brightness compensation data, and the second brightness compensation data.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0184647, filed on December 28, 2020, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The example embodiments generally relate to semiconductor integrated circuits, and more specifically, to brightness compensators and display systems including brightness compensators. Background Technology

[0003] A display system capable of operating at multiple frame rates is being developed. The display system may include display panels such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light-emitting diode displays (OLEDs), and each display panel may include multiple pixels. The multiple pixels can be manufactured to display the same brightness for input data of the same grayscale, and brightness compensation can be performed to compensate for brightness deviations caused by defects in the manufacturing process and design. However, brightness deviations are identified when the frame rate changes due to the display system operating at multiple frame rates, or when multiple areas are included in the display panel and each of the multiple areas is driven independently at a different frame rate. Summary of the Invention

[0004] Some example embodiments may provide a brightness compensator and display system that can efficiently generate brightness compensation data, reduce memory resource consumption, and perform optimized brightness compensation.

[0005] According to an example embodiment, the brightness compensator includes a memory device and a brightness compensation circuit. The memory device stores a plurality of brightness compensation data and provides a first brightness compensation data and a second brightness compensation data among the plurality of brightness compensation data in response to a frame rate dimming enable signal. The first brightness compensation data corresponds to a first frame rate. The second brightness compensation data corresponds to a second frame rate. The plurality of brightness compensation data is used to compensate for the brightness of at least one area. The at least one area is included in a display panel and operates at a plurality of frame rates. The frame rate dimming enable signal indicates the time interval at which the frame rate of the at least one area gradually changes. The brightness compensation circuit generates third brightness compensation data in response to the frame rate dimming enable signal, the first brightness compensation data, and the second brightness compensation data. The third brightness compensation data corresponds to a third frame rate.

[0006] According to an example embodiment, the display system includes a display panel, an external memory device, a timing controller, and a brightness compensator. The display panel includes at least one area. The at least one area operates at multiple frame rates and includes multiple pixels. The external memory device stores multiple brightness compensation data for compensating the brightness of the at least one area. The timing controller provides a frame rate dimming enable signal and frame rate information. The frame rate dimming enable signal indicates the time interval at which the frame rate of the at least one area gradually changes. The frame rate information indicates the frame rate of the at least one area. The brightness compensator stores the multiple brightness compensation data and generates third brightness compensation data in response to the frame rate dimming enable signal, the frame rate information, and a first brightness compensation data and a second brightness compensation data among the multiple brightness compensation data. The first brightness compensation data corresponds to a first frame rate, the second brightness compensation data corresponds to a second frame rate, and the third brightness compensation data corresponds to a third frame rate.

[0007] According to an example embodiment, the brightness compensator includes a memory device and a brightness compensation circuit. The memory device stores a plurality of brightness compensation data and provides a first brightness compensation data and a second brightness compensation data among the plurality of brightness compensation data in response to a frame rate dimming enable signal. The first brightness compensation data corresponds to a first frame rate. The second brightness compensation data corresponds to a second frame rate. The plurality of brightness compensation data is used to compensate for the brightness of at least one area. The at least one area is included in a display panel and operates at a plurality of frame rates. The frame rate dimming enable signal indicates the time interval at which the frame rate of the at least one area gradually changes. The brightness compensation circuit generates third brightness compensation data in response to the frame rate dimming enable signal, the first brightness compensation data, and the second brightness compensation data. The third brightness compensation data corresponds to a third frame rate. The memory device includes a first memory and a second memory. The first memory stores the plurality of brightness compensation data. The second memory receives the first brightness compensation data and the second brightness compensation data among the plurality of brightness compensation data in response to the frame rate dimming enable signal. The second memory provides the first brightness compensation data and the second brightness compensation data to the brightness compensation circuit. The brightness compensation circuit includes a brightness compensation data provider and an image data compensator. A brightness compensation data provider receives a frame rate dimming enable signal, frame rate information, first brightness compensation data, and second brightness compensation data. In response to the frame rate information, the first brightness compensation data, the second brightness compensation data, and the frame rate dimming enable signal, the brightness compensation data provider generates third brightness compensation data. An image data compensator receives multiple input image data and the third brightness compensation data. In response to the third brightness compensation data, the image data compensator compensates the multiple input image data to generate multiple output image data for displaying an image.

[0008] A brightness compensator according to an example embodiment can be used to compensate for the brightness of a display panel operating in at least one area. An external memory device can store multiple brightness compensation data sets, and an internal memory device can store a portion of these multiple brightness compensation data sets. The brightness compensator can use the portion of the multiple brightness compensation data sets stored in the internal memory device to generate brightness compensation data for compensating the brightness of the display panel. Therefore, even when at least one area included in the display panel operates at multiple frame rates, brightness compensation data can be generated efficiently, and memory resource consumption can be reduced while performing brightness compensation optimized for each area. Attached Figure Description

[0009] The exemplary embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a brightness compensation device including a brightness compensator according to an example embodiment.

[0011] Figure 2 It is used to describe the storage Figure 1 A diagram illustrating an example of brightness compensation data stored in an external memory device.

[0012] Figure 3 This shows the generation Figure 2 A block diagram of an example embodiment of a system for generating brightness compensation data.

[0013] Figure 4 This is a diagram used to illustrate an example of a display panel operating at multiple frame rates.

[0014] Figure 5 and Figure 6 It is used to describe in Figure 4 The example provided in the example shows a diagram of an example embodiment of brightness compensation data.

[0015] Figure 7 It is shown Figure 1 A block diagram of an example embodiment of the brightness compensation circuit.

[0016] Figure 8 It is shown Figure 7 A block diagram of an example embodiment of a brightness compensation data provider.

[0017] Figure 9 This is a diagram used to describe an example of multiple areas included in a display panel and driven independently of each other at different frame rates.

[0018] Figure 10 Is it showing stored Figure 1A diagram illustrating an example of brightness compensation data stored in an external memory device.

[0019] Figure 11 This is a diagram used to illustrate an example of a display panel operating at multiple frame rates.

[0020] Figure 12 and Figure 13 It is used to describe in Figure 11 The example provided is a diagram of an example embodiment of brightness compensation data.

[0021] Figure 14 It is shown Figure 7 A block diagram of an example of a brightness compensation data provider.

[0022] Figure 15 This is a block diagram illustrating a display system according to an example embodiment.

[0023] Figure 16 This is a block diagram illustrating a display system according to an example embodiment.

[0024] Figure 17 This is a flowchart illustrating a method for compensating brightness according to an example embodiment.

[0025] Figure 18 This is a block diagram illustrating a display mobile device according to an example embodiment. Detailed Implementation

[0026] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments are illustrated. In the drawings, the same reference numerals always denote the same elements. Repeated descriptions may be omitted.

[0027] Figure 1 This is a block diagram illustrating a brightness compensation device including a brightness compensator according to an example embodiment.

[0028] Reference Figure 1 The brightness compensation device 100 may include a brightness compensator 110 and an external memory device 170. The brightness compensator 110 may include a brightness compensation circuit 130 and an internal memory device 150.

[0029] The brightness compensator 110 can receive multiple input image data IMGs from an external source (e.g., from a host processor located outside the brightness compensation device 100) and multiple brightness compensation data LCDAT1 and LCDAT2 from an external memory device 170.

[0030] The brightness compensator 110 can compensate multiple input image data IMG in response to multiple brightness compensation data LCDAT1 and LCDAT2 to generate multiple output image data CIMG, and provide the multiple output image data CIMG to a data driver (not shown) that drives the display panel.

[0031] In some embodiments, the display panel can operate at multiple frame rates. The display panel may include at least one region. For example, the display panel may include K regions operating at multiple frame rates, where K is an integer greater than or equal to 1. In this case, the K regions may operate at frame rates different from each other, and the brightness compensator 110 may generate multiple output image data CIMGs for the K regions included in the display panel.

[0032] In some embodiments, the brightness compensator 110 may also receive a frame rate dimming-on signal FRDO, frame rate information FRINFO, and a selection signal SEL from an external source. The frame rate dimming-on signal FRDO may represent a time interval in which the frame rate of at least one region changes gradually to mitigate brightness deviation when the frame rate of that at least one region changes rapidly. The frame rate information FRINFO may represent the frame rate of the at least one region. The selection signal SEL may be a signal used to select one of the at least one regions.

[0033] External memory device 170 can receive frame rate dimming enable signal FRDO and frame rate information FRINFO from the outside, and can provide a portion of multiple brightness compensation data LCDAT1 and LCDAT2 to internal memory device 150 in response to frame rate dimming enable signal FRDO and frame rate information FRINFO.

[0034] In some embodiments, the brightness compensation data LCDAT1 and LCDAT2 may be the same as those referred to later. Figure 4 The description includes the brightness compensation data corresponding to the start and end frames of the frame rate dimming.

[0035] In some embodiments, the external memory device 170 may provide a plurality of brightness compensation data LCDAT1 and LCDAT2 to the internal memory device 150 in response to a frame rate dimming enable signal FRDO, and may select the type of brightness compensation data LCDAT1 and LCDAT2 provided to the internal memory device 150 in response to frame rate information FRINFO. However, the exemplary embodiments are not limited thereto. In some embodiments, the external memory device 170 may provide a plurality of brightness compensation data LCDAT1 and LCDAT2 to the internal memory device 150 only in response to the frame rate information FRINFO, regardless of the frame rate dimming enable signal FRDO. In this case, when the display system including the brightness compensator 110 is started, the external memory device 170 may pre-provide a plurality of brightness compensation data LCDAT1 and LCDAT2 to the internal memory device 150 in response to an external signal indicating start-up.

[0036] The internal memory device 150 can store only a portion of the multiple brightness compensation data. The internal memory device 150 can receive a frame rate dimming enable signal FRDO and frame rate information FRINFO from an external source, and can provide only a portion of the multiple brightness compensation data LCDAT1 and LCDAT2 to the brightness compensation circuit 130 in response to the frame rate dimming enable signal FRDO and the frame rate information FRINFO. In this case, the internal memory device 150 can provide a portion of the multiple brightness compensation data LCDAT1 and LCDAT2 to the brightness compensation circuit 130 in response to the frame rate dimming enable signal FRDO, and when the display panel includes multiple areas, the internal memory device 150 can provide a portion of the brightness compensation data LCDAT1 and LCDAT2 to the brightness compensation circuit 130 in response to the frame rate information FRINFO to compensate for the brightness of the multiple areas included in the display panel.

[0037] In some embodiments, the external memory device 170 may be a non-volatile memory device capable of stably storing a large amount of multiple brightness compensation data even when power is off, and the internal memory device 150 may be a volatile memory device with fast access speed (although the stored data is lost when power is off).

[0038] In some embodiments, the external memory device 170 may include NAND flash memory. In some embodiments, the external memory device 170 may include electrically erasable programmable read-only memory (EEPROM), phase-change random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), etc.

[0039] In some embodiments, the internal memory device 150 may include static random access memory (SRAM), and in some embodiments, the internal memory device 150 may include dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM).

[0040] The brightness compensation circuit 130 can receive multiple input image data IMG, frame rate dimming enable signal FRDO and frame rate information FRINFO from the outside, and can receive multiple brightness compensation data LCDAT1 and LCDAT2 from the internal memory device 150.

[0041] In some embodiments, the brightness compensation circuit 130 may compensate multiple input image data (IMG) to generate multiple output image data (CIMG) in response to control by an external timing controller. In this case, the brightness compensation circuit 130 may generate third brightness compensation data in response to a frame rate dimming enable signal (FRDO), first brightness compensation data (LCDAT1), and second brightness compensation data (LCDAT2). The first brightness compensation data (LCDAT1) and the second brightness compensation data (LCDAT2) may be included in at least one of the multiple brightness compensation data. The first brightness compensation data (LCDAT1) may correspond to a first frame rate, the second brightness compensation data (LCDAT2) may correspond to a second frame rate, and the third brightness compensation data (LCDAT3) may correspond to a third frame rate.

[0042] The third frame rate can be a value between the first and second frame rates. That is, when the first frame rate is higher than the second frame rate, the third frame rate can be lower than the first frame rate but higher than the second frame rate. When the first frame rate is lower than the second frame rate, the third frame rate can be higher than the first frame rate but lower than the second frame rate.

[0043] In some embodiments, the first brightness compensation data LCDAT1 and the second brightness compensation data LCDAT2 can be provided from the external memory device 170 to the internal memory device 150 and from the internal memory device 150 to the brightness compensation circuit 130 in the form of data streams. In this case, the data stream used to provide the first brightness compensation data LCDAT1 and the second brightness compensation data LCDAT2 from the external memory device 170 to the internal memory device 150 can be referred to as the first brightness compensation data stream LCDAT_STR1. The data stream used to provide the first brightness compensation data LCDAT1 and the second brightness compensation data LCDAT2 from the internal memory device 150 to the brightness compensation circuit 130 can be referred to as the second brightness compensation data stream LCDAT_STR2.

[0044] The brightness compensator 110 according to the example embodiment can be used to compensate the brightness of a display panel operating in multiple regions. An external memory device 170 can store multiple brightness compensation data sets, and an internal memory device 150 can store only a portion of these multiple brightness compensation data sets. The brightness compensator 110 can generate brightness compensation data for compensating the brightness of the display panel using only the portion of the multiple brightness compensation data sets stored in the internal memory device 150. Therefore, even when at least one region included in the display panel operates at multiple frame rates, brightness compensation data can be generated efficiently, and memory resource consumption can be reduced while performing brightness compensation optimized for each region.

[0045] Figure 2 It is used to describe the storage Figure 1 A diagram illustrating an example of brightness compensation data stored in an external memory device.

[0046] Reference Figure 1 and Figure 2 The display panel may include at least one area and can operate at multiple frame rates (FR). Figure 2 The image shows an example of brightness compensation data LCDAT used to compensate for the brightness of a display panel when the display panel includes a single area.

[0047] In some embodiments, a region of the display panel (e.g., the entire region) can operate at a first frame rate FR1, a second frame rate FR2, a third frame rate FR3, a fourth frame rate FR4, a fifth frame rate FR5, a sixth frame rate FR6, a seventh frame rate FR7, an eighth frame rate FR8, a ninth frame rate FR9, and a tenth frame rate FR10. In this case, multiple brightness compensation data LC1, LC2, LC3, LC4, LC5, LC6, LC7, LC8, LC9, and LC10 can be generated for compensating for the brightness of the region of the display panel.

[0048] As shown above (refer to the reference) Figure 1 As described, multiple brightness compensation data LC1 to LC10 can be stored in external memory device 170, and only a portion of the multiple brightness compensation data LC1 to LC10 can be provided to internal memory device 150.

[0049] In some embodiments, brightness compensation data LC1 may be brightness compensation data LCDAT used to compensate the brightness of a region when the region operates at a first frame rate FR1, brightness compensation data LC2 may be brightness compensation data LCDAT used to compensate the brightness of a region when the region operates at a second frame rate FR2, and brightness compensation data LC3 may be brightness compensation data LCDAT used to compensate the brightness of a region when the region operates at a third frame rate FR3. Similarly, brightness compensation data LC4 to LC10 may be brightness compensation data LCDAT used to compensate the brightness of a region when the region operates at a fourth frame rate FR4 to a tenth frame rate FR10.

[0050] exist Figure 2 The image shows luminance compensation data LC1 to LC10 corresponding to the first frame rate FR1 to the tenth frame rate FR10, but the number of frame rates and the number of luminance compensation data are not limited to this.

[0051] Figure 3 This shows the generation Figure 2 A block diagram of an example embodiment of a system for generating brightness compensation data.

[0052] Reference Figure 3 The brightness compensation data generation system 300 can generate multiple brightness compensation data sets for compensating the brightness of the display panel. (See above for reference.) Figure 1 and Figure 2 As described, the display panel can operate at multiple frame rates. The display panel may include at least one area, and when the display panel includes two or more areas, the two or more areas may operate at different frame rates relative to each other.

[0053] In some embodiments, the brightness compensation data generation system 300 can generate multiple brightness compensation data points corresponding to multiple frame rates at which the display panel operates. Multiple brightness compensation data points can be generated to compensate for defects in the manufacturing and design of the display panel before the display panel is implemented as a display system.

[0054] In some embodiments, when the manufacturers of the display panel and the display system are different from each other, multiple brightness compensation data are generated by a brightness compensation data generation system 300, which is separate from the display system. The multiple brightness compensation data can be stored in a memory device, which is then used as... Figure 1 The external memory device 170 is implemented in the display system.

[0055] The brightness compensation data generation system 300 may include a brightness compensation data generator 310, a display panel 350, and a shooting device 390.

[0056] The brightness compensation data generator 310 can provide a plurality of test image data TDs to the display panel 350. In some embodiments, each of the plurality of test image data TDs may correspond to a frame rate. For example, the plurality of test image data TDs may each correspond to "L" frame rates. In some embodiments, when the plurality of test image data TDs corresponding to a first frame rate to a tenth frame rate are provided to the display panel 350, the first frame rate to the tenth frame rate may respectively (e.g., and sequentially) be one of 1Hz, 10Hz, 20Hz, 30Hz, 40Hz, 50Hz, 60Hz, 70Hz, 80Hz, 90Hz, and 100Hz. However, the exemplary embodiments are not limited thereto.

[0057] The display panel 350 can display a panel image in response to multiple test image data TDs. The imaging device 390 can capture a panel image and generate multiple brightness data LDs. The brightness compensation data generator 310 can generate multiple brightness compensation data in response to the multiple brightness data LDs. The brightness compensation data generator 310 can store the multiple brightness compensation data in the brightness compensation data memory 320.

[0058] Figure 4 This is a diagram used to illustrate an example of a display panel operating at multiple frame rates.

[0059] Figure 4 The above reference is shown. Figures 1 to 3 The described display panel includes examples of areas that operate at multiple frame rates over time.

[0060] Reference Figure 4 The display panel can display multiple images from the first frame (F1) to the tenth frame (F10) over time. For example, although not shown in detail, the frame rate of the display panel can gradually change from the third frame (F3) to the ninth frame (F9). (See above reference...) Figure 1 As described, when the frame rate of the area included in the display panel changes rapidly, the frame rate can be (e.g., gradually) changed to mitigate brightness deviations.

[0061] The frame rate dimming start frame (FRDM_STR) and frame rate dimming end frame (FRDM_END) can be defined. The frame rate dimming start frame (FRDM_STR) represents the frame at which the frame rate change begins, and the frame rate dimming end frame (FRDM_END) represents the frame at which the frame rate change ends. The time interval between the frame rate dimming start frame (FRDM_STR) and the frame rate dimming end frame (FRDM_END) can be defined as the frame rate dimming interval (FRDM_INT).

[0062] In some embodiments, the above references Figure 1The frame rate dimming enable signal FRDO described can represent the frame rate dimming start frame FRDM_STR and the frame rate dimming end frame FRDM_END. In some embodiments, the frame rate dimming enable signal FRDO can also represent the frame rate dimming interval FRDM_INT.

[0063] Figure 5 and Figure 6 It is used to describe in Figure 4 The example provided in the example shows a diagram of an example embodiment of brightness compensation data.

[0064] exist Figure 5 The image shows the frame number FN of the display panel and the corresponding frame rate FR. The frame number FN is the same as the one referenced above. Figure 4 This describes a corresponding frame from F1 to F10. The frame rate FR corresponds to the one mentioned above. Figure 2 The description corresponds to one of the first frame rates FR1 to the tenth frame rate FR10.

[0065] In the following text, for ease of description, it is assumed that among the first frame rate FR1 to the tenth frame rate FR10, the first frame rate FR1 represents the minimum frame rate, and the tenth frame rate FR10 represents the maximum frame rate. That is, the first frame rate FR1 to the tenth frame rate FR10 are considered to represent frame rates increasing from the first frame rate FR1 to the tenth frame rate FR10. However, the exemplary embodiments are not limited to this. In some embodiments, the first frame rate FR1 may represent the maximum frame rate, and the tenth frame rate FR10 may represent the minimum frame rate.

[0066] exist Figure 6 The diagram shows the clock signal CLK, the frame rate dimming enable signal FRDO, the frame rate information FRINFO, the second brightness compensation data stream LCDAT_STR2, and the final brightness compensation data stream F_LCDAT_STR. (See also: [link to documentation]). Figure 7 and Figure 8 Describes the final brightness compensation data stream F_LCDAT_STR.

[0067] Reference Figures 1 to 6 In the first frame F1, the display panel operates at the third frame rate FR3, and this frame rate remains constant until the third frame F3. In the fourth frame F4, the frame rate increases to the fourth frame rate FR4, and in the fifth frame F5, the frame rate increases to the fifth frame rate FR5. In the sixth frame F6, the frame rate increases to the sixth frame rate FR6, and this frame rate remains constant until the eighth frame F8. In the ninth frame F9, the frame rate increases to the seventh frame rate FR7, and this frame rate remains constant until the tenth frame F10.

[0068] In some embodiments, the above references Figures 1 to 4 The described frame rate dimming enable signal FRDO can correspond to a first level in the first frame F1, the second frame F2, and the tenth frame F10 (e.g., Figure 6 The low level in the middle), and from the third frame F3 to the ninth frame F9 correspond to a second level that is different from the first level (e.g., the ... Figure 6 (high level in the middle).

[0069] When the frame rate dimming enable signal FRDO changes from a first level to a second level, FRDO can represent an interval in which the frame rate changes rapidly (i.e., an interval in which the frame rate increases or decreases). Conversely, when FRDO changes from a second level to a first level, FRDO can represent an interval in which the frame rate does not change (i.e., an interval in which the frame rate does not increase or decrease). In this case, the frame rate information FRINFO can represent the frame rate at which the display panel area operates. Specifically, when the frame rate dimming enable signal FRDO changes from a first level to a second level, the frame rate information FRINFO can represent the frame rates corresponding to the frame rate dimming start frame and the frame rate dimming end frame, respectively (e.g., ...). Figure 6 (FR3 and FR7 in the example). In this case, the external memory device 170 can store multiple luminance compensation data LC1 to LC10 corresponding to the first frame F1 to the tenth frame F10 or the first frame rate FR1 to the tenth frame rate FR10, respectively.

[0070] In the first frame F1 and the second frame F2, the external memory device 170 can provide the brightness compensation data LC3 corresponding to the third frame rate FR3 as the first brightness compensation data LCDAT1 to the internal memory device 150 based on the frame rate information FRINFO. The internal memory device 150 can temporarily store the brightness compensation data LC3 and provide the brightness compensation data LC3 to the brightness compensation circuit 130. In the third frame F3, the external memory device 170 can provide the brightness compensation data LC7 corresponding to the seventh frame rate FR7 as the second brightness compensation data LCDAT2 to the internal memory device 150 based on the frame rate information FRINFO.

[0071] In some embodiments, the brightness compensation data LC3 may correspond to the above reference. Figure 4 The frame rate dimming start frame described is FRDM_STR, and the brightness compensation data LC7 can correspond to the above reference. Figure 4 The frame rate dimming end frame described is FRDM_END.

[0072] The internal memory device 150 can temporarily store brightness compensation data LC3 and LC7, and provide the brightness compensation data LC3 and LC7 to the brightness compensation circuit 130.

[0073] In frames F4 through F9, external memory device 170 does not provide brightness compensation data to internal memory device 150, internal memory device 150 does not provide brightness compensation data to brightness compensation circuit 130, and external memory device 170 and internal memory device 150 may have rest intervals (e.g., Figure 6 The shaded portion of the second brightness compensation data stream LCDAT_STR2 in the image. The brightness compensation data (e.g., LC4, LC5, LC6, and LC7) corresponding to the fourth frame F4 to the ninth frame F9 can be obtained by the brightness compensation circuit 130 (more specifically, Figure 8 Included in Figure 7 The interpolation circuit 147 in the brightness compensation data provider 133 generates the data based on the brightness compensation data (e.g., LC3 and LC7) provided in the previous frames (e.g., F2 and F3).

[0074] In the tenth frame F10, the external memory device 170 can provide the brightness compensation data LC7 corresponding to the seventh frame rate FR7 as the second brightness compensation data LCDAT2 to the internal memory device 150. The internal memory device 150 can temporarily store the brightness compensation data LC7 and provide the brightness compensation data LC7 to the brightness compensation circuit 130.

[0075] In other words, when the Frame Rate Dimming Enable (FRDO) signal changes to the second level and remains there, the external memory device 170 can [operate] within a predetermined time interval (e.g., during [time period]). Figure 5 During this period, a portion of a plurality of brightness compensation data LC1 to LC10 is provided to the internal memory device 150 once, up to at least one interval in which the frame number increases. Furthermore, when the frame rate dimming enable signal FRDO changes to the first level and remains there, whenever the frame number FN changes, the external memory device 170 can provide the internal memory device 150 with the brightness compensation data from the plurality of brightness compensation data LC1 to LC10 that corresponds to the frame rate at which the display panel operates, based on the frame rate information FRINFO.

[0076] Figure 7 It is shown Figure 1 A block diagram of an example embodiment of the brightness compensation circuit.

[0077] Reference Figure 7 The brightness compensation circuit 130 may include an image data compensator 131 and a brightness compensation data provider 133. The image data compensator 131 and the brightness compensation data provider 133 may operate based on a common input clock signal CLK.

[0078] The brightness compensation data provider 133 can receive the frame rate dimming enable signal FRDO, the frame rate information FRINFO, the first brightness compensation data LCDAT1, and the second brightness compensation data LCDAT2.

[0079] In some embodiments, as referred to above Figure 1 As described, the first brightness compensation data LCDAT1 and the second brightness compensation data LCDAT2 can be received in the form of the second brightness compensation data stream LCDAT_STR2.

[0080] In some embodiments, as referred to above Figure 5 and Figure 6 As described, the brightness compensation data provider 133 may receive only the first brightness compensation data LCDAT1 before the frame rate dimming enable signal FRDO changes to the second level, the brightness compensation data provider 133 may receive only the second brightness compensation data LCDAT2 when the frame rate dimming enable signal FRDO changes to the second level (e.g., and holds), and the brightness compensation data provider 133 may receive only the second brightness compensation data LCDAT2 after the frame rate dimming enable signal FRDO changes from the second level to the first level.

[0081] When the frame rate dimming enable signal FRDO corresponds to the first level, the brightness compensation data provider 133 can provide one of the first brightness compensation data LCDAT1 and the second brightness compensation data LCDAT2 to the image data compensator 131. And when the frame rate dimming enable signal FRDO corresponds to the second level, the brightness compensation data provider 133 can generate a third brightness compensation data LCDAT3 in response to the frame rate information FRINFO, the first brightness compensation data LCDAT1, and the second brightness compensation data LCDAT2, and provide the third brightness compensation data LCDAT3 to the image data compensator 131. The third brightness compensation data LCDAT3 can correspond to the frame rate at which the display panel operates. (Refer to later...) Figure 8 and Figure 14 The configuration used to generate the third brightness compensation data LCDAT3 is described. For example, when the frame rate dimming enable signal FRDO corresponds to the second level, the first brightness compensation data LCDAT1 can correspond to the brightness compensation data LC3, the second brightness compensation data LCDAT2 can correspond to the brightness compensation data LC7, and the third brightness compensation data LCDAT3 can correspond to the brightness compensation data LC4, LC5, and LC6.

[0082] In some embodiments, the first brightness compensation data LCDAT1 to the third brightness compensation data LCDAT3 can be provided from the brightness compensation data provider 133 to the image data compensator 131 in the form of a final brightness compensation data stream F_LCDAT_STR. For example, in Figure 7 In the example shown, the final brightness compensation data stream F_LCDAT_STR can be provided from the brightness compensation data provider 133 to the image data compensator 131.

[0083] Image data compensator 131 can receive multiple input image data IMGs from an external source, and receives one of a first brightness compensation data LCDAT1, a second brightness compensation data LCDAT2, and a third brightness compensation data LCDAT3 from a brightness compensation data provider 133. Image data compensator 131 can compensate the multiple input image data IMGs in response to one of the first brightness compensation data LCDAT1, the second brightness compensation data LCDAT2, and the third brightness compensation data LCDAT3 to generate multiple output image data CIMGs for displaying an image.

[0084] Figure 8 It is shown Figure 7 A block diagram of an example embodiment of a brightness compensation data provider.

[0085] Reference Figure 7 and Figure 8 The brightness compensation data provider 133 may include a demultiplexer 141, a receive selection buffer 143, a receive buffer 145, and an interpolation circuit 147.

[0086] Demultiplexer 141 can receive first brightness compensation data LCDAT1 and second brightness compensation data LCDAT2. In some embodiments, demultiplexer 141 can receive... Figure 1 The internal memory device 150 receives first brightness compensation data LCDAT1 and second brightness compensation data LCDAT2.

[0087] In response to the frame rate dimming enable signal FRDO, demultiplexer 141 can provide one of the first brightness compensation data LCDAT1 and the second brightness compensation data LCDAT2 to the first terminal T1 or provide the second brightness compensation data LCDAT2 to the second terminal T2. In some embodiments, when the frame rate dimming enable signal FRDO corresponds to a first level, demultiplexer 141 can provide one of the first brightness compensation data LCDAT1 and the second brightness compensation data LCDAT2 to the receive selection buffer 143, and when the frame rate dimming enable signal FRDO corresponds to a second level, demultiplexer 141 can provide the second brightness compensation data LCDAT2 to the receive buffer 145.

[0088] The receive selection buffer 143 is connected to the first terminal T1 to receive and temporarily store the first brightness compensation data LCDAT1 and the second brightness compensation data LCDAT2 from the demultiplexer 141.

[0089] The receive selection buffer 143 also receives a frame rate dimming enable signal FRDO, and can output first brightness compensation data LCDAT1 and second brightness compensation data LCDAT2 to the image data compensator 131 or output the first brightness compensation data LCDAT1 to the interpolation circuit 147 in response to the frame rate dimming enable signal FRDO. In some embodiments, when the frame rate dimming enable signal FRDO corresponds to a first level, the receive selection buffer 143 can output the first brightness compensation data LCDAT1 and the second brightness compensation data LCDAT2 to the image data compensator 131, and when the frame rate dimming enable signal FRDO corresponds to a second level, the receive selection buffer 143 can output the first brightness compensation data LCDAT1 to the interpolation circuit 147.

[0090] The receive buffer 145 is connected to the second terminal T2 to receive and temporarily store the second brightness compensation data LCDAT2 from the demultiplexer 141.

[0091] Interpolation circuit 147 is connected to receive selection buffer 143 and receive buffer 145 to receive and temporarily store first brightness compensation data LCDAT1 and second brightness compensation data LCDAT2. Interpolation circuit 147 also receives frame rate information FRINFO and can generate third brightness compensation data LCDAT3 in response to frame rate information FRINFO, first brightness compensation data LCDAT1, and second brightness compensation data LCDAT2, to output the third brightness compensation data LCDAT3 to image data compensator 131. In some embodiments, when frame rate dimming enable signal FRDO corresponds to the second level, interpolation circuit 147 can generate third brightness compensation data LCDAT3 in response to frame rate information FRINFO, first brightness compensation data LCDAT1, and second brightness compensation data LCDAT2. In this case, frame rate information FRINFO may include coefficients required for the interpolation process. For example, in Figure 6 In the embodiment, the interpolation circuit 147 can receive brightness compensation data (e.g., LC3) as first brightness compensation data LCDAT1, and brightness compensation data (e.g., LC7) as second brightness compensation data LCDAT2. The interpolation circuit 147 can interpolate the first brightness compensation data LCDAT1 and the second brightness compensation data LCDAT2 to generate brightness compensation data LC4, LC5, and LC6 as third brightness compensation data LCDAT3.

[0092] In some embodiments, the first brightness compensation data LCDAT1 to the third brightness compensation data LCDAT3 can be provided from the brightness compensation data provider 133 to the image data compensator 131 in the form of a final brightness compensation data stream F_LCDAT_STR.

[0093] Figure 9 This is a diagram used to describe an example of multiple areas included in a display panel and driven independently of each other at different frame rates.

[0094] exist Figure 9 The image shows a foldable electronic device including a display panel. (See reference above.) Figure 1 As described, the display panel may include at least one area.

[0095] Reference Figure 9 The display panel can be centered around the folding axis F and include a first region R1 on one side and a second region R2 and a third region R3 on the other side.

[0096] Each of the first region R1, the second region R2, and the third region R3 can operate at a different frame rate. In this case, the frame rate dimming enable signal FRDO can be set independently for each of the first region R1, the second region R2, and the third region R3. For example, a first frame rate dimming enable signal FRDO1 can be set for the first region R1, a second frame rate dimming enable signal FRDO2 can be set for the second region R2, and a third frame rate dimming enable signal FRDO3 can be set for the third region R3.

[0097] Figure 10 Is it showing stored Figure 1 A diagram illustrating an example of brightness compensation data stored in an external memory device.

[0098] exist Figure 10 The image shows an example of brightness compensation data LCDAT used to compensate for the brightness of a display panel when the display panel comprises three areas.

[0099] In some embodiments, the first region R1 of the display panel can operate at an eleventh frame rate FR11 to a twentieth frame rate FR20. The second region R2 of the display panel can operate at a twenty-first frame rate FR21 to a thirtieth frame rate FR30. The third region R3 of the display panel can operate at a thirty-first frame rate FR31 to a fortieth frame rate FR40. In this case, multiple brightness compensation data LC11 to LC20 can be generated to compensate for the brightness of the first region R1, multiple brightness compensation data LC21 to LC30 can be generated to compensate for the brightness of the second region R2, and multiple brightness compensation data LC31 to LC40 can be generated to compensate for the brightness of the third region R3.

[0100] As shown above (refer to the reference) Figure 1 As described, multiple brightness compensation data LC11 to LC40 can be stored in an external memory device 170, and only a portion of the multiple brightness compensation data LC11 to LC40 can be provided to and stored in an internal memory device 150 to compensate for multiple input image data IMG input to the brightness compensator 110.

[0101] In some embodiments, brightness compensation data LC11 may be brightness compensation data LCDAT used to compensate the brightness of the first region R1 when the first region R1 operates at an eleventh frame rate FR11; brightness compensation data LC12 may be brightness compensation data LCDAT used to compensate the brightness of the first region R1 when the first region R1 operates at a twelfth frame rate FR12; and brightness compensation data LC13 may be brightness compensation data LCDAT used to compensate the brightness of the first region R1 when the first region R1 operates at a thirteenth frame rate FR13. Brightness compensation data LC14 to LC20 may be brightness compensation data LCDAT used in a similar manner to brightness compensation data LC11 to LC13 to compensate the brightness of the first region R1 when the first region R1 operates at a fourteenth frame rate FR14 to a twentieth frame rate FR20.

[0102] In some embodiments, brightness compensation data LC21 may be brightness compensation data LCDAT used to compensate the brightness of the second region R2 when the second region R2 operates at a twenty-first frame rate FR21; brightness compensation data LC22 may be brightness compensation data LCDAT used to compensate the brightness of the second region R2 when the second region R2 operates at a twenty-second frame rate FR22; and brightness compensation data LC23 may be brightness compensation data LCDAT used to compensate the brightness of the second region R2 when the second region R2 operates at a twenty-third frame rate FR23. Brightness compensation data LC24 to LC30 may be brightness compensation data LCDAT used in a similar manner to brightness compensation data LC21 to LC23 to compensate the brightness of the second region R2 when the second region R2 operates at a twenty-fourth frame rate FR24 to a thirtieth frame rate FR30.

[0103] In some embodiments, brightness compensation data LC31 may be brightness compensation data LCDAT used to compensate the brightness of the third region R3 when the third region R3 operates at a thirty-first frame rate FR31; brightness compensation data LC32 may be brightness compensation data LCDAT used to compensate the brightness of the third region R3 when the third region R3 operates at a thirty-second frame rate FR32; and brightness compensation data LC33 may be brightness compensation data LCDAT used to compensate the brightness of the third region R3 when the third region R3 operates at a thirty-third frame rate FR33. Brightness compensation data LC34 to LC40 may be brightness compensation data LCDAT used in a similar manner to brightness compensation data LC31 to LC33 to compensate the brightness of the third region R3 when the third region R3 operates at a thirty-fourth frame rate FR34 to a fortieth frame rate FR40.

[0104] Figure 11 This is a diagram used to illustrate an example of a display panel operating at multiple frame rates.

[0105] Figure 11 The above reference is shown. Figure 1 , Figure 9 and Figure 10 The described display panel includes examples of three areas operating at multiple frame rates over time.

[0106] Reference Figure 11The display panel can display multiple images from frame 1 (F1) to frame 10 (F10) over time. For example, the frame rate of the first area R1 included in the display panel can gradually change from frame 2 (F2) to frame 9 (F9). The frame rate of the second area R2 included in the display panel can gradually change from frame 4 (F4) to frame 10 (F10). The frame rate of the third area R3 included in the display panel can gradually change from frame 6 (F6) to frame 8 (F8). (Refer to the above...) Figure 1 As described, when the frame rate of each of the first region R1, the second region R2, and the third region R3 included in the display panel changes rapidly, the frame rate can be (e.g., gradually) changed to mitigate brightness deviation.

[0107] The frame rate dimming start frames FRDM_STR1, FRDM_STR2, and FRDM_STR3, and the frame rate dimming end frames FRDM_END1, FRDM_END2, and FRDM_END3 can be defined for the first region R1, the second region R2, and the third region R3, respectively. The frame rate dimming start frames FRDM_STR1, FRDM_STR2, and FRDM_STR3 can represent the frames at which the frame rate change begins, and the frame rate dimming end frames FRDM_END1, FRDM_END2, and FRDM_END3 can represent the frames at which the frame rate change ends. The time intervals between the frame rate dimming start frames FRDM_STR1, FRDM_STR2, and FRDM_STR3 and the frame rate dimming end frames FRDM_END1, FRDM_END2, and FRDM_END3 can be defined as frame rate dimming intervals FRDM_INT1, FRDM_INT2, and FRDM_INT3.

[0108] In some embodiments, the above references Figure 1 The frame rate dimming enable signal FRDO described can represent the frame rate dimming start frames FRDM_STR1, FRDM_STR2, and FRDM_STR3, and the frame rate dimming end frames FRDM_END1, FRDM_END2, and FRDM_END3. In some embodiments, the frame rate dimming enable signal FRDO can also represent the frame rate dimming intervals FRDM_INT1, FRDM_INT2, and FRDM_INT3.

[0109] Figure 12 and Figure 13 It is used to describe in Figure 11 The example provided is a diagram of an example embodiment of brightness compensation data.

[0110] exist Figure 12 The image shows the frame number FN of the display panel and the corresponding frame rate FR. The frame number FN corresponds to the reference above. Figure 11The description refers to one of the multiple frames F1 to F10. The frame rate FR corresponds to the reference above. Figure 10 The eleventh frame rate FR11 to the fortieth frame rate FR40 are described.

[0111] In the following text, for ease of description, it is assumed that among the eleventh frame rate FR11 to the fortieth frame rate FR40, the eleventh frame rate FR11 represents the minimum frame rate, and the fortieth frame rate FR40 represents the maximum frame rate. That is, the eleventh frame rate FR11 to the fortieth frame rate FR40 are considered to represent frame rates increasing from the eleventh frame rate FR11 to the fortieth frame rate FR40. However, the exemplary embodiments are not limited thereto. In some embodiments, the eleventh frame rate FR11 may represent the maximum frame rate, and the fortieth frame rate FR40 may represent the minimum frame rate.

[0112] exist Figure 13 The diagram illustrates a clock signal CLK, frame rate dimming enable signals FRDO1 to FRDO3, frame rate information FRINFO, a second brightness compensation data stream LCDAT_STR2, and a final brightness compensation data stream F_LCDAT_STR. In some embodiments, the frame rate information FRINFO may include frame rate information corresponding to the first regions R1 to the third regions R3 included in the display panel (e.g., ...). Figure 14 The example embodiments are not limited to FRINFO1, FRINFO2, and FRINFO3.

[0113] Will first refer to Figure 1 and Figures 9 to 12 Let's describe the first region R1. In the first frame F1, the display panel operates at a frame rate of thirteenth frame rate FR13, and this frame rate remains constant until the second frame F2. In the third frame F3, the frame rate increases to a frame rate of fourteenth frame rate FR14, and this frame rate remains constant until the fourth frame F4. In the fifth frame F5, the frame rate increases to a frame rate of fifteenth frame rate FR15, and this frame rate remains constant until the sixth frame F6. In the seventh frame F7, the frame rate increases to a frame rate of sixteenth frame rate FR16, and this frame rate remains constant until the eighth frame F8. In the ninth frame F9, the frame rate increases to a frame rate of seventeenth frame rate FR17, and this frame rate remains constant until the tenth frame F10.

[0114] In some embodiments, the frame rate dimming enable signal FRDO1 can correspond to a first level in the first frame F1 and the tenth frame F10 (e.g., Figure 13 The low level in the middle), and from the second frame F2 to the ninth frame F9 correspond to a second level that is different from the first level (e.g., the ... Figure 13 (high level in the middle).

[0115] When the frame rate dimming enable signal FRDO1 changes from a first level to a second level, FRDO1 can represent the interval of frame rate change (i.e., the interval of frame rate increase or decrease), and when the frame rate dimming enable signal FRDO1 changes from a second level to a first level, FRDO1 can represent the interval of frame rate not changing (i.e., the interval of frame rate not increasing or decreasing). In this case, the frame rate information FRINFO can represent the frame rate at which the display panel area operates. Specifically, when the frame rate dimming enable signal FRDO1 changes from a first level to a second level, the frame rate information FRINFO can represent the frame rates corresponding to the frame rate dimming start frame and the frame rate dimming end frame, respectively (e.g., ...). Figure 13 (FR13 and FR17 ​​in the example). In this case, the external memory device 170 can store multiple luminance compensation data LC11 to LC20 corresponding to the first frame F1 to the tenth frame F10 or the eleventh frame rate FR11 to the twentieth frame rate FR20, respectively.

[0116] In the first frame F1, the external memory device 170 can provide the brightness compensation data LC13 corresponding to the thirteenth frame rate FR13 as the first brightness compensation data LCDAT11 corresponding to the first region R1 to the internal memory device 150 based on the frame rate information FRINFO. The internal memory device 150 can temporarily store the brightness compensation data LC13 and provide the brightness compensation data LC13 to the brightness compensation circuit 130. In the second frame F2, the external memory device 170 can provide the brightness compensation data LC17 corresponding to the seventeenth frame rate FR17 ​​as the second brightness compensation data LCDAT12 to the internal memory device 150 based on the frame rate information FRINFO.

[0117] In some embodiments, the brightness compensation data LC13 may correspond to the above reference. Figure 11 The frame rate dimming start frame described is FRDM_STR1, and the brightness compensation data LC17 can correspond to the above reference. Figure 11 The frame rate dimming end frame described is FRDM_END1.

[0118] The internal memory device 150 can temporarily store brightness compensation data LC13 and LC17, and provide the brightness compensation data LC13 and LC17 to the brightness compensation circuit 130.

[0119] In frames F3 through F9, the external memory device 170 does not provide the brightness compensation data corresponding to the first region R1 to the internal memory device 150, and the internal memory device 150 does not provide the brightness compensation data corresponding to the first region R1 to the brightness compensation circuit 130. The brightness compensation data (e.g., LC14, LC15, LC16, and LC17) corresponding to the first region R1 in frames F3 through F9 can be generated by the brightness compensation circuit 130 based on the brightness compensation data (e.g., LC13 and LC17) provided in previous frames (e.g., F1 and F2).

[0120] In the tenth frame F10, the external memory device 170 can provide the brightness compensation data LC17 corresponding to the seventeenth frame rate FR17 ​​as the second brightness compensation data LCDAT12 corresponding to the first region R1 to the internal memory device 150. The internal memory device 150 can temporarily store the brightness compensation data LC17 and provide the brightness compensation data LC17 to the brightness compensation circuit 130.

[0121] In other words, when the frame rate dimming enable signal FRDO1 changes to the second level and remains there, the external memory device 170 can provide a portion of the multiple brightness compensation data LC11 to LC20 to the internal memory device 150 once within a predetermined time interval. Furthermore, when the frame rate dimming enable signal FRDO1 changes to the first level and remains there, whenever the frame number FN changes, the external memory device 170 can provide the internal memory device 150 with the brightness compensation data from the multiple brightness compensation data LC11 to LC20 that corresponds to the frame rate at which the display panel operates, based on the frame rate information FRINFO.

[0122] The second region R2 and the third region R3 will be described. The second region R2 and the third region R3 can also operate in a similar manner to the first region R1 described above. However, for the second region R2, the frame rate dimming enable signal FRDO2 corresponds to a first level from the first frame F1 to the third frame F3, and to a second level from the fourth frame F4 to the tenth frame F10. For the third region R3, the frame rate dimming enable signal FRDO3 corresponds to a first level from the first frame F1 to the fifth frame F5, and in the ninth frame F9 and the tenth frame F10, and to a second level from the sixth frame F6 to the eighth frame F8.

[0123] When the frame rate dimming enable signal FRDO2 changes from the first level to the second level, FRDO2 represents the interval at which the frame rate of the second region R2 changes. When FRDO2 changes from the second level to the first level, it represents the interval at which the frame rate of the second region R2 remains unchanged. Similarly, when the frame rate dimming enable signal FRDO3 changes from the first level to the second level, it represents the interval at which the frame rate of the third region R3 changes. And when FRDO3 changes from the second level to the first level, it represents the interval at which the frame rate of the third region R3 remains unchanged.

[0124] Figure 14 It is shown Figure 7 A block diagram of an example of a brightness compensation data provider.

[0125] Reference Figure 7 and Figure 14 The brightness compensation data provider 133-1 may include a first demultiplexer 149, a second demultiplexer 141-1, a third demultiplexer 141-2 and a fourth demultiplexer 141-3, a first receive selection buffer 143-1, a second receive selection buffer 143-2 and a third receive selection buffer 143-3, a first receive buffer 145-1, a second receive buffer 145-2 and a third receive buffer 145-3, and a first interpolation circuit 147-1, a second interpolation circuit 147-2 and a third interpolation circuit 147-3.

[0126] The first demultiplexer 149 can receive first brightness compensation data LCDAT11, LCDAT21, and LCDAT31 corresponding to the first region R1 to the third region R3, and second brightness compensation data LCDAT12, LCDAT22, and LCDAT32. In some embodiments, the first demultiplexer 149 can receive first brightness compensation data LCDAT11, LCDAT21, and LCDAT31 corresponding to the first region R1 to the third region R3, and second brightness compensation data LCDAT12, LCDAT22, and LCDAT32. Figure 1 The internal memory device 150 receives first brightness compensation data LCDAT11, LCDAT21 and LCDAT31 and second brightness compensation data LCDAT12, LCDAT22 and LCDAT32.

[0127] The first demultiplexer 149 may, in response to the selection signal SEL, provide a portion of the first brightness compensation data LCDAT11, LCDAT21, and LCDAT31, and the second brightness compensation data LCDAT12, LCDAT22, and LCDAT32 to one of the third terminal T41, the fourth terminal T42, and the fifth terminal T43.

[0128] In some embodiments, when the selection signal SEL corresponds to the first region R1, the first demultiplexer 149 can provide the first brightness compensation data LCDAT11 and the second brightness compensation data LCDAT12 corresponding to the first region R1 to the second demultiplexer 141-1. When the selection signal SEL corresponds to the second region R2, the first demultiplexer 149 can provide the first brightness compensation data LCDAT21 and the second brightness compensation data LCDAT22 corresponding to the second region R2 to the third demultiplexer 141-2. When the selection signal SEL corresponds to the third region R3, the first demultiplexer 149 can provide the first brightness compensation data LCDAT31 and the second brightness compensation data LCDAT32 corresponding to the third region R3 to the fourth demultiplexer 141-3.

[0129] The second demultiplexer 141-1 is connected to the third terminal T41 to receive first brightness compensation data LCDAT11 and second brightness compensation data LCDAT12 corresponding to the first region R1. In response to the frame rate dimming enable signal FRDO1, the second demultiplexer 141-1 can provide one of the first brightness compensation data LCDAT11 and the second brightness compensation data LCDAT12 to the sixth terminal T11 or provide the second brightness compensation data LCDAT12 to the seventh terminal T12. In some embodiments, the second demultiplexer 141-1 can provide one of the first brightness compensation data LCDAT11 and the second brightness compensation data LCDAT12 to the first receive select buffer 143-1 when the frame rate dimming enable signal FRDO1 corresponds to a first level, and provide the second brightness compensation data LCDAT12 to the first receive buffer 145-1 when the frame rate dimming enable signal FRDO1 corresponds to a second level.

[0130] The first receive selection buffer 143-1 is connected to the sixth terminal T11 to receive and temporarily store the first brightness compensation data LCDAT11 and the second brightness compensation data LCDAT12 corresponding to the first region R1 from the second demultiplexer 141-1.

[0131] The first receive selection buffer 143-1 can also receive the frame rate dimming enable signal FRDO1, and can output the first brightness compensation data LCDAT11 and the second brightness compensation data LCDAT12 to the image data compensator 131 or output the first brightness compensation data LCDAT11 to the first interpolation circuit 147-1 in response to the frame rate dimming enable signal FRDO1.

[0132] The first receive buffer 145-1 is connected to the seventh terminal T12 to receive and temporarily store the second brightness compensation data LCDAT12 corresponding to the first region R1 from the second demultiplexer 141-1.

[0133] The first interpolation circuit 147-1 is connected to the first receive selection buffer 143-1 and the first receive buffer 145-1 to receive and temporarily store the first brightness compensation data LCDAT11 and the second brightness compensation data LCDAT12 corresponding to the first region R1.

[0134] The first interpolation circuit 147-1 also receives frame rate information FRINFO1, and can generate third brightness compensation data LCDAT13 corresponding to the first region R1 in response to the frame rate information FRINFO1, the first brightness compensation data LCDAT11, and the second brightness compensation data LCDAT12. The first interpolation circuit 147-1 can output the third brightness compensation data LCDAT13 to the image data compensator 131.

[0135] The third demultiplexer 141-2, the second receive selection buffer 143-2, the second receive buffer 145-2, and the second interpolation circuit 147-2 can also operate on the second region R2 in a similar manner to the second demultiplexer 141-1, the first receive selection buffer 143-1, the first receive buffer 145-1, and the first interpolation circuit 147-1. For example, the third demultiplexer 141-2 can be connected to the fourth terminal T42, the second receive selection buffer 143-2 can be connected to the eighth terminal T21, and the second receive buffer 145-2 can be connected to the ninth terminal T22. For example, the second interpolation circuit 147-2 can generate third brightness compensation data LCDAT23 corresponding to the second region R2 in response to the frame rate information FRINFO2, the first brightness compensation data LCDAT21, and the second brightness compensation data LCDAT22.

[0136] The fourth demultiplexer 141-3, the third receive selection buffer 143-3, the third receive buffer 145-3, and the third interpolation circuit 147-3 can also operate on the third region R3 in a similar manner to the second demultiplexer 141-1, the first receive selection buffer 143-1, the first receive buffer 145-1, and the first interpolation circuit 147-1. For example, the fourth demultiplexer 141-3 can be connected to the fifth terminal T43, the third receive selection buffer 143-3 can be connected to the tenth terminal T31, and the third receive buffer 145-3 can be connected to the eleventh terminal T32. For example, the third interpolation circuit 147-3 can generate third brightness compensation data LCDAT33 corresponding to the third region R3 in response to frame rate information FRINFO3, first brightness compensation data LCDAT31, and second brightness compensation data LCDAT32.

[0137] Figure 15 This is a block diagram illustrating a display system according to an example embodiment.

[0138] Reference Figure 15 The display system 500 may include a host processor 550, a display device 510, and an external memory device 530. The display device 510 may include a display panel 511 and a display driver integrated circuit (IC) 513.

[0139] The host processor 550 can control the operation of the display system 500 as a whole. In some embodiments, the host processor 550 can be implemented as an application processor (AP), a baseband processor (BBP), or a microprocessor unit (MPU).

[0140] The host processor 550 can provide multiple input image data IMGs, a clock signal CLK, and a control signal CTRB required for the operation of the display device 510. In some embodiments, the multiple input image data IMGs are associated with an input image, may include multiple RGB pixel values, and may be data with a resolution of W×H, where W×H has a width W and a height H.

[0141] The control signal CTRB may include a command signal, a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal. In some embodiments, the control signal CTRB may also include the above-mentioned references. Figure 1 The selection signal SEL, the frame rate dimming enable signal FRDO, and the frame rate information FRINFO are described. In some embodiments, multiple input image data IMGs and control signals CTRB can be provided to the display driver IC 513 in the form of packets.

[0142] Command signals may include image processing control signals, image information, and display environment setting information. In some embodiments, the image processing control signals may be signals used to control the internal memory device 515 and the brightness compensator 517 included in the display driver IC 513 to compensate for pixel values ​​of a plurality of input image data IMGs. In some embodiments, the image information is information about a plurality of input image data IMGs input to the display driver IC 513, and may include the resolution of each of the plurality of input image data IMGs. Display environment setting information may include panel information and brightness setting values.

[0143] The display driver IC 513 can drive the display panel 511 based on multiple input image data IMGs and control signals CTRB received from the host processor 550. The display driver IC 513 can convert the multiple input image data IMGs, which are digital signals, into analog signals and use the analog signals to drive the display panel 511.

[0144] The display driver IC 513 may include a brightness compensator 517. The brightness compensator 517 may be... Figure 1 The brightness compensator 110 is included. Therefore, the brightness compensator 517 may include the brightness compensator 110. Figure 1 and Figure 7 The brightness compensation circuit 130 in the above reference may include the brightness compensation circuit 130 in the above reference. Figure 7 The brightness compensation data provider 133 and the image data compensator 131 are described.

[0145] Display panel 511 is a panel for displaying multiple input image data (IMGs), as shown above. Figure 1 The description describes operation at multiple frame rates and may also include at least one region capable of operating at different frame rates. In some embodiments, the display panel 511 may include a liquid crystal display (LCD) panel, an electrophoretic display panel, an organic light-emitting diode (OLED) panel, a light-emitting diode (LED) panel, an electroluminescent display panel, a field emission display (FED) panel, a surface conduction electron emission display (SED) panel, a plasma display panel (PDP), a cathode ray tube (CRT), etc.

[0146] The display system 500 can be implemented as a mobile phone, smartphone, tablet PC, personal digital assistant (PDA), wearable electronic device, or portable multimedia player (PMP) with image display capabilities. The display system 500 can be implemented using various electronic devices such as TVs, laptops, desktop PCs, and navigation devices.

[0147] Figure 16 This is a block diagram illustrating a display system according to an example embodiment.

[0148] Reference Figure 16 The display device 700 includes a display panel 730 containing a plurality of pixel rows 731, a display driver 750 for driving the display panel 730, and an external memory device 790.

[0149] The display driver 750 includes a data driver 751, a scan driver 755, a timing controller 753, a power supply 757, a gamma circuit 759, and a brightness compensator 770.

[0150] Display panel 730 can be connected to data driver 751 of display driver 750 via a data cable, and can be connected to scan driver 755 of display driver 750 via scan lines. Display panel 730 may include pixel rows 731. Display panel 730 may include pixels PX arranged in a matrix of rows and columns. A pixel row 731 refers to a row of pixels PX that can be connected to the same scan line.

[0151] In some embodiments, each pixel PX included in the display panel 230 may have various configurations depending on the driving method. For example, the driving method may be classified as analog driving or digital driving based on the method of expressing grayscale levels. The brightness compensation method according to the example embodiment can be applied to both analog driving and digital driving.

[0152] The data driver 751 can apply data signals to the display panel 730 via data lines, and the scan driver 755 can apply scan signals to the display panel 730 via scan lines. The timing controller 753 can control the operation of the display device 700. The timing controller 753 can control the operation of the display device 700 by providing predetermined control signals to the data driver 751 and the scan driver 755.

[0153] In some embodiments, the data driver 751, scan driver 755, and timing controller 753 can be implemented as a single integrated circuit (IC). In some embodiments, the data driver 751, scan driver 755, and timing controller 753 can be implemented using two or more ICs. A driver module that integrally forms the timing controller 753 and the data driver 751 can be referred to as a timing controller embedded data driver (TED).

[0154] The timing controller 753 receives data from the host device (e.g., Figure 15 The host processor 550 shown receives multiple input image data IMGs and control signals CTRB. For example, the input image data IMGs may include red image data R, green image data G, and blue image data B. The input image data IMGs may include white image data. The input image data IMGs may include magenta image data, yellow image data, and cyan image data.

[0155] The control signal CTRB may include a command signal, a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal. In some embodiments, the control signal CTRB may also include the above-mentioned references. Figure 1 The description includes the selection signal SEL, the frame rate dimming enable signal FRDO, and the frame rate information FRINFO.

[0156] Power supply 757 can supply power supply voltage and ground voltage to display panel 730. In some embodiments, the power supply voltage can correspond to a high power supply voltage, and the ground voltage can correspond to a low power supply voltage. Furthermore, power supply 757 can supply a regulated voltage to gamma circuit 759. In some embodiments, power supply 757 can be implemented using a power management integrated circuit (PMIC). Gamma circuit 759 can generate multiple gamma reference voltages based on the regulated voltage. For example, the regulated voltage can be the power supply voltage or a voltage generated by a separate regulator based on the power supply voltage.

[0157] External memory device 790 can correspond to the above reference. Figure 1 External memory device 170 is described.

[0158] According to an example embodiment, the brightness compensator 770 can generate brightness compensation data for compensating the brightness of the display panel 730. Figure 16 In this embodiment, the brightness compensator 770 is shown disposed between the data driver 751 and the timing controller, but the example embodiment is not limited thereto. In some embodiments, the brightness compensator 770 may be included in the timing controller 753, or may be disposed in front of the timing controller 753.

[0159] Figure 17 This is a flowchart illustrating a method for compensating brightness according to an example embodiment.

[0160] Reference Figure 17 Multiple brightness compensation data for compensating the brightness of at least one region are stored in an external memory device (S1000). In response to frame rate information, multiple brightness compensation data (e.g., a portion of the multiple brightness compensation data) are stored in an internal memory device (S2000). In response to a frame rate dimming enable signal, first brightness compensation data and second brightness compensation data are provided to the brightness compensation circuit (S3000). In response to the frame rate dimming enable signal, the first brightness compensation data, the second brightness compensation data (e.g., and frame rate information), third brightness compensation data is generated (S4000).

[0161] Figure 18 This is a block diagram illustrating a display mobile device according to an example embodiment.

[0162] Reference Figure 18 The display mobile device 900 may include a system-on-a-chip 910 and functional modules 940, 950, 960 and 970. The display mobile device 900 may also include a memory device 920, a storage device 930 and a power management device 980.

[0163] The system-on-chip 910 can control the overall operation of the display mobile device 900 and its constituent components (e.g., memory device 920, storage device 930, and functional modules 940, 950, 960, and 970). In some embodiments, the system-on-chip 910 may be an application processor (AP) disposed in the display mobile device 900.

[0164] The system-on-chip 910 may include a central processing unit 911 and a power management system 913. Memory device 920 and storage device 930 may store data required for the operation of the display mobile device 900. For example, memory device 920 may correspond to a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc., and storage device 930 may correspond to a non-volatile memory device such as an EPROM (erasable programmable read-only memory) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, an NFGM device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, or a ferroelectric random access memory (FRAM) device. In some embodiments, storage device 930 may also include a solid-state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc.

[0165] Functional modules 940, 950, 960, and 970 can respectively perform various functions of the display mobile device 900. For example, the display mobile device 900 may include: (1) a communication module 940 for performing communication functions, such as a Code Division Multiple Access (CDMA) module, a Long Term Evolution (LTE) module, a Radio Frequency (RF) module, an Ultra Wideband (UWB) module, a Wireless Local Area Network (WLAN) module, a Global Microwave Access Interoperability (WIMAX) module, etc.; (2) a camera module 950 for performing camera functions; (3) a display module 960 for performing display functions; and (4) a touch panel module 970 for performing touch input functions, etc. In some embodiments, the display mobile device 900 may also include a Global Positioning System (GPS) module, a microphone module, a speaker module, a gyroscope module, etc. However, those skilled in the art will recognize that many different functional modules can be included in the display mobile device 900.

[0166] The power management device 980 can provide drive voltages to the system-on-chip 910, memory device 920, storage device 930, and functional modules 940, 950, 960, and 970, respectively. In some embodiments, the power management device 980 can be implemented using a power management integrated circuit (PMIC).

[0167] According to an example embodiment, the display module 960 may include a brightness compensation circuit 961. The brightness compensation circuit 961 may correspond to the circuit described above. Figure 1 The brightness compensation circuit 130 is described.

[0168] As described above, the brightness compensator according to the example embodiment can be used to compensate the brightness of a display panel operating at multiple frame rates, including at least one area. An external memory device can store multiple brightness compensation data sets, and an internal memory device can store only a portion of these multiple brightness compensation data sets. The brightness compensator can generate brightness compensation data for compensating the brightness of the display panel using only the portion of the brightness compensation data stored in the internal memory device. Therefore, even when at least one area included in the display panel operates at at least one frame rate, brightness compensation data can be generated efficiently, and memory resource consumption can be reduced while performing region-optimized brightness compensation.

[0169] As is conventional in the art, embodiments can be described and illustrated based on blocks that perform one or more described functions. These blocks (which may be referred to herein as cells or modules, etc.) are physically implemented by analog and / or digital circuits (such as logic gates), integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, etc., and may optionally be driven by firmware and / or software. For example, the circuitry may be implemented in one or more semiconductor chips or on a substrate support such as a printed circuit board. The circuitry constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware performing some functions of the block and a processor performing other functions of the block. Without departing from the scope of disclosure, each block of an embodiment may be physically divided into two or more interactive and discrete blocks. Similarly, without departing from the scope of disclosure, the blocks of an embodiment may be physically combined into more complex blocks. Aspects of an embodiment may be implemented by instructions stored in a non-transitory storage medium and executed by a processor.

[0170] The foregoing is illustrative of exemplary embodiments and is not to be construed as limiting the exemplary embodiments. Although some exemplary embodiments have been described, it will be readily understood by those skilled in the art that many modifications are possible in the exemplary embodiments without substantially departing from the novel teachings and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments as defined in the claims. It will therefore be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limiting oneself to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A brightness compensator, the brightness compensator comprising: A memory device is configured to store a plurality of brightness compensation data and, in response to a frame rate dimming enable signal, provide first brightness compensation data and second brightness compensation data among the plurality of brightness compensation data, the first brightness compensation data corresponding to a first frame rate and the second brightness compensation data corresponding to a second frame rate, the plurality of brightness compensation data being used to compensate the brightness of at least one area included in a display panel and operating at a plurality of frame rates, the frame rate dimming enable signal representing a time interval, the frame rate of the at least one area being gradually changed during the time interval; as well as The brightness compensation circuit is configured to generate third brightness compensation data corresponding to the third frame rate in response to a frame rate dimming enable signal, first brightness compensation data, and second brightness compensation data. The brightness compensation circuit includes a brightness compensation data provider configured to receive a frame rate dimming enable signal, frame rate information, first brightness compensation data, and second brightness compensation data, and to generate third brightness compensation data in response to the frame rate information, the first brightness compensation data, the second brightness compensation data, and the frame rate dimming enable signal, wherein the frame rate information represents the frame rate of the at least one region, and The brightness compensation data provider includes: The demultiplexer is configured to: in response to a frame rate dimming enable signal, provide first brightness compensation data and second brightness compensation data to a first terminal or provide second brightness compensation data to a second terminal; A receive selection buffer is connected to the first terminal and configured to receive first brightness compensation data and second brightness compensation data and store the first brightness compensation data and the second brightness compensation data; A receive buffer, connected to the second terminal, is configured to receive and store the second brightness compensation data; and An interpolation circuit, connected to a receive selection buffer and a receive buffer, is configured to receive first brightness compensation data and second brightness compensation data, and to generate third brightness compensation data in response to frame rate information, the first brightness compensation data, and the second brightness compensation data.

2. The brightness compensator according to claim 1, wherein: The plurality of brightness compensation data are stored in an external memory device, and The memory device is configured to receive the plurality of brightness compensation data from an external memory device and to provide the first brightness compensation data and the second brightness compensation data to the brightness compensation circuit.

3. The brightness compensator according to claim 1, wherein, The brightness compensation circuit is configured as follows: Receive frame rate information, and In response to frame rate information, interpolation is performed on the first brightness compensation data and the second brightness compensation data to generate the third brightness compensation data.

4. The brightness compensator according to claim 3, wherein, The brightness compensation circuit also includes: An image data compensator is configured to receive multiple input image data and third brightness compensation data; and to compensate the multiple input image data in response to the third brightness compensation data to generate multiple output image data for displaying an image.

5. The brightness compensator according to claim 4, wherein: When the frame rate dimming enable signal corresponds to the first level, the brightness compensation data provider is configured to output one of the first brightness compensation data and the second brightness compensation data, and When the frame rate dimming enable signal corresponds to a second level that is different from the first level, the brightness compensation data provider is configured to output third brightness compensation data.

6. The brightness compensator according to claim 5, wherein: When the frame rate dimming enable signal corresponds to the first level, the demultiplexer is configured to provide one of the first brightness compensation data and the second brightness compensation data to the receive selection buffer, and When the frame rate dimming enable signal corresponds to the second level, the demultiplexer is configured to provide the second brightness compensation data to the receive buffer.

7. The brightness compensator according to claim 5, wherein, The receive selection buffer is configured to provide one of the first brightness compensation data and the second brightness compensation data to the image data compensator in response to the frame rate dimming enable signal.

8. The brightness compensator according to claim 5, wherein, The receive selection buffer is configured to provide first brightness compensation data to the interpolation circuit in response to a frame rate dimming enable signal.

9. The brightness compensator according to claim 8, wherein, When the frame rate dimming enable signal corresponds to the second level, the interpolation circuit is configured to interpolate the first brightness compensation data and the second brightness compensation data in response to the frame rate information to generate the third brightness compensation data.

10. The brightness compensator according to claim 1, wherein, The first brightness compensation data, the second brightness compensation data, and the third brightness compensation data are generated for each of the at least one region.

11. The brightness compensator according to claim 1, wherein: The at least one region includes a first region to an Xth region operating at frame rates different from each other, where X is a natural number greater than or equal to 2, and The frame rate dimming enable signal is set independently for each of the first to Xth regions.

12. The brightness compensator according to claim 11, wherein: The frame rate of the first region gradually changes from the first frame rate to the second frame rate, and The frame rate in the second region gradually changes from a fourth frame rate, which is different from the first frame rate, to a fifth frame rate, which is different from the second frame rate.

13. The brightness compensator according to claim 1, wherein: The first frame rate is higher or lower than the second frame rate, and The third frame rate is between the first frame rate and the second frame rate.

14. The brightness compensator according to claim 1, wherein, The memory device is configured to receive the plurality of brightness compensation data from an external memory device within a predetermined time interval before the frame rate dimming enable signal transitions from a first level to a second level.

15. The brightness compensator according to claim 1, wherein, The memory device is configured to receive the plurality of brightness compensation data from an external memory device within a predetermined time interval after the frame rate dimming enable signal changes from a first level to a second level.

16. A display system, the display system comprising: The display panel includes at least one area that operates at multiple frame rates, the at least one area including multiple pixels; An external memory device is configured to store a plurality of brightness compensation data for compensating the brightness of the at least one region; The timing controller is configured to provide a frame rate dimming enable signal and frame rate information, wherein the frame rate dimming enable signal represents a time interval, the frame rate of the at least one region gradually changes during the time interval, and the frame rate information represents the frame rate of the at least one region. as well as A brightness compensator is configured to: store the plurality of brightness compensation data, and generate third brightness compensation data in response to a frame rate dimming enable signal, frame rate information, and first and second brightness compensation data among the plurality of brightness compensation data, wherein the first brightness compensation data corresponds to a first frame rate, the second brightness compensation data corresponds to a second frame rate, and the third brightness compensation data corresponds to a third frame rate. The brightness compensator includes a brightness compensation data provider configured to receive a frame rate dimming enable signal, frame rate information, first brightness compensation data, and second brightness compensation data, and to generate third brightness compensation data in response to the frame rate dimming enable signal, the frame rate information, the first brightness compensation data, and the second brightness compensation data. The brightness compensation data provider includes: The demultiplexer is configured to: in response to a frame rate dimming enable signal, provide first brightness compensation data and second brightness compensation data to a first terminal or provide second brightness compensation data to a second terminal; A receive selection buffer is connected to the first terminal and configured to receive first brightness compensation data and second brightness compensation data and store the first brightness compensation data and the second brightness compensation data; A receive buffer, connected to the second terminal, is configured to receive and store the second brightness compensation data; and An interpolation circuit, connected to a receive selection buffer and a receive buffer, is configured to receive first brightness compensation data and second brightness compensation data, and to generate third brightness compensation data in response to frame rate information, the first brightness compensation data, and the second brightness compensation data.

17. The display system according to claim 16, wherein, The brightness compensator also includes: An image data compensator is configured to receive multiple input image data and third brightness compensation data; and to compensate the multiple input image data in response to the third brightness compensation data to generate multiple output image data for displaying an image.

18. The display system according to claim 17, wherein: When the frame rate dimming enable signal corresponds to the first level, the brightness compensation data provider is configured to output one of the first brightness compensation data and the second brightness compensation data, and When the frame rate dimming enable signal corresponds to a second level that is different from the first level, the brightness compensation data provider is configured to output third brightness compensation data.

19. A brightness compensator, the brightness compensator comprising: A memory device is configured to store a plurality of brightness compensation data and, in response to a frame rate dimming enable signal, provide first brightness compensation data and second brightness compensation data among the plurality of brightness compensation data, the first brightness compensation data corresponding to a first frame rate and the second brightness compensation data corresponding to a second frame rate, the plurality of brightness compensation data being used to compensate the brightness of at least one area included in a display panel and operating at a plurality of frame rates, the frame rate dimming enable signal representing a time interval, the frame rate of the at least one area being gradually changed during the time interval; as well as The brightness compensation circuit is configured to: generate third brightness compensation data corresponding to the third frame rate in response to a frame rate dimming enable signal, first brightness compensation data, and second brightness compensation data, wherein: The memory device includes: A first memory is configured to store the plurality of brightness compensation data; and The second memory is configured to: receive first brightness compensation data and second brightness compensation data from the plurality of brightness compensation data in response to a frame rate dimming enable signal; and provide the first brightness compensation data and second brightness compensation data to the brightness compensation circuit. The brightness compensation circuit includes: A brightness compensation data provider is configured to: receive a frame rate dimming enable signal, frame rate information, first brightness compensation data, and second brightness compensation data; and generate third brightness compensation data in response to the frame rate information, the first brightness compensation data, the second brightness compensation data, and the frame rate dimming enable signal, wherein the frame rate information represents the frame rate of the at least one region; and An image data compensator is configured to: receive multiple input image data and third brightness compensation data; and compensate the multiple input image data in response to the third brightness compensation data to generate multiple output image data for displaying an image. The brightness compensation data provider includes: The demultiplexer is configured to: in response to a frame rate dimming enable signal, provide first brightness compensation data and second brightness compensation data to a first terminal or provide second brightness compensation data to a second terminal; A receive selection buffer is connected to the first terminal and configured to receive first brightness compensation data and second brightness compensation data and store the first brightness compensation data and the second brightness compensation data; A receive buffer, connected to the second terminal, is configured to receive and store the second brightness compensation data; and An interpolation circuit, connected to a receive selection buffer and a receive buffer, is configured to receive first brightness compensation data and second brightness compensation data, and to generate third brightness compensation data in response to frame rate information, the first brightness compensation data, and the second brightness compensation data.

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