Front-end metal structure of semiconductor devices and its manufacturing method

Abstract

This invention discloses a front-end metal structure for a semiconductor device. The semiconductor device includes a top front metal layer, which is patterned to form a front metal electrode. The front-end metal structure is formed by patterning a front-end metal layer formed on the surface of the top front metal layer. The front-end metal layer is composed of a solderable metal material to form a bonding region for encapsulation on the surface of the front-end metal structure. The front-end metal structure is located on a portion of the surface of the front metal electrode, and the patterning of the front-end metal layer precedes the patterning of the top front metal layer. The semiconductor device also includes a front-end passivation layer that opens the bonding region. This invention also discloses a method for manufacturing the front-end metal structure of a semiconductor device. This invention provides a solderable front-end metal structure and reduces defects caused by the front-end metal structure formation process, thereby enabling the formation of a bonding region for encapsulation and making copper-sheet PDFN encapsulation possible.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and in particular to a front-end metal structure of a semiconductor device. BACKGROUND

[0002] With the development of new power devices, new packaging technology has also been rapidly developed. One of the most important ones is the copper sheet power dual flat no lead (PDFN) package, which can provide very low package on-resistance, parasitic resistance, and good thermal conductivity performance. Compared with traditional wire bonding packaging, it has better device reliability and better packaging yield.

[0003] Therefore, how to form a front-end metal structure of a semiconductor device suitable for PDFN packaging is very important, otherwise it cannot be well packaged, and the performance of the packaged device cannot be improved and the packaging yield cannot be improved. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a front-end metal structure of a semiconductor device, which can provide a front-end metal structure with weldability and reduce defects caused by the formation process of the front-end metal structure, so as to form a bonding area for packaging, making copper sheet PDFN packaging possible, developing a new research direction for the new packaging form of future integrated circuits; at the same time, it can also improve the overall reliability and packaging yield of the device. For this purpose, the present application also provides a manufacturing method of a front-end metal structure of a semiconductor device.

[0005] To solve the above technical problems, the front-end metal structure of the semiconductor device provided by the present application corresponds to a semiconductor device including a topmost front metal layer, and the topmost front metal layer is patterned to form a front metal electrode of the semiconductor device.

[0006] The front-end metal structure is formed by patterning a front-end metal layer formed on the surface of the topmost front metal layer, and the front-end metal layer is composed of a weldable metal material to form a bonding area for packaging on the surface of the front-end metal structure.

[0007] The front-end metal structure is located on the surface of a part of the front metal electrode, and the patterning of the front-end metal layer is performed before the patterning of the topmost front metal layer to reduce defects caused by the patterning of the front-end metal layer.

[0008] The semiconductor device further includes a front passivation layer that opens the bonding region to expose the surface of the front metal structure of the bonding region, and the front passivation layer covers the bonding region.

[0009] A further improvement is that the semiconductor device includes a power device, the semiconductor device has a vertical channel, and the front metal electrode includes a source or a gate.

[0010] A further improvement is that the material of the topmost front metal layer includes AlCu or Al.

[0011] A further improvement is that the front-end metal layer is a superposition of Ti, Ni and Ag layers or a superposition of Ni, Pd and Au layers.

[0012] A further improvement is that when the front-end metal layer is a superposition of the Ti layer, the Ni layer and the Ag layer, the thickness of the Ti layer is 100 nm, the thickness of the Ni layer is 200 nm, and the thickness of the Ag layer is 600 nm.

[0013] When the front-end metal layer is a superposition of the Ni layer, the Pd layer and the Au layer, the thickness of the Ni layer is 100 nm, the thickness of the Pd layer is 200 nm, and the thickness of the Au layer is 600 nm.

[0014] A further improvement is that the material of the front-end passivation layer includes epoxy resin, polyimide, or oxynitride.

[0015] A further improvement is that the bonding region is used to bond with the copper sheet during packaging.

[0016] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing the front-end metal structure of a semiconductor device, comprising the following steps:

[0017] Step 1: Form the top front metal layer of the semiconductor device.

[0018] Step 2: Form a front-end metal layer on the surface of the topmost front metal layer.

[0019] Step 3: Pattern the front-end metal layer to form a front-end metal structure.

[0020] The front-end metal layer is composed of a solderable metal material to form a bonding region for encapsulation on the surface of the front-end metal structure.

[0021] Step 4: After patterning the topmost front metal layer, the front metal electrode of the semiconductor device is formed; the front metal structure is located on a portion of the surface of the front metal electrode, and the patterning of the front metal layer is performed before the patterning of the topmost front metal layer to reduce defects caused by the patterning of the front metal layer.

[0022] Step 5: Form a front-end passivation layer and pattern the front-end passivation layer to open the bonding region and thereby expose the surface of the front-end metal structure of the bonding region. The front-end passivation layer covers the bonding region.

[0023] A further improvement is that the semiconductor device includes a power device, the semiconductor device has a vertical channel, and the front metal electrode includes a source or a gate.

[0024] A further improvement is that in step three, a photolithography definition and etching process is used to pattern the front-end metal layer.

[0025] After the etching process of the front-end metal layer is completed, cleaning is also performed to remove defects generated by the etching process of the front-end metal layer.

[0026] A further improvement is that in step four, a photolithography definition and etching process is used to pattern the topmost front metal layer.

[0027] A further improvement is that the material of the topmost front metal layer includes AlCu or Al.

[0028] A further improvement is that the front-end metal layer is a superposition of Ti, Ni and Ag layers or a superposition of Ni, Pd and Au layers.

[0029] A further improvement is that when the front-end metal layer is a superposition of the Ti layer, the Ni layer and the Ag layer, the thickness of the Ti layer is 100 nm, the thickness of the Ni layer is 200 nm, and the thickness of the Ag layer is 600 nm.

[0030] When the front-end metal layer is a superposition of the Ni layer, the Pd layer and the Au layer, the thickness of the Ni layer is 100 nm, the thickness of the Pd layer is 200 nm, and the thickness of the Au layer is 600 nm.

[0031] A further improvement is that the material of the front-end passivation layer includes epoxy resin, polyimide, or oxynitride.

[0032] A further improvement is that the bonding region is used to bond with the copper sheet during packaging.

[0033] The front-end metal structure of the semiconductor device of this invention is composed of a solderable metal material and is disposed on the surface of the top front metal layer. The patterning process for forming the front-end metal structure is performed before the patterning of the top front metal layer. This not only forms a bonding area on the surface of the front-end metal structure but also eliminates the defects caused by the patterning process. Finally, a bonding area for packaging can be formed, making copper sheet PDFN packaging possible. This opens up a new research direction for new packaging forms of future integrated circuits. This invention can also improve the overall reliability of the device and the packaging yield. Attached Figure Description

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0035] Figure 1 This is a schematic diagram of the front-end metal structure of the semiconductor device according to an embodiment of the present invention;

[0036] Figures 2A-2D This is a schematic diagram of the device structure in each step of the manufacturing method of the front-end metal structure of the semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0037] like Figure 1 The diagram shown is a schematic diagram of the front-end metal structure of a semiconductor device according to an embodiment of the present invention. The semiconductor device corresponding to the front-end metal structure of the semiconductor device according to the embodiment of the present invention includes a top-level front metal layer 2, which is patterned to form the front metal electrode of the semiconductor device.

[0038] The front-end metal structure is patterned from a front-end metal layer formed on the surface of the topmost front metal layer 2, the front-end metal layer being composed of a solderable metal material to form a bonding region for encapsulation on the surface of the front-end metal structure.

[0039] The front-end metal structure is located on a portion of the surface of the front metal electrode, and the patterning of the front-end metal layer is located before the patterning of the topmost front metal layer 2, in order to reduce defects caused by the patterning of the front-end metal layer.

[0040] The semiconductor device further includes a front passivation layer 6, which opens the bonding region to expose the surface of the front metal structure of the bonding region, and covers the bonding region.

[0041] In this embodiment of the invention, the semiconductor device is formed on a semiconductor substrate 1. The semiconductor substrate 1 includes a silicon substrate.

[0042] The semiconductor device includes a power device having a vertical channel. A source region is formed on the front surface region of the semiconductor substrate 1, and a gate structure formed by stacking a gate dielectric layer and a gate conductive material layer is formed on the front surface of the semiconductor substrate 1. The front metal electrode includes a source or a gate. The gate dielectric layer includes a gate oxide layer, and the gate conductive material layer includes a polysilicon gate.

[0043] The source electrode and the source region are connected, and the gate electrode and the gate conductive material layer are connected. The power device is a power MOSFET, and a drain region is also formed on the back side of the semiconductor substrate 1. The drain electrode consists of a back metal layer formed on the back side of the drain region.

[0044] The material of the topmost front metal layer 2 includes AlCu or Al.

[0045] In this embodiment of the invention, the front-end metal layer is a superposition of Ti layer 3, Ni layer 4 and Ag layer 5; the thickness of Ti layer 3 is 100 nm, the thickness of Ni layer 4 is 200 nm, and the thickness of Ag layer 5 is 600 nm.

[0046] In other embodiments, the front-end metal layer may be a superposition of a Ni layer, a Pd layer, and an Au layer; the thickness of the Ni layer is 100 nm, the thickness of the Pd layer is 200 nm, and the thickness of the Au layer is 600 nm.

[0047] The material of the front-end passivation layer 6 includes epoxy resin, polyimide, or oxynitride.

[0048] The bonding area is used to bond with the copper sheet during packaging. Figure 1 In the above view, the area exposed by the front passivation layer 6 is the bonding area. The size of the bonding area matches the size of the copper sheet to be bonded and can be bonded by soldering, such as tin soldering.

[0049] In this embodiment of the invention, the front-end metal structure of the semiconductor device is composed of a solderable metal material and is disposed on the surface of the top front metal layer 2. The patterning process for forming the front-end metal structure is performed before the patterning of the top front metal layer 2. This not only forms a bonding area on the surface of the front-end metal structure but also eliminates the defects caused by the patterning process. Finally, a bonding area for packaging can be formed, making copper sheet PDFN packaging possible. This opens up a new research direction for new packaging forms of next-generation integrated circuits. This embodiment of the invention can also improve the overall reliability of the device and the packaging yield.

[0050] like Figures 2A to 2DThe diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the front-end metal structure of the semiconductor device according to an embodiment of the present invention. The manufacturing method of the front-end metal structure of the semiconductor device according to an embodiment of the present invention includes the following steps:

[0051] Step 1, such as Figure 2A As shown, the topmost front metal layer 2 of the semiconductor device is formed.

[0052] In this embodiment of the invention, the semiconductor device is formed on a semiconductor substrate 1. The semiconductor substrate 1 includes a silicon substrate.

[0053] The semiconductor device includes a power device, the semiconductor device has a vertical channel, a source region is formed in the front surface region of the semiconductor substrate 1, and a gate structure formed by stacking a gate dielectric layer and a gate conductive material layer is formed on the front surface of the semiconductor substrate 1.

[0054] The gate dielectric layer includes a gate oxide layer, and the gate conductive material layer includes a polysilicon gate.

[0055] The material of the topmost front metal layer 2 includes AlCu or Al.

[0056] Step 2, as follows Figure 2B As shown, a front metal layer is formed on the surface of the topmost front metal layer 2.

[0057] In the method of this embodiment of the invention, the front-end metal layer is a superposition layer of Ti layer 3, Ni layer 4 and Ag layer 5; the thickness of Ti layer 3 is 100nm, the thickness of Ni layer 4 is 200nm, and the thickness of Ag layer 5 is 600nm.

[0058] In other embodiments, the front-end metal layer may be a superposition of a Ni layer, a Pd layer, and an Au layer; the thickness of the Ni layer is 100 nm, the thickness of the Pd layer is 200 nm, and the thickness of the Au layer is 600 nm.

[0059] Step 3, as follows Figure 2C As shown, the front-end metal layer is patterned to form a front-end metal structure.

[0060] In the method of this invention embodiment, a photolithography definition plus etching process is used to pattern the front-end metal layer.

[0061] After the etching process of the front-end metal layer is completed, cleaning is also performed to remove defects generated by the etching process of the front-end metal layer.

[0062] The front-end metal layer is composed of a solderable metal material to form a bonding region for encapsulation on the surface of the front-end metal structure.

[0063] Step 4, as follows Figure 2D As shown, the topmost front metal layer 2 is patterned to form the front metal electrode of the semiconductor device; the front metal structure is located on a portion of the surface of the front metal electrode, and the patterning of the front metal layer is performed before the patterning of the topmost front metal layer 2 to reduce defects caused by the patterning of the front metal layer.

[0064] The front-side metal electrode includes a source or a gate. The source is connected to the source region, and the gate is connected to the gate conductive material layer.

[0065] In the method of this invention embodiment, a photolithography definition plus etching process is used to pattern the topmost front metal layer 2.

[0066] Step 5, as follows Figure 1 As shown, a front passivation layer 6 is formed and patterned to open the bonding region and thereby expose the surface of the front metal structure of the bonding region, the front passivation layer 6 covering the bonding region.

[0067] In the method of this invention embodiment, the material of the front-end passivation layer 6 includes: epoxy resin, polyimide, or oxynitride.

[0068] The bonding area is used to bond with the copper sheet during packaging.

[0069] Figure 1 In the above view, the area exposed by the front passivation layer 6 is the bonding area. The size of the bonding area matches the size of the copper sheet to be bonded and can be bonded by soldering, such as tin soldering.

[0070] The method of this invention manufactures the front-end metal structure through two photolithography processes: photolithography of the front-end metal layer, specifically the topmost front metal layer 2; and the formation process of the front-end passivation layer 6. This method can form a solderable front-end metal structure, thus enabling copper sheet PDFN packaging and opening up new research directions for new packaging forms of next-generation integrated circuits.

[0071] Furthermore, because the process of the method in this embodiment of the invention differs from existing conventional front-end metal processes, employing a technique of first performing photolithography and etching on the front-end metal layer, and then performing photolithography and etching on the topmost front-side metal layer 2, defects generated during the etching process of the device's front-end metal layer are significantly reduced, thereby improving the device's stability and high reliability. The front-end passivation layer 6 protects the rest of the device during solder placement, thus improving the overall reliability of the device.

[0072] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A front-end metal structure for a semiconductor device, characterized in that: The semiconductor device includes a top front metal layer, which, after being patterned, forms the front metal electrode of the semiconductor device. The front-end metal structure is patterned from a front-end metal layer formed on the surface of the topmost front metal layer, the front-end metal layer being composed of a solderable metal material to form a bonding region for encapsulation on the surface of the front-end metal structure; The front-end metal structure is located on a portion of the surface of the front metal electrode, and the patterning of the front-end metal layer is located before the patterning of the topmost front metal layer, so as to reduce defects caused by the patterning of the front-end metal layer. The semiconductor device further includes a front passivation layer, which opens the bonding region to expose the surface of the front metal structure of the bonding region, and covers the outside of the bonding region. The semiconductor device includes a power device, the semiconductor device has a vertical channel, and the front metal electrode includes a source or a gate.

2. The front-end metal structure of the semiconductor device as described in claim 1, characterized in that: The material of the topmost front metal layer includes AlCu or Al.

3. The front-end metal structure of the semiconductor device as described in claim 1, characterized in that: The front-end metal layer is a superposition of Ti, Ni and Ag layers or a superposition of Ni, Pd and Au layers.

4. The front-end metal structure of the semiconductor device as described in claim 3, characterized in that: When the front-end metal layer is a superposition of the Ti layer, the Ni layer and the Ag layer, the thickness of the Ti layer is 100 nm, the thickness of the Ni layer is 200 nm, and the thickness of the Ag layer is 600 nm. When the front-end metal layer is a superposition of the Ni layer, the Pd layer and the Au layer, the thickness of the Ni layer is 100 nm, the thickness of the Pd layer is 200 nm, and the thickness of the Au layer is 600 nm.

5. The front-end metal structure of the semiconductor device as described in claim 1, characterized in that: The materials of the front-end passivation layer include epoxy resin, polyimide, or oxynitride.

6. The front-end metal structure of the semiconductor device as described in claim 1, characterized in that: The bonding area is used to bond with the copper sheet during packaging.

7. A method for manufacturing a front-end metal structure of a semiconductor device, characterized in that, Includes the following steps: Step 1: Form the top front metal layer of the semiconductor device; Step 2: Form a front-end metal layer on the surface of the topmost front metal layer; Step 3: Pattern the front-end metal layer to form a front-end metal structure; The front-end metal layer is composed of a weldable metal material to form a bonding region for encapsulation on the surface of the front-end metal structure; Step 4: After patterning the topmost front metal layer, the front metal electrode of the semiconductor device is formed; the front metal structure is located on a portion of the surface of the front metal electrode, and the patterning of the front metal layer is performed before the patterning of the topmost front metal layer to reduce defects caused by the patterning of the front metal layer. The semiconductor device includes a power device; The semiconductor device has a vertical channel, and the front metal electrode includes a source or a gate. Step 5: Form a front-end passivation layer and pattern the front-end passivation layer to open the bonding region and thereby expose the surface of the front-end metal structure of the bonding region. The front-end passivation layer covers the bonding region.

8. The method for manufacturing the front-end metal structure of the semiconductor device as described in claim 7, characterized in that: In step three, a photolithography-defined etching process is used to pattern the front-end metal layer; After the etching process of the front-end metal layer is completed, cleaning is also performed to remove defects generated by the etching process of the front-end metal layer.

9. The method for manufacturing the front-end metal structure of the semiconductor device as described in claim 8, characterized in that: In step four, a photolithography-defined etching process is used to pattern the topmost front metal layer.

10. The method for manufacturing the front-end metal structure of the semiconductor device as described in claim 7, characterized in that: The material of the topmost front metal layer includes AlCu or Al.

11. The method for manufacturing the front-end metal structure of the semiconductor device as described in claim 7, characterized in that: The front-end metal layer is a superposition of Ti, Ni and Ag layers or a superposition of Ni, Pd and Au layers.

12. The method for manufacturing the front-end metal structure of the semiconductor device as described in claim 11, characterized in that: When the front-end metal layer is a superposition of the Ti layer, the Ni layer and the Ag layer, the thickness of the Ti layer is 100 nm, the thickness of the Ni layer is 200 nm, and the thickness of the Ag layer is 600 nm. When the front-end metal layer is a superposition of the Ni layer, the Pd layer and the Au layer, the thickness of the Ni layer is 100 nm, the thickness of the Pd layer is 200 nm, and the thickness of the Au layer is 600 nm.

13. The method for manufacturing the front-end metal structure of the semiconductor device as described in claim 7, characterized in that: The materials of the front-end passivation layer include epoxy resin, polyimide, or oxynitride.

14. The method for manufacturing the front-end metal structure of the semiconductor device as described in claim 7, characterized in that: The bonding area is used to bond with the copper sheet during packaging.

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