Light emitting display device and multi-screen light emitting display device comprising the same

Abstract

A light emitting display apparatus includes a display area including a plurality of pixels arranged along a first direction and a second direction intersecting the first direction over a substrate, a light emitting device layer including self-light emitting devices disposed in the display area, a dam disposed in a closed loop shape along a peripheral portion of the substrate, and an encapsulation layer disposed on the light emitting device layer and including an organic encapsulation layer disposed in an encapsulation area surrounded by the dam, the dam can be configured to have a first height in a corner area of the display area and a second height lower than the first height in other areas of the display area except the corner area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0189781, filed on December 31, 2020, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a light-emitting display device and a multi-screen light-emitting display device including the light-emitting display device. Background Art

[0004] Unlike liquid crystal displays (LCDs), emissive display devices, as self-luminous display devices, do not require a separate light source, allowing them to be manufactured light and thin. Furthermore, emissive display devices are driven by low voltage, reducing power consumption. Furthermore, emissive display devices excel in color realization, response time, viewing angle, and contrast, making them a highly anticipated next-generation emissive display device.

[0005] The light-emitting display device displays an image based on the light emission of a light-emitting device layer including a light-emitting device interposed between two electrodes. In this case, the light emitted by the light-emitting device is released to the outside through the electrodes and the substrate.

[0006] A light-emitting display device includes a display panel configured to display an image. The display panel may include a display area including a plurality of pixels for displaying the image, an encapsulation layer including an organic encapsulation layer disposed in the display area, a dam for preventing diffusion of the encapsulation layer, and a frame area surrounding the display area.

[0007] The light-emitting display device in the related art may require a frame (or mechanism) for enclosing a frame area provided at the periphery of the display panel, and the frame width may increase due to the width of the frame. Furthermore, if the frame width of the light-emitting display device is significantly reduced, the reliability of the display panel may be reduced due to degradation of the light-emitting device caused by water (or moisture) penetration, and the reliability of the display panel may be reduced due to the lack of filling of the organic light-emitting layer or the overflow of the organic light-emitting layer.

[0008] Recently, a multi-display device that realizes a large screen by arranging a plurality of light-emitting display devices in a lattice type has been commercialized.

[0009] However, in a related art multi-screen light-emitting display device, a border portion such as a seam is formed between adjacent light-emitting display devices due to a frame area or frame of each of the plurality of light-emitting display devices. When an image is displayed on the entire screen of the multi-screen light-emitting display device, the border portion may cause a sense of discontinuity (or discontinuity) in the image, and for this reason, the immersion of the viewer viewing the image may be reduced. Summary of the Invention

[0010] Accordingly, the present disclosure is directed to providing a light-emitting display device and a multi-screen light-emitting display device including the same that substantially overcome one or more problems due to limitations and disadvantages of the related art.

[0011] One aspect of the present disclosure is to provide a light-emitting display device having a zero border width and preventing a decrease in reliability of a light-emitting display panel caused by penetration of water (or moisture), and a multi-screen display device including the light-emitting display device.

[0012] Another aspect of the present disclosure is to provide a light-emitting display device having zero border width, preventing water (or moisture) penetration from causing a decrease in the reliability of the light-emitting display panel, and preventing the organic encapsulation layer from not being filled or overflowing, as well as a multi-screen display device including the light-emitting display device.

[0013] Other advantages and features of the present disclosure will be partially described in the subsequent description, and some of these advantages and features will become apparent to those skilled in the art after studying the following, or may be learned through practice of the present disclosure. These and other advantages of the present disclosure can be achieved and obtained through the structures specifically pointed out in the specification, claims, and drawings.

[0014] To achieve these and other advantages and in accordance with the intent of the present disclosure, as embodied and generally described herein, a light-emitting display device includes: a display area, the display area including a plurality of pixels arranged on a substrate along a first direction and a second direction intersecting the second direction; a light-emitting device layer, the light-emitting device layer including a self-luminous device disposed in the display area; a dam disposed in a closed loop shape along a peripheral portion of the substrate; and an encapsulation layer disposed on the light-emitting device layer, the encapsulation layer including an organic encapsulation layer disposed in an encapsulation area surrounded by the dam, the dam being configured to have a first height in a corner area of ​​the display area and a second height lower than the first height in other areas of the display area except the corner area.

[0015] In another aspect of the present disclosure, a multi-screen light-emitting display device includes: a plurality of display devices arranged along at least one of a first direction and a second direction intersecting the first direction, each of the plurality of display devices including a light-emitting display device, the light-emitting display device including: a display area, the display area including a plurality of pixels arranged along the first direction and the second direction intersecting the second direction on a substrate; a light-emitting device layer, the light-emitting device layer including a self-luminous device arranged in the display area; a dam arranged in a closed loop shape along an outer portion of the substrate; and an encapsulation layer arranged on the light-emitting device layer, the encapsulation layer including an organic encapsulation layer arranged in an encapsulation area surrounded by the dam, the dam being configured to have a first height in a corner area of ​​the display area, and a second height lower than the first height in other areas of the display area except the corner area.

[0016] According to one embodiment of the present disclosure, a light-emitting display device having a narrow frame width and preventing reliability degradation caused by penetration of water (or moisture) and a multi-screen light-emitting display device including the same can be provided.

[0017] According to one embodiment of the present disclosure, a light-emitting display device having zero border width, preventing the reliability of the light-emitting display panel from being reduced due to the penetration of water (or moisture), and preventing the unfilled organic encapsulation layer or the organic filling layer from overflowing, as well as a multi-screen light-emitting display device including the light-emitting display device can be provided.

[0018] According to one embodiment of the present disclosure, a multi-screen light-emitting display device that displays images without a sense of discontinuity can be provided.

[0019] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application. They illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0021] Figure 1 is a plan view illustrating a light emitting display device according to one embodiment of the present disclosure.

[0022] Figure 2A It shows that according to Figure 1 A diagram of one pixel of one embodiment of the present disclosure is shown.

[0023] Figure 2B It shows that according to Figure 1A diagram of a pixel of another embodiment of the present disclosure is shown.

[0024] Figure 2C It shows that according to Figure 1 A diagram of a pixel of another embodiment of the present disclosure is shown.

[0025] Figure 3 yes Figure 1 An enlarged view of area "A" is shown.

[0026] Figure 4 It shows Figure 1 and 3 The equivalent circuit diagram of a pixel is shown.

[0027] Figure 5 It shows Figure 1 and 3 A diagram of the gate drive circuit is shown.

[0028] Figure 6 is a diagram illustrating a rear surface of a light-emitting display device according to one embodiment of the present disclosure.

[0029] Figure 7 is a diagram illustrating a rear surface of a light emitting display device according to another embodiment of the present disclosure.

[0030] Figure 8 is a plan view illustrating an arrangement structure of each of a dam and a device isolation portion in a light-emitting display apparatus according to an embodiment of the present disclosure.

[0031] Figure 9 It is along Figure 7 and 8 The cross-sectional view is taken along line II'.

[0032] Figure 10 yes Figure 9 An enlarged view of area "B" is shown.

[0033] Figure 11 It is along Figure 7 and 8 The cross-sectional view is taken along line II-II'.

[0034] Figure 12 yes Figure 9 An enlarged view of area "C" is shown.

[0035] Figure 13 yes Figure 11 An enlarged view of area "D" is shown.

[0036] Figure 14 It is along Figure 8The cross-sectional view is taken along line III-III'.

[0037] Figure 15 FIG. 1 is a diagram illustrating a multi-screen display device according to an embodiment of the present disclosure.

[0038] Figure 16 It is along Figure 15 The cross-sectional view is taken along line IV-IV'. DETAILED DESCRIPTION

[0039] Reference will now be made in detail to the exemplary embodiments of the present disclosure illustrated in the accompanying drawings. In the following description, detailed descriptions of known functions or structures associated with this document will be omitted when it is determined that such detailed descriptions would unnecessarily obscure the subject matter of the inventive concept. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to that set forth herein, and except for steps and / or operations that must occur in a particular order, the order of these steps and / or operations may be changed as is known in the art. Like reference numerals refer to like elements throughout. The names of the various elements used in the following description have been selected solely for ease of writing the specification and may therefore differ from the names used in the actual product.

[0040] The advantages and features of the present disclosure and their implementation methods will be illustrated by the following embodiments described in conjunction with the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, by providing these embodiments, the present disclosure can be made comprehensive and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art.

[0041] The shapes, sizes, proportions, angles and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and the embodiments of the present disclosure are not limited to these illustrated details. The same reference numerals always refer to the same components. In the following description, when it is determined that a detailed description of a related known function or configuration would unnecessarily confuse the main points of the present disclosure, the detailed description will be omitted. If "including", "having" and "comprising" described in this specification are used, other parts may be added unless "only..." is used. Unless otherwise indicated, terms in the singular may include plural forms.

[0042] When interpreting an element, although not explicitly described, the element is interpreted as including a range of error.

[0043] When describing a positional relationship, such as when describing a positional order as "on," "above," "below," and "after," one or more other parts may be set between the two parts, unless more restrictive terms (such as "immediately" or "directly") are used.

[0044] When describing a temporal relationship, for example, when describing a time sequence as "after," "subsequently," "next," and "before," discontinuous situations may be included unless "immediately" or "directly" is used.

[0045] It should be understood that although the terms "first," "second," and the like are used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and a second element may likewise be referred to as a first element without departing from the scope of this disclosure.

[0046] When describing the elements of the present disclosure, terms such as first, second, A, B, (a), (b) etc. can be used. These terms are only used to distinguish the corresponding elements from other elements, and the corresponding elements are not limited by these terms in terms of their essence, order or priority. It should be understood that when an element or layer is referred to as being "above" or "coupled" with another element or layer, the element can be directly located on another element or layer, or there can be an intermediate element or layer. Furthermore, it should be understood that when an element is arranged on or below another element, this can represent that these elements are arranged to be in direct contact with each other, or can represent that these elements are arranged when there is no direct contact with each other.

[0047] The term "at least one" should be understood to include any one and all combinations of one or more associated listed elements. For example, the meaning of "at least one of the first element, the second element, and the third element" refers to all combinations of elements listed from two or more elements among the first, second, and third elements, as well as the first element, the second element, or the third element.

[0048] The term "around" as used herein includes at least partially around as well as completely around one or more associated elements. Likewise, the term "cover" as used herein includes at least partially cover as well as completely cover one or more associated elements. For example, if the encapsulation layer surrounds the dam, this can be interpreted that the encapsulation layer at least partially surrounds the dam. However, in some embodiments, the encapsulation layer can completely surround the dam. The meaning of the term "around" as used herein can be further specified based on the associated drawings and embodiments. The terms "around", "at least partially around", or "completely around" and the like are used in the present disclosure. According to the definition of "around" set forth above, when only the term "surround" is used in an embodiment, it can mean at least partially surround or completely surround one or more associated elements. The same applies to the term "cover".

[0049] It will be fully appreciated by those skilled in the art that features of different embodiments of the present disclosure can be partially or fully coupled or combined with each other and can be mutually operated and technically driven in different ways. Embodiments of the present disclosure can be executed in a mutually independent manner or together in a mutually dependent relationship.

[0050] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. When adding reference numerals to elements of each drawing, the same reference numerals can refer to the same elements although the same elements are shown in other drawings. Also, the proportions of each element shown in the drawings are not limited to the proportions shown in the drawings for the convenience of description.

[0051] Figure 1 is a plan view illustrating a light emitting display apparatus according to an embodiment of the present disclosure.

[0052] Referring to Figure 1 A light emitting display apparatus (or display panel) 10 according to an embodiment of the present disclosure can include a substrate 100 including a display area AA, a plurality of pixels P located in the display area AA of the substrate 100, and a dam 104.

[0053] The substrate 100 can be referred to as a first substrate, a base substrate, or a pixel array substrate. For example, the substrate 100 can include a glass material or a plastic material. The substrate 100 can be a glass substrate, a bendable or flexible thin glass substrate, or a plastic substrate.

[0054] The display area AA of the substrate 100 may be an area where an image is displayed and may be referred to as an active portion, an active area, or a display screen. The size of the display area AA may be the same or substantially the same as that of the substrate 100 (or the light-emitting display device or the display panel). For example, the size of the display area AA may be the same as the total size of the first surface of the substrate 100. Therefore, the display area AA may be implemented (or provided) on the entire front surface of the substrate 100, whereby the substrate 100 may not include an opaque non-display portion provided along the peripheral portion (or edge portion) of the first surface to surround all of the display area AA. Accordingly, the display area AA may be implemented on the entire front surface of the light-emitting display device.

[0055] The end (or outermost portion) of the display area AA may overlap or be roughly aligned with the outer surface OS of the substrate 100. For example, relative to the thickness direction Z of the light-emitting display device, the side surface (or end line) of the display area AA may be roughly aligned with a vertical extension line extending vertically from the outer surface OS of the substrate 100. The side surface of the display area AA may not be surrounded by a separate mechanism and may only be adjacent to the surrounding air. For example, all side surfaces of the display area AA may be set to a structure that is in direct contact with the air and is not surrounded by a separate mechanism. Therefore, the outer surface OS of the substrate 100 corresponding to the end of the display area AA may only be surrounded by air (or adjacent to the surrounding air), and therefore, the light-emitting display device according to an embodiment of the present disclosure may have an air frame structure or a non-frame structure (or zero frame) in which the end (or side surface) of the display area AA is surrounded by air instead of an opaque non-display area.

[0056] A plurality of pixels P may be arranged (or disposed) on the display area AA of the substrate 100 so as to have a first interval D1 along a first direction X and a second direction Y. For example, the first direction X may intersect (or cross or intersect) with the second direction Y. The first direction X may be a lateral direction, a horizontal direction, or a first longitudinal direction (e.g., a lateral longitudinal direction) of the substrate 100 or the light-emitting display device. The second direction Y may be a longitudinal direction, a vertical direction, or a second longitudinal direction (e.g., a longitudinal longitudinal direction) of the substrate 100 or the light-emitting display device.

[0057] Each of the plurality of pixels P may be implemented on a plurality of pixel regions defined on the display area AA of the substrate 100. Each of the plurality of pixels P may have a first length L1 parallel to the first direction X and a second length L2 parallel to the second direction Y. The first length L1 may be the same as the second length L2 or the first interval D1. The first length L1 and the second length L2 may be the same as the first interval D1. Therefore, all of the plurality of pixels (or pixel regions) P may have the same size.

[0058] Two pixels P adjacent to each other in the first direction X and the second direction Y can have the same first interval D1 without a manufacturing process error. The first interval D1 can be a pitch (or pixel pitch) between two adjacent pixels P. For example, the first length L1 or the second length L2 of the pixel P can be referred to as a pixel pitch. For example, the first interval (or pixel pitch) D1 can be a distance (or length) between center portions of two adjacent pixels P. For example, the first interval (or pixel pitch) D1 can be a shortest distance (or shortest length) between center portions of two adjacent pixels P.

[0059] Each of the plurality of pixels P according to an embodiment can include a circuit layer including a pixel circuit implemented in a pixel region on the substrate 100, and a light emitting device layer disposed on the circuit layer and connected with the pixel circuit. The pixel circuit outputs a data current corresponding to a data signal in response to the data signal and a scan signal provided from a pixel driving line disposed in the pixel region. The light emitting device layer can include a self-light emitting device that emits light using the data current provided from the pixel circuit. The pixel driving line, the pixel circuit, and the light emitting device layer will be described below.

[0060] The plurality of pixels P can be divided (or classified) into outermost pixels Po and innermost pixels (or inner pixels) Pi.

[0061] The outermost pixels Po can be pixels disposed closest to the outer surface OS of the substrate 100 among the plurality of pixels P.

[0062] A second interval D2 between a center portion of each of the outermost pixels Po and the outer surface OS of the substrate 100 can be half or less of the first interval D1. For example, the second interval D2 can be a distance (or length) between the center portion of the outermost pixel Po and the outer surface OS of the substrate 100. For example, the second interval D2 can be a shortest distance (or shortest length) between the center portion of the outermost pixel Po and the outer surface OS of the first substrate 100.

[0063] When the second interval D2 is greater than half the first interval D1, the substrate 100 may have a size greater than the display area AA by the difference between half the first interval D1 and the second interval D2. As a result, the area between the end of the outermost pixel Po and the outer surface OS of the substrate 100 constitutes a non-display area surrounding the entire display area AA. For example, when the second interval D2 is greater than half the first interval D1, the substrate 100 necessarily includes a border area due to the non-display area surrounding the entire display area AA. On the other hand, when the second interval D2 is half the first interval D1 or less, the end of each outermost pixel Po may be aligned with (or disposed on) the outer surface OS of the substrate 100, or the end of the display area AA may be aligned with (or disposed on) the outer surface OS of the substrate 100, thereby enabling the display area AA to be implemented (or disposed) on the entire front surface of the substrate 100.

[0064] The internal pixel Pi may be a pixel other than the outermost pixel Po among the plurality of pixels P, or may be a pixel surrounded by the outermost pixel Po among the plurality of pixels P. The internal pixel (or second pixel) Pi may be implemented to have a different configuration or structure from the outermost pixel (or first pixel) Po.

[0065] The dam 104 may be implemented in the peripheral portion of the substrate 100, or may be implemented in the peripheral portion of each outermost pixel Po provided in the display area AA. For example, the dam 104 may be provided to have a closed loop line shape (or a closed loop shape) between the center portion of each outermost pixel Po and the outer surface OS of the substrate 100. Therefore, the outermost pixel Po may include the dam 104 and thus may be implemented in a different structure or configuration than the inner pixel Pi that does not include the dam 104.

[0066] According to another embodiment, the dam 104 can prevent the organic encapsulation layer of the encapsulation layer disposed above the light-emitting device layer from spreading or overflowing in the peripheral portion of each outermost pixel Po. For example, the organic encapsulation layer can be disposed above the light-emitting device layer in the encapsulation region surrounded by the dam 104. Accordingly, the dam 104 can block or prevent the organic encapsulation layer from spreading or overflowing toward the periphery of the substrate 100.

[0067] According to an embodiment, the display area AA can include a plurality of long sides parallel to the first direction X, a plurality of short sides parallel to the second direction Y, and a plurality of corner portions between the long sides and the short sides. In this case, the dam 104 can have a first height in a corner area of the display area AA adjacent to the corner portions, and can have a second height lower than the first height in each of the other long sides and short sides of the display area AA except for the corner area. For example, in a process of forming an organic encapsulation layer, spraying or coating of an organic encapsulation material can start and / or end in the corner area of the substrate 100 or the display area AA, whereby the organic encapsulation material overflow can occur in the corner area of the substrate 100 or the display area AA. To address such a problem, the dam 104 having the relatively higher first height can be formed or implemented in the corner area of the display area AA. This will be described below.

[0068] The light emitting display apparatus (or display panel) 10 according to an embodiment of the disclosure can further include a barrier structure 105.

[0069] The barrier structure 105 can be implemented in a peripheral portion of the substrate 100, or can be implemented in a peripheral portion of each outermost pixel Po disposed in the display area AA. For example, the barrier structure 105 can be disposed in the peripheral portion of each outermost pixel Po, thereby having a closed loop linear shape (or a closed loop shape) surrounded by or surrounding the dam 104. Accordingly, the outermost pixel Po can include the barrier structure 105, thereby can be implemented to have a different structure or configuration from the inner pixel Pi not including the barrier structure 105.

[0070] The barrier structure 105 according to an embodiment can isolate (or disconnect) the light emitting device layer in the peripheral portion of each outermost pixel Po, so as to block a lateral water penetration path, thereby preventing or minimizing a reliability reduction of the light emitting device layer caused by lateral penetration of water (or moisture). For example, the barrier structure 105 can be referred to as the following terms: for example, a water penetration blocking portion, a water penetration preventing portion, a device isolating portion, a trench pattern portion, a cliff pattern portion, or an eave structure material, etc. For example, the barrier structure 105 can be defined as an isolation area, an isolation line, a disconnection area, or a disconnection line of the light emitting device layer.

[0071] The barrier structure 105 according to one embodiment may include at least two barrier patterns. For example, the barrier structure 105 may include first to fourth barrier patterns arranged in parallel to form a closed loop line shape. Each of the at least two barrier patterns according to one embodiment may include an eaves structure for isolating (or disconnecting) the light-emitting device layer. For example, each of the at least two barrier structures may include an eaves structure implemented by an insulating layer and a metal pattern layer (or metal layer) above the insulating layer. As an example, the eaves structure may be referred to as a term such as an undercut structure or a cliff structure.

[0072] According to one embodiment, some of the at least two barrier patterns may be surrounded by the dam 104, and other of the at least two barrier patterns may surround the dam 104. As an example, the dam 104 may be disposed between the at least two barrier patterns.

[0073] The light emitting display device (or display panel) 10 according to one embodiment of the present disclosure may further include a first pad portion 110 .

[0074] The first pad portion 110 may be a first pad portion or a front pad portion and may include a plurality of pads to receive data signals, gate control signals, pixel driving power, reference voltage, and pixel common voltage from the driving circuit portion.

[0075] The first pad portion 110 may be included within the outermost pixel Po of the first peripheral portion parallel to the first direction X provided on the first surface of the first substrate 100. That is, the outermost pixel Po provided in the first peripheral portion of the substrate 100 may include at least one of the plurality of pads. Therefore, the plurality of pads may be provided or included inside the display area AA, whereby a non-display area (or border area) based on the first pad portion 110 may not be formed or may not exist on the first substrate 100. Therefore, the outermost pixel (or first pixel) Po may include the first pad portion 110, and thus may be implemented to have a different configuration or structure from the inner pixel (or second pixel) Pi that does not include the first pad portion 110.

[0076] For example, when the first pad portion 110 is not provided inside the outermost pixel Po and is disposed between the outermost pixel Po and the outer surface OS of the first substrate 100, the substrate 100 may include a non-display area (or non-display portion) corresponding to the area where the first pad portion 110 is disposed, and due to the non-display area, the second interval D2 between the outermost pixel Po and the outer surface OS of the substrate 100 may be greater than half of the first interval D1, and the entire substrate 100 will not be implemented as the display area AA, and a separate frame (or separate structure) may be required to cover the non-display area. On the other hand, according to one embodiment of the present disclosure, the first pad portion 110 may be disposed between the outermost pixel Po and the outer surface OS of the substrate 100 so as to be contained within the outermost pixel Po, thereby not forming or existing a non-display area (or frame area) based on the first pad portion 110 between the outermost pixel Po and the outer surface OS of the substrate 100.

[0077] The first pad portion 110 according to one embodiment may include a first pixel driving power pad, a first data pad, a first reference voltage pad, a first gate pad, and a first pixel common voltage pad, but embodiments of the present disclosure are not limited thereto.

[0078] The light emitting display device (or display panel) 10 according to one embodiment of the present disclosure may further include a gate driving circuit 150 .

[0079] The gate driving circuit 150 may be disposed in the display area AA to provide scanning signals (or gate signals) to the pixels P disposed on the substrate 100. The gate driving circuit 150 may simultaneously provide scanning signals to the pixels P disposed in a horizontal row parallel to the first direction X. For example, the gate driving circuit 150 may provide at least one scanning signal to the pixels P disposed in one horizontal row through at least one gate line GL.

[0080] The gate driving circuit 150 according to one embodiment may be implemented as a shift register including a plurality of stage circuit units. That is, the display device according to one embodiment of the present disclosure may include a shift register disposed in the display area AA of the first substrate 100 to provide a scan signal to the pixel P.

[0081] Each of the plurality of stage circuit units may include a plurality of branch circuits that are spaced apart from each other and arranged in each horizontal row along the first direction X of the substrate 100. Each of the plurality of branch circuits may include at least one thin film transistor (TFT) (or branch TFT) and may be disposed between two adjacent pixels among one or more pixels P (or pixel regions) in one horizontal row along the first direction X. Each of the plurality of stage circuit units may generate a scan signal by driving the plurality of branch circuits based on a gate control signal provided through a gate control line that is spaced apart from each other and disposed between the plurality of pixels P in the display area AA, and may provide the scan signal to the pixels P disposed in the corresponding horizontal row.

[0082] Figure 2A It shows that according to Figure 1 A diagram of one pixel of one embodiment of the present disclosure is shown. Figure 2B It shows that according to Figure 1 FIG. 1 is a diagram of a pixel of another embodiment of the present disclosure, Figure 2C It shows that according to Figure 1 A diagram of a pixel of another embodiment of the present disclosure is shown.

[0083] refer to Figure 1 and 2A , one pixel (or unit pixel) P according to one embodiment of the present disclosure may include first to fourth sub-pixels SP1 to SP4.

[0084] The first subpixel SP1 may be disposed in the first subpixel region of the pixel area PA, the second subpixel SP2 may be disposed in the second subpixel region of the pixel area PA, the third subpixel SP3 may be disposed in the third subpixel region of the pixel area PA, and the fourth subpixel SP4 may be disposed in the fourth subpixel region of the pixel area PA.

[0085] According to one embodiment, the first to fourth sub-pixels SP1 to SP4 may be arranged in a 2×2 format or a quad shape. The first to fourth sub-pixels SP1 to SP4 may include a plurality of emission areas EA1 to EA4 and a plurality of circuit areas CA1 to CA4, respectively. As an example, the emission areas EA1 to EA4 may be referred to as opening areas, opening portions, or emission portions.

[0086] The light emitting areas EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a uniform quadrilateral structure or a square shape having the same size (or the same area). According to one embodiment, each of the light emitting areas EA1 to EA4 having a uniform quadrilateral structure may be disposed close to the central portion CP of the pixel P within the corresponding sub-pixel region, thereby having a size smaller than each of the four equally divided regions of the pixel P, or may be disposed so as to be concentrated in the central portion CP of the pixel P. According to another embodiment, each of the light emitting areas EA1 to EA4 having a uniform quadrilateral structure may be disposed in the central portion CP of the corresponding sub-pixel region, thereby having a size smaller than each of the four equally divided regions of the pixel P.

[0087] Reference Figure 1 and 2B According to another embodiment, each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform square structure with different sizes. For example, each of the emission areas EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform square structure with different sizes.

[0088] The size of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quadrilateral structure may be set based on resolution, luminous efficiency, or image quality. According to another embodiment, when the luminous areas EA1 to EA4 have a non-uniform quadrilateral structure, among the luminous areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the luminous area EA4 of the fourth sub-pixel SP4 may have the smallest size, and the luminous area EA3 of the third sub-pixel SP3 may have the largest size. For example, each of the luminous areas EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quadrilateral structure may be arranged to be concentrated around (or near) the center portion of the pixel P.

[0089] Reference Figure 1 and 2C According to another embodiment, each of the first to fourth sub-pixels SP1 to SP4 may have a 1×4 form or a uniform stripe structure. For example, the emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may have a 1×4 form or a uniform stripe structure.

[0090] The light emitting areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 having the uniform stripe structure each have a rectangular shape including short sides parallel to the first direction X and long sides parallel to the second direction Y.

[0091] According to one embodiment, each of the light-emitting areas EA1 to EA4 having a uniform stripe structure can be arranged close to the center portion CP of the pixel P within the corresponding sub-pixel area, thereby having a size smaller than each of the four equally divided areas of the pixel P, or can be arranged to be concentrated in the center portion CP of the pixel P.

[0092] According to another embodiment, each of the light emitting areas EA1 to EA4 having a uniform stripe structure may be disposed at a center portion CP of a corresponding sub-pixel area, thereby having a size smaller than each of four equally divided areas of the pixel P.

[0093] According to another embodiment, each of the light emitting areas EA1 to EA4 having a uniform stripe structure may be disposed throughout the corresponding sub-pixel region, thereby having the same size as each of the four equally divided regions of the pixel P.

[0094] Alternatively, each of the light-emitting areas EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform stripe structure having different sizes. According to one embodiment, when the light-emitting areas EA1 to EA4 have the non-uniform stripe structure, among the light-emitting areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the light-emitting area EA4 of the fourth sub-pixel SP4 may have the smallest size, and the light-emitting area EA3 of the third sub-pixel SP3 may have the largest size, but embodiments of the present disclosure are not limited thereto.

[0095] refer to Figure 2A and 2B , the circuit areas CA1 to CA4 of each of the first to fourth sub-pixels SP1 to SP4 may be arranged around (or near) the corresponding light-emitting areas of the light-emitting areas EA1 to EA4. Each of the circuit areas CA1 to CA4 may include a pixel circuit and a pixel drive line for causing the corresponding sub-pixel of the first to fourth sub-pixels SP1 to SP4 to emit light. As an example, the circuit areas CA1 to CA4 may be referred to as a non-light-emitting area, a non-opening area, a non-light-emitting portion, a non-opening portion, or a peripheral portion.

[0096] Alternatively, to increase the aperture ratio of the subpixels SP1 to SP4 corresponding to the size of the emission areas EA1 to EA4 or to reduce the pixel pitch D1 as the resolution of the pixel P increases, the emission areas EA to EA4 of the first to fourth subpixels SP1 to SP4 may extend into the circuit areas CA1 to CA4 so as to overlap with some or all of the circuit areas CA1 to CA4. For example, since the emission areas EA1 to EA4 of the first to fourth subpixels SP1 to SP4 have a top-emission structure, each of the emission areas EA1 to EA4 may be arranged to overlap with a corresponding circuit area of ​​the circuit areas CA1 to CA4. In this case, each of the emission areas EA1 to EA4 may have a size equal to or larger than that of the corresponding circuit area CA1 to CA4.

[0097] exist Figures 2A to 2C In the embodiment, the first sub-pixel SP1 may be implemented to emit light of a first color, the second sub-pixel SP2 may be implemented to emit light of a second color, the third sub-pixel SP3 may be implemented to emit light of a third color, and the fourth sub-pixel SP4 may be implemented to emit light of a fourth color. As an example, each of the first to fourth colors may be different. As an embodiment, the first color may be red, the second color may be blue, the third color may be white, and the fourth color may be green. As another embodiment, some of the first to fourth colors may be the same. For example, the first color may be red, the second color may be a first green, the third color may be a second green, and the fourth color may be blue.

[0098] Alternatively, the white sub-pixel emitting white light among the first to fourth sub-pixels SP1 to SP4 having the uniform stripe structure or the non-uniform stripe structure may be omitted.

[0099] Figure 3 yes Figure 1 An enlarged view of area "A" is shown, Figure 4 It shows Figure 1 and 3 The equivalent circuit diagram of a pixel is shown.

[0100] refer to Figure 1 、 3 and 4, the substrate 100 according to one embodiment of the present disclosure may include pixel driving power lines DL, GL, PL, CVL, RL and GCL, a plurality of pixels P, a common electrode CE, a plurality of common electrode connection portions CECP, a dam 104, a barrier structure 105, and a first pad portion 110.

[0101] The pixel driving lines DL, GL, PL, CVL, RL, and GCL may include a plurality of data lines DL, a plurality of gate lines GL, a plurality of pixel driving power lines PL, a plurality of pixel common voltage lines CVL, a plurality of reference voltage lines RL, and a gate control line GCL.

[0102] The plurality of data lines DL may be elongated along the second direction Y and may be arranged in the display area AA of the substrate 100 at predetermined intervals along the first direction X. For example, among the plurality of data lines DL, the odd-numbered data lines DLo may be arranged along the second direction Y at a first peripheral portion of each of the plurality of pixel areas PA arranged on the first substrate 100, and the even-numbered data lines DLe may be arranged along the second direction Y at a second peripheral portion of each of the plurality of pixel areas PA arranged on the substrate 100, but embodiments of the present disclosure are not limited thereto.

[0103] The plurality of gate lines GL may be elongated along the first direction X and may be arranged in the display area AA of the substrate 100 at predetermined intervals along the second direction Y. For example, the odd-numbered gate lines Glo among the plurality of gate lines GL may be arranged at a third peripheral portion of each of the plurality of pixel areas PA arranged on the substrate 100 along the first direction X. The even-numbered gate lines GLe among the plurality of gate lines GL may be arranged at a fourth peripheral portion of each of the plurality of pixel areas PA arranged on the substrate 100 along the first direction X, but embodiments of the present disclosure are not limited thereto.

[0104] The plurality of pixel driving power lines PL may extend along the second direction Y and may be arranged in the display area AA of the substrate 100 in a manner spaced apart from each other at predetermined intervals along the first direction X. For example, among the plurality of pixel driving power lines PL, the odd-numbered pixel driving power lines PL may be arranged at a first peripheral portion of the odd-numbered pixel area PA in the first direction X, and the even-numbered pixel driving power lines PL may be arranged at a second peripheral portion of the even-numbered pixel area PA in the first direction X, but embodiments of the present disclosure are not limited thereto.

[0105] Two adjacent pixel drive power lines PL among the plurality of pixel drive power lines PL can be connected to a plurality of power sharing lines PSL arranged in each pixel area PA arranged along the second direction Y. For example, the plurality of pixel drive power lines PL can be electrically coupled to each other through the plurality of power sharing lines PSL, thereby having a ladder structure (ladder structure) or a mesh structure. The plurality of pixel drive power lines PL can have a ladder structure or a mesh structure, thereby preventing or minimizing the voltage drop (or IR drop) of the pixel drive power caused by the line resistance of each of the plurality of pixel drive power lines PL. Accordingly, the light-emitting display device according to an embodiment of the present disclosure can prevent or minimize the degradation of image quality caused by the deviation of the pixel drive power provided to each pixel P arranged on the display area AA.

[0106] Each of the plurality of power sharing lines PSL may branch from an adjacent pixel driving power line PL in parallel with the first direction X and may be disposed in a middle region of each pixel area PA, but embodiments of the present disclosure are not limited thereto.

[0107] The plurality of pixel common voltage lines CVL may be elongated along the second direction Y and may be disposed in the display area AA of the substrate 100 at predetermined intervals along the first direction X. For example, each of the plurality of pixel common voltage lines CVL may be disposed at a first peripheral portion of the even-numbered pixel area PA in the first direction X.

[0108] The plurality of reference voltage lines RL may extend along the second direction Y and may be arranged in the display area AA of the substrate 100 at predetermined intervals along the first direction X. Each of the plurality of reference voltage lines RL may be disposed at a central region of each pixel area PA arranged along the second direction Y.

[0109] Each of the plurality of reference voltage lines RL may be shared by two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) in each pixel area PA in the first direction X. To this end, each of the plurality of reference voltage lines RL may include a reference branch line RDL. The reference branch line RDL may branch (or protrude) to two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) in each pixel area PA in the first direction X, and may be electrically coupled to the two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)).

[0110] Each of the plurality of gate control lines GCL can be elongated along the second direction Y and can be disposed in the display area AA of the substrate 100 at a predetermined interval from each other in the first direction X. For example, each of the plurality of gate control lines GCL can be disposed in a boundary area between a plurality of pixel areas PA in the first direction X or between two adjacent pixel areas PA.

[0111] Each of the plurality of pixels P can include at least three sub-pixels. For example, each of the plurality of pixels P can include first to fourth sub-pixels SP1 to SP4.

[0112] Each of the first to fourth sub-pixels SP1 to SP4 can include a pixel circuit PC and a light emitting device layer.

[0113] The pixel circuit PC according to an embodiment can be disposed in a circuit area of the pixel area PA and can be coupled to a gate line GLo or GLe adjacent thereto, a data line DLo or DLe adjacent thereto, and a pixel driving power line PL. For example, the pixel circuit PC disposed in the first sub-pixel SP1 can be coupled to an odd-numbered data line DLo and an odd-numbered gate line GLo, the pixel circuit PC disposed in the second sub-pixel SP2 can be coupled to an even-numbered data line DLe and an odd-numbered gate line GLo, the pixel circuit PC disposed in the third sub-pixel SP3 can be coupled to an odd-numbered data line DLo and an even-numbered gate line GLe, and the pixel circuit PC disposed in the fourth sub-pixel SP4 can be coupled to an even-numbered data line DLe and an even-numbered gate line GLe.

[0114] The pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can sample a data signal provided from a corresponding data line DLo or DLe in response to a scan signal provided from a corresponding gate line GLo or GLe, and can control a current flowing to the light emitting device layer from the pixel driving power line PL based on the sampled data signal.

[0115] The pixel circuit PC according to an embodiment can include a first switching thin film transistor Tsw1, a second switching thin film transistor Tsw2, a driving thin film transistor Tdr, and a storage capacitor Cst, but embodiments of the present disclosure are not limited thereto. In the following description, a thin film transistor can be referred to as a TFT.

[0116] The first switching TFT Tsw1 may include a gate electrode coupled to the corresponding gate line GL (GLo or GLe); a first source / drain electrode coupled to the corresponding data line DL (DLo or DLe); and a second source / drain electrode coupled to the gate node n1 of the driving TFT Tdr. The first switching TFT Tsw1 may be turned on by a scan signal supplied via the corresponding gate line GL (GLo or GLe) and may transmit a data signal supplied via the corresponding data line DL (DLo or DLe) to the gate node n1 of the driving TFT Tdr.

[0117] The second switching TFT Tsw2 may include a gate electrode coupled to the corresponding gate line GL (GLo or GLe); a first source / drain electrode coupled to the source node n2 of the driving TFT Tdr; and a second source / drain electrode coupled to the corresponding reference voltage line RL. The second switching TFT Tsw2 may be turned on by a scan signal supplied via the corresponding gate line GL (GLo or GLe) and may transmit a reference voltage supplied via the corresponding reference voltage line RL to the source node n2 of the driving TFT Tdr. As an example, the second switching TFT Tsw2 may be turned on simultaneously with the first switching TFT Tsw1.

[0118] A storage capacitor Cst may be formed between the gate node n1 and the source node n2 of the driving TFT Tdr. According to one embodiment, the storage capacitor Cst may include a first capacitor electrode coupled to the gate node n1 of the driving TFT Tdr, a second capacitor electrode coupled to the source node n2 of the driving TFT Tdr, and a dielectric layer formed in an overlapping region between the first capacitor electrode and the second capacitor electrode. The storage capacitor Cst may be charged with a differential voltage between the gate node n1 and the source node n2 of the driving TFT Tdr and may then turn the driving TFT Tdr on or off based on the charged voltage.

[0119] The driving TFT Tdr may include: a gate electrode (or gate node n1) commonly coupled with the second source / drain electrodes of the first switching TFT Tsw1 and the first capacitor electrode of the storage capacitor Cst; a first source / drain electrode (or source node n2) commonly coupled with the first source / drain electrodes of the second switching TFT Tsw2, the second capacitor electrode of the storage capacitor Cst, and the pixel electrode PE of the light-emitting device layer; and a second source / drain electrode (or drain node) coupled with the corresponding pixel driving power line PL. The driving TFT Tdr may be turned on based on the voltage of the storage capacitor Cst and may control the amount of current flowing from the pixel driving power line PL to the light-emitting device layer.

[0120] The light-emitting device layer may be disposed in the light-emitting area EA of the pixel area PA and may be electrically coupled to the pixel circuit PC. The light-emitting device layer according to one embodiment of the present disclosure may include a pixel electrode PE electrically coupled to the pixel circuit PC, a common electrode CE electrically coupled to the pixel common voltage line CVL, and a self-luminous device ED interposed between the pixel electrode PE and the common electrode CE.

[0121] Each of the plurality of common electrode connection portions CECP may be disposed between the plurality of pixels P, overlap the plurality of pixel common voltage lines CVL, and electrically couple the common electrode CE to each of the plurality of pixel common voltage lines CVL. With respect to the second direction Y, each of the plurality of common electrode connection portions CECP according to one embodiment may be electrically coupled to each of the plurality of pixel common voltage lines CVL at a portion between the plurality of pixels P (or at a boundary between the plurality of pixels P), and may be electrically coupled to a portion of the common electrode CE, thereby electrically coupling the common electrode CE to each of the plurality of pixel common voltage lines CVL. For example, the common electrode CE may be coupled to each of the plurality of common electrode connection portions CECP via a side contact structure corresponding to an undercut structure.

[0122] Each of the plurality of common electrode connection portions CECP may be disposed at a portion between the plurality of pixels P to electrically couple the common electrode CE to each of the plurality of pixel common voltage lines CVL, thereby preventing or minimizing a voltage drop (IR drop) in the pixel common voltage caused by the surface resistance of the common electrode CE. Accordingly, the light-emitting display device according to one embodiment of the present disclosure can prevent or minimize image quality degradation caused by a deviation in the pixel driving voltage supplied to each pixel P arranged in the display area AA.

[0123] According to one embodiment of the present disclosure, each of the plurality of common electrode connection parts CECP may be formed together with a pixel electrode PE having at least a two-layer structure so as to be electrically coupled to each of the plurality of pixel common electrode lines CVL. Each of the plurality of common electrode connection parts CECP may be coupled to the common electrode CE through a side contact structure having a “(”-shaped cross-sectional structure or a “<”-shaped cross-sectional structure. For example, when each of the plurality of common electrode connection parts CECP is formed by first and second metal layers, on a side surface of the first metal layer, each of the plurality of common electrode connection parts CECP may include a side contact structure corresponding to an undercut structure or a tapered structure formed due to an etching speed difference between the first metal layer and the second metal layer. For example, when each of the plurality of common electrode connection parts CECP is formed by first to third metal layers, on a side surface of the first metal layer and / or the second metal layer, each of the plurality of common electrode connection parts CECP may include a side contact structure corresponding to an undercut structure or a tapered structure formed due to an etching speed difference between the first and second metal layers.

[0124] Each of the dam 104 and the barrier structure 105 may be provided or implemented at the outermost pixel Po or the peripheral portion of the substrate 100 so as to have a closed loop line shape (or a closed loop shape). Figure 1 This has been described, and thus its repeated description is omitted.

[0125] The first pad portion 110 may be disposed in a first peripheral portion parallel to the first direction X in the first surface of the substrate 100. The first pad portion 110 may be disposed in a third peripheral portion of each outermost pixel area PAo disposed in the first peripheral portion of the substrate 100. An end portion of the first pad portion 110 may overlap or be aligned with an end portion of each outermost pixel area PAo relative to the second direction Y. Therefore, the first pad portion 110 may be included (or disposed) in each outermost pixel area PAo disposed in the first peripheral portion of the substrate 100, whereby a non-display area (or frame area) based on the first pad portion 110 may not be formed or exist in the substrate 100.

[0126] The first pad portion 110 may include a plurality of first pads disposed parallel to one another at a first peripheral portion of the first substrate 100 along the first direction X. The plurality of first pads may be divided (or classified) into a first data pad DP, a first gate pad GP, a first pixel driving power pad PPP, a first reference voltage pad RVP, and a first pixel common voltage pad CVP.

[0127] Each of the first data pads DP may be connected individually (or in a one-to-one relationship) to one side of each of the plurality of data lines DLo and DLe disposed on the substrate 100 .

[0128] Each first gate pad GP may be connected individually (or in a one-to-one relationship) to one side of each gate control line GCL disposed on the first substrate 100. The first gate pads GP according to one embodiment may be divided (or classified) into a first start signal pad, a plurality of first shift clock pads, a plurality of first carry clock pads, at least one first gate driving power pad, and at least one first gate common power pad.

[0129] Each of the first pixel driving voltage pads PPP may be connected individually (or in a one-to-one relationship) to one side of each of the plurality of pixel driving power lines PL provided on the substrate 100. Each of the first reference voltage pads RVP may be connected individually (or in a one-to-one relationship) to one side of each of the plurality of reference voltage lines RL provided on the substrate 100. Each of the first pixel common voltage pads CVP may be connected individually (or in a one-to-one relationship) to one side of each of the plurality of pixel common voltage lines CVL provided on the substrate 100.

[0130] The first pad portion 110 according to one embodiment may include a plurality of pad groups PG arranged in the order of a first pixel driving power pad PPP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, a first gate pad GP, a first pixel common voltage pad CVP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, and a first pixel driving power pad PPP along the first direction X. Each of the plurality of pad groups PG may be connected to two adjacent pixels P disposed along the first direction X. For example, the plurality of pad groups PG may include a first pad group PG1 and a second pad group PG2, the first pad group PG1 including a first pixel driving power pad PPP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, and a first gate pad GP that are continuously arranged in the odd pixel area PA along the first direction X, and the second pad group PG2 including a first pixel common voltage pad CVP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, and a first pixel driving power pad PPP that are continuously arranged in the even pixel area PA along the first direction X.

[0131] The substrate 100 according to one embodiment may further include a plurality of auxiliary voltage lines SVL and a plurality of auxiliary line connection portions SLCP. As an example, the auxiliary voltage lines may be referred to as additional voltage lines or sub-voltage lines, etc.

[0132] Each of the plurality of auxiliary voltage lines SPL may extend along the second direction Y and may be disposed adjacent to a corresponding pixel common voltage line CVL among the plurality of pixel common voltage lines CVL. Each of the plurality of auxiliary voltage lines SPL may be electrically coupled to an adjacent pixel common voltage line CVL without being electrically coupled to the first pixel common voltage pad CVP, and may be provided with a pixel common voltage through the adjacent pixel common voltage line CVL. To this end, the substrate 100 according to one embodiment of the present disclosure may further include a plurality of line connection patterns LCP that electrically couple adjacent pixel common voltage lines CVL and auxiliary voltage lines SVL.

[0133] Each of the plurality of line connection patterns LCP may be disposed on the substrate 100 so that the line connection pattern LCP intersects the pixel common voltage line CVL and the auxiliary voltage line SVL adjacent to each other, and the pixel common voltage line CVL and the auxiliary voltage line SVL adjacent to each other may be electrically coupled by using a line jumping structure. For example, one side of each of the plurality of line connection patterns LCP may be electrically coupled to a portion of the auxiliary voltage line SVL through a first line contact hole formed in an insulating layer above the auxiliary voltage line SVL, and the other side of each of the plurality of line connection patterns LCP may be electrically coupled to a portion of the pixel common voltage line CVL through a second line contact hole formed in an insulating layer above the pixel common voltage line CVL.

[0134] Each of the plurality of auxiliary line connection portions SLCP can overlap with each of the plurality of auxiliary voltage lines SVL, electrically coupling the common electrode CE to each of the plurality of auxiliary voltage lines SVL between the plurality of pixels P. With respect to the second direction Y, each of the plurality of auxiliary line connection portions SLCP according to one embodiment can be electrically coupled to each of the plurality of auxiliary voltage lines SVL at a portion between the plurality of pixels P or at a boundary region between the plurality of pixels P, and can be electrically coupled to a portion of the common electrode CE, thereby electrically coupling the common electrode CE to each of the plurality of auxiliary voltage lines SVL. Therefore, the common electrode CE can be additionally coupled to each of the plurality of auxiliary voltage lines SVL through the auxiliary line connection portion SLCP. Accordingly, the light-emitting display device according to one embodiment of the present disclosure can prevent or minimize image quality degradation caused by a deviation in the pixel common voltage provided to each pixel P arranged in the display area AA. Furthermore, in a light-emitting display device according to an embodiment of the present disclosure, although a pixel common voltage pad CVP coupled to each of the multiple auxiliary voltage lines SVL is not additionally provided (or formed), the pixel common voltage can be provided to each of the multiple auxiliary voltage lines SVL through the pixel common voltage line CVL and each of the multiple line connection patterns LCP.

[0135] The substrate 100 according to one embodiment of the disclosure can further include an encapsulation layer.

[0136] The encapsulation layer can be implemented to surround the light emitting device layer. The encapsulation layer according to one embodiment can include a first inorganic encapsulation layer (or a first encapsulation layer) disposed above the light emitting device layer, the dam 104, and the barrier structure 105; a second inorganic encapsulation layer (or a third encapsulation layer) disposed above the first inorganic encapsulation layer; and an organic encapsulation layer (or a second encapsulation layer) interposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer, the organic encapsulation layer being disposed above the light emitting device layer defined by the dam 104.

[0137] The organic encapsulation layer can cover a top surface (or an upper surface) of the light emitting device layer and flow toward an end portion of the substrate 100, and the diffusion (or flow) of the organic encapsulation layer can be blocked by the dam 104. The dam 104 can define or limit a disposition area (or an encapsulation area) of the organic encapsulation layer, and in addition, can block or prevent diffusion or overflow of the organic encapsulation layer.

[0138] Figure 5 is a view illustrating Figure 1 and 3 a gate driving circuit.

[0139] Referring to Figure 1 , 3 and 5, the gate driving circuit 150 according to another embodiment of the disclosure can be implemented (or embedded) inside the display area AA of the substrate 100. The gate driving circuit 150 can generate scan signals based on gate control signals provided through the first pad portion 110 and the gate control line GCL, and can provide the scan signals to a plurality of gate lines GL in order.

[0140] The gate control line GCL can include a start signal line, a plurality of shift clock lines, at least one gate driving voltage line, and at least one gate common voltage line. The gate control line GCL can be elongated along the second direction Y, and can be disposed in the display area AA of the substrate 100 at a predetermined interval from each other along the first direction X. For example, the gate control line GCL can be disposed between at least one or more pixels P along the first direction X.

[0141] The gate driving circuit 150 according to one embodiment of the disclosure can be implemented with a shift register including a plurality of stage circuit portions 1501 to 150m, where m is an integer of 2 or more.

[0142] Each of the plurality of stage circuit portions 1501 to 150m can be individually disposed in each horizontal row of the first surface of the substrate 100 along the first direction X, and can be adjacently coupled to each other along the second direction Y. Each of the plurality of stage circuit portions 1501 to 150m can generate scan signals in a predetermined order in response to a gate control signal provided through the first pad portion 110 and the gate control line GCL, and can provide the scan signals to the corresponding gate lines GL.

[0143] Each of the plurality of stage circuit portions 1501 to 150m according to an embodiment can include a plurality of branch circuits 1511 to 151n and a branch network 153.

[0144] The plurality of branch circuits 1511 to 151n can be selectively coupled to the gate control line GCL through the branch network 153, and can be electrically coupled to each other through the branch network 153. Each of the plurality of branch circuits 1511 to 151n can generate scan signals based on a gate control signal provided through the gate control line GCL and a voltage of the branch network 153, and can provide the scan signals to the corresponding gate lines GL.

[0145] Each of the plurality of branch circuits 1511 to 151n can include at least one TFT (or branch TFT) of the plurality of TFTs constituting one of the stage circuit portions 1501 to 150m. Any one of the plurality of branch circuits 1511 to 151n can include a pull-up TFT coupled to the gate line GL. Another one of the plurality of branch circuits 1511 to 151n can include a pull-down TFT coupled to the gate line GL.

[0146] Each of the plurality of branch circuits 1511 to 151n according to an embodiment of the disclosure can be disposed in a circuit region between two adjacent pixels P or a circuit region between at least two adjacent pixels P in each horizontal row of the substrate 100, but embodiments of the disclosure are not limited thereto. For example, depending on the number of TFTs constituting each of the stage circuit portions 1501 to 150m and the number of pixels P disposed in one horizontal row, each of the plurality of branch circuits 1511 to 151n can be disposed in a circuit region (or a boundary region) between at least one or more adjacent pixels P.

[0147] The branch network 153 can be disposed in each horizontal row of the substrate 100, and can electrically couple the plurality of branch circuits 1511 to 151n to each other. The branch network 153 according to an embodiment of the disclosure can include a plurality of control node lines and a plurality of network lines.

[0148] A plurality of control node lines can be disposed in each horizontal row of the substrate 100, and can be selectively coupled to the plurality of branch circuits 1511 to 151n in one horizontal row. For example, a plurality of control node lines can be disposed in an upper edge region (or a lower edge region) of a pixel region arranged in each horizontal row of the substrate 100.

[0149] A plurality of network lines can be selectively coupled to the gate control line GCL disposed in the substrate 100, and can be selectively coupled to the plurality of branch circuits 1511 to 151n. For example, the plurality of network lines can transmit a gate control signal provided from the gate control line GCL to the corresponding branch circuits 1511 to 151n, and can transmit a signal between the plurality of branch circuits 1511 to 151n.

[0150] As described above, according to one embodiment of the disclosure, since the gate driving circuit 150 is disposed inside the display area AA of the substrate 100, the second interval D2 between the center portion of the outermost pixel region PAo and the outer surface OS of the substrate can be equal to or less than half of the first interval (or the pixel pitch) D1 between the adjacent pixel regions PA. For example, when the gate driving circuit 150 is not disposed in the display area AA of the first substrate 100 but is disposed in the peripheral portion of the substrate 100, the second interval D2 is not equal to or less than half of the first interval D1. Accordingly, in the light emitting display apparatus according to one embodiment of the disclosure, the gate driving circuit 150 can be disposed in the display area AA of the substrate 100, whereby the second interval D2 can be implemented to be equal to or less than half of the first interval D1, and the display apparatus can be implemented to have a zero bezel or an air bezel structure without a bezel region.

[0151] Figure 6 FIG. 7 is a diagram illustrating a rear surface of a light emitting display apparatus according to one embodiment of the disclosure.

[0152] Referring to Figure 1 , 3 and 6, the light emitting display apparatus according to one embodiment of the disclosure can further include a second pad portion 210 disposed at the rear surface (back surface) 100b of the substrate 100.

[0153] The second pad portion 210 can be disposed at one peripheral portion (or a first rear peripheral portion) of the rear surface 100b of the substrate 100 that overlaps the first pad portion 110 disposed at the front surface 100a of the substrate 100. In the following description with respect to Figure 6 The first pad portion 110 disposed at the front surface 100a of the substrate 100 can be referred to as the first pad portion 110 in the following description.

[0154] The second pad portion 210 may include a plurality of second pads (or wiring pads) arranged at intervals along the first direction X so as to overlap the pads of the first pad portion 110, respectively. Figure 6 In the description of FIG. 1 , the pads of the first pad portion 110 may be referred to as first pads.

[0155] The plurality of second pads may be divided (or classified) into a second pixel driving power pad overlapping with each first pixel driving power pad PPP of the first pad portion 110, a second data pad portion overlapping with each first data pad DP of the first pad portion 110, a second reference voltage pad overlapping with each first reference voltage pad RVP of the first pad portion 110, a second gate pad overlapping with each first gate pad GP of the first pad portion 110, and a second pixel common voltage pad overlapping with each first pixel common voltage pad CVP of the first pad portion 110.

[0156] The light emitting display device according to one embodiment of the present disclosure may further include at least one third pad portion 230 and a connection portion 250 provided on the rear surface 100 b of the substrate 100 .

[0157] At least one third pad portion 230 (or input pad portion) may be provided on the rear surface 100b of the substrate 100. For example, the at least one third pad portion 230 may be provided in a middle portion adjacent to the first peripheral portion of the rear surface 100b of the substrate 100. The at least one third pad portion 230 according to one embodiment of the present disclosure may include a plurality of third pads (or input pads) spaced apart from each other by a certain interval. For example, the at least one third pad portion 230 may include a third pixel driving power pad, a third data pad, a third reference voltage pad, a third gate pad, and a third pixel common voltage pad.

[0158] The connection line portion 250 may include a plurality of connection lines disposed between the second pad portion 210 and the at least one third pad portion 230 .

[0159] According to one embodiment of the present disclosure, the connection portion 250 may include: a plurality of pixel driving power lines that couple the second pixel driving power pad to the third pixel driving power pad individually (or in a one-to-one relationship), a plurality of data lines that couple the second data pad to the third data pad individually (or in a one-to-one relationship), a plurality of reference voltage lines that couple the second reference voltage pad to the third reference voltage pad individually (or in a one-to-one relationship), a plurality of gate lines that couple the second gate pad to the third gate pad individually (or in a one-to-one relationship), and a plurality of pixel common voltage lines that couple the second pixel common voltage pad to the third pixel common voltage pad individually (or in a one-to-one relationship).

[0160] Each of the plurality of pixel common voltage lines may include a first common line 251 and a second common line 253. The first common line 251 may be disposed between the second pad portion 210 and the at least one third pad portion 230 and commonly coupled to the plurality of second pixel common voltage pads. The second common line 253 may be commonly coupled to the plurality of third pixel common voltage pads and electrically coupled to the first common line 251. The second common line 253 may be disposed on a different layer from the first common line 251 and may be electrically coupled to the first common line 251 through a through hole. The size of the second common line 253 may gradually increase in a direction from the third pad portion 230 to the peripheral portion of the substrate 100 so as to reduce (or minimize) the voltage drop of the pixel common voltage.

[0161] The light-emitting display device according to one embodiment of the present disclosure may further include a wiring portion 400 disposed on the outer surface OS of the substrate 100 .

[0162] The wiring portion 400 may be disposed to surround the first pad portion 110 , the outer surface OS, and the second pad portion 210 of the substrate 100 .

[0163] According to one embodiment, the wiring portion 400 may include a plurality of wirings 410. Each of the plurality of wirings 410 may be arranged at a certain interval along the first direction X, may be formed to surround the first pad portion 110, the outer surface OS, and the second pad portion 210 of the substrate 100, and may be electrically coupled to each of the first pad of the first pad portion 110 and the second pad of the second pad portion 210 in a one-to-one relationship. According to one embodiment, each of the plurality of wirings 410 may be formed by a printing process using a conductive paste. According to another embodiment, each of the plurality of wirings 410 may be formed by a transfer process of transferring a conductive paste pattern to a transfer pad made of a flexible material and transferring the conductive paste pattern transferred to the transfer pad to the wiring portion 400. As an example, the conductive paste may be a silver paste, but the embodiments of the present disclosure are not limited thereto.

[0164] The plurality of wirings 410 according to one embodiment of the present disclosure may be divided (classified) into a plurality of pixel power wirings 411 , a plurality of data wirings 413 , a plurality of reference voltage wirings 415 , a plurality of gate wirings 417 , and a plurality of pixel common voltage wirings 419 .

[0165] A plurality of pixel power wirings 411 may be formed to surround the first pad portion 110, the outer surface OS, and the second pad portion 210, and may be electrically coupled to the plurality of first pixel driving power pads of the first pad portion 110 and the plurality of second pixel driving power pads of the second pad portion 210 in a one-to-one relationship.

[0166] A plurality of data wirings 413 may be formed to surround the first pad portion 110, the outer surface OS, and the second pad portion 210, and may be electrically coupled to the plurality of first data pads of the first pad portion 110 and the plurality of second data pads of the second pad portion 210 in a one-to-one relationship.

[0167] A plurality of reference voltage wirings 415 may be formed to surround the first pad portion 110, the outer surface OS, and the second pad portion 210, and may be electrically coupled to the plurality of first reference voltage pads of the first pad portion 110 and the plurality of second reference voltage pads of the second pad portion 210 in a one-to-one relationship.

[0168] A plurality of gate wirings 417 may be formed to surround the first pad portion 110 , the outer surface OS, and the second pad portion 210 , and may be electrically coupled to the plurality of first gate pads of the first pad portion 110 and the plurality of second gate pads of the second pad portion 210 in a one-to-one relationship.

[0169] A plurality of pixel common voltage wirings 419 may be formed to surround the first pad portion 110, the outer surface OS, and the second pad portion 210, and may be electrically coupled to the plurality of first pixel common voltage pads of the first pad portion 110 and the plurality of second pixel common voltage pads of the second pad portion 210 in a one-to-one relationship.

[0170] The display device or the wiring portion 400 according to one embodiment may further include an edge coating layer.

[0171] The edge coating may be implemented to cover the plurality of wiring portions 400. The edge coating according to one embodiment may be implemented to cover all of the first peripheral portion and the first outer surface OS of the substrate 100 and the plurality of wirings 410. The edge coating may prevent corrosion of each of the plurality of wirings 410 comprising a metal material or electrical short circuits between the plurality of wirings 410. Furthermore, the edge coating may prevent or minimize external light reflection caused by the plurality of wirings 410 and the first pads of the first pad portion 110. The edge coating according to one embodiment may include a light-shielding material containing black ink. For example, the edge coating may be an edge protection layer or an edge insulation layer.

[0172] The light emitting display device according to one embodiment of the present disclosure may further include a driving circuit part 500 .

[0173] The driver circuit portion 500 can drive the pixels P disposed on the first substrate 100 (or cause them to emit light) based on the digital video data and timing synchronization signals provided from the display driver system, so as to allow the display area AA to display an image corresponding to the image data. The driver circuit portion 500 can be coupled to at least one third pad portion 230 disposed on the rear surface 100b of the substrate 100, and can output data signals, gate control signals, and driving power for driving the pixels P disposed on the substrate 100 (or causing them to emit light) to the at least one third pad portion 230.

[0174] The driving circuit part 500 according to one embodiment may include a flexible circuit film 510 , a driving integrated circuit (IC) 530 , a printed circuit board (PCB) 550 , a timing controller 570 , and a power supply circuit 590 .

[0175] The flexible circuit film 510 may be coupled to at least one third pad portion 230 disposed on the rear surface 100 b of the substrate 100 .

[0176] The driver IC 530 may be mounted on the flexible circuit film 510. The driver IC 530 may receive sub-pixel data and a data control signal provided from the timing controller 570, and may convert the sub-pixel data into an analog data signal based on the data control signal, so as to provide the analog data signal to the corresponding data line DL. The data signal may be provided to the corresponding third data pad in the at least one third pad portion 230 through the flexible circuit film 510.

[0177] The driving IC 530 can sense the characteristic values ​​of the driving TFTs set in the sub-pixels SP through a plurality of reference voltage lines (or pixel sensing lines) RL set on the substrate 100, generate sensing raw data corresponding to the sensing value for each sub-pixel, and provide the sensing raw data of each sub-pixel to the timing controller 570.

[0178] The PCB 550 may be coupled to the other side peripheral portion of the flexible circuit film 510. The PCB 550 may transmit signals and power between elements of the driving circuit part 500.

[0179] The timing controller 570 may be mounted on the PCB 550 and may receive digital video data and timing synchronization signals provided from the display driving system through a user connector provided on the PCB 550. Alternatively, the timing controller 570 may not be mounted on the PCB 550 but may be implemented in the display driving system, or may be mounted on a separate control board coupled between the PCB 550 and the display driving system.

[0180] The timing controller 570 may arrange the digital video data based on the timing synchronization signal so as to generate pixel data matching the pixel arrangement structure provided in the display area AA, and may provide the generated pixel data to the driving IC 530 .

[0181] The timing controller 570 may generate each of a data control signal and a gate control signal based on the timing synchronization signal, control the driving timing of the driver IC 530 based on the data control signal, and control the driving timing of the gate driving circuit 150 based on the gate control signal. As an example, the timing synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a main clock (or dot clock).

[0182] The data control signal according to an embodiment of the present disclosure may include a source start pulse, a source shift clock, a source output signal, etc. The data control signal may be provided to the driving IC 530 through the flexible circuit film 510 .

[0183] The gate control signal according to one embodiment may include a start signal (or gate start signal), multiple shift clocks, a forward drive signal, and a reverse drive signal. In this case, the multiple shift clocks may include multiple scan clocks whose phases are sequentially shifted and multiple carry clocks whose phases are sequentially shifted. In addition, the gate control signal according to one embodiment may further include an external sensing line selection signal for sensing the characteristic value of the driving TFT set in the sub-pixel SP, an external sensing reset signal, and an external sensing control signal. The gate control signal can be provided to the gate drive circuit 150 through the flexible circuit film 510, at least one third pad portion 230, the connection portion 250, the second pad portion 210, the wiring portion 400, the first pad portion 110, and the gate control line GCL.

[0184] The timing controller 570 may drive each of the gate driver circuit 150 and the driver IC 530 based on an external sensing mode during a predetermined external sensing period, generate compensation data for each sub-pixel based on the raw sensing data provided by the driver IC 530 to compensate for characteristic variations of the driving TFT of each sub-pixel, and modulate the pixel data of each sub-pixel based on the generated compensation data for each sub-pixel. For example, the timing controller 570 may drive each of the gate driver circuit 150 and the driver IC 530 based on the external sensing mode during each external sensing period corresponding to the blanking period of the vertical synchronization signal (or the vertical blanking period). As an example, the external sensing mode may be executed during a power-on process of the display device, a power-off process of the display device, a process of powering off the display device after being driven for a long time, or a blanking period of a frame set in real time or periodically.

[0185] According to one embodiment, the timing controller 570 can store the sensing raw data of each sub-pixel provided from the driver IC 530 in the storage circuit based on the external sensing mode. Moreover, in the display mode, the timing controller 570 can correct the pixel data to be provided to each sub-pixel based on the sensing raw data stored in the storage circuit, and can provide the corrected pixel data to the driver IC 530. Here, the sensing raw data of each sub-pixel may include sequential change information related to each of the driving TFT and the self-luminous device set in the corresponding sub-pixel. Therefore, in the external sensing mode, the timing controller 570 can sense the characteristic value (such as threshold voltage or mobility) of the driving TFT set in each sub-pixel, and can correct the pixel data to be provided to each sub-pixel accordingly, thereby minimizing or preventing the degradation of image quality caused by the change in the characteristic value of the driving TFT of multiple sub-pixels. The external sensing mode of the display device can be a technology known to those skilled in the art, and its detailed description is omitted. As an example, the display device according to one embodiment of the present disclosure may sense a characteristic value of a driving TFT provided in each subpixel based on a sensing mode disclosed in Korean Patent Application Publication Nos. 10-2016-0093179, 10-2017-0054654, or 10-2018-0002099.

[0186] The power supply circuit 590 can be mounted on the PCB 550 and can generate various source voltages required for displaying an image on the pixel P by using an input power source provided from the outside, so as to provide the generated source voltages to the corresponding circuits. For example, the power supply circuit 590 can generate and output the logic source voltages required to drive each of the timing controller 570 and the driver IC 530, multiple reference gamma voltages provided to the driver IC 530, and at least one gate drive power supply and at least one gate common power supply required to drive the gate driver circuit 150. In addition, the power supply circuit 590 can generate and output pixel drive power supplies and pixel common voltages, but embodiments of the present disclosure are not limited thereto. For example, the driver IC 530 can generate and output pixel drive power supplies and pixel common voltages based on multiple reference gamma voltages.

[0187] Figure 7 is a rear perspective view showing a light emitting display device according to another embodiment of the present disclosure, and shows Figure 1 and Figure 6 In the illustrated light-emitting display device, an embodiment of a wiring substrate is additionally provided.

[0188] refer to Figure 7 , a light-emitting display device according to another embodiment of the present disclosure may include a substrate 100 , a second substrate 200 , a coupling member 300 , and a wiring portion 400 .

[0189] The substrate 100 may be referred to as a display substrate, a pixel array substrate, an upper substrate, a front substrate, or a base substrate. The substrate 100 may be a glass substrate, or may be a thin glass substrate or a plastic substrate that is bendable or flexible. Figure 7 In the description, the substrate 100 may be referred to as a first substrate 100 .

[0190] The first substrate 100 may be Figures 1 to 6 The substrate 100 of the illustrated light-emitting display device is substantially the same, and thus, the same reference numerals refer to the same elements, and repeated descriptions thereof may be omitted.

[0191] The second substrate 200 may be referred to as a wiring substrate, a circuit substrate, a wiring substrate, a lower substrate, a rear substrate, or wiring glass. The second substrate 200 may be a glass substrate, or a bendable or flexible thin glass substrate or a plastic substrate. For example, the second substrate 200 may be made of the same material as the first substrate 100. The size of the second substrate 200 may be the same or substantially the same as that of the first substrate 100, but the embodiments of the present disclosure are not limited thereto, and the size of the second substrate 200 may also be smaller than that of the first substrate 100. For example, the second substrate 200 may be configured to have the same size as the first substrate 100 in order to maintain or ensure the rigidity of the first substrate 100.

[0192] The second substrate 200 may include a second pad portion 210, at least one third pad portion 230, and a wiring portion 250. In addition to the second pad portion 210, at least one third pad portion 230 and the wiring portion 250 are provided on the rear surface (or back surface) 200b of the second substrate 200. Each of the second pad portion 210, at least one third pad portion 230, and the wiring portion 250 may be connected to the substrate 200b. Figure 6 The illustrated second pad portion 210 , the at least one third pad portion 230 , and the wiring portion 250 are substantially identical, and thus like reference numerals refer to like elements, and repeated descriptions thereof may be omitted.

[0193] The second substrate 200 may be coupled (or connected) to the second surface (or rear surface) of the first substrate 100 using a coupling member 300. The coupling member 300 may be inserted between the first substrate 100 and the second substrate 200. Thus, the first substrate 100 and the second substrate 200 may be relatively coupled to each other via the coupling member 300.

[0194] The wiring portion 400 may be referred to as a side wiring portion, a side wiring portion, a printed wiring portion, or a printed line portion. The wiring portion 400 according to one embodiment may include a plurality of wirings 410 provided on each of the first outer surface (or one surface) OS1a of the outer surface OS of the first substrate 100 and the first outer surface (or one surface) OS1b of the outer surface OS of the second substrate 200. In addition to providing the plurality of wirings 410 to surround the first pad portion 110 and the first outer surface OS1a of the first substrate 100 and the second pad portion 210 and the first outer surface OS1b of the second substrate 200, the wiring portion 400 is also provided with a plurality of wirings 410. Figure 6 The wiring portion 400 shown is substantially the same. Therefore, the same reference numerals refer to the same elements, and repeated descriptions thereof may be omitted.

[0195] The light emitting display device according to another embodiment of the present disclosure may further include a driving circuit part 500 .

[0196] The driving circuit portion 500 may include a flexible circuit film 510, a driving integrated circuit (IC) 530, a printed circuit board (PCB) 550, a timing controller 570, and a power supply circuit 590. In addition to coupling the flexible circuit film 510 to at least one third pad portion 230 provided on the rear surface 200b of the second substrate 200, the driving circuit portion 500 having such a configuration may be connected to Figure 6 The illustrated driving circuit portion 500 is substantially identical, and thus like reference numerals refer to like elements, and a repeated description thereof may be omitted.

[0197] Figure 8 is a plan view illustrating an arrangement structure of each of a dam and a device isolation portion in a light-emitting display apparatus according to an embodiment of the present disclosure.

[0198] refer to Figure 8 , the light-emitting display device according to one embodiment of the present disclosure may include a plurality of first dam areas DA1 and a plurality of second dam areas DA2 based on an arrangement area of ​​the dam 104 .

[0199] Each of the plurality of first dam areas DA1 may correspond to a corresponding corner area among corner areas adjacent to a corner portion of the display area AA (or the substrate 100). For example, each of the plurality of first dam areas DA1 may have a one-dimensional shape of "┏", "┓", "┗", or "┛" based on the position of each corner portion of the display area AA.

[0200] Each of the plurality of first dam areas DA1 according to one embodiment of the present disclosure may include a 1-1 dam area DA1a parallel to the first direction X and a 1-2 dam area DA1b coupled to the 1-1 dam area DA1a and parallel to the second direction Y. For example, the length of the 1-1 dam area DA1a may be less than or equal to half the length of the first side (or the length of the longer side) of the display area AA parallel to the first direction. The length of the 1-2 dam area DA1b may be less than or equal to half the length of the second side (or the length of the shorter side) of the display area AA parallel to the second direction Y.

[0201] Each of the plurality of second dam areas DA2 may correspond to an area of ​​the display area AA excluding the corner area. For example, each of the plurality of second dam areas DA2 may correspond to an area between adjacent first dam areas DA1 parallel to each of the first direction X and the second direction Y. As an example, each of the plurality of second dam areas DA2 may have a one-dimensional "━" or "┃" shape.

[0202] Each of the plurality of second dam areas DA2 according to one embodiment may be divided into a 2-1st dam area DA2a parallel to the first direction (X) and a 2-2nd dam area DA2b parallel to the second direction (Y).

[0203] The 2-1st dam area DA2a may be disposed between adjacent 1-1st dam areas DA1a parallel to the first direction X. The 2-1st dam area DA2a may be disposed between adjacent 1-1st dam areas DA1a. As an example, in the first side length of the substrate 100 or the display area AA, the length of the 2-1st dam area DA2a may be different from the length of the 1-1st dam area DA1a.

[0204] The 2-2 dam area DA2b may be disposed between adjacent 1-2 dam areas DA1b parallel to the second direction Y. The 2-2 dam area DA2b may be disposed between adjacent 1-2 dam areas DA1b. For example, in the second side length of the display area AA, the length of the 2-2 dam area DA2b may be different from the length of the 1-2 dam area DA1b.

[0205] The dam 104 may have a first height in each corner region of the display area AA, and may have a second height lower than the first height in each of other long side regions and short side regions except the corner regions in the display area AA.

[0206] The dam 104 according to one embodiment may include a first dam 104A provided at each corner region of the display area AA and a second dam 104B provided at each of the other long side regions and short side regions of the display area AA except the corner regions.

[0207] The first dam 104a may be configured to have a first height in each first dam area DA1 of the display area AA. For example, the first dam 104a may have a one-dimensional height based on the position of each corner area of ​​the display area AA. or As an example, the first dam 104A may have a one-dimensional shape at the periphery of each outermost pixel Po in each corner region of the display area AA. or shape.

[0208] The second dam 104B may be configured to have a second height in each second dam area DA2 of the display area AA. For example, based on the positions of the long side area and the short side area of ​​the display area AA, the second dam 104B may have a one-dimensional "s" or "|" shape. As an example, the second dam 104B may have a one-dimensional "s" or "|" shape at the peripheral portion of each outermost pixel Po of each of the first horizontal line (or the first pixel row) and the last horizontal line (or the last pixel row) parallel to the first direction X. Furthermore, the second dam 104B may have a one-dimensional "s" or "|" shape at the peripheral portion of each outermost pixel Po of the first vertical line (or the first pixel column) and the last vertical line (or the last pixel column) parallel to the second direction Y.

[0209] According to one embodiment of the present disclosure, the dam 104 can be formed or implemented to have a relatively high first height in the corner area of ​​the display area AA, thereby preventing the organic encapsulation material from overflowing in the corner area of ​​the display area AA due to the start and / or end of spraying or coating the organic encapsulation material during the process of forming the organic encapsulation layer, thereby preventing the reliability of the light-emitting display device from being reduced due to the overflow of the organic encapsulation material.

[0210] The barrier structure 105 according to one embodiment of the present disclosure may include first to fourth barrier patterns 105 a to 105 d .

[0211] Each of the first to fourth barrier patterns 105a to 105d may have a closed loop line shape (or a closed loop shape) surrounding the display area AA. For example, the first barrier pattern 105a may be disposed in an inner region of the dam 104 and may be surrounded by the dam 104. The second barrier pattern 105b may be disposed in an outer region of the dam 104 and may surround the dam 104. The third barrier pattern 105c may be disposed to surround the second barrier pattern 105b, and the fourth barrier pattern 105d may be disposed to surround the third barrier pattern 105c.

[0212] Figure 9 It is along Figure 7 and 8 The cross-sectional view taken along line II' is shown. Figure 10 yes Figure 9 An enlarged view of area "B" is shown, Figure 11 It is along Figure 7 and 8 The cross-sectional view is taken along line II-II'.

[0213] refer to Figures 7 to 11 , a light emitting display device according to one embodiment of the present disclosure may include a first substrate 100 , a second substrate 200 , a coupling member 300 , and a wiring portion 400 .

[0214] The first substrate 100 according to an embodiment of the present disclosure may include a circuit layer 101 , a planarization layer 102 , a light emitting device layer EDL, a bank 103 , a dam 104 , a barrier structure 105 , and an encapsulation layer 106 .

[0215] The circuit layer 101 may be disposed on the first substrate 100. The circuit layer 101 may be referred to as a pixel array layer or a TFT array layer.

[0216] The circuit layer 101 according to one embodiment of the present disclosure may include a buffer layer 101 a and a circuit array layer 101 b .

[0217] The buffer layer 101a can prevent a material (e.g., hydrogen) included in the first substrate 100 from diffusing to the circuit array layer 101b in a high-temperature process of a process of manufacturing a TFT. Also, the buffer layer 101a can prevent external moisture or humidity from penetrating to the light emitting device layer EDL. The buffer layer 101a according to an embodiment can include a single layer structure including one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure of the same, but embodiments of the disclosure are not limited thereto. For example, the buffer layer 101a can include a first buffer layer disposed on the first substrate 100 and including SiNx, and a second buffer layer disposed on the first buffer layer and including SiOx.

[0218] The circuit array layer 101b can include a pixel circuit PC including a driving TFT Tdr of each of a plurality of pixel areas PA disposed on the buffer layer 101a.

[0219] The driving TFT Tdr disposed in the circuit region of each of the pixel areas PA can include an active layer ACT, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer ILD, a first source / drain electrode SD1, a second source / drain electrode SD2, and a passivation layer PAS.

[0220] The active layer ACT can be disposed on the buffer layer 101a in each of the pixel areas PA. The active layer ACT can include a channel region overlapping the gate electrode GE, and first and second source / drain regions parallel to each other between adjacent channel regions. The active layer ACT can have conductivity in a conductive process, thereby directly coupling between lines in the display area AA, or can be used as a bridge line of a jumper structure electrically coupling lines disposed on different layers.

[0221] The gate insulating layer GI can be disposed on the channel region of the active layer ACT. The gate insulating layer GI can insulate the active layer ACT from the gate electrode GE.

[0222] The gate electrode GE can be disposed on the gate insulating layer GI and coupled to a gate line. The gate electrode GE can overlap the channel region of the active layer ACT with the gate insulating layer GI therebetween.

[0223] The interlayer insulating layer ILD can be disposed on the first substrate 100 so as to cover the gate electrode GE and the active layer ACT. The interlayer insulating layer ILD can electrically insulate (or isolate) the gate electrode GE from the source / drain electrodes SD1 and SD2. As an example, the interlayer insulating layer ILD can be referred to as an insulating layer or a first insulating layer.

[0224] The first source / drain electrode SD1 may be disposed on the interlayer insulating layer ILD overlapping the first source / drain region of the active layer ACT, and may be electrically coupled to the first source / drain region of the active layer ACT through a first source / drain contact hole disposed in the interlayer insulating layer ILD. As an example, the first source / drain electrode SD1 may be a source electrode of the driving TFT Tdr, and the first source / drain region of the active layer ACT may be a source region.

[0225] The second source / drain electrode SD2 may be disposed on the interlayer insulating layer ILD overlapping the second source / drain region of the active layer ACT, and may be electrically coupled to the second source / drain region of the active layer ACT via a second source / drain contact hole disposed in the interlayer insulating layer ILD. As an example, the second source / drain electrode SD2 may be a drain electrode of the driving TFT Tdr, and the second source / drain region of the active layer ACT may be a drain region.

[0226] The passivation layer PAS may be provided on the first substrate 100 so as to cover the pixel circuit PC including the driving TFT Tdr. The passivation layer PAS according to one embodiment may be formed of an inorganic material. For example, the passivation layer PAS may include a single layer structure including one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof. As an example, the passivation layer PAS may be referred to as a protective layer, a circuit protection layer, a circuit insulating layer, an inorganic insulating layer, a first inorganic insulating layer, a second insulating layer, or the like.

[0227] Each of the first and second switching TFTs Tsw1 and Tsw2 constituting the pixel circuit PC may be formed together with the driving TFT Tdr, and thus a detailed description thereof may be omitted.

[0228] The circuit layer 101 according to one embodiment may further include a lower metal layer BML disposed between the first substrate 100 and the buffer layer 101 a .

[0229] The lower metal layer BML may further include a light shielding pattern (or light shielding layer) LSP disposed below (or under) the active layer ACT of each of the TFTs Tdr, Tsw1, and Tsw2 constituting the pixel circuit PC.

[0230] A light-shielding pattern LSP may be provided in an island shape between the first substrate 100 and the active layer ACT. The light-shielding pattern LSP may block light incident on the active layer ACT through the first substrate 100, thereby preventing or minimizing changes in the threshold voltage of each TFT caused by external light. Alternatively, the light-shielding pattern LSP may be electrically coupled to the first source / drain electrode SD1 of the corresponding TFT, thereby functioning as a lower gate electrode of the corresponding TFT. In this case, changes in the characteristics of each TFT caused by light, as well as changes in the threshold voltage of each TFT caused by bias voltage, may be minimized or prevented.

[0231] The lower metal layer BML may be used as lines arranged parallel to one another among the gate lines GL, the data lines DL, the pixel driving power lines PL, the pixel common voltage lines CVL, and the reference voltage lines RL. For example, the lower metal layer BML may be used as a metal layer (or line) arranged parallel to the second direction Y among the pixel driving lines DL, GL, PL, CVL, RL, and GCL arranged on the first substrate 100.

[0232] The planarization layer 102 may be disposed on the first substrate 100 and may provide a flat surface on the circuit layer 101. The planarization layer 102 may cover the circuit layer 101 including the driving TFT Tdr of each pixel area disposed in the plurality of pixel areas PA. The planarization layer 102 according to one embodiment of the present disclosure may be formed of an organic insulating material, but is not limited thereto. The planarization layer 102 according to one embodiment of the present disclosure may be formed to cover the remaining circuit layer 101 except for the peripheral portion of the passivation layer PAS disposed on the first substrate 100. For example, the planarization layer 102 may be disposed between the first substrate 100 and the light-emitting device layer EDL, or below (or under) the light-emitting device layer EDL. The planarization layer 102 according to one embodiment may be formed of an organic insulating material including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide-based resin, a polyimide-based resin, or the like, but the embodiments of the present disclosure are not limited thereto.

[0233] The light emitting device layer EDL may be disposed on the planarization layer 102. The light emitting device layer EDL according to one embodiment may include a pixel electrode PE, a self-light emitting device ED, and a common electrode CE.

[0234] The pixel electrode PE may be referred to as an anode electrode, a reflective electrode, a lower electrode, an anode or a first electrode of the self-luminous device ED.

[0235] The pixel electrode PE may be disposed over the planarization layer 102, overlapping the emission area EA of each of the plurality of sub-pixels SP in the first substrate 100. The pixel electrode PE may be patterned into an island shape and disposed in each sub-pixel SP, and may be electrically coupled to the first source / drain electrodes SD1 of the driving TFT Tdr of the corresponding pixel circuit PC. For example, one side of the pixel electrode PE may extend onto the first source / drain electrodes SD1 of the driving TFT Tdr and may be electrically coupled to the first source / drain electrodes SD1 of the driving TFT Tdr through an electrode contact hole ECH provided in the planarization layer 102.

[0236] The pixel electrode PE may include a metal material having a low work function and excellent reflection efficiency.

[0237] The pixel electrode PE according to one embodiment of the present disclosure may have a double-layer structure including a first pixel electrode layer (or a first metal layer) PEL1 and a second pixel electrode layer (or a second metal layer) PEL2. The first pixel electrode layer PEL1 and the second pixel electrode layer PEL2 may be sequentially deposited on the planarization layer 102 and then patterned simultaneously, but the embodiments of the present disclosure are not limited thereto.

[0238] The first pixel electrode layer PEL1 may be disposed on the planarization layer 102. The second pixel electrode layer PEL2 may be disposed (or stacked) on the first pixel electrode layer PEL1. As an example, the first pixel electrode layer PEL1 may act as an adhesive layer corresponding to the planarization layer 102, and may act as an auxiliary electrode of the self-luminous device ED, and may include indium tin oxide (ITO) or indium zinc oxide (IZO), but the embodiments of the present disclosure are not limited thereto. For example, the second pixel electrode layer PEL2 may act as a reflector, and may perform the function of reducing the resistance of the pixel electrode PE, and may include one of aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti) and Mo-Ti alloy (MoTi), but the embodiments of the present disclosure are not limited thereto. For example, the pixel electrode PE may be formed as a double-layer structure of ITO / MoTi or IZO / MoTi.

[0239] According to another embodiment, the pixel electrode PE may have a three-layer structure including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 on the first pixel electrode layer PEL1, and a third pixel electrode layer (or third metal layer) PEL3 on the second pixel electrode layer PEL2. The first pixel electrode layer PEL1, the second pixel electrode layer PEL2, and the third pixel electrode layer PEL3 may be sequentially deposited on the planarization layer 102 and then patterned simultaneously, but the embodiments of the present disclosure are not limited thereto.

[0240] The third pixel electrode layer PEL3 can act as an electrode of the self-emissive device ED, and can include ITO or IZO. For example, the pixel electrode PE according to another embodiment can be formed in a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO.

[0241] The pixel electrode PE according to another embodiment can have a four-layer structure including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 on the first pixel electrode layer PEL1, a third pixel electrode layer (or a third metal layer) PEL3 on the second pixel electrode layer PEL2, and a fourth pixel electrode layer (or a fourth metal layer) on the third pixel electrode layer PEL3. The first to fourth pixel electrode layers can be sequentially deposited on the planarization layer 102 and then patterned at the same time, but embodiments of the present disclosure are not limited thereto.

[0242] In the pixel electrode PE of the four-layer structure, the first pixel electrode layer can act as an adhesion layer corresponding to the planarization layer 102, and can act as an auxiliary electrode of the self-emissive device ED, and can include one or more materials of ITO, Mo, and Mo-Ti. The second pixel electrode layer can function to reduce the resistance of the pixel electrode PE and can include Cu. The third pixel electrode layer can act as a reflector, and can include one or more materials of Al, Ag, Mo, Ti, and MoTi. The fourth pixel electrode layer can act as an electrode of the self-emissive device ED, and can include ITO or IZO. For example, the pixel electrode PE according to another embodiment can be formed in a four-layer structure of ITO / Cu / MoTi / ITO.

[0243] The pixel electrode PE according to another embodiment can have a five-layer structure of a first pixel electrode layer made of ITO, a second pixel electrode layer made of MoTi, a third pixel electrode layer made of ITO, a fourth pixel electrode layer made of Ag, and a fifth pixel electrode layer made of ITO.

[0244] The self-emissive device ED can be disposed on the first substrate 100. The self-emissive device ED can be formed on the pixel electrode PE, and can directly contact the pixel electrode PE. The pixel electrode PE can be disposed under (or below) the self-emissive device ED. For example, the pixel electrode PE can be disposed between the planarization layer 102 and the self-emissive device ED.

[0245] The self-luminous device ED according to one embodiment may be a common layer formed in each of a plurality of sub-pixels SP, and thus is not distinguished per sub-pixel SP. The self-luminous device ED may react to a current flowing between the pixel electrode PE and the common electrode CE to emit white light (or blue light). The self-luminous device ED according to another embodiment may include an organic light-emitting device, or may include a stacked or combined structure of an organic light-emitting device and a quantum dot light-emitting device. For example, the self-luminous device ED according to another embodiment may include an organic light-emitting layer, or may include a stacked or combined structure of an organic light-emitting layer and a quantum dot light-emitting layer.

[0246] An organic light-emitting device may include two or more organic light-emitting portions for emitting white light (or blue light). For example, the organic light-emitting device may include a first organic light-emitting portion and a second organic light-emitting portion that emit white light based on a combination of a first light and a second light. As an example, the first organic light-emitting portion may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer. The second organic light-emitting portion may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer that emits a second light that combines with the first light from the first organic light-emitting portion to produce white light.

[0247] The organic light emitting device according to one embodiment may further include at least one or more functional layers for improving luminous efficiency and / or lifespan. For example, the functional layer may be disposed above and / or below the light emitting layer.

[0248] The common electrode CE may be disposed on the display area AA of the first substrate 100 and may be electrically coupled to the self-luminous device ED of each of the plurality of pixels P. For example, the common electrode CE may be disposed on the remaining display area AA of the first substrate 100 except for the peripheral portion of the first substrate 100. As an example, the common electrode CE may be disposed on the remaining display area AA of the first substrate 100 except for the first pad portion 110 of the first substrate 100.

[0249] The common electrode CE may be referred to as a cathode electrode, a transparent electrode, an upper electrode, a cathode, or a second electrode of the self-luminous device ED. The common electrode CE may be formed on the self-luminous device ED and may directly contact the self-luminous device ED or may electrically directly contact the self-luminous device ED. The common electrode CE may include a transparent conductive material that transmits light emitted from the self-luminous device ED.

[0250] The common electrode CE according to one embodiment of the present disclosure may be formed in a single-layer structure or a multi-layer structure, including at least one of graphene with a relatively high work function and a transparent conductive material. For example, the common electrode CE may include a metal oxide such as ITO or IZO, or a combination of an oxide and a metal such as ZnO:Al or SnO2:Sb.

[0251] In addition, the light emitting device layer EDL may further include a capping layer disposed on the common electrode CE. The capping layer may be disposed on the common electrode CE and may improve light emission efficiency by adjusting a refractive index of light emitted from the light emitting device layer EDL.

[0252] The bank 103 may be provided on the planarization layer 102 to define a pixel area PA on the first substrate 100. The bank 103 may be provided on the planarization layer 102 to cover the peripheral portion of the pixel electrode PE. The bank 103 may define the emission area EA (or opening portion) of each of the plurality of sub-pixels SP and may electrically isolate the pixel electrodes PE provided in adjacent sub-pixels SP. The bank 103 may be formed to cover the electrode contact hole ECH of each pixel area provided in the plurality of pixel areas PA. The bank 103 may be covered by the self-luminous device ED of the light-emitting device layer EDL. For example, the self-luminous device ED may be provided on the bank 103 and on the pixel electrode PE of each of the plurality of sub-pixels SP.

[0253] The bank 103 according to one embodiment may be a transparent bank including a transparent material or a black bank (or an opaque bank) including a black pigment.

[0254] The dam 104 may be provided at the outer portion of the first substrate 100 or at the outer portion of the outermost pixel Po. For example, the dam 104 may be provided as an element of each outermost pixel Po provided at the outer portion of the first substrate 100, whereby the outermost pixel Po may have a structure different from that of the inner pixels.

[0255] The dam 104 may be disposed above the circuit layer 101 located at the outer portion of the first substrate 100 or the outermost pixel Po so as to have a closed loop shape (or a closed loop shape). For example, the dam 104 may be disposed above the passivation layer PAS of the circuit layer 101 so as to have a closed loop shape surrounding the display area AA and may be supported by the passivation layer PAS. As an example, the dam 104 may be implemented to be surrounded by the barrier structure 105. The dam 104 may prevent the encapsulation layer 106 disposed above the first substrate 100 from spreading or overflowing.

[0256] The dam 104 may have a first height in each corner region of the display area AA, and may have a second height lower than the first height in each of other long side regions and short side regions except the corner regions in the display area AA.

[0257] According to one embodiment, the dam 104 may include a first dam 104A disposed at each corner region of the display area AA, and a second dam 104B disposed at each of the other long and short side regions of the display area AA, excluding the corner regions. For example, the first dam 104A may be disposed to have a first height in the first dam region DA1 of the display area AA. The second dam 104B may be disposed to have a second height in the second dam region DA2 of the display area AA. The dam 104 including the first dam region DA1 and the second dam region DA2 will be described below.

[0258] The barrier structure 105 may be provided or implemented in a barrier region provided in the peripheral portion of the first substrate 100 or the peripheral portion of each outermost pixel Po. For example, the barrier structure 105 may be provided as an element of each outermost pixel Po provided in the peripheral portion of the first substrate 100, whereby the outermost pixel Po may have a structure different from that of each inner pixel.

[0259] The barrier structure 105 may be provided at the outer portion of the first substrate 100 so as to have a one-dimensional closed loop line shape (or closed loop shape), or may be provided at the outer portion of each outermost pixel Po. The barrier structure 105 may be implemented to isolate the self-luminous devices ED provided at the outer portion of each outermost pixel Po. By implementing the barrier structure 105, water (or moisture) may be prevented from penetrating in the lateral direction of the first substrate 100, thereby preventing degradation of the self-luminous devices ED caused by the lateral penetration of water (or moisture). The barrier structure 105 may isolate (or disconnect) the self-luminous devices ED of the light-emitting device layer EDL near the dam 104 at least once, thereby preventing the lateral penetration of water (or moisture).

[0260] The barrier structure 105 may be implemented on the interlayer insulating layer ILD over the first substrate 100 so as to surround the display area AA. For example, the barrier structure 105 may be implemented in a closed loop shape over the interlayer insulating layer ILD so as to one-dimensionally surround the display area AA. According to one embodiment, the barrier structure 105 may include first to fourth barrier patterns 105a, 105b, 105c, and 105d disposed in parallel with each other over the interlayer insulating layer ILD.

[0261] The first barrier pattern 105a may be disposed in an inner region of the dam 104 and may be surrounded by the dam 104. The second barrier pattern 105b may be disposed in an outer region of the dam 104 and may surround the dam 104. The third barrier pattern 105c may be disposed to surround the second barrier pattern 105b, and the fourth barrier pattern 105d may be disposed to surround the third barrier pattern 105c. The barrier structure 105 including the first to fourth barrier patterns 105a, 105b, 105c, and 105d will be described below.

[0262] The encapsulation layer 106 may be provided on the remaining portion of the first substrate 100 except for the outermost portion of the first substrate 100 and may be implemented to cover the light-emitting device layer EDL. The encapsulation layer 106 may be implemented on the first substrate 100 so as to surround all front and side surfaces of the light-emitting device layer EDL. For example, the encapsulation layer 106 may be implemented to surround all front and side surfaces of the light-emitting device layer EDL, thereby preventing oxygen or water (or moisture) from penetrating into the light-emitting device layer EDL, thereby improving the reliability of the light-emitting device layer EDL.

[0263] The encapsulation layer 106 according to one embodiment of the present disclosure may include first to third encapsulation layers 106 a , 106 b , and 106 c .

[0264] The first encapsulation layer 106a may be implemented to prevent oxygen or water (or moisture) from penetrating into the light-emitting device layer EDL. The first encapsulation layer 106a may be disposed above the common electrode CE and may surround the light-emitting device layer EDL. Thus, all front and side surfaces of the light-emitting device layer EDL may be surrounded by the first encapsulation layer 106a. According to one embodiment, the first encapsulation layer 106a may include an inorganic insulating material.

[0265] When the self-luminous device ED and the common electrode CE are isolated by the barrier structure 105, the first encapsulation layer 106a may surround the isolated surfaces (or disconnected surfaces) of the self-luminous device ED and the common electrode CE isolated by the barrier structure 105. For example, the first encapsulation layer 106a may be filled (or buried) into the isolation space between the self-luminous device ED and the common electrode CE formed by the barrier structure 105 to seal or completely surround the barrier structure 105, thereby completely surrounding or covering each of the isolated self-luminous device ED and the common electrode CE, thereby fundamentally (or completely) preventing lateral penetration of water (or moisture).

[0266] According to one embodiment, the first encapsulation layer 106a may be a first inorganic encapsulation layer including an inorganic insulating material. For example, the first encapsulation layer 106a may include a single-layer structure including one of the following: silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx) or a stacked structure.

[0267] Second encapsulation layer 106b may be implemented on first encapsulation layer 106a, thereby having a thickness greater than that of first encapsulation layer 106a. Second encapsulation layer 106b may have a thickness sufficient to completely cover particles (or undesirable materials or undesirable structural components) located or potentially located on first encapsulation layer 106a. Due to its relatively thick thickness, second encapsulation layer 106b may diffuse into the outer periphery of first substrate 100. However, such diffusion of second encapsulation layer 106b may be blocked by dam 104.

[0268] According to one embodiment of the present disclosure, the second encapsulation layer 106b may include an organic insulating material or a liquid organic insulating material. For example, the second encapsulation layer 106b may include an organic insulating material such as SiOCz, acrylic resin, or epoxy resin. The second encapsulation layer 106b may be referred to as a particle covering layer, an organic encapsulation layer, or the like.

[0269] The third encapsulation layer 106c may be implemented to primarily prevent oxygen or water (or moisture) from penetrating into the light-emitting device layer EDL. The third encapsulation layer 106c may be implemented to surround the entirety of the second encapsulation layer 106b disposed inside the dam 104 and the first encapsulation layer 106a disposed outside the dam 104. The third encapsulation layer 106c according to one embodiment of the present disclosure may include the same or different inorganic insulating material as the first encapsulation layer 106a.

[0270] The light emitting display device or the first substrate 100 according to one embodiment of the present disclosure may further include a first margin area MA1 , a second margin area MA2 , and a third margin area MA3 .

[0271] The first margin area MA1 may be provided between the dam 104 of the outermost pixel Po and the emission area EA. Based on the reliability margin of the light-emitting device layer EDL based on lateral penetration of water (or moisture), the first margin area MA1 may have a first width between the dam 104 of the outermost pixel Po and the end of the emission area EA (or the bank 103). Accordingly, the dam 104 may be implemented to be spaced from the end of the emission area EA by a first width in the first direction X of the first margin area MA1.

[0272] The second margin area MA2 may be provided between the dam 104 and the outer surface OS of the first substrate 100. Based on the reliability margin of the light-emitting device layer EDL based on lateral penetration of water (or moisture), the second margin area MA2 may have a second width between the dam 104 and the outer surface OS of the first substrate 100. Accordingly, the dam 104 may be implemented to be spaced apart from the outer surface OS of the first substrate 100 by the second margin area MA2 in the first direction X. For example, the second margin area MA2 may be a region including the first pad portion 110 and the second to fourth barrier patterns 105b, 105c, and 105d of the barrier structure 105.

[0273] The third margin area MA3 may be provided between the first margin area MA1 and the second margin area MA2. The third margin area MA3 may have a third width corresponding to the width of the lowermost surface (or bottom surface) of the dam 104. For example, the third margin area MA3 may be a region including the dam 104.

[0274] In the first direction X, the width of each of the first to third margin areas MA1, MA2, and MA3 may be implemented such that a second interval D2 between a center portion of the outermost pixel Po and the outer surface OS of the first substrate 100 is half the pixel pitch or less.

[0275] refer to Figure 3 、 8 and 9. The first substrate 100 according to one embodiment of the present disclosure may further include a first pad portion 110.

[0276] The first pad portion 110 may be disposed at one peripheral portion of the first substrate 100 and may be electrically coupled to the pixel driving lines DL, GL, PL, CVL, RL, and GCL in a one-to-one relationship.

[0277] The first pad portion 110 according to one embodiment of the present disclosure may include a plurality of first pads 111 disposed inside the circuit layer 101 .

[0278] The plurality of first pads 111 may be divided (or classified) into a first data pad DP, a first gate pad GP, a first pixel driving power pad PPP, a first reference voltage pad RVP, and a first pixel common voltage pad CVP.

[0279] Each of the plurality of first pads 111 may be disposed above the interlayer insulating layer ILD and may be electrically coupled to a corresponding one of the pixel drive lines DL, GL, PL, CVL, RL, and GCL via a pad contact hole passing through the interlayer insulating layer ILD and the buffer layer 101a. For example, each of the plurality of first pads 111 according to one embodiment may include the same material as the pixel electrode PE and may be formed together with the pixel electrode PE. Each of the plurality of first pads 111 according to another embodiment may include the same material as the source / drain electrodes of a TFT and may be formed together with the source / drain electrodes of the TFT.

[0280] A portion of each of the plurality of first pads 111 may be exposed above the first substrate 100 through a pad opening POH formed in the passivation layer PAS. For example, the pad opening POH may be implemented by removing or opening a portion of the passivation layer PAS that overlaps a portion of each of the plurality of first pads 111.

[0281] refer to Figure 9 and 11 The light-emitting display device or the first substrate 100 according to one embodiment of the present disclosure may further include a wavelength conversion layer 107 disposed above the encapsulation layer 106 .

[0282] The wavelength conversion layer 107 may convert the wavelength of light incident thereon from the light emitting region of each pixel region PA. For example, the wavelength conversion layer 107 may convert white light (or blue light) incident thereon from the light emitting region into color light corresponding to the sub-pixel SP, or may transmit only the color light corresponding to the sub-pixel SP. For example, the wavelength conversion layer 107 may include at least one of a wavelength conversion member and a color filter layer.

[0283] The wavelength conversion layer 107 according to one embodiment may include a plurality of wavelength conversion members 107 a and a protective layer 107 b .

[0284] A plurality of wavelength conversion members 107a may be disposed over the encapsulation layer 106 disposed in the emission area EA of each of the plurality of sub-pixel regions SP. For example, each of the plurality of wavelength conversion members 107a may be implemented to have a size equal to or larger than the emission area EA of each sub-pixel region.

[0285] According to one embodiment, the plurality of wavelength conversion members 107a may be divided (or classified) into a red filter that converts white light into red light, a green filter that converts white light into green light, and a blue filter that converts white light into blue light. For example, a red filter (or a first filter) may be disposed above the encapsulation layer 106 in the emission area EA of the red sub-pixel SP, a green filter (or a second filter) may be disposed above the encapsulation layer 106 in the emission area EA of the green sub-pixel SP, and a blue filter (or a third filter) may be disposed above the encapsulation layer 106 in the emission area EA of the blue sub-pixel SP.

[0286] According to another embodiment, a plurality of wavelength conversion members 107a may be disposed over the encapsulation layer 106 of each sub-pixel region. For example, each of the plurality of wavelength conversion members 107a may be disposed over the encapsulation layer 106 so as to overlap the entire corresponding sub-pixel region SP.

[0287] According to another embodiment, a plurality of wavelength conversion members 107a may be implemented to overlap each other in the encapsulation layer 106 that overlaps the circuit area CA (or non-emission area) excluding the emission area EA of each sub-pixel SP. For example, two or more wavelength conversion members 107a having different colors may be provided in the encapsulation layer 106 that overlaps the circuit area CA (or non-emission area) excluding the emission area EA of each sub-pixel SP. The two or more wavelength conversion members 107a provided in the encapsulation layer 106 that overlaps the circuit area CA (or non-emission area) may function as a light-shielding pattern to prevent color mixing between adjacent sub-pixels SP or between adjacent pixels P.

[0288] The protective layer 107b may be implemented to cover the wavelength conversion member 107a and provide a flat surface above the wavelength conversion member 107a. The protective layer 107b may be provided to cover the wavelength conversion member 107a and the encapsulation layer 106 where the wavelength conversion member 107a is not provided. According to one embodiment, the protective layer 107b may include an organic insulating material. Alternatively, the protective layer 107b may further include a getter material for absorbing water and / or oxygen.

[0289] Alternatively, the wavelength conversion layer 107 according to another embodiment may include two or more wavelength conversion members 107a disposed above the encapsulation layer 106 and overlapping the circuit area CA (or non-light-emitting area) excluding the light-emitting area EA in each sub-pixel SP. The two or more wavelength conversion members 107a may function as a light-shielding pattern.

[0290] Alternatively, the wavelength conversion layer 107 may be a sheet-like wavelength conversion sheet and may be disposed on the encapsulation layer 106. In this case, the wavelength conversion sheet (or quantum dot sheet) may include a wavelength conversion member 107a disposed between a pair of thin films. For example, when the wavelength conversion layer 107 includes quantum dots for re-emitting the color light set in the sub-pixel SP, the light-emitting device layer EDL of the sub-pixel SP may be implemented to emit white light or blue light.

[0291] The light-emitting display device or the first substrate 100 according to one embodiment of the present disclosure may further include a functional film 108 .

[0292] The functional film 108 may be provided above the wavelength conversion layer 107. For example, the functional film 108 may be bonded to the wavelength conversion layer 107 by a transparent adhesive member. The functional film 108 according to one embodiment may include at least one of an anti-reflection layer (or anti-reflection film), a barrier layer (or barrier film), a touch sensing layer, and a light path control layer (or light path control film).

[0293] The anti-reflection layer may include a circular polarization layer (or a circular polarization film) that prevents external light reflected by the TFT and / or the pixel driving line disposed on the first substrate 100 from being transmitted to the outside.

[0294] The barrier layer may comprise a material with a low water permeability (eg, a polymeric material) and may primarily prevent the permeation of water or oxygen.

[0295] The touch sensing layer may include a touch electrode layer based on a mutual capacitance method or a self-capacitance method, and may output touch data corresponding to a user's touch through the touch electrode layer.

[0296] The light path control layer may include a stack structure in which high refractive index layers and low refractive index layers are alternately stacked, and may change a path of light incident from each pixel P so as to minimize color shift based on a viewing angle.

[0297] The light emitting display device or the first substrate 100 according to one embodiment of the present disclosure may further include a side sealing member 109 .

[0298] The side sealing member 109 can be formed between the first substrate 100 and the functional film 108, and can cover all side surfaces of the circuit layer 101 and the wavelength conversion layer 107. For example, the side sealing member 109 can cover all side surfaces of each of the circuit layer 101 and the wavelength conversion layer 107, which are exposed to the outside of the display apparatus, between the functional film 108 and the first substrate 100. Also, the side sealing member 109 can cover a portion of the wiring portion 400 coupled with the first pad portion 110 of the first substrate 100. The side sealing member 109 can prevent lateral light leakage caused by light emitted from the inside of the wavelength conversion layer 107 to the outside surface thereof, among the light emitted from the self-emitting device ED of each sub-pixel SP. In particular, the side sealing member 109 overlapping the first pad portion 110 of the first substrate 100 can prevent or minimize external light reflection caused by the first pad 111 disposed in the first pad portion 110.

[0299] Optionally, the side sealing member 109 can further include a getter material for absorbing water and / or oxygen.

[0300] The light emitting display apparatus or the first substrate 100 according to one embodiment of the present disclosure can further include a first chamfer 100c disposed at a corner portion between the front surface 100a and the outer surface OS. The first chamfer 100c can reduce or minimize damage to the corner portion of the first substrate 100 caused by a physical impact applied from the outside, and can prevent disconnection of the wiring portion 400 caused by the corner portion of the first substrate 100. As an example, the first chamfer 100c can have a 45-degree angle, but embodiments of the present disclosure are not limited thereto. The first chamfer 100c can be implemented by a chamfer process using a cutting wheel, a polishing wheel, a laser, or the like. Accordingly, each outer surface of the first pads 111 of the first pad portion 110 disposed in contact with the first chamfer 100c can include an inclined surface inclined at an angle corresponding to that of the first chamfer 100c by removing or polishing the corresponding portion thereof together with the corner portion of the first substrate 100 by means of the chamfer process. For example, when the first chamfer 100c is formed at an angle of 45 degrees between the outer surface OS and the front surface 100a of the first substrate 100, the outer surface (or one end) of the first pad 111 of the first pad portion 110 can be formed at an angle of 45 degrees.

[0301] Reference Figure 7 , 9 And 11, the second substrate 200 according to one embodiment of the present disclosure can include a second pad portion 210, at least one third pad portion 230, and a wire portion 250 as described with reference to Figure 7 Thus, a repeated description thereof will be omitted or will be brief.

[0302] The second substrate 200 according to one embodiment may include a metal pattern layer and an insulating layer insulating the metal pattern layer.

[0303] The metal pattern layer (or conductive pattern layer) may include multiple metal layers. According to one embodiment, the metal pattern layer may include a first metal layer 201, a second metal layer 203, and a third metal layer 205. The insulating layer may include multiple insulating layers. For example, the insulating layer may include a first insulating layer 202, a second insulating layer 204, and a third insulating layer 206. The insulating layer may be referred to as a rear insulating layer or a patterned insulating layer.

[0304] The first metal layer 201 may be implemented on the rear surface 200b of the second substrate 200. The first metal layer 201 according to one embodiment may include a first metal pattern. For example, the first metal layer 201 may be referred to as a first connection layer or a wiring layer.

[0305] The first metal pattern according to one embodiment may have a two-layer structure of Cu and MoTi (Cu / MoTi) The first metal pattern may be used as a wiring of the wiring portion 250 , and thus a repeated description thereof is omitted.

[0306] The first insulating layer 202 may be implemented on the rear surface 200b of the second substrate 200 so as to cover the first metal layer 201. The first insulating layer 202 according to one embodiment may include an inorganic material.

[0307] The second metal layer 203 may be implemented on the first insulating layer 202. The second metal layer 203 according to one embodiment may include a second metal pattern. As an example, the second metal layer 203 may be referred to as a second connection layer, a jumper layer, or a bridge layer.

[0308] According to one embodiment, the second metal pattern may have a two-layer structure of Cu and MoTi (Cu / MoTi). The second metal pattern may be used as multiple gate lines among the multiple lines of the wiring portion 250, but is not limited thereto. For example, the second metal layer 203 may be used as a jumper (or bridge line) for electrically coupling lines formed of different metal materials on different layers in the wiring portion 250.

[0309] Optionally, the wiring (eg, multiple first wirings) set in the second metal layer 203 may be modified to be set in the first metal layer 201 , and the wiring (eg, multiple second wirings) set in the first metal layer 201 may be modified to be set in the second metal layer 203 .

[0310] The second insulating layer 204 may be implemented on the rear surface 200b of the second substrate 200 so as to cover the second metal layer 203. The second insulating layer 204 according to one embodiment may include an inorganic material.

[0311] A third metal layer 205 can be implemented on the second insulating layer 204. The third metal layer 205 according to an embodiment can include a third metal pattern. As an example, the third metal layer 205 can be referred to as a third connection layer or a pad electrode layer.

[0312] The third metal pattern according to an embodiment can have a stack structure of at least two materials among ITO (or IZO), Mo, Ti, and MoTi. For example, the third metal pattern can have a three-layer structure of any one of ITO / Mo / ITO, ITO / MoTi / ITO, IZO / Mo / ITO, or IZO / MoTi / ITO. The third metal pattern can be used as a pad of the second pad portion 210. For example, the pad of the second pad portion 210 formed by the third metal layer 205 can be electrically coupled to the first metal layer 201 through a pad contact hole formed in the first and second insulating layers 202 and 204.

[0313] A third insulating layer 206 can be implemented on the rear surface 200b of the second substrate 200 so as to cover the third metal layer 205. The third insulating layer 206 according to an embodiment can include an organic material. For example, the third insulating layer 206 can include an insulating material such as optical acrylic. The third insulating layer 206 can cover the third metal layer 205 so as to prevent the third metal layer 205 from being exposed to the outside. The third insulating layer 206 can be referred to as an organic insulating layer, a protective layer, a rear protective layer, an organic protective layer, a rear coating layer, or a rear cover layer.

[0314] Each of the plurality of second pads provided in the second pad portion 210 can be electrically coupled to a wire of the wire portion 250 made of the first metal layer 201 or the second metal layer 203 provided on the rear surface 200b of the second substrate 200 through a second pad contact hole provided in the first and second insulating layers 202 and 204. For example, the second data pad can be electrically coupled to one end of a data wire through a second pad contact hole provided in the first and second insulating layers 202 and 204.

[0315] The coupling member 300 according to an embodiment of the disclosure can be disposed between the first substrate 100 and the second substrate 200. The first substrate 100 and the second substrate 200 can be relatively bonded to each other through the coupling member 300. The coupling member 300 according to an embodiment can be a transparent adhesive member or a double-sided tape containing an optically clear adhesive (OCA), an optically clear resin (OCR), or a pressure sensitive adhesive (PSA). The coupling member 300 according to another embodiment can include glass fibers.

[0316] The coupling member 300 according to one embodiment can be disposed in the entire space between the first substrate 100 and the second substrate 200. For example, the entire second surface 100b of the first substrate 100 can be coupled to the entire one surface of the coupling member 300, and the entire front surface 200a of the second substrate 200 can be coupled to the entire other surface of the coupling member 300.

[0317] The coupling member 300 according to another embodiment can be disposed in a pattern structure between the first substrate 100 and the second substrate 200. For example, the coupling member 300 can have a line pattern structure or a mesh pattern structure. The mesh pattern structure can further include a curved portion that discharges a bubble occurring between the first substrate 100 and the second substrate 200 to the outside in a process of bonding the first substrate 100 to the second substrate 200.

[0318] The wiring part 400 according to one embodiment of the disclosure can include a plurality of wirings 410 electrically coupled to the first pad part 110 and the second pad part 210 in a one-to-one relationship. This has been described with reference to FIG. 1, and thus repetitive description thereof is omitted. Figure 7

[0319] The light emitting display apparatus or the wiring part 400 according to one embodiment of the disclosure can further include an edge coating layer 430.

[0320] The edge coating layer 430 can be implemented to cover the wiring part 400. The edge coating layer 430 can be implemented to cover the plurality of wirings 410. As an example, the edge coating layer 430 can be an edge protection layer or an edge insulation layer.

[0321] The edge coating layer 430 according to one embodiment of the disclosure can be implemented to cover the entire first edge part and the first outer surface OS1a of the first substrate 100 and the entire first edge part and the first outer surface OS1b of the second substrate 200, in addition to the plurality of wirings 410. The edge coating layer 430 can prevent corrosion of each of the plurality of wirings 410 including a metal material or occurrence of an electrical short between the plurality of wirings 410. In addition, the edge coating layer 430 can prevent or minimize reflection of external light caused by the plurality of wirings 410 and the first pad 111 of the first pad part 110. As another embodiment, the edge coating layer 430 can implement (or constitute) an outermost surface (or a sidewall) of the display apparatus (or the display panel), and thus can include an impact absorbing material (or substance) or a ductile material in order to prevent damage of the outer surface OS of each of the first substrate 100 and the second substrate 200. As another embodiment, the edge coating layer 430 can include a mixed material of a light shielding material and an impact absorbing material.

[0322] ​According to one embodiment, the edge coating layer 430 may be formed to surround one outer surface OS of each of the first and second substrates 100 and 200 , where the wiring portion 400 is provided.

[0323] According to another embodiment, Figure 7 、 9 As shown in Figures 11 and 12 , the edge coating 430 may be formed to surround all outer surfaces OS of each of the first substrate 100 and the second substrate 200, except for the one outer surface OS on which the wiring portion 400 is provided. For example, the edge coating 430 may be formed to surround all outer surfaces of each of the first substrate 100 and the second substrate 200. In this case, one outer surface OS (or the first outer surface) of each of the first substrate 100 and the second substrate 200 may be surrounded by the plurality of wirings 410 and the edge coating 430. The outer surfaces OS (or the second to fourth outer surfaces) of each of the first substrate 100 and the second substrate 200, except for the one outer surface OS, may be surrounded only by the edge coating 430. For example, the first outer surface of each of the first substrate 100 and the second substrate 200 may include the plurality of wirings 410 and the edge coating 430, and the second to fourth outer surfaces of each of the first substrate 100 and the second substrate 200, except for the first outer surface, may include only the edge coating 430.

[0324] According to one embodiment, when the plurality of wirings 410 and the edge coating 430 provided on the first outer surface are referred to as a first sidewall structure, and the edge coating 430 provided on the second to fourth outer surfaces is referred to as a second sidewall structure, the first sidewall structure and the second sidewall structure may have different thicknesses (or widths). For example, the thickness (or width) of the second sidewall structure may be thinner or narrower than the thickness (or width) of the first sidewall structure by the thickness of the plurality of wirings 410.

[0325] Figure 12 yes Figure 9 An enlarged view of area "C" is shown, Figure 13 yes Figure 11 An enlarged view of area "D" is shown, Figure 14 It is along Figure 8 These drawings are used to describe the cross-sectional view taken along line III-III'. Figure 8 、 9 and 11 are diagrams of barrier structures and enclosure dams.

[0326] The dam 104 according to one embodiment of the present disclosure may include a first dam 104A disposed in a first dam area DA1 of the display area AA, and a second dam 104B disposed in a second dam area DA1 of the display area AA and coupled to the first dam 104A.

[0327] refer to Figure 8 、 9 , 12, and 14, the first dam 104A may be provided to have a first height H1 in each first dam area DA1 of the display area AA. For example, the first dam 104A may have the first height H1 and may have a one-dimensional shape of “┏”, “┓”, “┗”, or “┛” based on the position of each corner area of ​​the display area AA.

[0328] According to one embodiment, the first dam 104A may include a first lower dam pattern 104a1 disposed over the circuit layer 101, a first upper dam pattern 104b1 disposed over the first lower dam pattern 104a1, and a middle dam pattern 104c disposed between the first lower dam pattern 104a1 and the first upper dam pattern 104b1.

[0329] The first lower dam pattern 104a1 may be disposed over the passivation layer PAS disposed in the third margin area MA3 of the first substrate 100. As an example, the first lower dam pattern 104a1 may one-dimensionally have a shape of “┏”, “┓”, “┗”, or “┛” based on a position of the first dam area DA1 defined in the display area AA.

[0330] According to one embodiment, the first lower dam pattern 104a1 may be formed before forming (or manufacturing) the barrier structure 105. For example, the first lower dam pattern 104a1 may be formed between forming the planarization layer 102 and forming the pixel electrode PE.

[0331] According to one embodiment, the first lower dam pattern 104a1 may include an organic insulating material. For example, the first lower dam pattern 104a1 may be formed of the same material as the planarization layer 102, but the embodiments of the present disclosure are not limited thereto. The first lower dam pattern 104a1 may have the same height (or thickness) as the planarization layer 102.

[0332] The middle dam pattern 104c may be disposed above the first lower dam pattern 104a1. The middle dam pattern 104c may have the same planar structure as the first lower dam pattern 104a1 and may have a smaller width than the first lower dam pattern 104a1. For example, the middle dam pattern 104c may have a smaller width than the first lower dam pattern 104a1 and may have a one-dimensional shape of "┏", "┓", "┗", or "┛".

[0333] According to one embodiment, the middle dam pattern 104c may include the same material as the first lower dam pattern 104a1, or may include the same material as the planarization layer 102, but the embodiments of the present disclosure are not limited thereto. For example, the middle dam pattern 104c may have a height (or thickness) greater than or equal to that of the planarization layer 102, or may have a height (or thickness) greater than or equal to that of the first lower dam pattern 104a1. As an example, the total height (or thickness) of the first lower dam pattern 104a1 and the middle dam pattern 104c may be two or more times the height (or thickness) of the planarization layer 102, but the embodiments of the present disclosure are not limited thereto, and the total height (or thickness) of the first lower dam pattern 104a1 and the middle dam pattern 104c may vary based on the thickness of the encapsulation layer 106.

[0334] The first upper dam pattern 104b1 may be disposed above the middle dam pattern 104c. The first upper dam pattern 104b1 may have the same planar structure as the middle dam pattern 104c and may have a smaller width than the middle dam pattern 104c. For example, the first upper dam pattern 104b1 may have a smaller width than the middle dam pattern 104c and may have a one-dimensional shape of "┏", "┓", "┗", or "┛".

[0335] According to one embodiment, the first upper dam pattern 104b1 may include the same material as the bank 103 , but the present disclosure is not limited thereto. For example, the first upper dam pattern 104b1 may have the same height (or thickness) as the bank 103 .

[0336] Furthermore, in the first dam 104A, the middle dam pattern 104c according to another embodiment may include a different material from the first lower dam pattern 104a1, and in this case, a boundary portion between the first lower dam pattern 104a1 and the middle dam pattern 104c may be clearly distinguished.

[0337] According to another embodiment, the middle dam pattern 104c may include a different material from each of the first lower dam pattern 104a1 and the first upper dam pattern 104b1. For example, the middle dam pattern 104c may include at least one of a red color filter layer, a green color filter layer, and a blue color filter layer of a wavelength conversion member. In this case, the first lower dam pattern 104a1, the middle dam pattern 104c, and the first upper dam pattern 104b1 may include different materials, thereby clearly distinguishing the boundaries therebetween.

[0338] In addition, in the first dam 104A, the middle dam pattern 104c according to another embodiment may include the same material as the bank 103 or one color filter layer of the wavelength conversion member, and the first upper dam pattern 104b1 may include the same material as the bank 103 or another color filter layer of the wavelength conversion member. In this case, the first lower dam pattern 104a1, the middle dam pattern 104c, and the first upper dam pattern 104b1 may include different materials, thereby clearly distinguishing the boundary portions therebetween.

[0339] As described above, the first dam 104A may include a triple-layered structure including the first lower dam pattern 104a1, the middle dam pattern 104c, and the first upper dam pattern 104b1, and may be formed or implemented to have a total first height H1 from the passivation layer PAS.

[0340] refer to Figure 8 、 11 , 13, and 14, a second dam 104B may be provided in each second dam area DA2 of the display area AA, thereby having a second height H2 lower than the first height H1. The second dam 104B may be provided between the first dams 104A and may be coupled between adjacent first dams 104A. For example, the second dam 104B may have a second height H2 and may have a one-dimensional "━" or "┃" shape based on the position of each second dam area DA2 of the display area AA.

[0341] The second dam 104B according to one embodiment of the present disclosure may include a second lower dam pattern 104 a 2 disposed over the circuit layer 101 and a second upper dam pattern 104 b 2 disposed over the second lower dam pattern 104 a 2 .

[0342] The second lower dam pattern 104a2 may be disposed over the passivation layer PAS disposed in the third margin area MA3 of the first substrate 100. For example, the second lower dam pattern 104a2 may one-dimensionally have a shape of “━” or “┃” based on the position of the second dam area DA2 defined on the display area AA.

[0343] According to one embodiment, the second lower dam pattern 104a2 may be formed together with the first lower dam pattern 104a1. For example, the second lower dam pattern 104a2 may be formed as the planarization layer 102 disposed in the third margin area MA3 of the first substrate 100. As an example, the planarization layer 102 disposed in the third margin area MA3 and the first dam area DA1 of the first substrate 100 may be patterned into the first lower dam pattern 104a1 through a patterning process, and the planarization layer 102 disposed in the third margin area MA3 and the second dam area DA2 of the first substrate 100 may be patterned into the second lower dam pattern 104a2 through a patterning process. Accordingly, the second lower dam pattern 104a2 may have the same height (or thickness) as the first lower dam pattern 104a1, or may have the same height (or thickness) as the planarization layer 102.

[0344] The second upper dam pattern 104b2 may be disposed above the second lower dam pattern 104a2. The second upper dam pattern 104b2 may have the same planar structure as the second lower dam pattern 104a2 and may have a smaller width than the second lower dam pattern 104a2. For example, the second upper dam pattern 104b2 may have a smaller width than the second lower dam pattern 104a2 and may have a one-dimensional "━" or "┃" shape.

[0345] According to one embodiment, the second upper dam pattern 104b2 may include a different material than the second lower dam pattern 104a2. In one embodiment, the second upper dam pattern 104b2 may include the same material as the bank 103 and may have the same height (or thickness) as the bank 103. In another embodiment, when the first upper dam pattern 104b1 of the first dam 104A includes at least one of a red color filter layer, a green color filter layer, and a blue color filter layer, the second upper dam pattern 104b2 may include the same color filter layer as the first upper dam pattern 104b1.

[0346] As described above, the second dam 104B may include a double-layer structure having a second lower dam pattern 104a2 and a second upper dam pattern 104b2, and may be formed or implemented to have a second height H2 from the passivation layer PAS in total, thereby having a second height H2 lower than the total first height H1 of the first dam 104A.

[0347] The barrier 104 according to an embodiment of the disclosure can include a first barrier 104A having a relatively higher first height H1 in a corner region of the display region AA, whereby it can prevent overflow of the organic encapsulation material caused by starting and / or ending of the spraying or coating of the organic encapsulation material in the corner region of the display region AA in a process of forming the organic encapsulation layer 106b, thereby preventing a decrease in reliability of the light emitting display apparatus caused by the overflow of the organic encapsulation material. For example, in a barrier 104 implemented to have the same height, in order to prevent a phenomenon in which the organic encapsulation layer 106b is not filled in a region adjacent to the barrier 104, the amount of coating of the organic encapsulation material should be increased, however, if the amount of coating of the organic encapsulation material is increased, it is possible that overflow of the organic encapsulation material occurs in the corner region of the display region AA. On the other hand, the barrier 104 according to an embodiment of the disclosure can include the first barrier 104A having the relatively higher first height H1 in the corner region of the display region AA corresponding to the starting and / or ending position of the spraying or coating of the organic encapsulation material, whereby even if the amount of coating of the organic encapsulation material is increased in order to prevent a phenomenon in which the organic encapsulation layer 106b is not filled in a region adjacent to the barrier 104, it is possible to prevent or block overflow of the organic encapsulation material in the corner region of the display region AA.

[0348] Reference Figure 9 and 11 -13, the barrier structure 105 according to an embodiment of the disclosure can be implemented on the interlayer insulation layer ILD of the first substrate 100 so as to surround the display region AA. For example, the barrier structure 105 can be implemented to have a closed loop linear shape on the interlayer insulation layer ILD so as to surround the display region AA in one dimension.

[0349] The barrier structure 105 according to an embodiment can include a plurality of barrier patterns 105a, 105b, 105c, and 105d disposed on the interlayer insulation layer ILD of the outermost pixel Po. For example, the barrier structure 105 can include first to fourth barrier patterns 105a, 105b, 105c, and 105d implemented in parallel with each other so as to have a closed loop linear shape. As an example, the first barrier pattern 105a can be disposed in an inner region of the barrier 104 and can be surrounded by the barrier 104. The second to fourth barrier patterns 105b, 105c, and 105d can be disposed in an outer region of the barrier 104 and can be disposed in parallel with each other so as to surround the barrier 104.

[0350] Each of the first to fourth barrier patterns 105a, 105b, 105c, and 105d according to an embodiment can include a first trench structure TS1, a metal pattern layer MPL, and a second trench structure TS2.

[0351] The first trench structure TS1 may be implemented by the passivation layer PAS. The first trench structure TS1 may be formed by performing a patterning process on the passivation layer PAS disposed in the outermost pixel Po. For example, the first trench structure TS1 may be formed by performing a patterning process using an etching process on the passivation layer PAS. As an example, the first trench structure TS1 may be referred to as a first isolation structure, a first tapered structure, or the like.

[0352] According to an embodiment, the side surface (or side surface) of the first trench structure TS1 may be implemented in an inclined structure or a forward tapered structure. For example, a cross section of the first trench structure TS1 taken along the width direction may have a trapezoidal cross-sectional structure with a top side narrower than a bottom side.

[0353] The metal pattern layer MPL may be disposed above the first trench structure TS1. The metal pattern layer MPL may have at least a two-layer structure similar to that of the pixel electrode PE. For example, the metal pattern layer MPL may include a first metal layer formed together with the first pixel electrode layer PEL1 of the pixel electrode PE and directly contacting the upper surface of the first trench structure TS1, and a second metal layer formed together with the second pixel electrode layer PEL2 of the pixel electrode PE and disposed (or stacked) on the first metal layer.

[0354] The metal pattern layer MPL may have a width wider than the upper surface of the first trench structure TS1. The side surface of the metal pattern layer MPL may be implemented in an inclined structure or a forward tapered structure. For example, a cross-section of the metal pattern layer MPL taken along the width direction may have a trapezoidal cross-sectional structure similar to that of the first trench structure TS1. In the width direction, each of the peripheral portion on one side and the peripheral portion on the other side of the metal pattern layer MPL may protrude beyond the side surface of the first trench structure TS1.

[0355] The side surface of the first trench structure TS1 may have an undercut structure relative to the metal pattern layer MPL. For example, the boundary portion between the first trench structure TS1 and the metal pattern layer MPL or the upper side surface (or upper side surface) of the first trench structure TS1 may have an undercut structure relative to the metal pattern layer MPL. Accordingly, the metal pattern layer MPL may have an eaves structure relative to the first trench structure TS1.

[0356] The second trench structure TS2 may be disposed above the metal pattern layer MPL. For example, the second trench structure TS2 may be referred to as a second isolation structure or a second tapered structure, etc.

[0357] The second trench structure TS2 may include an organic insulating material. The second trench structure TS2 according to one embodiment may include the same material as the bank 103 , but the embodiments of the present disclosure are not limited thereto.

[0358] The bottom surface of the second trench structure TS2 may have the same width as the upper surface of the metal pattern layer MPL. In the second trench structure TS2, the upper surface may have the same width as the bottom surface or may have a narrower width. For example, the side surface of the second trench structure TS2 may be implemented in an inclined structure or a forward tapered structure.

[0359] As described above, the barrier structure 105 including the first to fourth barrier patterns 105a, 105b, 105c, and 105d can isolate (or separate) the self-luminous device ED, or can isolate (or separate) the self-luminous device ED and the common electrode CE. For example, during a deposition process, the self-luminous device ED formed (or deposited) on the barrier structure 105 can be automatically isolated by the undercut structure (or eaves structure) of each of the first to fourth barrier patterns 105a, 105b, 105c, and 105d without a separate isolation process. Accordingly, the self-luminous device ED can include an isolated region isolated by the barrier structure 105.

[0360] According to one embodiment of the present disclosure, the deposited material for the self-emitting device ED formed from an organic light-emitting device can have linearity, thereby preventing deposition on the side surfaces of the first trench structure TS1 covered by the metal pattern layer MPL due to the undercut structure (or eaves structure) of each of the first to fourth barrier patterns 105a, 105b, 105c, and 105d. Therefore, the self-emitting device ED formed (or deposited) above the barrier structure 105 can be isolated (or separated) between the first trench structure TS1 of each of the first to fourth barrier patterns 105a, 105b, 105c, and 105d and the metal pattern layer MPL. Therefore, during the deposition process, the self-emitting device ED can be automatically isolated (or separated) by the first to fourth barrier patterns 105a, 105b, 105c, and 105d of the barrier structure 105, thereby eliminating the need for a separate patterning process for isolating (or separating) the self-emitting device ED. Accordingly, the self-luminous device ED provided on the first substrate 100 can be isolated (or separated) at the outer portion of the first substrate 100, whereby the lateral water penetration path of the first substrate 100 is blocked by the first to fourth barrier patterns 105a, 105b, 105c and 105d of the barrier structure 105.

[0361] Optionally, the common electrode CE disposed above the self-luminous device ED can be automatically isolated (or separated) by the first to fourth barrier patterns 105a, 105b, 105c and 105d of the barrier structure 105 during the execution of a deposition-based deposition process, or can be formed to surround all isolated island-shaped self-luminous devices EDi and the first to fourth barrier patterns 105a, 105b, 105c and 105d of the barrier structure 105 during the execution of a deposition-based deposition process.

[0362] As described above, the light-emitting display device according to one embodiment of the present disclosure may include a dam 104 arranged in the shape of a closed loop along the outer portion of the first substrate 100 or the outermost pixel Po. The dam 104 has a relatively high first height H1 in the corner region of the display area AA. This can prevent the organic encapsulation material from overflowing in the corner region of the display area AA due to the start and / or end of spraying or coating the organic encapsulation material during the formation of the organic encapsulation layer 106b, thereby preventing the reliability reduction caused by the overflow of the organic encapsulation material. In addition, the light-emitting display device according to one embodiment of the present disclosure may include a barrier structure 105 and a dam 104 arranged in the outermost pixel Po, thereby having an air frame structure that does not include a frame area or has a zero frame, thereby preventing or minimizing the reliability reduction of the self-luminous device ED caused by lateral penetration of water (or moisture).

[0363] In addition, if Figure 3 As shown, the metal pattern layer MPL provided in at least one of the first to fourth barrier patterns 105a, 105b, 105c, and 105d of the barrier structure 105 can be electrically coupled to at least one pixel common voltage line CVL via a via hole VH formed in the first trench structure TS1. For example, the via hole VH can be formed to sequentially pass through the passivation layer PAS, the interlayer insulating layer ILD, and the buffer layer 101a at the intersection between the pixel common voltage line CVL and the metal pattern layer MPL having a closed loop line shape. Therefore, the metal pattern layer MPL provided in at least one of the first to fourth barrier patterns 105a, 105b, 105c, and 105d can be electrically coupled to the at least one pixel common voltage line CVL via the corresponding via hole VH. Accordingly, the metal pattern layer MPL can form an equivalent potential with the plurality of pixel common voltage lines CVL and can primarily block static electricity from flowing from the outside to the interior of the display area AA, thereby preventing defects caused by static electricity. For example, the metal pattern layer MPL provided in at least one of the first to fourth barrier patterns 105 a , 105 b , 105 c , and 105 d may discharge static electricity flowing from the outside to the pixel common voltage line CVL to prevent defects caused by static electricity.

[0364] Figure 15 is a diagram showing a multi-screen display device according to an embodiment of the present disclosure, Figure 16 It is along Figure 15 The cross-sectional view is taken along line IV-IV'. Figure 15 and 16 Shown by splicing according to Figures 1 to 14 The light-emitting display device according to another embodiment of the present disclosure implements a multi-screen light-emitting display device.

[0365] refer to Figure 15 and 16 According to an embodiment of the present disclosure, a multi-screen light-emitting display device (or a spliced ​​light-emitting display device) may include a plurality of display devices DM1 to DM4.

[0366] The plurality of display devices DM1 to DM4 may respectively display separate images or may display one divided image. Each of the plurality of display devices DM1 to DM4 may include Figures 1 to 14 The light emitting display device according to one embodiment of the present disclosure is shown in FIG. 1 , and thus a repeated description thereof is omitted or briefly given.

[0367] Multiple display devices DM1 to DM4 can be spliced ​​on a separate tiling frame so as to contact each other at their side surfaces. For example, multiple display devices DM1 to DM4 can be laid out in an N×M format to realize a multi-screen display device with a large screen. As an example, N is a positive integer of 1 or greater, and M is a positive integer of 2 or greater, but the embodiments of the present disclosure are not limited thereto. For example, N is a positive integer of 2 or greater, and M is a positive integer of 1 or greater.

[0368] Each of the plurality of display devices DM1 to DM4 does not include a frame area (or non-display area) surrounding the entire display area AA where an image is displayed, but may have an air frame structure where the display area AA is surrounded by air. For example, in each of the plurality of display devices DM1 to DM4, the entire first surface of the first substrate 100 may be implemented as the display area AA.

[0369] According to this embodiment, in each of the plurality of display devices DM1 to DM4, the second interval D2 between the center portion CP of the outermost pixel Po and the outermost outer surface VL of the first substrate 100 can be implemented to be half or less of the first interval D1 (or pixel pitch) between adjacent pixels. Accordingly, in two adjacent display devices DM1 to DM4 that are bonded (or in contact) with each other at the side surfaces along the first direction X and the second direction Y based on the lateral bonding method, the interval "D2+D2" between adjacent outermost pixels Po can be equal to or less than the first interval D1 between the two adjacent pixels.Figure 16 In the first and third display apparatuses DM1 and DM3 coupled to each other (or in contact with each other) at the side surface in the second direction Y, the interval "D2+D2" between the center portions CP of the outermost pixels Po of the first display apparatus DM1 and the center portions CP of the outermost pixels Po of the third display apparatus DM3 can be equal to or less than the first interval D1 (or the pixel pitch) between two adjacent pixels provided in each of the first and third display apparatuses DM1 and DM3.

[0370] Accordingly, the interval "D2+D2" between the center portions CP of the outermost pixels Po of two adjacent display apparatuses DM1 to DM4 coupled to each other (or in contact with each other) at the side surface in the first direction X and the second direction Y can be equal to or less than the first interval D1 between two adjacent pixels provided in each of the display apparatuses DM1 to DM4, whereby there can be no seam or boundary portion between the two adjacent display apparatuses DM1 to DM4, and thus there can be no dark area caused by the boundary portion provided between the display apparatuses DM1 to DM4. As a result, an image displayed on the multiple-screen light emitting display apparatus in which the plurality of display apparatuses DM1, DM2, DM3, and DM4 are tiled in the N×M form can be continuously displayed without a sense of discontinuity (or a sense of discontinuity) at the boundary portion between the plurality of display apparatuses DM1, DM2, DM3, and DM4.

[0371] In Figure 15 and 16 the plurality of display apparatuses DM1 to DM4 are tiled in the 2×2 form, but embodiments of the present disclosure are not limited thereto, and the plurality of display apparatuses DM1 to DM4 can be tiled in the x×1 form, the 1×y form, or the x×y form. As an example, x and y can be natural numbers of 2 or more, equal to or different from each other. For example, x can be a natural number of 2 or more or equal to y, and y can be a natural number of 2 or more or greater or less than x.

[0372] As described above, when the display areas AA of the plurality of display apparatuses DM1 to DM4 are one screen and one image is displayed, the multiple-screen light emitting display apparatus according to an embodiment of the present disclosure can display an image without a sense of discontinuity and continuously at the boundary portion between the plurality of display apparatuses DM1 to DM4, whereby the immersion of a viewer in viewing the image displayed by the multiple-screen light emitting display apparatus can be enhanced.

[0373] Hereinafter, a light emitting display apparatus according to an embodiment of the present disclosure and a multiple-screen display apparatus including the same will be described.

[0374] According to one embodiment of the present disclosure, a light-emitting display device may include: a display area, the display area including a plurality of pixels arranged above a substrate along a first direction and a second direction intersecting the first direction; a light-emitting device layer, the light-emitting device layer including a self-luminous device arranged in the display area; a dam, the dam being arranged in a closed loop shape along an outer portion of the substrate; and an encapsulation layer, the encapsulation layer being arranged on the light-emitting device layer and including an organic encapsulation layer arranged in an encapsulation area surrounded by the dam, the dam being configured to have a first height in a corner area of ​​the display area, and a second height lower than the first height in other areas of the display area except the corner area.

[0375] According to some embodiments of the present disclosure, the display area may include a plurality of first dam areas arranged in the corner areas of the display area, and a plurality of second dam areas arranged between the plurality of first dam areas, and the dam may be configured to have the first height in each of the plurality of first dam areas and the second height in each of the plurality of second dam areas.

[0376] According to some embodiments of the present disclosure, each of the plurality of first dam regions may have a one-dimensional shape of “┏”, “┓”, “┗” or “┛”, and each of the plurality of second dam regions may have a one-dimensional shape of “━” or “┃”.

[0377] According to some embodiments of the present disclosure, each of the multiple first dam areas may include: a 1-1 dam area, the 1-1 dam area being configured to have a length less than or equal to half of the first side length of the display area parallel to the first direction; and a 1-2 dam area, the 1-2 dam area being coupled to the 1-1 dam area and being configured to have a length less than or equal to half of the second side length of the display area parallel to the second direction.

[0378] According to some embodiments of the present disclosure, the dam may include a first dam provided at each corner region of the display area, and a second dam provided at each other region of the display area except the corner region and coupled to the first dam.

[0379] According to some embodiments of the present disclosure, the first dam may include a first lower dam pattern, a first upper dam pattern disposed on the first lower dam pattern, and an intermediate dam pattern disposed between the first lower dam pattern and the first upper dam pattern.

[0380] According to some embodiments of the present disclosure, the light-emitting display device may further include a planarization layer arranged between the substrate and the light-emitting device layer, and a partition wall arranged on the planarization layer to define a pixel area on the substrate, each of the first lower dam pattern and the middle dam pattern may include the same material as the material of the planarization layer, and the first upper dam pattern may include the same material as the material of the partition wall.

[0381] According to some embodiments of the present disclosure, the light-emitting display device may further include a planarization layer arranged between the substrate and the light-emitting device layer, a dam arranged on the planarization layer to define a pixel area on the substrate, and a wavelength conversion layer including a wavelength conversion component arranged on the encapsulation layer. The first lower dam pattern may include the same material as the material of the planarization layer, the middle dam pattern may include the same material as the material of one of the dam and the wavelength conversion component, and the first upper dam pattern may include the same material as the material of the other of the dam and the wavelength conversion component.

[0382] According to some embodiments of the present disclosure, the second dam may include a first lower dam pattern and a first upper dam pattern disposed above the first lower dam pattern.

[0383] According to some embodiments of the present disclosure, the light-emitting display device may further include a planarization layer arranged between the substrate and the light-emitting device layer, and a partition wall arranged on the planarization layer to define a pixel area on the substrate, the first lower dam pattern may include the same material as the planarization layer, and the first upper dam pattern may include the same material as the partition wall.

[0384] According to some embodiments of the present disclosure, the light-emitting display device may further include a barrier structure, which is arranged in a closed loop shape along the outer portion of the substrate so as to isolate the self-luminous device. The barrier structure may include a first barrier pattern surrounded by a dam, and a second barrier pattern surrounding the dam.

[0385] According to some embodiments of the present disclosure, the light-emitting display device may further include a passivation layer arranged on the substrate to support the dam, and each of the first barrier pattern and the second barrier pattern may include a first groove structure implemented as the passivation layer, a metal pattern layer arranged on the first groove structure, and a second groove structure formed on the metal pattern layer, wherein the metal pattern layer is wider than the upper surface of the first groove structure.

[0386] According to some embodiments of the present disclosure, a side surface of the first trench structure may be configured to have an undercut structure relative to the metal pattern layer, and the self-luminous device may be isolated by the undercut structure.

[0387] According to some embodiments of the present disclosure, the light-emitting display device may further include a pixel common voltage line electrically coupled to the common electrode of the light-emitting device layer arranged in the display area, and the metal pattern layer may be electrically coupled to the pixel common voltage line through a through hole formed in the first groove structure and the passivation layer.

[0388] According to some embodiments of the present disclosure, the encapsulation layer may include a first inorganic encapsulation layer arranged on the light-emitting device layer, the dam and the barrier structure; and a second inorganic encapsulation layer arranged on the first inorganic encapsulation layer. The organic encapsulation layer may be arranged in an encapsulation area on the light-emitting device layer surrounded by the dam between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the dam may be configured to block the diffusion of the organic encapsulation layer.

[0389] According to some embodiments of the present disclosure, the light-emitting display device may further include: a first pad portion, the first pad portion including a plurality of first pads arranged in a peripheral portion of the substrate; a second pad portion, the second pad portion including a plurality of second pads overlapping with each of the plurality of first pads; and a wiring portion, the wiring portion being arranged on a side surface of the substrate and including a plurality of wirings coupling the plurality of first pads to the plurality of second pads in a one-to-one relationship.

[0390] According to some embodiments of the present disclosure, the light-emitting display device may further include: a first pad portion, the first pad portion including a plurality of first pads arranged in a peripheral portion of the substrate; a wiring substrate, the wiring substrate including a second pad portion, the second pad portion including a plurality of second pads respectively overlapping with the plurality of first pads; a coupling member arranged between the substrate and the wiring substrate; and a wiring portion, the wiring portion being arranged on a side surface of each of the substrate and the wiring substrate, and including a plurality of wirings coupling the plurality of first pads to the plurality of second pads in a one-to-one relationship.

[0391] According to some embodiments of the present disclosure, the size of the display area may be the same as the size of the substrate, or the distance between the center portion of the outermost pixel among the multiple pixels and the outer surface of the substrate may be half of the pixel pitch or less, and the pixel pitch may be the distance between the center portions of two adjacent pixels.

[0392] A multi-screen light emitting display apparatus according to some embodiments of the disclosure can include a plurality of display devices disposed along at least one of a first direction and a second direction crossing the first direction, each of the plurality of display devices can include a light emitting display apparatus, the light emitting display apparatus can include a display area including a plurality of pixels arranged along the first direction and the second direction over a substrate, a light emitting device layer including a self-light emitting device disposed in the display area, a dam disposed in a closed loop shape along a peripheral portion of the substrate, and an encapsulation layer disposed on the light emitting device layer and including an organic encapsulation layer disposed in an encapsulation area surrounded by the dam, the dam can be configured to have a first height at a corner area of the display area and a second height lower than the first height at other areas of the display area except the corner area.

[0393] According to some embodiments of the disclosure, in first and second display devices adjacent along the first and second directions, a distance between a center portion of an outermost pixel of the first display device and a center portion of an outermost pixel of the second display device can be less than or equal to a pitch between centers of adjacent pixels along the first and second directions.

[0394] Various modifications and changes can be made to the present disclosure without departing from its spirit or essential characteristics. It is to be understood that the present disclosure is not limited to the examples described herein, but encompasses any and all modifications within the scope of the present disclosure, including full use of the principles of the present disclosure. Therefore, the present disclosure is intended to cover all modifications and changes within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting display device, comprising: a display area including a plurality of pixels arranged along a first direction and a second direction intersecting the first direction over a substrate; a light-emitting device layer, the light-emitting device layer including self-luminous devices disposed in the display area; a dam provided in a closed loop shape along a peripheral portion of the substrate; an encapsulation layer disposed on the light-emitting device layer and comprising an organic encapsulation layer disposed in an encapsulation region surrounded by the dam; as well as a barrier structure provided in a closed loop shape along the peripheral portion of the substrate so as to isolate the self-luminous device, The barrier structure comprises: a first barrier pattern surrounded by the dam; as well as a second barrier pattern surrounding the dam, The dam is configured to have a first height in a corner region of the display area, and to have a second height lower than the first height in other regions of the display area except the corner region.

2. The light-emitting display device according to claim 1, The display area includes: a plurality of first dam areas arranged in corner areas of the display area; as well as a plurality of second dam areas arranged between the plurality of first dam areas; The dam is configured to have the first height in each of the plurality of first dam regions and the second height in each of the plurality of second dam regions.

3. The light-emitting display device according to claim 2, wherein each of the plurality of first dam regions is configured to one-dimensionally have a shape of “┏”, “┓”, “┗” or “┛”; Each of the plurality of second dam regions is configured to have a one-dimensional shape of “━” or “┃”.

4. The light-emitting display device according to claim 2 , wherein each of the plurality of first dam regions comprises: a 1-1 dam region, wherein the 1-1 dam region is configured to have a length less than or equal to half of a first side length of the display region parallel to the first direction; as well as A 1-2 dam region is coupled to the 1-1 dam region and is configured to have a length less than or equal to half of a second side length of the display region parallel to the second direction.

5. The light-emitting display device according to claim 1 , wherein the dam comprises: a first dam provided at each corner region of the display region; as well as A second dam is provided in each other area of ​​the display area except the corner area and is coupled to the first dam.

6. The light-emitting display device according to claim 5, wherein the first dam comprises: The first lower dam pattern; a first upper dam pattern disposed on the first lower dam pattern; as well as An intermediate dam pattern is disposed between the first lower dam pattern and the first upper dam pattern.

7. The light-emitting display device according to claim 6, further comprising: a planarization layer disposed between the substrate and the light-emitting device layer; as well as A bank is provided on the planarization layer to define a pixel area on the substrate, wherein each of the first lower dam pattern and the middle dam pattern comprises the same material as that of the planarization layer, The first upper dam pattern comprises the same material as that of the bank.

8. The light-emitting display device according to claim 6, further comprising: a planarization layer disposed between the substrate and the light-emitting device layer; a bank disposed on the planarization layer to define a pixel area on the substrate; as well as a wavelength conversion layer including a wavelength conversion member provided on the encapsulation layer, wherein the first lower dam pattern comprises the same material as that of the planarization layer, wherein the intermediate dam pattern comprises the same material as that of one of the bank and the wavelength conversion member, The first upper dam pattern includes a same material as that of the other of the bank and the wavelength conversion member.

9. The light emitting display device according to claim 5, wherein the second dam comprises: The first lower dam pattern; as well as A first upper dam pattern is disposed above the first lower dam pattern.

10. The light emitting display device according to claim 9, further comprising: a planarization layer disposed between the substrate and the light-emitting device layer; as well as A bank is provided on the planarization layer to define a pixel area on the substrate, wherein the first lower dam pattern comprises the same material as that of the planarization layer, The first upper dam pattern comprises the same material as that of the bank.

11. The light emitting display device according to claim 10, further comprising a passivation layer disposed on the substrate to support the dam, wherein each of the first barrier pattern and the second barrier pattern comprises: a first trench structure implemented as the passivation layer; a metal pattern layer disposed on the first trench structure, wherein the metal pattern layer is wider than an upper surface of the first trench structure; as well as A second trench structure is formed on the metal pattern layer.

12. The light-emitting display device according to claim 11, wherein a side surface of the first trench structure is configured to have an undercut structure relative to the metal pattern layer, The self-luminous device is isolated by the undercut structure.

13. The light emitting display device according to claim 11, further comprising a pixel common voltage line electrically coupled to a common electrode of the light emitting device layer provided in the display area, The metal pattern layer is electrically coupled to the pixel common voltage line through a through hole formed in the first trench structure and the passivation layer.

14. The light-emitting display device according to claim 1, The encapsulation layer comprises: a first inorganic encapsulation layer disposed on the light-emitting device layer, the dam, and the barrier structure; as well as a second inorganic encapsulation layer disposed on the first inorganic encapsulation layer, wherein, in the encapsulation region on the light-emitting device layer surrounded by the dam, the organic encapsulation layer is disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer; The dam is configured to block diffusion of the organic encapsulation layer.

15. The light emitting display device according to claim 1, further comprising: a first pad portion including a plurality of first pads provided at a peripheral portion of the substrate; a second pad portion including a plurality of second pads overlapping each of the plurality of first pads; as well as A wiring portion is provided on one side surface of the substrate and includes a plurality of wirings coupling the plurality of first pads to the plurality of second pads in a one-to-one relationship.

16. The light emitting display device according to claim 1, further comprising: a first pad portion including a plurality of first pads provided at a peripheral portion of the substrate; a wiring substrate including a second pad portion, wherein the second pad portion includes a plurality of second pads respectively overlapping the plurality of first pads; a coupling member disposed between the substrate and the wiring substrate; as well as A wiring portion is provided on one side surface of each of the substrate and the wiring substrate and includes a plurality of wirings coupling the plurality of first pads to the plurality of second pads in a one-to-one relationship.

17. The light-emitting display device according to claim 1, wherein the size of the display area is the same as the size of the substrate, or wherein a distance between a center portion of an outermost pixel of the plurality of pixels and an outer surface of the substrate is half a pixel pitch or less, The pixel pitch is the distance between the center parts of two adjacent pixels.

18. A multi-screen light-emitting display device, comprising: a plurality of display devices arranged along at least one of a first direction and a second direction intersecting the first direction, Each of the plurality of display devices comprises the light-emitting display apparatus according to any one of claims 1 to 17.

19. The multi-screen light-emitting display device according to claim 18, wherein in a first display device and a second display device adjacent to each other along the first direction or the second direction, a distance between a center portion of an outermost pixel of the first display device and a center portion of an outermost pixel of the second display device is less than or equal to a pixel pitch, The pixel pitch is a distance between center portions of adjacent pixels along the first direction or the second direction.

Images