Light-emitting display device and multi-screen light-emitting display device including the same

Abstract

A light-emitting display device includes: a substrate configured to include a display area; a planarization layer arranged above the display area; a groove line arranged along a peripheral portion of the substrate and configured to surround a side of the planarization layer; a dam configured to surround the groove line; a light-emitting device layer configured to include a self-luminous device arranged above the planarization layer, the groove line, and the dam; an encapsulation layer, the encapsulation layer being configured to include an organic encapsulation layer arranged above an encapsulation area surrounded by the dam, the organic encapsulation layer being configured to fill the groove line and configured to surround a side of the light-emitting device layer and a side of the planarization layer, and the self-luminous device being configured to be isolated at each of the groove line and the dam.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0189782, filed on December 31, 2020, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a light-emitting display device and a multi-screen light-emitting display device including the same. Background Art

[0004] Unlike liquid crystal display (LCD) devices, light-emitting display devices, which are self-luminous display devices, do not require a separate light source and can therefore be manufactured to be lightweight and thin. In addition, light-emitting display devices are driven by low voltage, thereby reducing power consumption. Furthermore, light-emitting display devices are excellent in color realization, response time, viewing angle, and contrast, and therefore, are attracting considerable attention as next-generation light-emitting display devices.

[0005] The light emitting display device displays an image based on the light emitting device layer including the light emitting device interposed between two electrodes. In this case, the light emitted by the light emitting device is released to the outside through the electrodes and the substrate.

[0006] The light-emitting display device includes a display panel implemented to display an image. The display panel may include a display area including a plurality of pixels for displaying the image, an encapsulation layer including an organic encapsulation layer disposed in the display area, a dam to prevent diffusion of the encapsulation layer, and a frame area surrounding the display area.

[0007] Conventional light-emitting display devices may require a bezel (or mechanism) to block a bezel region provided at the periphery of the display panel, and the bezel width may increase due to the width of the bezel. Furthermore, when the bezel of a light-emitting display device is significantly reduced, the reliability of the display panel may be reduced due to degradation of the light-emitting display device caused by water (or water vapor) penetration, and the reliability of the display panel may be reduced due to non-filling or overflow of the organic encapsulation layer.

[0008] Recently, a multi-screen light-emitting display device has been commercialized, in which a large screen is realized by arranging light-emitting display devices in a dot matrix or a matrix.

[0009] However, in conventional multi-screen light-emitting display devices, border portions such as gaps are formed between adjacent light-emitting display devices due to the frame areas or frames of the respective light-emitting display devices. When an image is displayed on the total screen of the multi-screen light-emitting display device, the border portions may cause a sense of discontinuity (or discontinuity) in the image, and thus, the immersion of the viewer viewing the image may be reduced. Summary of the Invention

[0010] Accordingly, the present disclosure is directed to providing a light-emitting display device and a multi-screen light-emitting display device including the same that substantially obviate one or more problems due to limitations and disadvantages of the prior art.

[0011] One aspect of the present disclosure is to provide a light-emitting display device and a multi-screen light-emitting display device including the same, which have a zero bezel width and prevent reliability degradation of a light-emitting display panel caused by water (or water vapor) penetration.

[0012] Another aspect of the present disclosure is to provide a light-emitting display device and a multi-screen light-emitting display device including the same, which have zero border width, prevent the reliability of the light-emitting display panel from being reduced due to water (or water vapor) penetration, and prevent non-filling or overflow of the organic encapsulation layer.

[0013] The objectives and other advantages of the disclosure will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0014] To achieve these and other advantages and in accordance with the inventive purposes of the present disclosure, as embodied and broadly described herein, a light-emitting display device includes: a substrate configured to include a display area; a planarization layer disposed above the display area; a groove line disposed along a peripheral portion of the substrate and configured to surround a side of the planarization layer, the groove line being configured to surround a dam of the groove line; a light-emitting device layer configured to include a self-luminous device disposed above the planarization layer, the groove line, and the dam; an encapsulation layer, the encapsulation layer being configured to include an organic encapsulation layer disposed above an encapsulation area surrounded by the dam, the organic encapsulation layer being configured to fill the groove line and configured to surround a side of the light-emitting device layer and a side of the planarization layer, and the self-luminous device being configured to be isolated at each of the groove line and the dam.

[0015] In another aspect of the present disclosure, a multi-screen light-emitting display device includes: a plurality of display devices arranged along at least one of a first direction and a second direction intersecting the first direction, the plurality of display devices each including a light-emitting display device, and the light-emitting display device including: a substrate configured to include a display area; a planarization layer arranged above the display area; a groove line arranged along a peripheral portion of the substrate and configured to surround a side of the planarization layer; a dam configured to surround the groove line; a light-emitting device layer configured to include a self-luminous device arranged above the planarization layer, the groove line, and the dam; an encapsulation layer, the encapsulation layer being configured to include an organic encapsulation layer arranged above an encapsulation area surrounded by the dam, the organic encapsulation layer being configured to fill the groove line and configured to surround a side of the light-emitting device layer and a side of the planarization layer, and the self-luminous device being configured to be isolated at each of the groove line and the dam.

[0016] Specific details of various examples according to the present specification, in addition to means for solving the above-mentioned problems, are included in the following description and drawings.

[0017] According to an embodiment of the present disclosure, a light-emitting display device having a zero bezel width and preventing reliability degradation caused by water (or water vapor) penetration and a multi-screen light-emitting display device including the same may be provided.

[0018] According to an embodiment of the present disclosure, a light-emitting display device and a multi-screen light-emitting display device including the same can be provided, which have zero border width, prevent the reliability of the light-emitting display panel from being reduced due to water (or water vapor) penetration, and prevent non-filling or overflow of the organic encapsulation layer.

[0019] According to an embodiment of the present disclosure, a multi-screen display device for displaying images without a sense of choppiness can be provided.

[0020] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain the principle of the disclosure.

[0022] Figure 1 is a plan view illustrating a light emitting display device according to an embodiment of the present disclosure.

[0023] Figure 2A It is a diagram Figure 1, a diagram of one pixel according to an embodiment of the present disclosure is shown in .

[0024] Figure 2B It is a diagram Figure 1 FIG. 1 is a diagram of a pixel according to another embodiment of the present disclosure.

[0025] Figure 2C It is a diagram Figure 1 FIG. 1 is a diagram of a pixel according to another embodiment of the present disclosure.

[0026] Figure 3 yes Figure 1 An enlarged view of area "A" is shown in FIG.

[0027] Figure 4 It is a diagram Figure 1 and Figure 3 The equivalent circuit diagram of a sub-pixel is shown in FIG.

[0028] Figure 5 It is a diagram Figure 1 and Figure 3 Schematic diagram of the gate drive circuit shown in .

[0029] Figure 6 is a diagram illustrating a rear surface of a light-emitting display device according to an embodiment of the present disclosure.

[0030] Figure 7 is a diagram illustrating a rear surface of a light-emitting display device according to another embodiment of the present disclosure.

[0031] Figure 8 It is along Figure 7 A cross-sectional view taken along the line II' shown in FIG.

[0032] Figure 9 yes Figure 8 An enlarged view of area "B" is shown in FIG.

[0033] Figure 10 It is along Figure 7 The cross-sectional view is taken along the line II-II' shown in FIG.

[0034] Figure 11 yes Figure 8 An enlarged view of area "C" is shown in FIG.

[0035] Figure 12 It is along Figure 7 Another cross-sectional view taken along the line II' shown in FIG.

[0036] Figure 13 It is along Figure 7 Another cross-sectional view taken along the line II-II' shown in FIG.

[0037] Figure 14 yes Figure 12 An enlarged view of area "D" is shown in FIG.

[0038] Figure 15 yes Figure 11 Microscope photograph of the undercut region of the passivation layer is shown in FIG.

[0039] Figure 16 yes Figure 11 Microscope photograph of the undercut region of the passivation layer is shown in FIG.

[0040] Figure 17 is a diagram illustrating a multi-screen light-emitting display device according to an embodiment of the present disclosure.

[0041] Figure 18 It is along Figure 17 A cross-sectional view taken along line III-III' shown in FIG. DETAILED DESCRIPTION

[0042] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, detailed descriptions of known functions or configurations related to this document will be omitted when it is determined that such detailed descriptions would unnecessarily obscure the subject matter of the inventive concept. The described progression of processing steps and / or operations are examples; however, the order of steps and / or operations is not limited to that set forth herein and may be changed as known in the art, with the exception of steps and / or operations that must occur in a particular order. Similar reference numerals designate similar elements throughout. The names of the various elements used in the following explanations have been selected solely for the convenience of writing this specification and may therefore differ from those used in the actual product.

[0043] The advantages and features of the present disclosure, as well as methods for implementing the same, will become apparent through the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and convey the scope of the present disclosure to those skilled in the art.

[0044] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the embodiments of the present disclosure are not limited to the details shown in the drawings. Similar reference numerals refer to similar elements throughout the text. In the following description, when it is determined that a detailed description of a related known function or configuration does not necessarily obscure the focus of the present disclosure, its detailed description will be omitted. Where "including", "having", and "comprising" described in this specification are used, another component may be added unless "only to" is used. Terms in the singular may include plural forms unless otherwise stated.

[0045] When interpreting an element, although there is no explicit description, the element is interpreted as including an error range.

[0046] In describing positional relationships, for example, when the positional relationship between two components is described as "on," "above," "under," or "near," one or more other components may be disposed between the two components, unless more restrictive terms, such as "only" or "directly," are used.

[0047] In describing temporal relationships, for example, when a temporal sequence is described as, for example, "after," "subsequently," "next," and "before," discontinuities may be included unless more restrictive terms such as "only," "immediately," or "directly" are used.

[0048] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and, similarly, a second element may be referred to as a first element without departing from the scope of this disclosure.

[0049] In describing the elements of the present disclosure, terms such as first, second, A, B, (a), (b) etc. can be used. These terms are only used to distinguish the corresponding elements from other elements, and these corresponding elements are not limited by these terms in terms of their essence, order, priority. It should be understood that when an element or layer is referred to as being "on" or "coupled" to another element or layer on another element or layer, it can be directly on or directly coupled to the other element or layer, or there can be an intermediate element or layer. In addition, it should be understood that when an element is arranged on or under another element, this can represent the situation that these elements are arranged to directly contact each other, but can also represent the situation that these elements are arranged when there is no direct contact with each other.

[0050] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed elements. For example, the meaning of "at least one of a first element, a second element, and a third element" refers to all combinations of elements selected from two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0051] As used herein, the term "surrounding" includes at least partially surrounding as well as completely surrounding one or more of the relevant elements. Similarly, as used herein, the term "covering" includes at least partially covering as well as completely covering one or more of the relevant elements. For example, if the encapsulation layer surrounds the dam, this can be interpreted as the encapsulation layer at least partially surrounding the dam. However, in some embodiments, the encapsulation layer may completely surround the dam. The meaning of the term "surrounding" used herein may be further specified based on the relevant drawings and embodiments. In the present disclosure, the terms "surrounding", "at least partially surrounding", "completely surrounding" or the like are used. According to the definition of "surrounding" as set out above, when only the term "surrounding" is used in an embodiment, it may mean either at least partially surrounding or completely surrounding one or more of the relevant elements. The same applies to the term "covering".

[0052] The features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate and technically drive each other as will be fully understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0053] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the elements of each drawing, similar reference numerals may refer to similar elements even though the same elements are shown in other drawings. Furthermore, for the convenience of description, the scale of each element shown in the accompanying drawings is different from the actual scale, and therefore, the present invention is not limited to the scale shown in the drawings.

[0054] Figure 1 is a plan view illustrating a light emitting display device according to an embodiment of the present disclosure.

[0055] Reference Figure 1 A light-emitting display device (or display panel) 10 according to an embodiment of the present disclosure may include a substrate 100 including a display area AA, a plurality of pixels P in the display area AA of the substrate 100 , and a dam 104 .

[0056] The substrate 100 may be referred to as a first substrate, a base substrate, or a pixel array substrate. The substrate 100 may be a glass substrate, or may be a thin glass substrate or a plastic substrate that is bendable or flexible.

[0057] The display area AA of the substrate 100 may be an area where an image is displayed, and may be referred to as an active portion, an active area, a display portion, or a display portion. The size of the display area AA may be the same as or substantially the same as that of the substrate 100 (or the light-emitting display device or the display panel). For example, the size of the display area AA may be the same as the total size of the first surface of the substrate 100. Therefore, the display area AA may be implemented (or provided) on the entire front surface of the substrate 100, and therefore, the substrate 100 may not include an opaque non-display portion provided along the peripheral portion (or edge portion) of the first surface to surround the entire display area AA. Accordingly, the entire front surface of the light-emitting display device may implement the display area AA.

[0058] The end (or outermost portion) of the display area AA may overlap with or be substantially aligned with the outer surface OS of the substrate 100. For example, with respect to the thickness direction Z of the light-emitting display device, the side (or end line) of the display area AA may be on a vertical extension line VL (see FIG. Figure 8 ) are substantially aligned at . The sides of the display area AA may not be surrounded by a separate mechanism and may be in contact with the surrounding air only. For example, all sides of the display area AA may be provided in a structure that is in direct contact with the air without being surrounded by a separate mechanism. Therefore, the outer surface OS of the substrate 100 corresponding to the end of the display area AA may be surrounded by air only (or in contact with the surrounding air), and therefore, the light-emitting display device according to the embodiment of the present disclosure may have an air-bezel structure or a non-bezel structure (or a zeroized bezel or no bezel) in which the end (or side) of the display area AA is surrounded by air rather than an opaque non-display area.

[0059] A plurality of pixels P may be arranged (or disposed) at the display area AA of the substrate 100 to have a first interval D1 along a first direction X and a second direction Y. For example, the first direction X may traverse (or intersect or cross) the second direction Y. The first direction X may be a lateral direction, a horizontal direction, or a first longitudinal direction (e.g., a lateral longitudinal direction) of the substrate 100 or the light-emitting display device. The second direction Y may be a longitudinal direction, a vertical direction, or a second longitudinal direction (e.g., a longitudinal longitudinal direction) of the substrate 100 or the light-emitting display device.

[0060] Each of the plurality of pixels P may be implemented on a plurality of pixel regions defined on the display area AA of the substrate 100. Each of the plurality of pixels P may have a first length L1 parallel to the first direction X and a second length L2 parallel to the second direction Y. The first length L1 may be the same as the second length L2 or the first interval D1. The first length L1 and the second length L2 may be the same as the first interval D1. Therefore, the plurality of pixels (or pixel regions) P may all have the same size.

[0061] Two pixels P adjacent to each other along the first direction X and the second direction Y may have the same first interval D1 without a margin of error in the manufacturing process. The first interval D1 may be the pitch (or pixel pitch) between the two adjacent pixels P. For example, the first length L1 or the second length L2 of the pixel P may be referred to as the pixel pitch. For example, the first interval (or pixel pitch) D1 may be the distance (or length) between the center portions of the two adjacent pixels P. For example, the first interval (or pixel pitch) D1 may be the shortest distance (or shortest length) between the center portions of the two adjacent pixels P.

[0062] Each of the plurality of pixels P according to the embodiment may include a circuit layer including a pixel circuit implemented in a pixel region on the substrate 100, and a light-emitting device layer provided at the circuit layer and coupled to the pixel circuit. The pixel circuit outputs a data current corresponding to the data signal in response to a data signal and a scan signal supplied from a pixel drive line provided in the pixel region. The light-emitting device layer may include a self-luminous device that emits light by the data current supplied from the pixel circuit. The pixel drive line, the pixel circuit, and the light-emitting device layer will be described below.

[0063] The plurality of pixels P may be divided (or classified) into outermost pixels Po and inner pixels (or intra-pixels) Pi.

[0064] The outermost pixel Po may be a pixel disposed closest to the outer surface OS of the substrate 100 of the plurality of pixels P.

[0065] The second interval D2 between the center portion of each outermost pixel Po and the outer surface OS of the substrate 100 may be half or less than the first interval D1. For example, the second interval D2 may be the distance (or length) between the center portion of the outermost pixel area PAo and the outer surface OS of the substrate 100. For example, the second interval D2 may be the shortest distance (or shortest length) between the center portion of the outermost pixel area PAo and the outer surface OS of the substrate 100.

[0066] When the second interval D2 is greater than half the first interval D1, the substrate 100 may have a size that is larger than the display area AA by half the first interval D1 and the difference area between the second interval D2, and therefore, the area between the end of the outermost pixel Po and the outer surface OS of the substrate 100 may be configured as a non-display area surrounding all the display areas AA. For example, when the second interval D2 is greater than half the first interval D1, the substrate 100 may necessarily include a frame area based on the non-display area surrounding all the display areas AA. On the other hand, when the second interval D2 is half the first interval D1 or less, the end of each outermost pixel Po may be aligned with (or set to) the outer surface OS of the substrate 100, or the end of the display area AA may be aligned with (or set to) the outer surface OS of the substrate 100, and therefore, the display area AA may be implemented (or set) on the entire front surface of the substrate 100.

[0067] The internal pixel Pi may be a pixel other than the outermost pixel Po among the plurality of pixels P, or may be a pixel surrounded by the outermost pixel Po among the plurality of pixels P. The internal pixel (or second pixel) Pi may be implemented to have a different configuration or structure from the outermost pixel (or first pixel) Po.

[0068] The dam 104 may be implemented at the peripheral portion of the substrate 100, or may be implemented at the peripheral portion of each outermost pixel Po provided in the display area AA. For example, the dam 104 may be provided to have a closed loop line shape (or a closed loop shape) between the center portion of each outermost pixel Po and the outer surface OS of the substrate 100. Therefore, the outermost pixel Po may include the dam 104 and, therefore, may be implemented in a structure or configuration different from that of the inner pixel Pi that does not include the dam 104.

[0069] The dam 104 according to an embodiment of the present disclosure can prevent the diffusion or overflow of the organic encapsulation layer of the encapsulation layer above the light-emitting device layer at the peripheral portion of each outermost pixel Po. In addition, the dam 104 can isolate (or disconnect) at least some layers of the light-emitting device layer at the peripheral portion of each outermost pixel Po, thereby preventing or minimizing the reduction in reliability of the light-emitting device layer caused by lateral penetration of water (or water vapor). The dam 104 may include a function of physically isolating at least some layers of the light-emitting device layer at the peripheral portion of the substrate 100 or the peripheral portion of each outermost pixel Po, a function of preventing the diffusion or overflow of the organic encapsulation layer, and a function of preventing water (or water vapor) from penetrating in the lateral direction of the substrate 100.

[0070] The light-emitting display device (or display panel) 10 according to an embodiment of the present disclosure may further include a groove line GRV.

[0071] The groove line GRV may be provided in a groove region (or trench region) defined at an inner region of the dam 104. According to an embodiment, the groove line GRV may be provided on a side of the planarization layer 102 (see FIG. Figure 8 ) and the dam 104 have a closed loop shape. For example, the groove line GRV can be formed or implemented by removing all elements such as the structure and / or stepped portion provided at the groove region provided in the inner region of the dam 104. For example, the groove line GRV can be implemented to expose the circuit layer provided between the side surface of the planarization layer 102 and the dam 104. In addition, the groove line GRV can be implemented to isolate at least some layers of the light emitting device layer provided in the inner region of the dam 104.

[0072] The light-emitting display device (or display panel) 10 according to an embodiment of the present disclosure may further include a blocking structure 105 .

[0073] The blocking structure 105 may be implemented at the peripheral portion of the substrate 100, or may be implemented at the peripheral portion of each outermost pixel Po provided in the display area AA. For example, the blocking structure 105 may be provided at the peripheral portion of each outermost pixel Po to have a closed loop line shape (or closed loop shape) between the outer surface OS of the substrate 100 and the dam 104. For example, the blocking structure 105 may be provided at the peripheral portion of each outermost pixel Po to surround the dam 104. Accordingly, the outermost pixel Po may include the blocking structure 105 and, therefore, may be implemented to have a structure or configuration different from that of the inner pixel Pi that does not include the blocking structure 105.

[0074] The blocking structure 105 according to an embodiment of the present disclosure can isolate (or disconnect) the light-emitting device layer at the peripheral portion of each outermost pixel Po to block the lateral water penetration path, thereby preventing or minimizing the reliability reduction of the light-emitting device layer caused by lateral penetration of water (or water vapor).

[0075] The barrier structure 105 according to an embodiment of the present disclosure may include a plurality of barrier patterns or at least two barrier patterns arranged in parallel to each other to have a closed loop line shape (closed loop shape) surrounding the dam 104. For example, the barrier structure 105 may include first to third barrier patterns arranged in parallel to each other to have a closed loop line shape.

[0076] Each of the plurality of blocking patterns according to an embodiment of the present disclosure may include an undercut structure for isolating (or disconnecting) a light-emitting device layer. For example, each of the plurality of blocking patterns may include an undercut region implemented by an eaves structure. Accordingly, at least some layers of the light-emitting device layer may be physically isolated (or disconnected) by the undercut region of each of the plurality of blocking patterns.

[0077] The light-emitting display device (or display panel) 10 according to an embodiment of the present disclosure may further include a pad part 110 .

[0078] The pad part 110 may be a first pad part or a front pad part. The pad part 110 may include a plurality of first pads that receive a data signal, a gate control signal, a pixel driving power, a reference voltage, a pixel common voltage, or the like from a driving circuit part.

[0079] The pad component 110 may be included in the outermost pixel Po at the first peripheral portion of the first surface of the first substrate 100, which is arranged parallel to the first direction X. That is, the outermost pixel Po arranged at the first peripheral portion of the first substrate 100 may include at least one of the plurality of first pads. Therefore, the plurality of first pads may be provided or included in the display area AA, and therefore, the non-display area (or frame area) based on the pad component 110 may not be formed or may not be on the first substrate 100. Therefore, the outermost pixel (or first pixel) Po may include the pad component 110, and therefore, may be implemented to have a different configuration or structure from the inner pixel (or second pixel) Pi that does not include the pad component 110.

[0080] For example, when the pad member 110 is not provided within the outermost pixel Po but is provided between the outermost pixel Po and the outer surface OS of the first substrate 100, the substrate 100 may include a non-display area (or non-display portion) corresponding to the area where the pad member 110 is provided, and due to the non-display area, the second interval D2 between the outermost pixel Po and the outer surface OS of the substrate 100 may be greater than half of the first interval D1, and not all of the substrate 100 may be implemented as the display area AA, and a separate frame (or separate structure) for covering the non-display area may be required. On the other hand, the pad member 110 according to an embodiment of the present disclosure may be provided between the outermost pixel Po and the outer surface OS of the substrate 100 to be included within the outermost pixel Po, and therefore, the non-display area (or frame area) based on the pad member 110 may not be formed or may not be between the outermost pixel Po and the outer surface OS of the substrate 100.

[0081] The pad part 110 according to an embodiment may include a first pixel driving power pad, a first data pad, a first reference voltage pad, a first gate pad, and a first pixel common voltage pad, but embodiments of the present disclosure are not limited thereto.

[0082] The light-emitting display device (or display panel) 10 according to an embodiment of the present disclosure may further include a gate driving circuit 150 .

[0083] The gate driving circuit 150 may be disposed in the display area AA to supply scan signals (or gate signals) to the pixels P disposed on the substrate 100. The gate driving circuit 150 may simultaneously supply scan signals to the pixels P disposed in a horizontal line parallel to the first direction X. For example, the gate driving circuit 150 may supply at least one scan signal to the pixels P disposed in one horizontal line through at least one gate line.

[0084] The gate driving circuit 150 according to an embodiment of the present disclosure may be implemented with a shift register including a plurality of stage circuit units. That is, the display device according to an embodiment of the present disclosure may include a shift register provided in the display area AA of the substrate 100 to supply scan signals to the pixels P.

[0085] Each of the multiple stages may include a plurality of branch circuits arranged to be spaced apart from each other in each horizontal line of the substrate 100 in the first direction X. Each of the multiple branch circuits may include at least one thin film transistor (TFT) (or branch TFT) and may be disposed between two adjacent pixels in one or more pixels P (or display area) in one horizontal line in the first direction X. Each of the multiple stage circuits may generate a scan signal by driving the multiple branch circuits based on a gate control signal supplied through a gate control line disposed to be spaced apart from each other between the multiple pixels P in the display area AA, and may supply the scan signal to the pixels P arranged in the corresponding horizontal line.

[0086] Figure 2A It is a diagram Figure 1 A diagram of a pixel according to an embodiment of the present disclosure is shown in FIG. Figure 2B It is a diagram Figure 1 FIG. 1 is a diagram of a pixel according to another embodiment of the present disclosure, Figure 2C It is a diagram Figure 1 FIG. 1 is a diagram of a pixel according to another embodiment of the present disclosure.

[0087] Reference Figure 1 and Figure 2A , one pixel (or unit pixel) P according to an embodiment of the present disclosure may include first to fourth sub-pixels SP1 to SP4.

[0088] Subpixel SP1 can be set in the subpixel area of ​​the pixel area PA, the second subpixel SP2 can be set in the second subpixel area of ​​the pixel area PA, the third subpixel SP3 can be set in the third subpixel area of ​​the pixel area PA, and the fourth subpixel SP4 can be set in the fourth subpixel area of ​​the pixel area PA.

[0089] The first to fourth sub-pixels SP1 to SP4 according to the embodiment may be arranged in a 2×2 form or a quad form. The first to fourth sub-pixels SP1 to SP4 may each include a plurality of emission areas EA1 to EA4 and a plurality of circuit areas CA1 to CA4. For example, the emission areas EA1 to EA4 may be referred to as opening areas, opening portions, or emission portions.

[0090] The light-emitting areas EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a uniform quadrilateral structure to have a square shape of the same size (or the same area). According to an embodiment, the light-emitting areas EA1 to EA4 having the uniform quadrilateral structure may each be arranged close to the center portion CP of the pixel P within the corresponding sub-pixel region to have a size smaller than each of the four equally divided regions of the pixel P, or may be arranged to be concentrated at the center portion CP of the pixel P. According to another embodiment, the light-emitting areas EA1 to EA4 having the uniform quadrilateral structure may each be arranged at the center portion of the corresponding sub-pixel region to have a size smaller than each of the four equally divided regions of the pixel P.

[0091] Reference Figure 1 and Figure 2B According to another embodiment, the first to fourth sub-pixels SP1 to SP4 may each have a non-uniform square structure with different sizes. For example, the emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may each have a non-uniform square structure with different sizes.

[0092] The size of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quadrilateral structure can be set based on resolution, luminous efficiency, or image quality. According to another embodiment, when the emission areas EA1 to EA4 have a non-uniform quadrilateral structure, among the emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the emission area EA4 of the fourth sub-pixel SP4 may have the smallest size, while the emission area EA3 of the third sub-pixel SP3 may have the largest size. For example, the emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quadrilateral structure can be arranged to be concentrated around (or near) the center portion CP of the pixel P.

[0093] Reference Figure 1 and Figure 2C According to another embodiment, the first to fourth sub-pixels SP1 to SP4 may each have a 1×4 form or a uniform stripe structure. For example, the emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may have a 1×4 form or a uniform stripe structure.

[0094] The emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 having the uniform stripe structure may each have a rectangular shape including short sides parallel to the first direction X and long sides parallel to the second direction Y.

[0095] According to an embodiment, the light emitting areas EA1 to EA4 having a uniform stripe structure may each be arranged close to the center portion CP of the pixel P within the corresponding sub-pixel area to have a size smaller than each of the four equally divided areas of the pixel P, or may be arranged to be concentrated in the center portion of the pixel P.

[0096] According to another embodiment, each of the light emitting areas EA1 to EA4 having the uniform stripe structure may be disposed at the center portion CP of the corresponding sub-pixel area to have a size smaller than each of the four equally divided areas of the pixel P.

[0097] According to another embodiment, each of the light emitting areas EA1 to EA4 having a uniform stripe structure may be disposed throughout the corresponding sub-pixel region to have the same size as each of the four equally divided regions of the pixel P.

[0098] Alternatively, the emission areas EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may each have a non-uniform stripe structure having different sizes. According to an embodiment, when the emission areas EA1 to EA4 have a non-uniform stripe structure, among the emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the emission area EA4 of the fourth sub-pixel SP4 may have the smallest size, and the emission area EA3 of the third sub-pixel SP3 may have the largest size, but embodiments of the present disclosure are not limited thereto.

[0099] Reference Figure 2A and Figure 2B , the circuit areas CA1 to CA4 of the first to fourth subpixels SP1 to SP4 can be arranged around (or near) the corresponding light-emitting areas of the light-emitting areas EA1 to EA4. The circuit areas CA1 to CA4 can each include pixel circuits and pixel drive lines to enable the corresponding subpixels of the first to fourth subpixels SP1 to SP4 to emit light. For example, the circuit areas CA1 to CA4 can be referred to as non-light-emitting areas, non-opening areas, non-light-emitting portions, non-opening portions, or peripheral portions.

[0100] Alternatively, to increase the aperture ratio of the subpixels SP1 to SP4 corresponding to the size of the emission areas EA1 to EA4 or to reduce the pixel pitch D1 as the resolution of the pixel P becomes higher, the emission areas EA1 to EA4 of the first to fourth subpixels SP1 to SP4 may extend into the circuit areas CA1 to CA4 to overlap with some or all of the circuit areas CA1 to CA4. For example, because the emission areas EA1 to EA4 of the first to fourth subpixels SP1 to SP4 have a top-emission structure, each emission area EA1 to EA4 may be arranged to overlap with the corresponding circuit area CA1 to CA4. In this case, each emission area EA1 to EA4 may have a size that is greater than or equal to the size of the corresponding circuit area CA1 to CA4.

[0101] exist Figures 2A to 2C In the embodiment, the first sub-pixel SP1 can be implemented to emit light of a first color, the second sub-pixel SP2 can be implemented to emit light of a second color, the third sub-pixel SP3 can be implemented to emit light of a third color, and the fourth sub-pixel SP4 can be implemented to emit light of a fourth color. For example, the first to fourth colors can be different. As an embodiment, the first color can be red, the second color can be blue, the third color can be white, and the fourth color can be green. As another embodiment, some of the first to fourth colors can be the same. For example, the first color can be red, the second color can be a first green, the third color can be a second green, and the fourth color can be blue.

[0102] Alternatively, the white sub-pixels implemented to emit white light from the first to fourth sub-pixels SP1 to SP4 having the uniform stripe structure or the non-uniform stripe structure may be omitted.

[0103] Figure 3 yes Figure 1 An enlarged view of area "A" is shown in FIG. Figure 4 It is a diagram Figure 1 and Figure 3 The equivalent circuit diagram of a sub-pixel is shown in FIG.

[0104] Reference Figure 1 、 Figure 3 ,and Figure 4 , the substrate 100 according to an embodiment of the present disclosure may include pixel driving power lines DL, GL, PL, CVL, RL, and GCL, a plurality of pixels P, a common electrode CE, a plurality of common electrode connection portions CECP, a dam 104, a blocking structure 105, and a pad part 110.

[0105] The pixel driving power lines DL, GL, PL, CVL, RL, and GCL may include a plurality of data lines DL, a plurality of gate lines GL, a plurality of pixel driving power lines PL, a plurality of pixel common voltage lines CVL, a plurality of reference voltage lines RL, and a gate control line GCL.

[0106] The plurality of data lines DL may extend long in the second direction Y and may be arranged at predetermined intervals apart from each other along the first direction X in the display area AA of the substrate 100. For example, among the plurality of data lines DL, the odd-numbered data lines DLo may be arranged at the first peripheral portion of each of the plurality of pixel areas PA arranged along the second direction Y on the substrate 100, and the even-numbered data lines DLe may be arranged at the second peripheral portion of each of the plurality of pixel areas PA arranged along the second direction Y on the substrate 100, but embodiments of the present disclosure are not limited thereto.

[0107] The plurality of gate lines GL may extend long in the first direction X and may be arranged at predetermined intervals in the display area AA of the substrate 100 along the second direction Y. For example, odd-numbered gate lines GLo among the plurality of gate lines GL may be arranged at the third peripheral portion of each of the plurality of pixel areas PA arranged along the first direction X on the substrate 100. Even-numbered gate lines GLe among the plurality of gate lines GL may be arranged at the fourth peripheral portion of each of the plurality of pixel areas PA arranged along the first direction X on the substrate 100, but embodiments of the present disclosure are not limited thereto.

[0108] The plurality of pixel driving power lines PL may extend long in the second direction Y and may be arranged along the first direction X to be spaced apart from each other by a predetermined interval in the display area AA of the substrate 100. For example, among the plurality of pixel driving power lines PL, odd-numbered pixel driving power lines PL may be arranged at a first peripheral portion of the odd-numbered display area PA with respect to the first direction X, and even-numbered pixel driving power lines PL may be arranged at a second peripheral portion of the even-numbered pixel area PA with respect to the first direction X, but embodiments of the present disclosure are not limited thereto.

[0109] Two adjacent pixel driving power lines PL among the plurality of pixel driving power lines PL may be coupled to a plurality of power sharing lines PSL provided in each sub-pixel PA arranged in the second direction Y. For example, the plurality of pixel driving power lines PL may be electrically connected to each other through the plurality of power sharing lines PSL, and therefore, may have a ladder structure or a grid structure. The plurality of pixel driving power lines PL may have a ladder structure or a grid structure, and therefore, may prevent or reduce (in some embodiments, minimize) the voltage drop (IR drop) of the pixel driving power caused by the line resistance of each of the plurality of pixel driving power lines PL. Accordingly, the light-emitting display device according to an embodiment of the present disclosure may prevent or reduce (in some embodiments, minimize) image quality degradation caused by deviation of the pixel driving power supplied to each pixel P arranged at the display area AA.

[0110] Each of the plurality of power share lines PSL may be branched from an adjacent pixel driving power line PL parallel to the first direction X and may be disposed in a middle region of each pixel area PA, but embodiments of the present disclosure are not limited thereto.

[0111] The plurality of pixel common voltage lines CVL may extend long in the second direction Y and may be spaced apart from each other by a predetermined interval in the display area AA of the substrate 100 along the first direction X. For example, each of the plurality of pixel common voltage lines CVL may be disposed at a first peripheral portion of an even-numbered pixel area PA with respect to the first direction X.

[0112] The plurality of reference voltage lines RL may extend long in the second direction Y and may be disposed at predetermined intervals in the display area AA of the substrate 100 in the first direction X. Each of the plurality of reference voltage lines RL may be disposed in a central region of each pixel area PA arranged in the second direction Y.

[0113] Each of the plurality of reference voltage lines RL may be shared by two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) in each pixel area PA in the first direction X. Accordingly, in some embodiments, each of the plurality of reference voltage lines RL may include a reference branch line RDL. The reference branch line RDL may branch (protrude) to two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) in each pixel area PA in the first direction X and may be electrically coupled to the two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)).

[0114] The plurality of gate control lines GCL may extend long in the second direction Y and may be disposed at predetermined intervals apart from each other in the display area AA of the substrate 100 in the first direction X. For example, each of the plurality of gate control lines GCL may be disposed between the plurality of pixel areas PA or at a boundary area between two adjacent pixel areas PA with respect to the first direction X.

[0115] Each of the plurality of pixels P may include at least three sub-pixels. For example, each of the plurality of pixels P may include first to fourth sub-pixels SP1 to SP4.

[0116] Each of the first to fourth sub-pixels SP1 to SP4 may include a pixel circuit PC and a light emitting device layer.

[0117] The pixel circuit PC according to an embodiment may be provided in the circuit area of ​​the pixel area PA and may be coupled to the adjacent gate line GLo or GLe, the adjacent data line DLo or DLe, and the pixel driving power line PL. For example, the pixel circuit PC provided in the sub-pixel SP1 may be coupled to the odd-numbered data line DLo and the odd-numbered gate line GLo, the pixel circuit PC provided in the second sub-pixel SP2 may be coupled to the even-numbered data line DLe and the even-numbered gate line GLo, the pixel circuit PC provided in the third sub-pixel SP3 may be coupled to the odd-numbered data line DLo and the even-numbered gate line GLe, and the pixel circuit PC provided in the fourth sub-pixel SP4 may be coupled to the even-numbered data line DLe and the even-numbered gate line GLe.

[0118] The pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can sample the data signal supplied from the corresponding data line DLo or DLe in response to the scan signal supplied from the corresponding gate line GLo or GLe, and can control the current flowing from the pixel driving power line PL to the light emitting device layer based on the sampled data signal.

[0119] The pixel circuit PC according to an embodiment may include a first switching thin film transistor Tsw1, a second switching thin film transistor Tsw2, a driving thin film transistor Tdr, and a storage capacitor Cst, but embodiments of the present disclosure are not limited thereto. In the following description, a thin film transistor may be referred to as a TFT.

[0120] The first switch TWT Tsw1 may include a gate coupled to the corresponding gate line GL (GLo or GLe), a first source / drain coupled to the corresponding data line DL (DLo or DLe), and a second source / drain coupled to the gate node n1 of the driving TFT Tdr. The first switch TFT Tsw1 may be turned on by a scan signal supplied through the corresponding gate line GL (GLo or GLe) and may transmit a data signal supplied through the corresponding data line DL (DLo or DLe) to the gate node n1 of the driving TFT Tdr.

[0121] The second switch TWT Tsw2 may include a gate coupled to the corresponding gate line GL (GLo or GLe), a first source / drain coupled to the source node n2 of the driving TFT Tdr, and a second source / drain coupled to the corresponding reference voltage line RL. The second switch TFT Tsw2 may be turned on by a scan signal supplied via the corresponding gate line GL (GLo or GLe) and may transmit a reference voltage supplied via the corresponding reference line RL to the source node n2 of the driving TFT Tdr. For example, the second switch TFT Tsw2 may be turned on simultaneously with the first switch TFT Tsw1.

[0122] A storage capacitor Cst may be formed between the gate node n1 and the source node n2 of the driving TFT Tdr. The storage capacitor Cst according to an embodiment may include a first capacitor coupled to the gate node n1 of the driving TFT Tdr, a second capacitor coupled to the source node n2 of the driving TFT Tdr, and a dielectric layer formed in an overlapping region between the first capacitor electrode and the second capacitor electrode. The storage capacitor Cst may be charged by a voltage difference between the gate node n1 and the source node n2 of the driving TFT Tdr and may then turn the driving TFT Tdr on or off based on the charged voltage.

[0123] The driving TFT Tdr may include a gate electrode (or gate node n1) commonly coupled to the second source / drain electrode of the first switching TFT Tsw1 and the first capacitor electrode of the storage capacitor Cst, a first source / drain electrode commonly coupled to the second switching TFT Tsw2, the second capacitor electrode of the storage capacitor Cst, and a first source / drain electrode (or source node n2) of the pixel electrode PE of the light-emitting device layer, and a second source / drain electrode (or drain node) coupled to the corresponding pixel driving power line PL. The driving TFT Tdr may be turned on based on the voltage of the storage capacitor Cst and may control the amount of current flowing from the pixel driving power line PL to the light-emitting device layer.

[0124] The light emitting device layer may be provided in the light emitting area EA of the pixel area PA and electrically coupled to the pixel circuit PC. The light emitting device layer according to an embodiment may include a pixel electrode PE electrically coupled to the pixel circuit PC, a common electrode CE electrically coupled to the pixel common voltage line CVL, and a self-luminous device ED interposed between the pixel electrode PE and the common electrode CE.

[0125] Each of the plurality of common electrode connection portions CECP may be disposed between a plurality of pixels P that respectively overlap with a plurality of pixel common voltage lines CVL, and may electrically couple the common electrode CE to each of the plurality of pixel common voltage lines CVL. With respect to the second direction Y, each of the plurality of common electrode connection portions CECP according to an embodiment may be electrically coupled to each of the plurality of pixel common voltage lines CVL at a portion between the plurality of pixels P (or at a boundary between the plurality of pixels P), and may be electrically coupled to a portion of the common electrode CE, thereby electrically coupling the common electrode CE to each of the plurality of pixel common voltage lines CVL. For example, the common electrode CE may be coupled to each of the plurality of common electrode connection portions CECP via a side contact structure corresponding to an undercut structure.

[0126] Each of the plurality of common electrode connection portions CECP may be provided between the plurality of pixels P to electrically couple the common electrode CE to each of the plurality of pixel common voltage lines CVL. This prevents or reduces (in some embodiments, minimizes) a voltage drop (IR drop) in the pixel common voltage caused by the surface resistance of the common electrode CE. Accordingly, the light-emitting display device according to an embodiment of the present disclosure can prevent or reduce (in some embodiments, minimize) image quality degradation caused by a deviation in the pixel common voltage supplied to each pixel P arranged in the display area AA.

[0127] According to an embodiment of the present disclosure, each of the plurality of common electrode connection parts CECP may be formed together with a pixel electrode PE having at least a two-layer structure so as to be electrically connected to each of the plurality of pixel common voltage lines CVL. Each of the plurality of common electrode connection parts CECP may be coupled to the common electrode CE via a side contact structure having a “(”-shaped cross-sectional structure or a “<”-shaped cross-sectional structure. For example, when each of the plurality of common electrode connection parts CECP is formed by a first and a second metal layer, each of the plurality of common electrode connection parts CECP may include a side contact structure corresponding to an undercut structure or a tapered structure formed on the side of the first metal layer by the etching rate difference between the first metal layer and the second metal layer. For example, when each of the plurality of common electrode connection parts CECP is formed by a first to a third metal layer, each of the plurality of common electrode connection parts CECP may include a side contact structure corresponding to an undercut structure or a tapered structure formed at the side of the first metal layer and / or the second metal layer by the etching rate difference between the first and the second metal layer.

[0128] The dam 104, the groove line GRV, and the barrier structure 105 may each be provided or implemented at the outermost pixel Po or the peripheral portion of the substrate 100 to have a closed loop line shape (or closed loop shape). Figure 1 and therefore, their repeated descriptions are omitted.

[0129] The pad component 110 may be provided at a first peripheral portion of the first surface of the substrate 100 parallel to the first direction X. The pad component 110 may be provided at a third peripheral portion of each outermost pixel area PAo provided at the first peripheral portion of the substrate 100. An end portion of the pad component 110 may overlap or align with an end portion of each outermost pixel area PAo with respect to the second direction Y. Therefore, the pad component 110 may be included (or provided) in each outermost pixel area PAo provided at the first peripheral portion of the substrate 100, and therefore, a non-display area (or frame area) based on the first pad component 110 may not be formed or may not be in the substrate 100.

[0130] The pad part 110 may include a plurality of first pads arranged parallel to each other along the first direction X at a first peripheral portion of the substrate 100. The plurality of first pads may be divided (or classified) into a first data pad DP, a first gate pad GP, a first pixel driving power pad PPP, a first reference voltage pad RVP, and a first pixel common voltage pad CVP.

[0131] Each of the first data pads DP may be coupled individually (or in a one-to-one relationship) to one side of each of the plurality of data lines D1o and DLe provided at the substrate 100.

[0132] Each of the first gate pads GP may be individually (or in a one-to-one relationship) coupled to one side of each gate control line GCL disposed at the first substrate 100. The first gate pads GP according to an embodiment may be divided (or classified) into a first start signal pad, a plurality of first shift clock pads, a plurality of first carry clock pads, at least one first gate driving power pad, and at least one first gate common power pad.

[0133] Each of the first pixel driving voltage pads PPP may be individually (or in a one-to-one relationship) coupled to one side end of each of the plurality of pixel driving power lines PL disposed on the substrate 100. Each of the first reference voltage pads RVP may be individually (or in a one-to-one relationship) coupled to one side end of each of the plurality of reference voltage lines RL disposed on the substrate 100. Each of the first pixel common voltage pads CVP may be individually (or in a one-to-one relationship) coupled to one side end of each of the plurality of pixel common voltage lines CVL disposed on the substrate 100.

[0134] The pad part 110 according to an embodiment may include a plurality of pad groups PG arranged in the order of a first pixel driving power pad PPP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, a first gate pad GP, a first pixel common voltage pad CVP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, and a first pixel driving power pad PPP along the first direction X. Each of the plurality of pad groups PG may be coupled to two adjacent pixels P disposed along the first direction X. For example, the plurality of pad groups PG may include a first pad group PG1 and a second pad group PG2, the first pad group PG1 including a first pixel driving power pad PPP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, and a first gate pad GP that are consecutively arranged in odd-numbered pixel areas PA along the first direction X, and the second pad group PG2 including a first pixel common voltage pad CVP, a first data pad DP, a first reference voltage pad RVP, a first data pad DP, and a first pixel driving power pad PPP that are arranged in even-numbered pixel areas PA along the first direction X.

[0135] The substrate 100 according to the embodiment may further include a plurality of secondary voltage lines SVL and a plurality of secondary line connection parts SLCP. For example, the secondary voltage lines may be referred to as additional voltage lines or auxiliary voltage lines, or the like.

[0136] Each of the plurality of secondary voltage lines SVL may extend long along the second direction Y and may be disposed adjacent to a corresponding pixel common voltage line CVL of the plurality of pixel common voltage lines CVL. Each of the plurality of secondary voltage lines SVL may be electrically coupled to an adjacent pixel common voltage line CVL without being electrically coupled to the pixel common voltage pad CVP, and may be supplied with a pixel common voltage through the adjacent pixel common voltage line CVL. Accordingly, in some embodiments, the substrate 100 according to an embodiment of the present disclosure may further include a plurality of line connection patterns LCP that electrically couple the pixel common voltage lines CVL and the secondary voltage lines SVL to each other.

[0137] Each of the plurality of line connection patterns LCP may be disposed on the substrate 100 such that the line connection pattern LCP and adjacent pixel common voltage lines CVL and secondary voltage lines SVL intersect with each other, and the pixel common voltage lines CVL and the secondary voltage lines SVL may be electrically coupled to each other using a jumper structure. For example, one side of each of the plurality of line connection patterns LCP may be electrically coupled to a portion of the secondary voltage line SVL via a first line contact hole formed in the insulating layer above the secondary voltage line SVL, and the other side of each of the plurality of line connection patterns LCP may be electrically coupled to a portion of the pixel common voltage line CVL via a second line contact hole formed in the insulating layer above the pixel common voltage line CVL.

[0138] Each of the multiple secondary line connection portions SLCP can electrically couple the common electrode CE with the multiple secondary voltage lines SVL at the multiple pixels P that each overlap with the multiple secondary voltage lines SVL. With respect to the second direction Y, each of the multiple secondary line connection portions SLCP according to the embodiment can be electrically coupled to each of the multiple secondary voltage lines SVL at a portion between the multiple pixels P or a boundary area between the multiple pixels P, and can be electrically coupled to a portion of the common electrode CE, and therefore, the common electrode CE can be electrically coupled to each of the multiple secondary voltage lines SVL. Therefore, the common electrode CE can be additionally coupled to each of the multiple secondary voltage lines SVL through the secondary line connection portion SLCP. Accordingly, the light-emitting display device according to the embodiment of the present disclosure can prevent or reduce (in some embodiments, minimize) image quality degradation caused by the deviation of the pixel common voltage supplied to each pixel P arranged in the display area AA. In addition, in the light-emitting display device according to an embodiment of the present disclosure, although a pixel common voltage pad CVP coupled to each of the multiple secondary voltage lines SVL is not additionally provided (or formed), the pixel common voltage can be supplied to each of the multiple secondary voltage lines SVL through the pixel common voltage line CVL and each of the multiple line connection portions LCP.

[0139] The substrate 100 according to an embodiment of the present disclosure may further include an encapsulation layer.

[0140] The encapsulation layer may be implemented to surround the light-emitting device layer. The encapsulation layer according to the embodiment may include a first inorganic encapsulation layer (or first encapsulation layer) disposed over the light-emitting device layer, the dam 104, and the barrier structure 105, a second inorganic encapsulation layer (or third encapsulation layer) disposed over the first inorganic encapsulation layer, and an organic encapsulation layer (or second encapsulation layer) disposed over the light-emitting device layer defined by the dam 104 and interposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0141] The organic encapsulation layer may cover the top surface (or upper surface) of the light-emitting device layer and flow toward the end of the substrate 100, and the diffusion (or flow) of the organic encapsulation layer may be blocked by the dam 104. The dam 104 may further define or limit the deposition area (or encapsulation area) of the organic encapsulation layer, and may block or prevent the diffusion or overflow of the organic encapsulation layer.

[0142] Figure 5 It is a diagram Figure 1 and Figure 3 Schematic diagram of the gate drive circuit shown in .

[0143] Reference Figure 1 、 Figure 3 ,and Figure 5, a gate driving circuit 150 according to another embodiment of the present disclosure may be implemented (or embedded) in the display area AA of the substrate 100. The gate driving circuit 150 may generate a scan signal based on a gate control signal supplied through the pad part 110 and the gate control line GCL, and sequentially supply the scan signal to the plurality of gate lines GL.

[0144] The gate control lines GCL may include a start signal line, a plurality of shift clock lines, at least one gate driving voltage line, and at least one gate common voltage line. The gate control lines GCL may extend long in the second direction Y and may be arranged along the first direction X at predetermined intervals in the display area AA of the substrate 100. For example, the gate control lines GCL may be arranged between at least one or more pixels P along the first direction.

[0145] The gate driving circuit 150 according to an embodiment of the present disclosure may be implemented with a shift register including a plurality of stage circuit parts 1501 to 150m, where m is an integer of 2 or greater.

[0146] Each of the plurality of stage circuit portions 1501 to 150m may be individually disposed in each horizontal line of the first surface of the substrate 100 along the first direction X, and may be independently coupled to one another along the second direction Y. Each of the plurality of stage circuit portions 1501 to 150m may generate a scan signal in a predetermined order in response to a gate control signal supplied through the pad part 110 and the gate control line GCL, and may supply the scan signal to the corresponding gate line GL.

[0147] Each of the plurality of stage circuit parts 1501 to 150 m according to the embodiment may include a plurality of branch circuits 1511 to 151 n and a branch network 153 .

[0148] The plurality of branch circuits 1511 to 151n may be selectively coupled to a conductive line of the gate control line GCL through the branch network 153, and may be electrically coupled to each other through the branch network 153. Each of the plurality of branch circuits 1511 to 151n may generate a scan signal based on a gate control signal supplied through a voltage of the gate control line GCL and the branch network 153, and may supply the scan signal to a corresponding gate line GL.

[0149] Each of the plurality of branch circuits 1511 to 151n may include at least one TFT (or branch TFT) configuring one of the stage circuit sections 1501 to 150m. Any one of the plurality of branch circuits 1511 to 151n may include a pull-up TFT coupled to the gate line GL. Another one of the plurality of branch circuits 1511 to 151n may include a pull-down TFT coupled to the gate line GL.

[0150] Each of the plurality of branch circuits 1511 to 151n according to an embodiment of the present disclosure may be provided in a circuit region between two adjacent pixels P in each horizontal line of the substrate 100 or in a circuit region between at least two adjacent pixels P, but the embodiments of the present disclosure are not limited thereto. For example, each of the plurality of branch circuits 1511 to 151n may be provided in a circuit region (or boundary region) between at least one or more adjacent pixels P, depending on the number of TFTs configuring each of the stage circuit portions 1501 to 150m and the number of pixels P provided in one horizontal line.

[0151] The branch network 153 may be provided at each horizontal line of the substrate 100 and may electrically couple the plurality of branch circuits 1511 to 151n to one another. The branch network 153 according to an embodiment of the present disclosure may include a plurality of control node lines and a plurality of network lines.

[0152] A plurality of control node lines may be provided at each horizontal line of the substrate 100 and may be selectively coupled to a plurality of branch circuits 1511 to 151n in one horizontal line. For example, a plurality of control node lines may be provided at the upper edge region (or lower edge region) of pixels arranged at each horizontal line of the substrate 100.

[0153] The plurality of network lines may be selectively coupled to the gate control line GCL provided on the substrate 100 and may be selectively coupled to the plurality of branch circuits 1511 to 151n. For example, the plurality of network lines may transmit gate control signals supplied from the gate control line GCL to the corresponding branch circuits 1511 to 151n and may transmit signals between the plurality of branch circuits 1511 to 151n.

[0154] As described above, according to an embodiment of the present disclosure, since the gate driver circuit 150 is disposed in the display area AA of the substrate 100, the second interval D2 between the center portion of the outermost pixel area PAo and the outer surface OS of the substrate 100 may be less than or equal to half of the first interval (or pixel pitch) D1 between adjacent pixel areas PA. For example, when the gate driver circuit 150 is not disposed in the display area AA of the substrate 100 but is disposed at the peripheral portion of the substrate 100, the second interval D2 may not be less than or equal to half of the first interval D1. Accordingly, in the light-emitting display device according to an embodiment of the present disclosure, the gate driver circuit 150 may be disposed in the display area AA of the substrate 100, and therefore, the second interval D2 may be implemented to be less than or equal to half of the first interval D1, and furthermore, the display device may be implemented to have an air frame structure having a return-to-zero frame or in which no frame area is provided.

[0155] Figure 6 is a diagram illustrating a rear surface of a light-emitting display device according to an embodiment of the present disclosure.

[0156] Reference Figure 1 、 Figure 3 ,and Figure 6 The light-emitting display device according to an embodiment of the present disclosure may further include a second pad part 210 provided at the rear surface (or back surface) 100 b of the substrate 100 .

[0157] The second pad part 210 may be provided at ab one peripheral portion (or first rear peripheral portion) of the rear surface 100b of the substrate 100 overlapping with the pad part 110 provided at the front surface 100a of the substrate 100. Figure 6 In the following description, the pad part 110 disposed at the front surface 100 a of the substrate 100 may be referred to as a first pad part 110 .

[0158] The second pad part 210 may include a plurality of second pads (or routing pads) arranged at certain intervals along the first direction X so as to overlap the pads of the first pad part 110, respectively. Figure 6 In the following description, the pads of the pad part 110 may be referred to as first pads.

[0159] The plurality of second pads may be divided (classified) into a second pixel driving power pad overlapping with each of the first pixel driving power pads PPP of the first pad part 110, a second data pad overlapping with each of the first data pads DP of the first pad part 110, a second reference voltage pad overlapping with each of the first reference voltage pads RVP of the first pad part 110, a second gate pad overlapping with each of the first gate pads GP of the first pad part 110, and a second pixel common voltage pad overlapping with each of the first pixel common voltage pads CVP of the first pad part 110.

[0160] The light-emitting display device according to an embodiment of the present disclosure may further include at least one third pad part 230 and a link line portion 250 disposed over the rear surface 100 b of the substrate 100 .

[0161] At least one third pad component 230 (or input pad component) may be provided at the rear surface 100b of the substrate 100. For example, the at least one third pad component 230 may be provided at a middle portion adjacent to the first peripheral portion of the rear surface 100b of the substrate 100. The at least one third pad component 230 according to an embodiment of the present disclosure may include a plurality of third pads (or input pads) spaced apart from each other at specific intervals. For example, the at least one third pad component 230 may include a third pixel driving power pad, a third data pad, a third reference voltage pad, a third gate pad, and a third pixel common voltage pad.

[0162] The link line portion 250 may include a plurality of link lines disposed between the second pad part 210 and the at least one third pad part 230 .

[0163] According to an embodiment of the present disclosure, the link line portion 250 may include a plurality of pixel driving power link lines that individually (or in a one-to-one relationship) couple the second pixel driving power pad to the third pixel driving power pad, a plurality of data link lines that individually (or in a one-to-one relationship) couple the second data pad to the third data pad, a plurality of reference voltage link lines that individually (or in a one-to-one relationship) couple the second reference voltage pad to the third reference voltage pad, a plurality of gate link lines that individually (or in a one-to-one relationship) couple the second gate pad to the third gate pad, and a plurality of pixel common voltage link lines that individually (or in a one-to-one relationship) couple the second pixel common voltage pad to the third pixel common voltage pad.

[0164] Each of the plurality of pixel common voltage link lines may include a first common link line 251 and a second common link line 253. The first common link line 251 may be disposed between the second pad component 210 and the at least one third pad component 230 and may be commonly coupled to the plurality of second pixel common voltage pads. The second common link line 253 may be commonly coupled to the plurality of third pixel common voltage pads and may be electrically coupled to the first common link line 251. The second common link line 253 may be disposed on a different layer than the first common link line 251 and may be electrically coupled to the first common link line 251 through a via. The size of the second common link line 253 may gradually increase in a direction from the third pad component 230 to the peripheral portion of the substrate 100 to reduce (or minimize) the voltage drop of the pixel common voltage.

[0165] The light-emitting display device according to an embodiment of the present disclosure may further include a routing portion 400 provided at the outer surface OS of the substrate 100 .

[0166] The routing portion 400 may be disposed to surround the first pad part 110 , the outer surface OS, and the second pad part 210 of the substrate 100 .

[0167] The routing portion 400 according to an embodiment may include a plurality of routing lines 410. Each of the plurality of routing lines 410 may be arranged at specific intervals along the first direction X, may be formed to surround the first pad component 110, the outer surface OS, and the second pad component 210 of the substrate 100, and may be electrically coupled to each of the first pad of the first pad component 110 and the second pad of the second pad component 210 in a one-to-one relationship. According to an embodiment, each of the plurality of routing lines 410 may be formed by a printing process using a conductive paste. As another embodiment, each of the plurality of routing lines 410 may be formed by a transfer process of transferring a conductive paste pattern to a transfer pad made of a flexible material and transferring the conductive paste pattern transferred to the transfer pad to the routing portion 400. For example, the conductive paste may be Ag paste, but the embodiments of the present disclosure are not limited thereto.

[0168] The plurality of selection lines 410 according to an embodiment of the present disclosure may be divided (classified) into a plurality of pixel power selection lines 411 , a plurality of data selection lines 413 , a plurality of reference voltage selection lines 415 , a plurality of gate selection lines 417 , and a plurality of pixel common voltage selection lines 419 .

[0169] Multiple pixel power selection lines 411 can be formed to surround the first pad part 110, the outer surface OS, and the second pad part 210, and can be electrically coupled to the multiple first pixel driving power pads of the first pad part 110 and the multiple second pixel driving power pads of the second pad part 210 in a one-to-one relationship.

[0170] A plurality of data selection lines 413 may be formed to surround the first pad part 110 , the outer surface OS, and the second pad part 210 , and may be electrically coupled to the plurality of first data pads of the first pad part 110 and the plurality of second data pads of the second pad part 210 in a one-to-one relationship.

[0171] A plurality of reference voltage selection lines 415 may be formed to surround the first pad part 110 , the outer surface OS, and the second pad part 210 , and may be electrically coupled to the plurality of first reference voltage pads of the first pad part 110 and the plurality of second reference voltage pads of the second pad part 210 in a one-to-one relationship.

[0172] A plurality of data selection lines 417 may be formed to surround the first pad part 110 , the outer surface OS, and the second pad part 210 , and may be electrically coupled to the plurality of first gate pads of the first pad part 110 and the plurality of second gate pads of the second pad part 210 in a one-to-one relationship.

[0173] A plurality of pixel common voltage selection lines 419 may be formed to surround the first pad component 110, the outer surface OS, and the second pad component 210, and may be electrically coupled to the plurality of first pixel common voltage pads of the first pad component 110 and the plurality of second pixel common voltage pads of the second pad component 210 in a one-to-one relationship.

[0174] The display device or the routing portion 400 according to an embodiment of the present disclosure may further include an edge coating layer.

[0175] The edge coating may be implemented to cover the plurality of routing portions 400. The edge coating according to an embodiment may be implemented to cover the entire first peripheral portion and the first outer surface OS of the substrate 100 and the plurality of routing lines 410. The edge coating may prevent corrosion of each of the plurality of routing lines 410 comprising a metal material or electrical short circuits between the plurality of routing lines 410. In addition, the edge coating may prevent or reduce (in some embodiments, minimize) reflection of external light caused by the plurality of routing lines 410 and the first pad of the first pad component 110. The edge coating according to an embodiment may include a light-blocking material containing black ink. For example, the edge coating may be an edge protection layer or an edge insulation layer.

[0176] The light emitting display device according to an embodiment of the present disclosure may further include a driving circuit part 500 .

[0177] The driving circuit component 500 can drive (or cause to emit light) the pixels P provided on the first substrate 100 based on the digital video data and the timing synchronization signal supplied from the display driving system to allow the display area AA to display an image corresponding to the image data. The driving circuit component 500 can be coupled to at least one third pad component 230 provided on the rear surface 100b of the substrate 100, and can output data signals, gate control signals, and driving power for driving (or causing to emit light) the pixels P provided on the substrate 100 to the at least one third pad component 230.

[0178] The driving circuit part 500 according to the embodiment may include a flexible circuit film 510 , a driving integrated circuit (IC) 530 , a printed circuit board (PCB) 550 , a timing controller 570 , and a power circuit 590 .

[0179] The flexible circuit film 510 may be coupled to at least one third pad part 230 disposed at the rear surface 100 b of the substrate 100 .

[0180] The driver IC 530 may be disposed on the flexible circuit film 510. The driver IC 530 may receive sub-pixel data and a data control signal provided from the timing controller 570, and convert the sub-pixel data into an analog data signal based on the data control signal and supply the analog data signal to the corresponding data line DL. The data signal may be supplied to the corresponding third data pad in the at least one third pad member 230 through the flexible circuit film 510.

[0181] The driver IC 530 can sense the characteristic values ​​of the driving TFTs set in the sub-pixels SP through multiple reference voltage lines RL (or pixel sensing lines) set on the substrate 100, generate sensing raw data corresponding to the sensing value for each sub-pixel, and provide the sensing raw data to the timing controller 570 for each sub-pixel.

[0182] The PCB 550 may be coupled to the other side peripheral portion of the flexible circuit film 510. The PCB 550 may transfer signals and power between elements of the driving circuit part 500.

[0183] The timing controller 570 may be mounted on the PCB 550 and may receive digital video data and timing synchronization signals provided from the display driving system through a user connector provided on the PCB 550. Alternatively, the timing controller 570 may not be mounted on the PCB 550 and may be implemented in the display driving system or may be mounted on a separate control board between the PCB 550 and the display driving system.

[0184] The timing controller 570 may align the digital video data based on the timing synchronization signal to generate a pixel arrangement structure matching that provided in the display area AA, and may provide the generated pixel data to the driving IC 530 .

[0185] The timing controller 570 may generate each of a data control signal and a gate control signal based on the timing synchronization signal, control the driving timing of the driver IC 530 based on the data control signal, and control the driving timing of the gate driving circuit 150 based on the gate control signal. For example, the timing synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a main clock (or dot clock).

[0186] The data control signal according to an embodiment of the present disclosure may include a source start pulse, a source shift clock, and a source output signal, or the like. The data control signal may be supplied to the driving IC 530 through the flexible circuit film 510 .

[0187] The gate control signal according to the embodiment may include a start signal (or gate start signal), a plurality of shift clocks, a forward drive signal, and a reverse drive signal. In this case, the plurality of shift clocks may include a plurality of scan clocks whose phases are sequentially shifted and a plurality of carry clocks whose phases are sequentially shifted. In addition, the gate control signal according to the embodiment may further include an external sensing line selection signal for sensing the characteristic value of the driving TFT provided in the sub-pixel SP, an external sensing reset signal, and an external sensing control signal. The gate control signal may be supplied to the gate drive circuit 150 via the flexible circuit film 510, at least one third pad component 230, the link line portion 250, the second pad component 210, the routing portion 400, the first pad component 110, and the gate control line GCL.

[0188] The timing controller 570 may drive each of the driver IC 530 and the gate driver circuit 150 based on an external sensing pattern during a predetermined external sensing period, generate compensation data for each subpixel based on the raw sensing data provided from the driver IC 530 to compensate for characteristic variations of the driving TFT of each subpixel, and modulate the pixel data of each subpixel based on the generated compensation data for each subpixel. For example, the timing controller 570 may drive each of the driver IC 530 and the gate driver circuit 150 based on the external sensing pattern during each external sensing period corresponding to a blank period (or a vertical blank period) of a vertical synchronization signal. For example, the external sensing pattern may be executed during a process of powering on the display device, a process of powering off the display device, a process of powering off the display device after being driven for a long period of time, and a blank period of a frame set in real time or periodically.

[0189] The timing controller 570 according to an embodiment may store the sensing raw data of each sub-pixel provided from the driver IC 530 in a storage circuit based on the external sensing mode. Furthermore, in the display mode, the timing controller 570 may correct the pixel data to be supplied to each sub-pixel based on the sensing raw data stored in the storage circuit, and may provide the corrected pixel data to the driver IC 530. Here, the raw data sensing each sub-pixel may include sequential change information about each of the driving TFT and the self-luminous device provided in the corresponding sub-pixel. Therefore, in the external sensing mode, the timing controller 570 may sense the characteristic value (e.g., threshold voltage or mobility) of the driving TFT provided in each sub-pixel, and based on this, may correct the pixel data to be supplied to each sub-pixel, thereby reducing (in some embodiments, minimizing) or preventing image quality degradation caused by deviations in the characteristic values ​​of the driving TFTs of the plurality of sub-pixels. The external sensing mode of the display device may be a technique known to those skilled in the art, and therefore, a detailed description thereof is omitted. For example, the display device according to an embodiment of the present disclosure may sense a characteristic value of a driving TFT provided in each subpixel P based on a sensing mode disclosed in Korean Patent Publication No. 10-2016-0093179, No. 10-2017-0054654, or No. 10-2018-0002099.

[0190] The power supply circuit 590 can be mounted on the PCB 550 and can generate various source voltages required to display an image on the pixel P using an externally supplied input power source, and then supply the generated source voltages to corresponding circuits. For example, the power supply circuit 590 can generate and output logic source voltages required to drive each of the timing controller 570 and the driver IC 530, multiple reference gamma voltages provided to the driver IC 530, and at least one gate drive power supply and at least one gate common power supply required to drive the gate driver circuit 150. In addition, the power supply circuit 590 can generate and output pixel drive power supplies and pixel common voltages, but embodiments of the present disclosure are not limited thereto. For example, the driver IC 530 can generate and output pixel drive power supplies and pixel common voltages based on multiple reference gamma voltages.

[0191] Figure 7 is a rear perspective view illustrating a light emitting display device according to another embodiment of the present disclosure, illustrating Figures 1 to 6 An embodiment in which a wiring substrate is additionally provided in the light-emitting display device shown in .

[0192] Reference Figure 7 A light-emitting display device according to another embodiment of the present disclosure may include a substrate 100 , a second substrate 200 , a coupling element 300 , and a routing portion 400 .

[0193] The substrate 100 may be referred to as a display substrate, a pixel array substrate, an upper substrate, a front substrate, and a base substrate. The substrate 100 may be a glass substrate, or may be a thin glass substrate or a plastic substrate that is bendable or flexible. Figure 7 In the following description, the substrate 100 may be referred to as a first substrate 100 .

[0194] The first substrate 100 may be Figures 1 to 6 The substrate 100 of the light-emitting display device shown in is substantially the same, and thus, like reference numerals refer to like elements, and their repeated descriptions may be omitted.

[0195] The second substrate 200 may be referred to as a wiring substrate, a line substrate, a link substrate, a lower substrate, a rear substrate, or a link glass. The second substrate 200 may be a glass substrate, or may be a thin glass substrate or a plastic substrate that is bendable or flexible. For example, the second substrate 200 may include the same material as the first substrate 100. The size of the second substrate 200 may be the same or substantially the same as that of the first substrate 100, but the embodiments of the present disclosure are not limited thereto, and the second substrate 200 may have a size smaller than that of the first substrate 100. For example, the second substrate 200 may be configured to have the same size as the first substrate 100 in order to maintain or ensure the hardness of the first substrate 100.

[0196] The second substrate 200 may include a second pad part 210, at least one third pad part 230, and a link line portion 250. In addition to the second pad part 210, at least one third pad part 230, and the link line portion 250 being provided at the rear surface (or back surface) 200b of the second substrate 200, the second pad part 210, at least one third pad part 230, and the link line portion 250 may each be connected to the rear surface (or back surface) 200b of the second substrate 200. Figure 6 The second pad part 210, the at least one third pad part 230, and the link line portion 250 shown in FIG. 1 are each substantially the same, and thus, like reference numerals refer to like elements, and their repeated descriptions may be omitted.

[0197] The second substrate 200 may be coupled (connected) to the second surface (or rear surface) of the first substrate 100 by using the coupling element 300. The coupling element 300 may be interposed between the first substrate 100 and the second substrate 200. Thus, the first substrate 100 and the second substrate 200 may be coupled relative to each other by the coupling element 300.

[0198] The routing portion 400 may be referred to as a side routing portion, a side wiring portion, a printed wiring portion, or a printed line portion. The routing portion 400 according to an embodiment may include a plurality of routing lines 410 provided at each of the first outer surface (or one surface) OS1a among the outer surface OS of the first substrate 100 and the first outer surface (or one surface) OS1b among the outer surface OS of the second substrate 200. In addition to the plurality of routing lines 410 being provided around the first pad component 110 and the first outer surface OS1a of the first substrate 100 and the second pad component 210 and the first outer surface OS1b of the second substrate 200, the routing portion 400 may be provided with Figure 6 The routing section 400 shown in FIG. 4 is substantially the same, and therefore, like reference numerals refer to like elements, and their repeated descriptions may be omitted.

[0199] The light emitting display device according to another embodiment of the present disclosure may further include a driving circuit part 500 .

[0200] The circuit component 500 may include a flexible circuit film 510, a driving integrated circuit (IC) 530, a printed circuit board (PCB) 550, a timing controller 570, and a power supply circuit 590. In addition to the flexible circuit film 510 being coupled to at least one third pad part 230 provided at the rear surface 200b of the second substrate 200, the driving circuit component 500 having such a configuration may be connected to Figure 6 The driving circuit component 500 shown in FIG. 5 is substantially the same, and therefore, like reference numerals refer to like elements, and their repeated descriptions may be omitted.

[0201] Figure 8 It is along Figure 7 The cross-sectional view taken along the straight line II' shown in FIG. Figure 9 yes Figure 8 An enlarged view of area "B" is shown in FIG. Figure 10 It is along Figure 7 The cross-sectional view is taken along the line II-II' shown in FIG.

[0202] Reference Figures 7 to 11 , a light-emitting display device according to an embodiment of the present disclosure may include a first substrate 100 , a second substrate 200 , a coupling element 300 , and a routing portion 400 .

[0203] The first substrate 100 according to an embodiment may include a circuit layer 101 , a passivation layer PAS, a planarization layer 102 , a light emitting device layer EDL, a bank BK, a dam 104 , a groove line GRV, and an encapsulation layer 106 , and may further include a barrier structure 105 .

[0204] The circuit layer 101 may be disposed over the first substrate 100. The circuit layer 101 may be referred to as a pixel array layer or a TFT array layer.

[0205] The circuit layer 101 according to an embodiment of the present disclosure may include a buffer layer 101 a and a circuit array layer 101 b .

[0206] The buffer layer 101a can prevent materials such as hydrogen included in the first substrate 100 from diffusing to the circuit array layer 101b during the high temperature process of the process of manufacturing the TFT. In addition, the buffer layer 101a can prevent external water or water vapor from penetrating into the light-emitting device layer EDL. According to the embodiment, the buffer layer 101a may include a single-layer structure containing one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx) or a stacked structure thereof, but the embodiments of the present disclosure are not limited thereto. For example, the buffer layer 101a may include a first buffer layer BL1 containing SiNx and disposed on the first substrate 100 and a second buffer layer BL2 containing SiOx and disposed on the first buffer layer BL1.

[0207] The circuit array layer 101 b may include a pixel circuit PC including a driving TFT Tr disposed at each of a plurality of display areas PA above the buffer layer 101 a .

[0208] The driving TFT Tr disposed at the circuit region of each pixel area PA may include an active layer ACT, a gate insulating layer GI, a gate GE, an interlayer insulating layer 101 c , a first source / drain electrode SD1 , and a second source / drain electrode SD2 .

[0209] An active layer ACT may be disposed above the buffer layer 101a in each pixel area PA. The active layer ACT may include a channel region overlapping the gate electrode GE, and first and second source / drain regions parallel to each other between adjacent channel regions. The active layer ACT may have electrical conductivity during conduction and, therefore, may directly couple lines in the display area AA or may serve as a bridge line of a skip structure that electrically couples lines disposed on different layers.

[0210] The gate insulating layer GI may be disposed at the channel region of the active layer ACT and may insulate the active layer ACT from the gate electrode GE.

[0211] The gate electrode GE may be disposed above the gate insulating layer GI and coupled to the gate line. The gate electrode GE may overlap with the channel region of the active layer ACT with the gate insulating layer GI therebetween.

[0212] An interlayer insulating layer 101c may be provided at the first substrate 100 to cover the gate GE and the active layer ACT. The interlayer insulating layer 101c may electrically insulate (or isolate) the gate GE from the source / drain electrodes SD1 and SD2. For example, the interlayer insulating layer 101c may be referred to as an insulating layer or a first insulating layer.

[0213] The first source / drain electrode SD1 may be disposed on the interlayer insulating layer 101c overlapping the first source / drain region of the active layer ACT, and may be electrically coupled to the first source / drain region of the active layer ACT via a first source / drain contact hole disposed in the interlayer insulating layer 101c. For example, the first source / drain electrode SD1 may be the source electrode of the driving TFT Tdr, and the first source / drain region of the active layer ACT may be the source region.

[0214] The second source / drain electrode SD2 may be disposed on the interlayer insulating layer 101 c overlapping the second source / drain region of the active layer ACT, and may be electrically coupled to the second source / drain region of the active layer ACT via a second source / drain contact hole disposed in the interlayer insulating layer 101 c. For example, the second source / drain electrode SD2 may be the drain electrode of the driving TFT Tdr, and the second source / drain region of the active layer ACT may be the drain region.

[0215] Each of the first and second switching TFTs Tsw1 and Tsw2 configuring the pixel circuit PC may be formed together with the driving TFT Tdr, and therefore, their repeated descriptions are omitted.

[0216] The circuit layer 101 according to an embodiment may further include a lower metal layer BML disposed between the first substrate 100 and the buffer layer 101 a .

[0217] The lower metal layer BML may further include a light blocking pattern (or light blocking layer) LSP disposed under (or below) the active layer ACT of each of the TFTs Tdr, Tsw1, and Tsw2 configuring the pixel circuit PC.

[0218] The light-blocking pattern LSP may be provided in an island shape between the first substrate 100 and the active layer ACT. The light-blocking pattern LSP may block light incident on the active layer ACT through the first substrate 100, thereby preventing or reducing (in some embodiments, minimizing) a change in the threshold voltage of each TFT caused by external light. The light-blocking pattern LSP may be electrically coupled to the first source / drain SD1 of the corresponding TFT and may thus function as a lower gate of the corresponding TFT. In this case, changes in the characteristics of each TFT caused by light and changes in the threshold voltage of each TFT caused by a bias voltage may be reduced (in some embodiments, minimized) or prevented.

[0219] The lower metal layer BML may be used as lines arranged parallel to one another among the gate lines GL, the data lines DL, the pixel driving power lines PL, the pixel common voltage lines CVL, and the reference voltage lines RL. For example, the lower metal layer BML may be used as a metal layer (or line) arranged parallel to the second direction Y among the pixel driving lines DL, GL, PL, CVL, RL, and GCL provided on the first substrate 100.

[0220] A passivation layer PAS may be disposed over the first substrate 100 to cover the pixel circuit PC including the driving TFT Tdr. The passivation layer PAS may cover the circuit layer 101 including the driving TFT Tdr disposed at each pixel area PA.

[0221] The passivation layer PAS according to the embodiment may be formed of an inorganic material. For example, the passivation layer PAS may include a single layer structure containing one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof. For example, the passivation layer PAS may be referred to as a protective layer, a short circuit protection layer, a circuit insulating layer, an inorganic insulating layer, a first inorganic insulating layer, a second insulating layer, or the like.

[0222] The planarization layer 102 may be disposed on the first substrate 100 over which the passivation layer PAS is disposed, and may provide a flat surface on the passivation layer PAS. The planarization layer 102 may cover the circuit layer 101 including the driving TFT Tdr disposed at each of the plurality of pixel areas PA. For example, the planarization layer 102 may be disposed between the interlayer insulating layer 101c and the passivation layer PAS.

[0223] The planarization layer 102 according to an embodiment of the present disclosure may be formed to cover the remaining circuit layer 101 except for the peripheral portion of the passivation layer PAS provided on the first substrate 100. For example, the planarization layer 102 may be provided between the first substrate 100 and the light-emitting device layer EDL or provided under (or below) the light-emitting device layer EDL. The planarization layer 102 according to an embodiment may be formed of an organic material, but the embodiments of the present disclosure are not limited thereto. For example, the planarization layer 102 may be formed of an organic material including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide-based resin, a polyimide-based resin, or the like, but the embodiments of the present disclosure are not limited thereto.

[0224] The light emitting device layer EDL may be disposed over the planarization layer 102. The light emitting device layer EDL according to an embodiment may include a pixel electrode PE, a self-light emitting device ED, and a common electrode CE.

[0225] The pixel electrode PE may be referred to as an anode electrode, a reflective electrode, a lower electrode, an anode, or a first electrode of the self-luminous device ED.

[0226] The pixel electrode PE may be disposed over the planarization layer 102, overlapping the emission area EA of each of the plurality of sub-pixels SP in the first substrate 100. The pixel electrode PE may be patterned into an island shape and disposed in each sub-pixel SP, and may be electrically coupled to the first source / drain SD1 of the driving TFT Tdr of the corresponding pixel circuit PC. For example, one side of the pixel electrode PE may extend onto the first source / drain SD1 of the driving TFT Tdr, and may be electrically coupled to the first source / drain SD1 of the driving TFT Tdr through an electrode contact hole ECH provided in the planarization layer 102.

[0227] The pixel electrode PE may include a metal material with low work function and good reflection efficiency.

[0228] The pixel electrode PE according to an embodiment of the present disclosure may have a two-layer structure including a first pixel electrode layer (or a first metal layer) PEL1 and a second pixel electrode layer (or a second metal layer) PEL2. The first and second pixel electrode layers PEL1 and PEL2 may be sequentially deposited on the planarization layer 102 and then patterned simultaneously, but the embodiments of the present disclosure are not limited thereto.

[0229] The first pixel electrode layer PEL1 may be disposed above the planarization layer 102. The second pixel electrode layer PEL2 may be disposed (or stacked) on the first pixel electrode layer PEL1. For example, the first pixel electrode layer PEL1 may serve as an adhesive layer corresponding to the planarization layer 102 and may serve as a secondary electrode of the self-luminous device ED, and further, may include indium tin oxide (ITO) or indium zinc oxide (IZO), but the embodiments of the present disclosure are not limited thereto. For example, the second pixel electrode layer PEL2 may serve as a reflector and may perform a function of reducing the resistance of the pixel electrode PE, and further, may include one of aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti), and Mo-Ti alloy (MoTi), but the embodiments of the present disclosure are not limited thereto. For example, the pixel electrode PE may be formed as a two-layer structure of ITO / MoTi or IZO / MoTi.

[0230] According to another embodiment, the pixel electrode PE may have a three-layer structure including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 on the first pixel electrode layer PEL1, and a third pixel electrode layer (or a third metal layer) on the second pixel electrode layer PEL2. The first pixel electrode layer PEL1, the second pixel electrode layer PEL2, and the third pixel electrode layer may be sequentially deposited on the planarization layer 102 and then patterned simultaneously, but embodiments of the present disclosure are not limited thereto.

[0231] The third pixel electrode layer may serve as an electrode of the self-luminous device ED and may include ITO or IZO. For example, the pixel electrode PE according to another embodiment may be formed in a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO.

[0232] According to another embodiment, the pixel electrode PE may have a four-layer structure including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 on the first pixel electrode layer PEL1, a third pixel electrode layer (or a third metal layer) PEL3 on the second pixel electrode layer PEL2, and a fourth pixel electrode layer (or a fourth metal layer) on the third pixel electrode layer. The first to fourth pixel electrode layers may be sequentially deposited on the planarization layer 102 and then patterned simultaneously, but embodiments of the present disclosure are not limited thereto.

[0233] In the four-layer pixel electrode PE, the first pixel electrode layer can serve as an adhesive layer corresponding to the planarization layer 102 and can serve as a secondary electrode of the self-luminous device ED, and in addition, can include one or more materials of ITO, Mo, and Mo-Ti. The second pixel electrode layer can play a role in reducing the resistance of the pixel electrode PE and can include Cu. The third pixel electrode layer can serve as a reflector and can include one or more materials of Al, Ag, Mo, Ti, and MoTi. The fourth pixel electrode layer can serve as an electrode of the self-luminous device ED and can include ITO or IZO. For example, the pixel electrode PE according to another embodiment can be formed into a four-layer structure of ITO / Cu / MoTi / ITO.

[0234] The pixel electrode PE according to another embodiment may have a five-layer structure including a first pixel electrode layer made of ITO, a second pixel electrode layer made of MoTi, a third pixel electrode layer made of ITO, a fourth pixel electrode layer made of Ag, and a fifth pixel electrode layer made of ITO.

[0235] The self-luminous device ED may be disposed above the first substrate 100. The self-luminous device ED may be formed above the pixel electrode PE and may directly contact the pixel electrode PE. The pixel electrode PE may be disposed below (or under) the self-luminous device ED. For example, the pixel electrode PE may be disposed between the planarization layer 102 and the self-luminous device ED.

[0236] The self-luminous device ED according to an embodiment may be a common layer formed in each of the plurality of sub-pixels SP, thereby not being distinguished by the sub-pixel SP unit. The self-luminous device ED may respond to the current flowing between the pixel electrode PE and the common electrode CE to emit white light (or blue light). The self-luminous device ED according to an embodiment may include an organic light-emitting device, or may include a stacked or combined structure of an organic light-emitting device and a quantum dot light-emitting device. For example, the self-luminous device ED according to another embodiment may include an organic light-emitting layer, or may include a stacked or combined structure of an organic light-emitting layer and a quantum dot light-emitting layer.

[0237] An organic light-emitting device may include two or more organic light-emitting components to emit white light (or blue light). For example, the organic light-emitting device may include a first organic light-emitting component and a second organic light-emitting component to emit white light based on a combination of the first light and the second light. For example, the first organic light-emitting component may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer. The second organic light-emitting component may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer to emit a second light that combines with the first light from the first organic light-emitting component to generate white light.

[0238] The organic light emitting device according to the embodiment may further include at least one or more functional layers for enhancing luminous efficiency and / or lifespan. For example, the functional layer may be disposed on and / or under the light emitting layer.

[0239] The common electrode CE may be disposed over the display area AA of the first substrate 100 and may be electrically coupled to the self-luminous device ED of each of the plurality of pixels P. For example, the common electrode CE may be disposed over the remaining display area AA of the first substrate 100 excluding the peripheral portion of the first substrate 100. For example, the common electrode CE may be disposed over the remaining display area AA of the first substrate 100 excluding the first pad part 110 of the first substrate 100.

[0240] The common electrode CE may be referred to as a cathode electrode, a transparent electrode, an upper electrode, a cathode, or a second electrode of the self-luminous device ED. The common electrode CE may be formed above the self-luminous device ED and may directly contact the self-luminous device ED or may electrically and directly contact the self-luminous device ED. The common electrode CE may include a transparent conductive material that transmits light emitted from the self-luminous device ED.

[0241] The common electrode CE according to an embodiment of the present disclosure may be formed in a single-layer structure or a multi-layer structure, and may include at least one of graphene and a transparent conductive material having a relatively high work function. For example, the common electrode CE may include a metal oxide such as ITO or IZO, or may include a combination of an oxide and a metal such as ZnO:Al or SnO2:Sb.

[0242] In addition, the light emitting device layer EDL may further include a capping layer disposed over the common electrode CE. The capping layer may be disposed over the common electrode CE and may improve light emission efficiency by adjusting a refractive index of light emitted from the light emitting device layer EDL.

[0243] The bank BK may be disposed above the planarization layer 102 to define a pixel area PA above the first substrate 100. The bank BK may be disposed above the planarization layer 102 to cover the periphery of the pixel electrode PE. The bank BK may define a light-emitting area EA (or opening) for each of the plurality of sub-pixels SP and may electrically isolate the pixel electrodes PE disposed at adjacent sub-pixels SP. The bank BK may be formed to cover the electrode contact hole ECH disposed at each of the plurality of pixel areas PA. The bank BK may be covered by the self-luminous device ED of the light-emitting device layer EDL. For example, the self-luminous device ED may be disposed above the bank BK and above the pixel electrode PE for each of the plurality of sub-pixels SP.

[0244] The bank BK according to an embodiment may be a transparent bank including a transparent material or a black bank (or non-transparent bank) including a black pigment.

[0245] The dam 104 may be provided at the periphery of the first substrate 100 or the periphery of the outermost pixel Po. For example, the dam 104 may be provided as an element of each outermost pixel Po provided at the periphery of the first substrate 100, and thus, the outermost pixel Po may have a structure different from that of the inner pixels.

[0246] The dam 104 may be provided above the circuit layer 101 at the periphery of the first substrate 100 or the periphery of the outermost pixel Po to have a closed loop shape. For example, the dam 104 may be provided above the circuit layer 101 to have a closed loop shape surrounding the display area AA and may be supported by the interlayer insulating layer 101c of the circuit layer 101. For example, the dam 104 may be implemented to be surrounded by the blocking structure 105. In addition, the dam 104 may be implemented to isolate the self-luminous device ED provided at the periphery of the first substrate 100 or the periphery of each outermost pixel Po.

[0247] At the periphery of the first substrate 100 or the periphery of the outermost pixel Po, the dam 104 may include functions of isolating the self-luminous devices ED of the light-emitting device layer EDL, blocking diffusion or overflow of the organic encapsulation layer, and preventing water (or water vapor) from penetrating in the lateral direction of the substrate 100. The dam 104 will be described below.

[0248] The groove line GRV may be provided at a groove area (or groove area) defined in an inner area of ​​the dam 104. According to an embodiment, the groove line GRV may be provided above the circuit layer 101 to have a closed loop line shape (or closed loop shape) between the end of the planarization layer 102 and the dam 104. For example, the groove line GRV may be formed or implemented by removing all of the planarization layer 102 and the passivation layer PAS at the groove area provided in the inner area of ​​the dam 104. For example, the groove line GRV may be implemented to expose a partial area of ​​the interlayer insulating layer 101c provided between the end of the planarization layer 102 and the dam 104. In addition, the groove line GRV may be implemented to isolate the self-luminous device ED provided at the peripheral portion of the first substrate 100 or the peripheral portion of each outermost pixel Po. The groove line GRV will be described below.

[0249] The blocking structure 105 may be provided or realize a blocking area set at the peripheral portion of the first substrate 100 or the peripheral portion of each outermost pixel Po. For example, the blocking structure 105 may be provided as an element of each outermost pixel Po provided at the peripheral portion of the first substrate 100, and thus, the outermost pixel Po may have a structure different from that of each inner pixel.

[0250] The blocking structure 105 may be provided at the periphery of the first substrate 100 or the periphery of each outermost pixel Po to have a one-dimensional closed loop shape. For example, the blocking structure 105 may be provided above the circuit layer 101 to have a closed loop shape surrounding the display area AA, and may be supported by the interlayer insulating layer 101c of the circuit layer 101. For example, the blocking structure 105 may be implemented to surround the dam 104. The blocking structure 105 may be implemented to additionally isolate the self-luminous device ED provided at the periphery of each outermost pixel Po. The blocking structure 105 may be implemented to prevent water (or water vapor) from penetrating in the lateral direction of the first substrate 100 to prevent degradation of the self-luminous device ED caused by the lateral penetration of water (or water vapor). The blocking structure 105 may isolate (or disconnect) the self-luminous device ED of the light-emitting device layer EDL at the outer area of ​​the dam 104 at least once, thereby preventing the lateral penetration of water (or water vapor).

[0251] The barrier structure 105 according to the embodiment may include first to third barrier pattern portions 105a, 105b, and 105c disposed parallel to each other above the interlayer insulating layer 101c. The first to third barrier pattern portions 105a, 105b, and 105c may each be disposed at an outer region of the dam 104 and may be surrounded by the dam 104. The barrier structure 105 including the first to third barrier pattern portions 105a, 105b, and 105c will be described below.

[0252] The encapsulation layer 106 may be disposed over the remaining portion of the first substrate 100, excluding the outermost peripheral portion of the first substrate 100, and may be implemented to cover the light-emitting device layer EDL. For example, the encapsulation layer 106 may be implemented over the first substrate 100 to surround all of the front and side surfaces of the light-emitting device layer EDL. The encapsulation layer 106 may be implemented to surround all of the front and side surfaces of the light-emitting device layer EDL, thereby preventing oxygen or water (or water vapor) from penetrating into the light-emitting device layer EDL, thereby improving the reliability of the light-emitting device layer EDL against oxygen or water (or water vapor).

[0253] The encapsulation layer 106 according to an embodiment of the present disclosure may include first to third encapsulation layers 106 a , 106 b , and 106 c .

[0254] The first encapsulation layer 106a may be implemented to prevent oxygen or water (or water vapor) from penetrating into the light-emitting device layer EDL. The first encapsulation layer 106a may be disposed above the common electrode CE and may surround the light-emitting device layer EDL. Therefore, all of the front and side surfaces of the light-emitting device layer EDL may be surrounded by the first encapsulation layer 106a.

[0255] The first encapsulation layer 106a may completely surround or seal the light-emitting device layer EDL including the self-luminous device ED isolated at the groove line GRV. The first encapsulation layer 106a may completely surround or seal the light-emitting device layer EDL including the self-luminous device ED isolated at each of the groove line GRV and the dam 104. The first encapsulation layer 106a may completely surround or seal the light-emitting device layer EDL including the self-luminous device ED isolated at each of the groove line GRV, the dam 104, and the blocking structure 105. For example, when the self-luminous device ED and the common electrode CE are isolated at each of the groove line GRV, the dam 104, and the blocking structure 105, the first encapsulation layer 106a may completely surround or seal each isolation surface (or disconnection surface) of the isolated self-luminous device ED and the common electrode CE, thereby fundamentally (or completely) preventing lateral penetration of water (or water vapor).

[0256] According to an embodiment, the first encapsulation layer 106a may include a first inorganic encapsulation layer of an inorganic insulating material. For example, the first encapsulation layer 106a may include a single layer structure containing one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof.

[0257] Second encapsulation layer 106b may be implemented over first encapsulation layer 106a disposed at the encapsulation region defined by dam 104 to have a thickness relatively greater than first encapsulation layer 106a. Second encapsulation layer 106b may have a thickness sufficient to completely cover particles (or undesirable materials or undesirable structural elements) that may be present on or above first encapsulation layer 106a. Due to its relatively thick thickness, second encapsulation layer 106b may diffuse to the periphery of first substrate 100, but diffusion of second encapsulation layer 106b may be blocked by dam 104.

[0258] According to an embodiment, the second encapsulation layer 106b may include an organic material or a liquid organic material. For example, the second encapsulation layer 106b may include an organic material such as SiOCz acrylic or epoxy resin. The second encapsulation layer 106b may be referred to as a particle covering layer, an organic encapsulation layer, or the like.

[0259] According to an embodiment, the second encapsulation layer 106b can smoothly diffuse to the dam 104 through the groove line GRV, and thus, a non-filling phenomenon of the second encapsulation layer 106b can be prevented from occurring in a region adjacent to an inner region of the dam 104. For example, the diffusion of the second encapsulation layer 106b can smoothly advance to the dam 104 through the groove line GRV without being hindered by other structures, and thus, the second encapsulation layer 106b can completely fill a region adjacent to the inner region of the dam 104.

[0260] According to an embodiment, when an inner groove structure for isolating the light-emitting device layer EDL is provided at an inner region of the dam 104 instead of the groove line GRV, the diffusion of the second encapsulation layer 106b may be hindered or blocked by the height and step height of the inner groove structure, and thus may not be able to proceed to the dam 104, and due to this, a non-filling phenomenon of the second encapsulation layer 106b may occur in an area adjacent to the inner region of the dam 104.

[0261] The third encapsulation layer 106c may be implemented to primarily prevent oxygen or water (or water vapor) from penetrating into the light-emitting device layer EDL. The third encapsulation layer 106c may be implemented to surround the entirety of the second encapsulation layer 106b disposed at an inner region from the dam 104 and the first encapsulation layer 106a disposed at an outer region from the dam 104. The third encapsulation layer 106c according to an embodiment of the present disclosure may include the same or different inorganic material as the first encapsulation layer 106a.

[0262] The light-emitting display device or the first substrate 100 according to an embodiment of the present disclosure may include a first margin area MA1 , a second margin area MA2 , and a third margin area MA3 .

[0263] The first margin area MA1 may be provided between the dam 104 and the emission area EA of the outermost pixel P. Based on the reliability margin of the light-emitting device layer EDL against lateral permeation of water (or water vapor), the first margin area MA1 may have a first width between the dam 104 and the end (or bank BK) of the emission area EA of the outermost pixel Po. Accordingly, the dam 104 may be implemented to be spaced apart from the end of the emission area EA with respect to the first direction X by the first width of the first margin area MA1.

[0264] The second margin area MA2 may be provided between the dam 104 and the outer surface OS of the first substrate 100. Based on the reliability margin of the light-emitting device layer EDL against lateral permeation of water (or water vapor), the second margin area MA2 may have a second width between the dam 104 and the outer surface OS of the first substrate 100. Accordingly, the dam 104 may be implemented to be spaced apart from the outer surface OS of the first substrate 100 with respect to the first direction X by the second margin area MA2. For example, the second margin area MA2 may be a region including the first pad component 110 and the first to third barrier pattern portions 105a, 105b, and 105c of the barrier structure 105.

[0265] The third margin area MA3 may be disposed between the first margin area MA1 and the second margin area MA2. The third margin area MA3 may have a third width corresponding to the width of the lowest bottom surface (or bottom surface) of the dam 104. For example, the third margin area MA3 may be a region including the dam 104.

[0266] With respect to the first direction X, the width of each of the first to third margin areas MA1, MA2, and MA3 may be implemented so that a second interval D2 between the center portion of the outermost pixel Po and the outer surface OS of the first substrate 100 is half the pixel pitch or less.

[0267] Reference Figure 3 、 Figure 7 ,and Figure 8 , the first substrate 100 according to an embodiment of the present disclosure may further include a first pad part 110 .

[0268] The first pad part 110 may be disposed at one peripheral portion of the first substrate 100 and may be electrically coupled to the pixel driving lines DL, GL, PL, CVL, RL, and GCL in a one-to-one relationship.

[0269] The first pad part 110 according to an embodiment of the present disclosure may include a plurality of first pads 111 disposed within the circuit layer 101 .

[0270] The plurality of first pads 111 may be divided (or classified) into a first data pad DP, a first gate pad GP, a first pixel driving power pad PPP, a first reference voltage pad RVP, and a first pixel common voltage pad CVP.

[0271] Each of the plurality of first pads 111 may be disposed above the interlayer insulating layer 101c and may be electrically coupled to a corresponding one of the pixel drive lines DL, GL, PL, CVL, RL, and GCL via a pad contact hole PCH passing through the interlayer insulating layer 101c and the buffer layer 101a. For example, each of the plurality of first pads 111 according to an embodiment may include the same material as the pixel electrode PE and may be located together with the pixel electrode PE. Each of the plurality of first pads 111 according to another embodiment may include the same material as the source / drain of a TFT and may be located together with the source / drain of the TFT.

[0272] A portion of each of the plurality of first pads 111 may be exposed above the first substrate 100 through a pad open hole POH formed above the passivation layer PAS. For example, the pad open hole POH may be implemented by a pad open process of removing or opening a portion of the passivation layer PAS that overlaps with the portion of each of the plurality of first pads 111.

[0273] Reference Figure 8 and Figure 10 The light-emitting display device or the first substrate 100 according to an embodiment of the present disclosure may further include a wavelength conversion layer 107 disposed above the encapsulation layer 106 .

[0274] The wavelength conversion layer 107 may convert the wavelength of light incident thereon from the light-emitting region of each pixel area PA. For example, the wavelength conversion layer 107 may convert white light (or blue light) incident thereon from the light-emitting region into light of the color corresponding to the sub-pixel SP, or may transmit only the light of the color corresponding to the sub-pixel SP. For example, the wavelength conversion layer 107 may include at least one of a wavelength conversion element and a color filter layer.

[0275] The wavelength conversion layer 107 according to an embodiment may include a plurality of wavelength conversion elements 107 a and a protective layer 107 b .

[0276] A plurality of wavelength conversion elements 107a may be disposed over the encapsulation layer 106 disposed at the emission area EA of each of the plurality of sub-pixels SP. For example, each of the plurality of wavelength conversion elements 107a may be implemented to have a size that is the same as or wider than the emission area EA of each sub-pixel region.

[0277] According to an embodiment, the plurality of wavelength conversion elements 107a may be divided (or classified) into a red light filter that converts white light into red light, a green light filter that converts white light into green light, and a blue light filter that converts white light into blue light. For example, the red light filter (or first light filter) may be disposed above the encapsulation layer 106 in the emission area EA of the red sub-pixel SP, the green light filter (or second light filter) may be disposed above the encapsulation layer 106 in the emission area EA of the green sub-pixel SP, and the blue light filter (or third light filter) may be disposed above the encapsulation layer 106 in the emission area EA of the blue sub-pixel SP.

[0278] According to another embodiment, a plurality of wavelength conversion elements 107a may be disposed over the encapsulation layer 106 in each sub-pixel region. For example, each of the plurality of wavelength conversion elements 107a may be disposed over the encapsulation layer 106 to overlap the entire corresponding sub-pixel SP.

[0279] According to another embodiment, a plurality of wavelength conversion elements 107a may be implemented to overlap one another at the encapsulation layer 106 that overlaps the circuit area CA (or non-emission area) other than the emission area EA of each sub-pixel SP. For example, two or more wavelength conversion elements 107a having different colors may be provided at the encapsulation layer 106 that overlaps the circuit area CA (or non-emission area) other than the emission area EA of each sub-pixel SP. The two or more wavelength conversion elements 107a provided at the encapsulation layer 106 that overlaps the circuit area CA (or non-emission area) may function as a light-blocking pattern that prevents color mixing between adjacent sub-pixels SP or between adjacent pixels P.

[0280] The protective layer 107b may be implemented to cover the wavelength conversion element 107a and provide a flat surface above the wavelength conversion element 107a. The protective layer 107b may be provided to cover the wavelength conversion element 107a and the encapsulation layer 106 not provided with the wavelength conversion element 107a. According to an embodiment, the protective layer 107b may include an organic material. Alternatively, the protective layer 107b may further include a getter material for absorbing water (or water vapor) and / or oxygen.

[0281] Alternatively, the wavelength conversion layer 107 according to another embodiment may include two or more wavelength conversion elements 107a disposed above the encapsulation layer 106 and overlapping the circuit area CA (or non-light-emitting area) excluding the light-emitting area EA of each sub-pixel SP. The two or more wavelength conversion elements 107a may function as a light-blocking pattern.

[0282] Alternatively, the wavelength conversion layer 107 may be modified to a wavelength conversion sheet in sheet form and may be disposed above the encapsulation layer 106. In this case, the wavelength conversion sheet (or quantum dot sheet) may include a wavelength conversion element 107a disposed between a pair of films. For example, when the wavelength conversion layer 107 includes quantum dots that re-emit light of the color set in the sub-pixel SP, the light-emitting device layer EDL of the sub-pixel SP can be implemented to emit white light or blue light.

[0283] The light-emitting display device or the first substrate 100 according to an embodiment of the present disclosure may further include a functional film 108 .

[0284] The functional film 108 may be disposed over the wavelength conversion layer 107. For example, the functional film 108 may be coupled to the wavelength conversion layer 107 via a transparent adhesive member. The functional film 108 according to an embodiment may include at least one of an anti-reflection layer (or anti-reflection film), a barrier layer (or barrier film), a touch sensing layer, or an optical path control layer (or optical path control film).

[0285] The anti-reflection layer may include a circular polarization layer (or a circular polarization film) that prevents external light reflected by the TFTs and / or pixel driving lines provided at the substrate 10 from traveling to the outside.

[0286] The barrier layer may include a material with a low water permeability (eg, a polymeric material) and may primarily prevent the permeation of water (or water vapor) or oxygen.

[0287] The touch sensing layer may include touch electrodes based on a mutual capacitance method or a self-capacitance method, and may output touch data corresponding to a user's finger through the touch electrode layer.

[0288] The light path control layer may include a stack structure in which high-refractive layers and low-refractive layers are alternately stacked, and may change a path of light incident from each pixel P to reduce (in some embodiments, minimize) color shift based on a viewing angle.

[0289] The light-emitting display device or the first substrate 100 according to an embodiment of the present disclosure may further include a side sealing member 109 .

[0290] The side sealant 109 may be formed between the first substrate 100 and the functional film 108 and may cover all sides of the circuit layer 101 and the wavelength conversion layer 107. For example, the side sealant 109 may cover all sides of each of the circuit layer 101 and the wavelength conversion layer 107 that are exposed to the outside of the display device and between the functional film 108 and the first substrate 100. Furthermore, the side sealant 109 may cover a portion of the routing portion 400 coupled to the first pad component 110 of the first substrate 100. The side sealant 109 may prevent lateral light leakage caused by light emitted from the self-luminous element ED of each sub-pixel SP traveling from the interior of the wavelength conversion layer 107 to the outer surface thereof. Specifically, the side sealant 109, overlapping the first pad component 110 of the first substrate 100, may prevent or reduce (in some embodiments, minimize) reflection of external light caused by the first pad 111 provided in the first pad component 110.

[0291] Optionally, the side sealing member 109 may further include a getter material for absorbing water (or water vapor) and / or oxygen.

[0292] The light-emitting display device or the first substrate 100 according to an embodiment of the present disclosure may further include a first chamfer 100c provided at the corner between the first surface 100a and the outer surface OS. The first chamfer 100c can reduce or minimize damage to the corner of the first substrate 100 caused by physical impact applied from the outside, and can prevent disconnection of the routing portion 400 caused by the corner of the first substrate 100. For example, the first chamfer 100c may have a 45-degree angle, but the embodiments of the present disclosure are not limited thereto. The first chamfer 100c can be achieved by a chamfering process using a cutting wheel, a polishing wheel, a laser, or the like. Accordingly, the outer surfaces of the first pads 111 of the first pad component 110 that are arranged to contact the first chamfer 100c may each include an inclined surface inclined by the angle of the corresponding first chamfer 100c. The angle of the first chamfer 100c can be formed by removing or polishing the corresponding portion thereof together with the corner of the first substrate 100 through the chamfering process. For example, when the first chamfer 100c is formed at an angle of 45 degrees between the outer surface OS of the first substrate 100 and the first surface 100a, the outer surface (or one end) of the first pad 111 of the first pad part 110 may be formed at an angle of 45 degrees.

[0293] Reference Figure 7 、 Figure 8 ,and Figure 10 The second substrate 200 according to the embodiment of the present disclosure may include a second pad part 210, at least one third pad part 230, and a link line portion 250, as shown in FIG. Figure 7 As described above, and therefore, their repeated descriptions are omitted or may be brief.

[0294] The second substrate 200 according to an embodiment may include a metal pattern layer and an insulating layer that insulates the metal pattern layer.

[0295] The metal pattern layer (or conductive pattern layer) may include multiple metal layers. The metal pattern layer according to the embodiment may include a first metal layer 201, a second metal layer 203, and a third metal layer 205. The insulating layer may include multiple insulating layers. For example, the insulating layer may include a first insulating layer 202, a second insulating layer 204, and a third insulating layer 206. The insulating layer may be referred to as a rear insulating layer or a patterned insulating layer.

[0296] The first metal layer 201 may be implemented over the rear surface 202b of the second substrate 200. The first metal layer 201 according to an embodiment may include a first metal pattern. For example, the first metal layer 201 may be referred to as a first link layer or a link line layer.

[0297] The first metal pattern according to an embodiment may have a two-layer structure of Cu and MoTi (Cu / MoTi). The first metal pattern may be used as a link line of the link line part 250, and thus, a repeated description thereof may be omitted.

[0298] The first insulating layer 202 may be implemented over the rear surface 200b of the second substrate 200 to cover the first metal layer 201. The first insulating layer 202 according to an embodiment may include an inorganic insulating material.

[0299] The second metal layer 203 may be implemented over the first insulating layer 202. The second metal layer 203 according to an embodiment may include a second metal pattern. For example, the second metal layer 203 may be referred to as a second link layer, a jump line layer, or a bridge line layer.

[0300] The second metal pattern according to an embodiment may have a two-layer structure of Cu and MoTi (Cu / MoTi). The second metal pattern may be used as a plurality of gate link lines of a plurality of link lines in the link line section 250, but is not limited thereto. For example, the second metal layer 203 may be used as a jumper (or bridge line) to electrically couple link lines formed of different metal materials on different layers in the link line section 250.

[0301] Optionally, the link lines (e.g., multiple first link lines) set at the second metal layer 203 can be modified to be set at the first metal layer 201, and the link lines (e.g., multiple second link lines) set at the first metal layer 201 can be modified to be set at the second metal layer 203.

[0302] The second insulating layer 204 may be implemented over the rear surface 200b of the second substrate 200 to cover the second metal layer 203. The second insulating layer 204 according to an embodiment may include an inorganic insulating material.

[0303] The third metal layer 205 may be implemented over the second insulating layer 204. The third metal layer 205 according to an embodiment may include a third metal pattern. For example, the third metal layer 205 may be referred to as a third link layer or a pad electrode layer.

[0304] The third metal pattern according to the embodiment may have a stacked structure of at least two materials among ITO (or IZO), Mo, Ti, and MoTi. For example, the third metal pattern may have a three-layer structure of any one of ITO / Mo / ITO, ITO / MoTi / ITO, IZO / Mo / ITO, or IZO / MoTi / ITO. The third metal pattern may be used as a pad for the second pad component 210. For example, the pad of the second pad component 210 formed by the third metal layer 205 can be electrically coupled to the first metal layer 201 through a pad contact hole formed at the first and second insulating layers 202 and 204.

[0305] A third insulating layer 206 may be formed over the rear surface 200b of the second substrate 200 to cover the third metal layer 205. Depending on the embodiment, the third insulating layer 206 may include an organic material. For example, the third insulating layer 206 may include an insulating material such as photo acrylic. The third insulating layer 206 may cover the third metal layer 205 to prevent the third metal layer 205 from being exposed to the outside. The third insulating layer 206 may be referred to as an organic insulating layer, a protective layer, a rear protective layer, an organic protective layer, a rear coating layer, or a rear covering layer.

[0306] Each of the plurality of second pads provided at the second pad part 210 can be electrically coupled to a link line of the link line portion 250 made of the first metal layer 201 or the second metal layer 203 provided at the rear surface 200b of the second substrate 200 through a second pad contact hole provided at the first and second insulating layers 202 and 204. For example, the second data pad can be electrically coupled to one end of the data link line through the second pad contact hole provided at the first and second insulating layers 202 and 204.

[0307] The coupling element 300 according to an embodiment of the present disclosure may be disposed between the first substrate 100 and the second substrate 200. The first substrate 100 and the second substrate 200 may be coupled relative to each other via the coupling element 300. The coupling element 300 according to an embodiment may be a transparent adhesive element including an optically clear adhesive (OCA), an optically clear resin (OCR), or a pressure sensitive adhesive (PSA), or a double-sided tape. The coupling element 300 according to another embodiment may include glass fiber.

[0308] The coupling element 300 according to the embodiment may be provided at the entire space between the first substrate 100 and the second substrate 200. For example, the entire second surface 100b of the first substrate 100 may be coupled to the entire one surface of the coupling element 300, and the entire front surface 200a of the second substrate 200 may be coupled to the entire other surface of the coupling element 300.

[0309] The coupling element 300 according to another embodiment may be provided in a pattern structure between the first substrate 100 and the second substrate 200. For example, the coupling element 300 may have a line pattern structure or a mesh pattern structure. The mesh pattern structure may further include a curved portion that discharges air bubbles to the outside, which may occur between the first substrate 100 and the second substrate 200 during the process of bonding the first substrate 100 to the second substrate 200.

[0310] The routing section 400 according to an embodiment of the present disclosure may include a plurality of routing lines 410 electrically coupling the first pad part 110 and the second pad part 210 in a one-to-one relationship. Figure 7 and therefore, their repeated descriptions are omitted.

[0311] The light emitting display device or the routing portion 400 according to an embodiment of the present disclosure may further include an edge coating layer 430 .

[0312] The edge coating 430 may be implemented to cover the routing portion 400. The edge coating 430 may be implemented to cover the plurality of routing lines 410. For example, the edge coating 430 may be an edge protection layer or an edge insulation layer.

[0313] The edge coating 430 according to an embodiment of the present disclosure may be implemented to cover the first edge portion and first outer surface OS1a of the first substrate 100, the first edge portion and first outer surface OS1b of the second substrate 200, and all of the plurality of selected lines 410. The edge coating 430 may prevent corrosion of each of the plurality of selected lines 410, which may include a metal material, or electrical short circuits between the plurality of selected lines 410. Furthermore, the edge coating 430 may prevent or reduce (in some embodiments, minimize) reflection of external light caused by the plurality of selected lines 410 and the first pad 111 of the first pad component 110. As another embodiment, the edge coating 430 may be implemented (or configured) on the outermost surface (or sidewall) of the display device (or display panel), and thus, may include an impact-absorbing material (or substance) or a ductile material to prevent damage to the outer surface OS of each of the first and second substrates 100 and 200. As another embodiment, the edge coating 430 may include a mixed material of a light-blocking material and an impact-absorbing material.

[0314] According to an embodiment, the edge coating layer 430 may be formed to surround one outer surface OS of each of the first and second substrates 100 and 200 on which the routing portion 400 is formed.

[0315] According to another embodiment, Figure 7 、 Figure 8 ,and Figure 10 As shown in , the edge coating 430 may be formed to surround all of the one outer surface OS and the other outer surface OS of each of the first and second substrates 100 and 200 on which the routing portion 400 is formed. For example, the edge coating 430 may be formed to surround all of the outer surfaces OS of each of the first and second substrates 100 and 200. In this case, the one outer surface OS (or the first outer surface) of each of the first and second substrates 100 and 200 may be surrounded by a plurality of routing lines 410 and the edge coating 430. The other outer surfaces OS (or the second to fourth outer surfaces) of each of the first and second substrates 100 and 200 other than the one outer surface OS may be surrounded only by the edge coating 430. For example, the first outer surface of each of the first and second substrates 100 and 200 may include a plurality of routing lines 410 and the edge coating 430, and the second to fourth outer surfaces of each of the first and second substrates 100 and 200 other than the first outer surface may include only the edge coating 430.

[0316] According to an embodiment, when the plurality of selected lines 410 and the edge coating 430 provided on the first outer surface are referred to as a first sidewall structure, and the edge coating 430 provided on the second to fourth outer surfaces are referred to as a second sidewall structure, the first sidewall structure and the second sidewall structure may have different thicknesses (or widths). For example, the thickness (or width) of the second sidewall structure may be thinner or narrower than the thickness (or width) of the first sidewall structure by the thickness of the plurality of selected lines 410.

[0317] Figure 11 yes Figure 8 The area "C" shown in FIG is an enlarged view of the Figure 8 and Figure 9 Illustration of the trench lines, dams, and barrier structures shown in .

[0318] Reference Figure 8 、 Figure 10 ,and Figure 11 , the groove line GRV according to an embodiment of the present disclosure may be disposed or formed to have a closed loop line shape at the first margin area MA1 of the first substrate 100 or the outermost pixel Po.

[0319] The groove line GRV according to the embodiment may correspond to an area from which all structures in the diffusion path through which the encapsulation layer 106 diffuses to the dam 104 have been removed. The groove line GRV may be an area from which all of a single structure or a multi-layer structure, including at least one of the passivation layer PAS, the planarization layer 102, the pixel electrode material layer, and the bank BK, which are disposed above the interlayer insulating layer 101c near the inner area of ​​the dam 104, have been removed. For example, the groove line GRV may be formed or implemented by patterning (or removing) the passivation layer PAS and the planarization layer 102 disposed at the outermost pixel Po or the first margin area MA1 of the first substrate 100. Accordingly, the groove line GRV may define the side surface 102s of the planarization layer 102 and may have a closed loop line shape (or a closed loop shape) surrounding the side surface 102s of the planarization layer 102.

[0320] According to an embodiment, the groove line GRV can be formed by patterning (or removing) the passivation layer PAS and the planarization layer 102 on the interlayer insulating layer 101c, and thus, the uppermost surface (or surface) of the interlayer insulating layer 101c can be exposed. For example, the groove line GRV may include a main groove line and a secondary groove line, the main groove line being formed above the passivation layer PAS by a patterning process of patterning the planarization layer 102 to form the electrode contact hole ECH of the TFT, and the secondary groove line being formed above the interlayer insulating layer 101c by a patterning process of patterning the passivation layer PAS provided at the main groove line. The interlayer insulating layer 101c can be exposed by the groove line GRV between the end 102e of the planarization layer 102 and the dam 104, and thus, the bottom surface of the groove line GRV can be realized. For example, the groove line GRV may have a width wider than or equal to the width of the dam 104.

[0321] One side of the groove line GRV may define a side surface 102s of the planarization layer 102 and a side surface PASs of the passivation layer PAS disposed on the first substrate 100 or on the display area AA. For example, the side surface 102s of the planarization layer 102 and the side surface PASs of the passivation layer PAS may be exposed to realize one sidewall of the groove line GRV.

[0322] According to an embodiment, the side end 102e of the planarization layer 102 may protrude from the side surface PASs of the passivation layer PAS toward the center portion (or dam 104) of the groove line GRV. For example, the distance between the side end 102e of the planarization layer 102 and the outer surface OS of the first substrate 100 may be smaller than the distance between the side surface PASs of the passivation layer PAS and the outer surface OS of the first substrate 100. The distance between the side end 102e of the planarization layer 102 and the side surface PASs of the passivation layer PAS may be greater than the thickness obtained by summing the thickness of the self-luminous device ED and the thickness of the common electrode CE. Therefore, the planarization layer 102 includes a peripheral portion of the side surface 102s and the side end 102e of the planarization layer 102 may cover the side surface PASs of the passivation layer PAS and directly face the top surface of the interlayer insulating layer 101c. Accordingly, the peripheral portion of the planarization layer 102 may have an eaves structure relative to the side surface PASs of the passivation layer PAS.

[0323] According to an embodiment, the side PASs of the passivation layer PAS may be implemented in an inclined structure or a forward tapered structure. For example, the angle between the side PASs of the passivation layer PAS and the interlayer insulating layer 101c may be an acute angle. Therefore, the side PASs of the passivation layer PAS may have an undercut structure relative to the peripheral portion of the planarization layer 102. For example, the upper side portion of the passivation layer PAS provided at one side of the groove line GRV or the boundary portion between the passivation layer PAS and the planarization layer 102 may have an undercut structure relative to the planarization layer 102. Based on the undercut structure, an undercut area UCA may be implemented between the side PASs of the passivation layer PAS and the planarization layer 102, and the undercut area UCA may be a structure for isolating (disconnecting) the peripheral portion of the planarization layer 102 and at least some layers of the light-emitting device layer EDL provided above the groove line GRV. For example, the undercut area UCA between the side surfaces PASs of the passivation layer PAS and the planarization layer 102 may be formed or implemented by an over-etching process performed on the passivation layer PAS.

[0324] The dam 104 according to an embodiment of the present disclosure may be provided or formed to have a closed loop shape at the third margin MA3 of the first substrate 100 or the outermost pixel Po. The dam 104 may surround the groove line GRV and, therefore, may form or realize the other side of the groove line GRV. Accordingly, the groove line GRV may be formed to have a width between the side surface 102s of the planarization layer 102 and the dam 104 that is relatively wider than the dam 104.

[0325] The dam 104 according to an embodiment may be provided above the circuit layer 101 of the outermost pixel Po or the third margin area MA3 of the first substrate 100. For example, the dam 104 may be formed or implemented by performing a patterning process on the passivation layer PAS, the planarization layer 102, and the bank BK provided above the interlayer insulating layer 101c. The dam 104 may prevent diffusion or overflow of the second encapsulation layer 106b (or the organic encapsulation layer) of the encapsulation layer 106 and may isolate (or disconnect) some layers of the light-emitting device layer EDL.

[0326] The dam 104 according to an embodiment of the present disclosure may include a first dam pattern 104 a , a second dam pattern 104 b , and a third dam pattern 104 c .

[0327] The first dam pattern 104 a may be disposed over the outermost pixel Po or the circuit layer 101 of the third margin area MA3 of the first substrate 100 .

[0328] The first dam pattern 104a according to an embodiment may include an inorganic insulating material. For example, the first dam pattern 104a may include the same material as the passivation layer PAS. The first dam pattern 104a may be implemented in a single-layer structure of the passivation layer PAS. In this case, the first dam pattern 104a may be formed or implemented by the portion (or non-patterned area) of the passivation layer PAS that remains above the interlayer insulating layer 101c when the passivation layer PAS is not patterned (or removed) by the patterning process performed on the passivation layer PAS above the interlayer insulating layer 101c provided in the third residual area MA3.

[0329] According to another embodiment, the first dam pattern 104a may be implemented in a stacked structure of the passivation layer PAS and the interlayer insulating layer 101c. In this case, the first dam pattern 104a may be formed or implemented by portions (or unpatterned regions) of the passivation layer PAS and the interlayer insulating layer 101c that remain above the interlayer insulating layer 101c when the passivation layer PAS and the interlayer insulating layer 101c are not patterned (or removed) by the patterning process performed on the passivation layer PAS and the interlayer insulating layer 101c disposed above the buffer layer 101a of the third margin area MA3.

[0330] The side of the first dam pattern 104a according to the embodiment may be implemented in an inclined structure or a forward tapered structure. The lower surface of the first dam pattern 104a may be in direct contact with the upper surface (or surface) of the interlayer insulating layer 101c. The upper surface of the first dam pattern 104a may be disposed above the lower surface of the first dam pattern 104a and may have a width narrower than the lower surface. The side of the first dam pattern 104a may be formed to be inclined between its upper surface and lower surface. In the first dam pattern 104a, the angle between the lower surface and the side may be an acute angle, while the angle between the upper surface and the side may be an obtuse angle. For example, the cross section of the first dam pattern 104a taken along the width direction may have a trapezoidal cross-sectional structure in which the upper side is narrower than the lower side.

[0331] The second dam pattern 104 b may be disposed over the first dam pattern 104 a .

[0332] The second dam pattern 104b according to an embodiment of the present disclosure may include an organic insulating material. For example, the second dam pattern 104b may include the same material as the planarization layer 102. For example, the second dam pattern 104b may have the same height (or thickness) as the planarization layer 102, or may have a height higher than the planarization layer 102. For example, the height (or thickness) of the second dam pattern 104b may be twice the height (or thickness) of the planarization layer 102. The second dam pattern 104b may be formed or implemented by a portion (or unpatterned region) of the planarization layer 102 that remains after the planarization layer 102 has not been patterned (or removed) by the patterning process performed on the planarization layer 102.

[0333] The second dam pattern 104b according to the embodiment may have a width wider than the upper surface of the first dam pattern 104a. The second dam pattern 104b may have a width wider than or equal to the width of the lower surface of the first dam pattern 104a. The side surface of the second dam pattern 104b may be implemented in an inclined structure or a forward tapered structure. For example, the cross section of the second dam pattern 104b obtained along the width direction may have the same trapezoidal cross-sectional structure as the first dam pattern 104a. With respect to the lateral direction, one peripheral portion and the other peripheral portions of the second dam pattern 104b may each protrude to the outside of the side surface of the first dam pattern 104a. For example, the distance between the side end portion of the second dam pattern 104b and the side surface of the first dam pattern 104a may be greater than the thickness obtained by summing the thickness of the self-luminous device ED and the thickness of the common electrode CE.

[0334] According to embodiments, the side surface of the first dam pattern 104a may have an undercut structure relative to the second dam pattern 104b. For example, the dam 104 may include an undercut region UCA disposed at a boundary between the first dam pattern 104a and the second dam pattern 104b, or on an upper side surface of the first dam pattern 104a. The undercut region UCA between the first dam pattern 104a and the second dam pattern 104b may be a structure for isolating (or disconnecting) at least some layers of the light-emitting device layer EDL disposed above the dam 104. For example, the undercut region UCA between the first dam pattern 104a and the second dam pattern 104b may be formed or implemented by an overetching process performed on the passivation layer PAS. Based on the undercut structure of the first dam pattern 104a, the second dam pattern 104b may protrude outward from the side surface of the first dam pattern 104a and, therefore, may cover the side surface of the first dam pattern 104a. Accordingly, the second dam pattern 104b may have an eaves structure relative to the first dam pattern 104a.

[0335] The third dam pattern 104c may be disposed above the second dam pattern 104b. The third dam pattern 104c may have a width less than or equal to the width of the upper surface of the second dam pattern 104b. The side surface of the third dam pattern 104c may be implemented in an inclined structure or a forward tapered structure. For example, the third dam pattern 104c, taken along the lateral direction, may have a trapezoidal cross-sectional structure similar to that of the second dam pattern 104bx.

[0336] The third dam pattern 104c, depending on the embodiment, may include an organic insulating material or an inorganic insulating material. For example, the third dam pattern 104c may be stacked above the second dam pattern 104b and may include the same material as the bank BK. The third dam pattern 104c may be formed or implemented by a portion (or unpatterned area) of the bank BK that remains above the second dam pattern 104b without being patterned (or removed) by the patterning process performed on the bank BK.

[0337] The blocking structure 105 according to an embodiment of the present disclosure may be disposed over the circuit layer 101 of the first substrate 100 or the second margin area MA2 of the outermost pixel Po. The blocking structure 105 may be implemented over the circuit layer 101 to surround the dam 104. For example, the blocking structure 105 may be implemented in the form of a closed loop line shape over the circuit layer 101 to one-dimensionally surround the dam 104.

[0338] The barrier structure 105 according to an embodiment may include at least one of first to third barrier pattern portions 105a, 105b, and 105c, which are parallel to each other and have a closed loop shape. For example, the barrier structure 105 may include first to third barrier pattern portions 105a, 105b, and 105c. Each of the first to third barrier pattern portions 105a, 105b, and 105c may be disposed at an outer region of the dam 104 and may be disposed parallel to each other to surround the dam 104. The spacing between the first to third barrier pattern portions 105a, 105b, and 105c may be greater than the thickness obtained by summing the thickness of the self-luminous device ED and the thickness of the common electrode CE.

[0339] Each of the first to third barrier pattern parts 105 a , 105 b , and 105 c according to an embodiment may include a first barrier pattern BP1 , a second barrier pattern BP2 , and a third barrier pattern BP3 .

[0340] The first barrier pattern BP1 may be disposed to have a closed loop line shape over the outermost pixel Po or the circuit layer 101 of the second margin area MA2 of the first substrate 100 .

[0341] The first barrier pattern BP1 according to an embodiment may be implemented in a single-layer structure of the passivation layer PAS. In this case, the first barrier pattern BP1 may be formed or implemented by a portion (or non-patterned area) of the passivation layer PAS that remains above the interlayer insulating layer 101c when the passivation layer PAS is not patterned (or removed) by the patterning process performed on the passivation layer PAS above the interlayer insulating layer 101c disposed in the second margin area MA2.

[0342] According to another embodiment, the first barrier pattern BP1 may be implemented in a stacked structure of the passivation layer PAS and the interlayer insulating layer 101c. In this case, the first barrier pattern BP1 may be formed or implemented by portions (or unpatterned regions) of the passivation layer PAS and the interlayer insulating layer 101c that remain above the interlayer insulating layer 101c when the passivation layer PAS and the interlayer insulating layer 101c are not patterned (or removed) by the patterning process performed on the passivation layer PAS and the interlayer insulating layer 101c disposed above the buffer layer 101a of the second margin area MA2.

[0343] The side surface of the first barrier pattern BP1 according to an embodiment may be implemented in an inclined structure or a forward tapered structure. For example, a cross-section of the first barrier pattern BP1 taken along the lateral direction may have a trapezoidal cross-sectional structure in which the upper side is narrower than the lower side. Except that the first barrier pattern BP1 has a width smaller than that of the first dam pattern 104a, the first barrier pattern BP1 may have the same structure as the first dam pattern 104a and may be formed together with the first dam pattern 104a, and therefore, their repeated description is omitted. The first barrier pattern BP1 may have a width smaller than that of the first dam pattern 104a.

[0344] The second barrier pattern BP2 may be configured to have a plate shape including a metal layer on the first barrier pattern BP1. According to an embodiment, the second barrier pattern BP2 may include a metal layer having at least a two-layer structure similar to that of the pixel electrode PE. For example, the second barrier pattern BP2 may include a first metal layer formed together with the first pixel electrode layer of the pixel electrode PE and directly contacting the upper surface of the first barrier pattern BP1, and a second metal layer formed together with the second pixel electrode layer of the pixel electrode PE and formed (or stacked) above the first metal layer. The second barrier pattern BP2 may be formed or implemented by a portion (or non-patterned area) of the pixel electrode material remaining above the first barrier pattern BP1 without being patterned (or removed) by the patterning process performed on the pixel electrode PE.

[0345] According to an embodiment, the second barrier pattern BP2 may have a width wider than the upper surface of the first barrier pattern BP1. With respect to the lateral direction, one peripheral edge portion and the other peripheral edge portions of the second barrier pattern BP2 may each protrude outside the side surface of the first barrier pattern BP1. For example, the distance between the side end portion of the second barrier pattern BP2 and the side surface of the first barrier pattern BP1 may be greater than the thickness obtained by summing the thickness of the self-luminous device ED and the thickness of the common electrode CE. For example, the peripheral edge portion of the second barrier pattern BP2 that protrudes outside the side surface of the first barrier pattern BP1 may be referred to as a protruding tip.

[0346] According to another embodiment, the side surface of the second barrier pattern BP2 may be implemented in an inclined structure or a forward tapered structure. For example, a cross-section of the second barrier pattern BP2 taken along the lateral direction may have the same trapezoidal shape as the first barrier pattern BP1 taken along the lateral direction. With respect to the lateral direction, one peripheral edge portion and the other peripheral edge portion of the second barrier pattern BP2 may each protrude outside the side surface of the first barrier pattern BP1. For example, the distance between the side end portion of the second barrier pattern BP2 and the side surface of the first barrier pattern BP1 may be greater than the thickness obtained by summing the thickness of the self-luminous device ED and the thickness of the common electrode CE.

[0347] According to an embodiment, the side surface of the first barrier pattern BP1 may have an undercut structure relative to the second barrier pattern BP2. For example, the barrier structure 105 may include an undercut area UCA disposed at a boundary portion between the first barrier pattern BP1 and the second barrier pattern BP2 or above an upper side surface of the first barrier pattern BP1. The undercut area UCA between the first barrier pattern BP1 and the second barrier pattern BP2 may be a structure for isolating (or disconnecting) at least some of the light-emitting device layers disposed above the barrier structure 105. For example, the undercut area UCA between the first barrier pattern BP1 and the second barrier pattern BP2 may be formed or implemented by an overetching process performed on the passivation layer PAS. The second barrier pattern BP2 may protrude outward from the side surface of the first barrier pattern BP1 based on the undercut structure of the first barrier pattern BP1 and, therefore, may cover the side surface of the first barrier pattern BP1. Accordingly, the second barrier pattern BP2 may have an eaves structure relative to the first barrier pattern BP1.

[0348] The third barrier pattern BP3 may be disposed above the second barrier pattern BP2. The third barrier pattern BP3 may have a width less than or equal to the width of the upper surface of the second barrier pattern BP2. The side surface of the third barrier pattern BP3 may be implemented in an inclined structure or a forward tapered structure. For example, the third barrier pattern BP3 taken along the lateral direction may have a trapezoidal cross-sectional structure similar to that of the second barrier pattern BP2.

[0349] According to embodiments, the third barrier pattern BP3 may include an organic insulating material or an inorganic insulating material. For example, the third barrier pattern BP3 may be stacked above the second barrier pattern BP2 and may include the same material as the bank BK. The third barrier pattern BP3 may be formed or implemented by a portion (or unpatterned area) of the bank BK remaining above the second barrier pattern BP2 when the bank BK is not patterned (or removed) by the patterning process performed on the bank BK together with the third dam pattern 104c of the dam 104.

[0350] According to an embodiment, the undercut area UCA between the side surface PASs of the passivation layer PAS and the planarization layer 102 may be referred to as a first undercut area, a first eaves area, or the like. The first dam pattern 104a may be referred to as an undercut structure, a first undercut structure, or the like. The second dam pattern 104b may be referred to as an eaves structure, a protruding tip structure, a first eaves structure, a first protruding tip structure, or the like. The undercut area UCA between the first dam pattern 104a and the second dam pattern 104b may be referred to as a second undercut area, a second eaves area, or the like. The first barrier pattern BP1 may be referred to as a trench structure, a trench pattern, a tapered structure, a tapered pattern, an undercut structure, a second undercut structure, or the like. The second barrier pattern BP2 may be referred to as an eaves structure, a protruding tip structure, a second eaves structure, a second protruding tip structure, or the like. The undercut area UCA between the first barrier pattern BP1 and the second barrier pattern BP2 may be referred to as a third undercut area, a third eaves area, or the like.

[0351] According to the embodiment of the present disclosure, the groove line GRV, the dam 104, and the blocking structure 105 can each be formed or implemented after the process of forming the bank BK and before the process of forming the self-luminous device ED, and can isolate (or disconnect) the self-luminous device ED during the process of forming (or depositing) the self-luminous device ED.

[0352] According to an embodiment, based on the undercut area UCA (or eaves structure) between the side end 102e of the planarization layer 102 and the side PASs of the passivation layer PAS, the material layer of the self-luminous device ED provided on the peripheral portion of the groove line GRV and the planarization layer 102 can be automatically isolated (or disconnected) when performing the deposition process. For example, the deposited material of the self-luminous device ED may have linearity, and therefore, may not be deposited above the side PASs of the passivation layer PAS covered (or blocked) by the side end 102e of the planarization layer 102, but may be deposited above the interlayer insulating layer 101c in the groove line GRV and the side PASs of the passivation layer PAS, thereby the deposited material of the self-luminous device ED may be isolated (or disconnected) at the undercut area UCA between the side end 102e of the planarization layer 102 and the side PASs of the passivation layer PAS. Accordingly, the self-luminous device ED can be automatically isolated (or disconnected) at the groove line GRV when performing the deposition process.

[0353] According to embodiments, based on the undercut area UCA (eaves structure) between the first and second dam patterns 104a and 104b, the material layer of the self-luminous device ED disposed above the dam 104 can be automatically isolated (or disconnected) during the deposition process. For example, the deposited material of the self-luminous device ED may have a linear structure and, therefore, may not be deposited above the side of the first dam pattern 104a covered (or blocked) by the second dam pattern 104b. Instead, it may be deposited on the upper surface and side surfaces of the dam 104 and above the interlayer insulating layer 101c near the dam 104. As a result, the deposited material of the self-luminous device ED can be isolated (or disconnected) at the undercut area UCA between the first and second dam patterns 104a and 104b. Accordingly, the self-luminous device ED can be automatically isolated (or disconnected) at the dam 104 during the deposition process.

[0354] According to embodiments, based on the undercut area UCA (eaves structure) between the first and second barrier patterns BP1 and BP2 of each of the first to third barrier pattern parts 105a, 105b, and 105c, the material layer of the self-luminous device ED disposed above the barrier structure 105 can be automatically isolated (or disconnected) during a deposition process. For example, the deposited material of the self-luminous device ED may have a linear structure and, therefore, may not be deposited on the side of the first barrier pattern BP1 covered (or blocked) by the second barrier pattern part BP2 of each of the first to third barrier pattern parts 105a, 105b, and 105c. Instead, the deposited material may be deposited on the upper surface and side surfaces of each of the first to third barrier pattern parts 105a, 105b, and 105c and on the interlayer insulating layer 101c between the first to third barrier pattern parts 105a, 105b, and 105c. As a result, the deposited material of the self-luminous device ED can be isolated (or disconnected) at the undercut area UCA between the first and second barrier patterns BP1 and BP2. Accordingly, the self-luminous device ED may be automatically isolated (or disconnected) at each of the first to third barrier pattern parts 105 a , 105 b , and 105 c when the deposition process is performed.

[0355] According to an embodiment, the self-luminous device ED arranged at the outermost pixel Po or the peripheral portion of the first substrate 100 can be isolated (or disconnected) at least three times by the groove line GRV, the dam 104, and the blocking structure 105, and the isolated self-luminous device EDi can be formed into an island shape on the upper surface (or top surface) of each of the interlayer insulating layer 101c arranged above the groove line GRV, the interlayer insulating layer 101c between the dam 104 and the blocking structure 105, and the interlayer insulating layer 101c between the first to third blocking pattern portions 105a, 105b, and 105c of the blocking structure 105.

[0356] According to an embodiment, the self-luminous device ED provided at the outermost pixel Po or the peripheral portion of the first substrate 100 can be individually isolated (or disconnected) by the groove line GRV, the dam 104, and the blocking structure 105 when performing the deposition process, and therefore, a separate patterning process for isolating (or disconnecting) the self-luminous device ED provided at the peripheral portion of the first substrate 100 can be omitted to prevent lateral penetration of water (or water vapor).

[0357] According to an embodiment, a lateral water permeation path of the first substrate 100 may be blocked by the undercut area UCA of each of the groove line GRV, the dam 104 , and the barrier structure 105 .

[0358] Optionally, the common electrode CE arranged above the self-luminous device EDi isolated by the groove line GRV, the dam 104, and the blocking structure 105 may be automatically isolated (or disconnected) by the eaves structure or undercut area UCA of the groove line GRV, the dam 104, and the blocking structure 105 based on the eaves structure or undercut area UCA of the groove line GRV, the dam 104, and the blocking structure 105 and / or the deposition process, or may be formed to surround the self-luminous device pattern EDi that continues without being isolated by the undercut area UCA (or eaves structure) of the blocking structure 105 and is arranged in an island shape above the interlayer insulating layer 101c. For example, the common electrode CE can directly contact the upper surface (or top surface) of the interlayer insulating layer 101c at each of the groove line GRV, the dam 104, and the blocking structure 105, and thus, can seal the boundary portions between the interlayer insulating layer 101 layer and the self-luminous device ED and the self-luminous device pattern EDi, thereby preventing or blocking water (or water vapor) from laterally penetrating through the boundary portions between the interlayer insulating layer 101 layer and the self-luminous device ED and the self-luminous device pattern EDi.

[0359] According to embodiments, the second encapsulation layer 106b (or organic encapsulation layer) formed in the encapsulation region of the display area AA defined by the dam 104 may spread toward the groove line GRV surrounding the side surface 102s of the planarization layer 102 and may completely surround the light-emitting device layer EDL disposed above the upper surface and side surfaces of the planarization layer 102. The second encapsulation layer 106b may spread smoothly through the groove line GRV to the dam 104, thereby completely filling the area adjacent to the inner region of the dam 104. Furthermore, the spreading of the second encapsulation layer 106b may ultimately be blocked by the second dam pattern 104b and the third dam pattern 104c of the dam 104, thereby blocking or preventing overflow of the second encapsulation layer 106b. Accordingly, the dam 104 according to embodiments of the present disclosure may function to physically isolate the light-emitting device layer, prevent the diffusion or overflow of the second encapsulation layer 106b, and prevent water (or water vapor) from penetrating laterally of the substrate 100.

[0360] As described above, in the light-emitting display device according to an embodiment of the present disclosure, the diffusion of the second encapsulation layer 106b can smoothly advance to the dam 104 via the groove line GRV provided between the end of the planarization layer 102 and the dam 104. Therefore, the non-filling phenomenon of the second encapsulation layer 106b in the area adjacent to the inner area of ​​the dam 104 can be prevented or reduced (in some embodiments, minimized). Furthermore, in the light-emitting display device according to an embodiment of the present disclosure, the dam 104 provided at the periphery of the first substrate 100 (or the outermost pixel) can include the functions of isolating the self-luminous device ED, blocking the diffusion or overflow of the organic encapsulation layer, and preventing the penetration of water (or water vapor), thereby preventing the reliability of the self-luminous device ED from being reduced due to the lateral penetration of water (or water vapor). Because the dam 104 is provided at the periphery of the outermost pixel, the light-emitting display device can prevent the reliability of the self-luminous device ED from being reduced due to the lateral penetration of water (or water vapor), and can have an air frame structure that does not include a frame area or has a zero frame.

[0361] In addition, if Figure 3 As shown in FIG, a second barrier pattern BP2 having a metal layer, disposed in at least one of the first to third barrier pattern sections 105a, 105b, and 105c of the barrier structure 105, can be electrically connected to at least one pixel common voltage line CVL via a via hole VH formed in the first barrier pattern BP1. For example, the via hole VH can be formed to sequentially penetrate the passivation layer PAS, the interlayer insulating layer 101c, and the buffer layer 101a, disposed at the intersection between the pixel common voltage line CVL and the second barrier pattern BP2 having a closed-loop line shape. Therefore, the second barrier pattern BP2, disposed in at least one of the first to third barrier pattern sections 105a, 105b, and 105c, can be electrically connected to at least one pixel common voltage line CVL via the corresponding via hole VH. Accordingly, the second barrier pattern BP2 can form an equivalent electric potential with the plurality of pixel common voltage lines CVL and can primarily block static electricity flowing from the exterior to the interior of the display area AA, thereby preventing defects caused by static electricity. For example, the second barrier pattern BP2 disposed in at least one of the first to third barrier pattern parts 105 a , 105 b , and 105 c may discharge static electricity flowing from the outside to the pixel common voltage line CVL to prevent defects caused by the static electricity.

[0362] Figure 12 It is along Figure 7 Another cross-sectional view taken along the straight line II' shown in FIG. Figure 13 It is along Figure 7 Another cross-sectional view taken along the line II-II' shown in FIG. Figure 14 yes Figure 12The accompanying drawings illustrate the improved Figures 1 to 12 In the following description, therefore, the trench lines, dams, and barrier structures, respectively, and elements related thereto are referred to by similar reference numerals, and therefore, their repeated descriptions are omitted or will be briefly given. Figure 12 An enlarged view of area "B" shown in FIG. Figure 9 middle

[0363] Reference Figure 7 and Figures 12 to 14 The light-emitting display device or the first substrate 100 according to an embodiment of the present disclosure may further include an auxiliary insulating layer 103 disposed between the light-emitting device layer EDL and the planarization layer 102 .

[0364] The auxiliary insulating layer 103 may include an electrode contact hole overlapping the electrode contact hole ECH formed at the planarizing layer 102. The electrode contact hole ECH may be formed by patterning the planarizing layer 102 and the auxiliary insulating layer 103 overlapping the portion of the first source / drain electrode SD1 of the driving TFT Tdr.

[0365] Furthermore, the remaining auxiliary insulating layer 103 except for the peripheral portion of the first substrate 100 or the peripheral portion of the outermost pixel Po may be removed from the auxiliary insulating layer 103. For example, the auxiliary insulating layer 103 may have a closed loop shape only at the peripheral portion of the first substrate 100 or the peripheral portion of the outermost pixel Po. For example, the auxiliary insulating layer 103 may be provided only over the first to third margin areas MA1, MA2, and MA3 of the first substrate 100.

[0366] The auxiliary insulating layer 103 according to an embodiment may be formed of an inorganic insulating material. For example, the auxiliary insulating layer 103 may include a single layer structure containing one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof. The auxiliary insulating layer 103 may be referred to as an inorganic insulating layer, a second inorganic insulating layer, a third insulating layer, an additional insulating layer, or the like.

[0367] The auxiliary insulating layer 103 may be disposed above the planarization layer 102. The auxiliary insulating layer 103 may directly contact the upper surface (or top surface) of the planarization layer 102, may be supported by the planarization layer 102, and may support the bank BK. For example, the auxiliary insulating layer 103 disposed in the display area AA other than the outermost pixel Po or the peripheral portion of the first substrate 100 may be disposed between the planarization layer 102 and the pixel electrode PE, and may be disposed between the bank BK and the planarization layer 102. Accordingly, the auxiliary insulating layer 103 may be disposed between the planarization layer 102 and each of the light-emitting device layer EDL and the bank BK.

[0368] The groove line GRV according to another embodiment of the present disclosure may be disposed or formed to have a closed loop line shape at the outermost pixel Po or the first margin area MA1 of the first substrate 100 .

[0369] The groove line GRV according to the embodiment may correspond to an area from which all structures in the diffusion path through which the encapsulation layer 106 diffuses to the dam 104 have been removed. The groove line GRV may be an area from which all of a single structure or a multi-layer structure, including at least one of the planarization layer 102, the auxiliary insulating layer 103, the pixel electrode material layer, and the bank BK arranged near the inner area of ​​the dam 104, have been removed. The groove line GRV may be implemented to expose the passivation layer PAS arranged at the outermost pixel Po or the first margin area MA1 of the first substrate 100. For example, the groove line GRV may be formed or implemented by patterning (or removing) the planarization layer 102, the auxiliary insulating layer 103, the pixel electrode material layer, and the bank BK arranged above the passivation layer PAS in the first margin area MA1. Accordingly, the groove line GRV may define the side surface 102s of the planarization layer 102 and may have a closed loop line shape surrounding the side surface 102s of the planarization layer 102.

[0370] According to an embodiment, the groove line GRV can be formed by patterning (or removing) each of the passivation layer PAS, the planarization layer 102, and the auxiliary insulating layer 103, and thus, the uppermost surface (or topmost surface) of the passivation layer PAS can be exposed. For example, the groove line GRV may include a main groove line and a secondary groove line, the main groove line being formed above the passivation layer PAS by a patterning process of patterning the planarization layer 102 to form the electrode contact hole ECH of the TFT, and the secondary groove line being formed above the passivation layer PAS by a patterning process of patterning the auxiliary insulating layer 103 provided at the main groove line. The passivation layer PAS may be exposed by the groove line GRV between the end 102e of the planarization layer 102 and the dam 104, and thus, the bottom surface of the groove line GRV can be realized. For example, the groove line GRV may have a width wider than or equal to the width of the dam 104.

[0371] One side of the groove line GRV may define a side surface 102s of the planarization layer 102 disposed over the first substrate 100 or the display area AA, and may have a closed loop line shape surrounding the side surface 102s of the planarization layer 102. For example, each side surface 102s of the planarization layer 102 may be exposed at the groove line GRV to realize one sidewall of the groove line GRV.

[0372] According to an embodiment, the end portion of the auxiliary insulating layer 103 disposed above the planarization layer 102 may protrude from the side surface 102s of the planarization layer 102 toward the center portion (or dam 104) of the groove line GRV. For example, the distance between the end portion of the auxiliary insulating layer 103 and the outer surface OS of the first substrate 100 may be smaller than the distance between the side surface 102s of the planarization layer 102 and the outer surface OS of the first substrate 100. The distance between the side surface 102s of the planarization layer 102 and the end portion of the auxiliary insulating layer 103 may be greater than the thickness obtained by summing the thickness of the self-luminous device ED and the thickness of the common electrode CE. Therefore, the peripheral portion 103e of the auxiliary insulating layer 103, including the end portion of the auxiliary insulating layer 103, may cover the side surface 102s of the planarization layer 102 and may directly face the upper surface of the passivation layer PAS. Accordingly, the peripheral portion 103e of the auxiliary insulating layer 103 may have an eaves structure relative to the side surface 102s of the planarization layer 102. For example, the peripheral edge portion 103 e of the auxiliary insulating layer 103 may be referred to as a protruding tip or a first protruding tip.

[0373] According to an embodiment, the side surface 102s of the planarization layer 102 may be implemented in an inclined structure or a forward tapered structure. For example, the angle between the side surface 102s of the planarization layer 102 and the passivation layer PAS may be an acute angle. Therefore, the side surface 102s of the planarization layer 102 may have an undercut structure relative to the peripheral portion 103e (protruding tip) of the auxiliary insulating layer 103. For example, the upper side portion of the planarization layer 102 disposed at one side of the groove line GRV may have an undercut structure relative to the auxiliary insulating layer 103. Based on the undercut structure, an undercut area UCA may be implemented between the side surface 102s of the planarization layer 102 and the auxiliary insulating layer 103, and the undercut area UCA may be a structure for isolating (disconnecting) at least some layers of the light-emitting device layer EDL disposed above the groove line GRV and the peripheral portion 103e (protruding tip) of the auxiliary insulating layer 103. For example, the undercut area UCA between the side surface 102 s of the planarization layer 102 and the peripheral edge portion 103 e (protruding tip) of the auxiliary insulating layer 103 may be formed or implemented by an over-etching process performed on the planarization layer 102 .

[0374] In addition, if Figure 11As shown in FIG, the bottom surface of the groove line GRV may be implemented as the upper surface (or top surface) of the interlayer insulating layer 101c. In this case, the groove line GRV may be a region from which all of the single structure or the multi-layer structure, including at least one of the passivation layer PAS disposed above the interlayer insulating layer 101c near the inner region of the dam 104, the planarization layer 102, the pixel electrode material layer, and the bank BK, has been removed.

[0375] The dam 104 according to an embodiment of the present disclosure may be provided or formed to have a closed loop shape at the third margin MA3 of the first substrate 100 or the outermost pixel Po. The dam 104 may surround the groove line GRV and, therefore, may form or realize the other side of the groove line GRV. Accordingly, the groove line GRV may be formed to have a width between the side surface 102s of the planarization layer 102 and the dam 104 that is relatively wider than the dam 104.

[0376] The dam 104 according to an embodiment may be provided above the passivation layer PAS of the outermost pixel Po or the third margin area MA3 of the first substrate 100. For example, the dam 104 may be formed or implemented by a patterning process performed on the planarization layer 102 and the bank BK provided above the passivation layer PAS. The dam 104 may prevent diffusion or overflow of the second encapsulation layer 106b (or organic encapsulation layer) of the encapsulation layer 106 and may isolate (or disconnect) some layers of the light-emitting device layer EDL.

[0377] The dam 104 according to an embodiment of the present disclosure may include a first dam pattern 104 d , a second dam pattern 104 e , a third dam pattern 104 f , and a fourth dam pattern 104 g .

[0378] The first dam pattern 104 d may be disposed over the passivation layer PAS of the outermost pixel Po or the third margin area MA3 of the first substrate 100 .

[0379] According to an embodiment, the first dam pattern 104d may include an inorganic insulating material. For example, the first dam pattern 104d may include the same material as the planarization layer 102. For example, the first dam pattern 104d may be formed or implemented by a portion (or non-patterned region) of the planarization layer 102 that remains above the passivation layer PAS when the planarization layer 102 is not patterned (or removed) by the patterning process performed on the passivation layer PAS disposed above the third margin area MA3.

[0380] According to an embodiment, the first dam pattern 104d may include a lower surface (or bottom surface) directly contacting the passivation layer PAS, an inclined side surface (or sidewall) perpendicular to the lower surface in the thickness direction Z of the first substrate 100, and an upper surface (or top surface) parallel to the lower surface and directly contacting the second dam pattern 104e. For example, in the first dam pattern 104d, the width of the lower surface may be wider than the upper surface, and thus, the side surface may be implemented in an inclined structure or a forward tapered structure. For example, the first dam pattern 104d taken along the first direction X may have a trapezoidal cross-sectional structure in which the upper side is narrower than the lower side.

[0381] According to an embodiment, the first dam pattern 104d may have the same height (or thickness) as the planarization layer 102, or may have a height higher than the planarization layer 102. For example, the height (or thickness) of the first dam pattern 104d may be twice that of the planarization layer 102.

[0382] The second dam pattern 104 e may be disposed over the first dam pattern 104 d .

[0383] According to an embodiment, the second dam pattern 104e may include an inorganic insulating material. For example, the second dam pattern 104e may include the same material as the auxiliary insulating layer 103. For example, the second dam pattern 104e may be formed or implemented by a portion (or non-patterned area) of the auxiliary insulating layer 103 that remains above the first dam pattern 104d when the auxiliary insulating layer 103 is not patterned (or removed) by the patterning process performed on the auxiliary insulating layer 103 above the first dam pattern 104d.

[0384] According to an embodiment, the second dam pattern 104e may have a width wider than the upper surface of the first dam pattern 104d. The second dam pattern 104e may have a width wider than or equal to the upper surface of the first dam pattern 104d. Therefore, the second dam pattern 104e may include a protruding tip (or isolated tip) 104t that protrudes to the outside of the side surface of the first dam pattern 104d. For example, the peripheral edge portion of the second dam pattern 104e may protrude to cover or occlude the side surface of the first dam pattern 104d, thereby forming the protruding tip 104t. For example, the distance between the end of the protruding tip 104t of the second dam pattern 104e and the side surface of the first dam pattern 104d may be greater than the thickness obtained by summing the thickness of the self-luminous device ED and the thickness of the common electrode CE. For example, the protruding tip 104t of the second dam pattern 104e may be referred to as a second protruding tip.

[0385] According to embodiments, the side surfaces of the first dam pattern 104d may have an undercut structure relative to the second dam pattern 104e. For example, the dam 104 may include an undercut region UCA disposed on the upper side surface of the first dam pattern 104a or at the boundary between the first dam pattern 104d and the second dam pattern 104e. The undercut region UCA between the first dam pattern 104d and the second dam pattern 104e may be a structure for isolating (or disconnecting) at least some layers of the light-emitting device layer EDL disposed above the dam 104. For example, the undercut region UCA between the first dam pattern 104d and the second dam pattern 104e may be formed or implemented by an overetching process performed on the planarization layer 102. The second dam pattern 104e may protrude beyond the side surfaces of the first dam pattern 104a and may cover the side surfaces of the first dam pattern 104d. Accordingly, the second dam pattern 104e may have an eaves structure relative to the first dam pattern 104d.

[0386] The third dam pattern 104f may be disposed above the second dam pattern 104e. The third dam pattern 104f may have a width less than or equal to that of the upper surface of the second dam pattern 104e. The side surface of the third dam pattern 104f may be implemented in an inclined structure or a forward tapered structure. For example, the third dam pattern 104f taken along the lateral direction may have a trapezoidal cross-sectional structure similar to that of the second dam pattern 104e.

[0387] The third dam pattern 104f may include a metal material above the second dam pattern 104e. According to an embodiment, the third dam pattern 104f may include a metal layer having the same at least two-layer structure as the pixel electrode PE. For example, the third dam pattern 104f may include a first metal layer formed together with the first pixel electrode layer of the pixel electrode PE and directly contacting the upper surface of the second dam pattern 104e, and a second metal layer formed together with the second pixel electrode layer of the pixel electrode PE and disposed (or stacked) above the first metal layer. The third dam pattern 104f may be formed or implemented by a portion (or unpatterned area) of the pixel electrode material remaining above the second dam pattern 104e without being patterned (or removed) by the patterning process performed on the pixel electrode PE.

[0388] The fourth dam pattern 104g may be stacked above the third dam pattern 104f. The fourth dam pattern 104g may have a width less than or equal to the width of the upper surface of the third dam pattern 104f. The side surface of the fourth dam pattern 104g may be implemented in an inclined structure or a forward tapered structure. For example, the fourth dam pattern 104g taken along the lateral direction may have a trapezoidal cross-sectional structure similar to that of the third dam pattern 104f.

[0389] The fourth dam pattern 104g, according to embodiments, may include an organic insulating material or an inorganic insulating material. For example, the fourth dam pattern 104g may be stacked above the third dam pattern 104f and may include the same material as the bank BK. The fourth dam pattern 104g may be formed or implemented by a portion (or unpatterned area) of the bank BK that remains above the third dam pattern 104f without being patterned (or removed) by the patterning process performed on the bank BK. The fourth dam pattern 104g may prevent etching of the second dam pattern 104e and the third dam pattern 104f.

[0390] A blocking structure 105 according to another embodiment may be provided over the passivation layer PAS of the outermost pixel Po or the second margin area MA2 of the first substrate 100. The blocking structure 105 may be implemented over the passivation layer PAS to surround the dam 104. For example, the blocking structure 105 may be implemented in a closed loop shape over the passivation layer PAS to one-dimensionally surround the dam 104.

[0391] The barrier structure 105 according to another embodiment may include a plurality of first and second barrier pattern portions 105a and 105b implemented in parallel with each other to have a closed loop line shape. For example, the barrier structure 105 may include the first and second barrier pattern portions 105a and 105b.

[0392] The first and second barrier pattern portions 105a and 105b may be disposed at outer areas of the dam 104 and may be disposed in parallel to surround the dam 104. An interval between the first and second barrier pattern portions 105a and 105b may be greater than a thickness obtained by summing the thickness of the self-luminous device ED and the thickness of the common electrode CE.

[0393] Each of the first and second barrier pattern parts 105 a and 105 b according to an embodiment may include a first barrier pattern BPa and a second barrier pattern BPb.

[0394] The first barrier pattern BPa may be disposed to have a closed loop line shape over the passivation layer PAS of the outermost pixel Po or the second margin area MA2 of the first substrate 100 .

[0395] The first barrier pattern BPa according to an embodiment may include an organic insulating material. For example, the first barrier pattern BPa may include the same material as the planarization layer 102. For example, the first barrier pattern BPa may be formed or implemented by a portion (or non-patterned region) of the planarization layer 102 that remains above the passivation layer PAS when the planarization layer 102 is not patterned (or removed) by the patterning process performed on the passivation layer PAS disposed above the second margin area MA2.

[0396] The first barrier pattern BPa according to an embodiment may include a lower surface (or bottom surface) directly contacting the passivation layer PAS, an inclined side surface (or sidewall) perpendicular to the lower surface in the thickness direction Z of the first substrate 100, and an upper surface (or top surface) parallel to the circular surface and directly contacting the second dam pattern 104e. For example, in the first barrier pattern BPa, the width of the bottom surface may be wider than the upper surface, and thus, the side surface may be implemented in an inclined structure or a forward tapered structure. For example, the first barrier pattern BPa taken along the first direction X may have a trapezoidal cross-sectional structure in which the upper side is narrower than the lower side.

[0397] The first barrier pattern BPa according to an embodiment may have the same height (or thickness) as the planarization layer 102, or may have a height higher than the planarization layer 102. For example, the height (or thickness) of the first barrier pattern BPa may be twice that of the planarization layer 102.

[0398] The second barrier pattern BPb may be disposed over the first barrier pattern BPa.

[0399] According to an embodiment, the second barrier pattern BPb may include an inorganic insulating material. For example, the second barrier pattern BPb may include the same material as the auxiliary insulating layer 103. For example, the second barrier pattern BPb may be formed or implemented by a portion (or non-patterned area) of the auxiliary insulating layer 103 that remains above the first barrier pattern BPa when the auxiliary insulating layer 103 is not patterned (or removed) by the patterning process performed on the auxiliary insulating layer 103 above the first barrier pattern BPa.

[0400] According to an embodiment, the second barrier pattern BPb may have a width wider than the upper surface of the first barrier pattern BPa. The second barrier pattern BPb may have a width wider than or equal to the upper surface of the first barrier pattern BPa. Therefore, the second barrier pattern BPb may include a protruding tip (or isolated tip) 105t that protrudes to the outside of the side surface of the first barrier pattern BPa. For example, the peripheral edge portion of the second barrier pattern BPb may protrude to cover or occlude the side surface of the first barrier pattern BPa to form the protruding tip 105t. For example, the distance between the end of the protruding tip 105t of the second barrier pattern BPb and the side surface of the first barrier pattern BPa may be greater than the thickness obtained by summing the thickness of the self-luminous device ED and the thickness of the common electrode CE. For example, the protruding tip 105t of the second barrier pattern BPb may be referred to as a third protruding tip.

[0401] According to an embodiment, the side surface of the first barrier pattern BPa may have an undercut structure relative to the second barrier pattern BPb. For example, the barrier structure 105 may include an undercut region UCA disposed on the upper side surface of the first barrier pattern BPa or in the boundary portion between the first barrier pattern BPa and the second barrier pattern BPb. The undercut region UCA between the first barrier pattern BPa and the second barrier pattern BPb may be a structure for isolating (or disconnecting) at least some layers of the light-emitting device layer EDL disposed above the barrier structure 105. For example, the undercut region UCA between the first barrier pattern BPa and the second barrier pattern BPb may be formed or implemented by an over-etching process performed on the planarization layer 102. The second barrier pattern BPa may protrude outward from the side surface of the first barrier pattern BPa based on the undercut structure of the first barrier pattern BPa and may cover the side surface of the first barrier pattern BPa. Accordingly, the second barrier pattern BPb may have an eaves structure relative to the first barrier pattern BPa.

[0402] According to embodiments, the undercut region UCA between the side surface 102s of the planarization layer 102 and the peripheral edge portion 103e (protruding tip) of the auxiliary insulating layer 103 may be referred to as a first undercut region, a first eaves region, or the like. The first dam pattern 104d may be referred to as an undercut structure, a first undercut structure, or the like. The second dam pattern 104e may be referred to as an eaves structure, a protruding tip structure, a first eaves structure, a first protruding tip structure, or the like. The undercut region UCA between the first dam pattern 104d and the second dam pattern 104e may be referred to as a second undercut region, a second eaves region, or the like. The first barrier pattern BPa may be referred to as an undercut structure, a second undercut structure, or the like. The second barrier pattern BPb may be referred to as an eaves structure, a protruding tip structure, a third eaves structure, a third protruding tip structure, or the like. The undercut region UCA between the first barrier pattern BPa and the second barrier pattern BPb may be referred to as a third undercut region, a third eaves region, or the like.

[0403] According to the embodiment of the present disclosure, the groove line GRV, the dam 104, and the blocking structure 105 can each be formed or implemented after the process of forming the bank BK and before the process of forming the self-luminous device ED, and can isolate (or disconnect) the self-luminous device ED during the process of forming (or depositing) the self-luminous device ED.

[0404] According to an embodiment, based on the undercut area UCA (or eaves structure) between the side surface 102s of the planarization layer 102 and the peripheral portion 103e (protruding tip) of the auxiliary insulating layer 103, the material layer of the self-luminous device ED disposed above the groove line GRV and the peripheral portion of the planarization layer 102 can be automatically isolated (or disconnected) during the deposition process. For example, the deposited material of the self-luminous device ED may have a linear structure and, therefore, may not be deposited above the side surface 102s of the planarization layer 102 covered (or blocked) by the peripheral portion 103e (protruding tip) of the auxiliary insulating layer 103. Instead, it may be deposited above the passivation layer PAS in the groove line GRV and the peripheral portion 103e (protruding tip) of the auxiliary insulating layer 103. As a result, the deposited material of the self-luminous device ED can be isolated (or disconnected) at the undercut area UCA between the side surface 102s of the planarization layer 102 and the peripheral portion 103e (protruding tip) of the auxiliary insulating layer 103. Accordingly, the self-luminous device ED can be automatically isolated (or disconnected) at the groove line GRV when performing the deposition process.

[0405] According to embodiments, based on the undercut area UCA (eaves structure) between the first dam pattern 104d and the second dam pattern 104e, the material layer of the self-luminous device ED disposed above the dam 104 can be automatically isolated (or disconnected) during the deposition process. For example, the deposited material of the self-luminous device ED may have a linear structure and, therefore, may not be deposited on the side of the first dam pattern 104d covered (or blocked) by the second dam pattern 104e. Instead, it may be deposited on the upper surface and side surfaces of the dam 104 and on the passivation layer PAS near the dam 104. As a result, the deposited material of the self-luminous device ED can be isolated (or disconnected) in the undercut area UCA between the first dam pattern 104d and the second dam pattern 104e. Accordingly, the self-luminous device ED can be automatically isolated (or disconnected) within the dam 104 during the deposition process.

[0406] According to embodiments, based on the undercut area UCA (eaves structure) between the first and second barrier patterns BPa and BPb of each of the first and second barrier pattern sections 105a and 105b, the material layer of the self-luminous device ED disposed above the barrier structure 105 can be automatically isolated (or disconnected) during the deposition process. For example, the deposited material of the self-luminous device ED may have a linear structure and, therefore, may not be deposited on the side of the first barrier pattern BPa covered (or blocked) by the second barrier pattern section BPb of each of the first and second barrier pattern sections 105a and 105b. Instead, the deposited material may be deposited on the upper surface and side surfaces of each of the first and second barrier pattern sections 105a and 105b and on the passivation layer PAS between the first to third barrier pattern sections 105a, 105b, and 105c. As a result, the deposited material of the self-luminous device ED can be isolated (or disconnected) at the undercut area UCA between the first and second barrier patterns BPa and BPb. Accordingly, the self-luminous device ED may be automatically isolated (or disconnected) at each of the first and second barrier pattern parts 105 a and 105 b of the barrier structure 105 when the deposition process is performed.

[0407] According to an embodiment, the self-luminous device ED arranged at the outermost pixel Po or the peripheral portion of the first substrate 100 can be isolated (or disconnected) at least three times by the groove line GRV, the dam 104, and the blocking structure 105, and the isolated self-luminous device EDi can be formed into an island shape on the upper surface (or top surface) of the passivation layer PAS arranged above the groove line GRV, the passivation layer PAS between the dam 104 and the blocking structure 105, and the passivation layer PAS between the first and second blocking pattern portions 105a and 105b of the blocking structure 105.

[0408] According to an embodiment, the self-luminous device ED provided at the outermost pixel Po or the peripheral portion of the first substrate 100 can be individually isolated (or disconnected) by the groove line GRV, the dam 104, and the blocking structure 105 when performing the deposition process, and therefore, a separate patterning process for isolating (or disconnecting) the self-luminous device ED provided at the peripheral portion of the first substrate 100 can be omitted to prevent lateral penetration of water (or water vapor).

[0409] According to an embodiment, a lateral water permeation path of the first substrate 100 may be blocked by the undercut area UCA of each of the groove line GRV, the dam 104 , and the barrier structure 105 .

[0410] Optionally, the common electrode CE arranged above the self-luminous device EDi isolated by the groove line GRV, the dam 104, and the blocking structure 105 may be automatically isolated (or disconnected) by the eaves structure or undercut area UCA of the groove line GRV, the dam 104, and the blocking structure 105 based on the eaves structure or undercut area UCA of the groove line GRV, the dam 104, and the blocking structure 105 and / or the deposition process, or may be formed to surround the self-luminous device pattern EDi that continues without being isolated by the undercut area UCA (or eaves structure) of the blocking structure 105 and is arranged in an island shape above the passivation layer PAS. For example, the common electrode CE may directly contact the upper surface (or top surface) of the passivation layer PAS at each of the groove line GRV, the dam 104, and the blocking structure 105, and thus, may seal the boundary portions between the passivation layer PAS and each of the self-luminous device ED and the self-luminous device pattern EDi, thereby preventing or blocking water (or water vapor) from laterally penetrating through the boundary portions between the interlayer insulating layer 101 and each of the self-luminous device ED and the self-luminous device pattern EDi.

[0411] According to embodiments, the second encapsulation layer 106b (or organic encapsulation layer) formed in the encapsulation region of the display area AA defined by the dam 104 may spread toward the groove line GRV surrounding the side surface 102s of the planarization layer 102 and may completely surround the light-emitting device layer EDL disposed above the upper surface and side surfaces of the planarization layer 102. The second encapsulation layer 106b may spread smoothly through the groove line GRV to the dam 104, thereby completely filling the area adjacent to the inner region of the dam 104. Furthermore, the spreading of the second encapsulation layer 106b may ultimately be blocked by the second dam pattern 104b and the third dam pattern 104c of the dam 104, thereby blocking or preventing overflow of the second encapsulation layer 106b. Accordingly, the dam 104 according to embodiments of the present disclosure may function to physically isolate the light-emitting device layer, prevent the diffusion or overflow of the second encapsulation layer 106b, and prevent water (or water vapor) from penetrating laterally of the substrate 100.

[0412] In addition, similar to the above reference Figure 3The third dam pattern 104f of the dam 104 can be electrically connected to at least one pixel common voltage line CVL via a via hole VH, as described above. For example, the via hole VH can be formed to sequentially pass through the second dam pattern 104e, the first dam pattern 104d, the passivation layer PAS, the interlayer insulating layer 101c, and the buffer layer 101a, located at the intersection between the pixel common voltage line CVL and the third dam pattern 104f having a closed-loop shape. Thus, the third dam pattern 104f of the dam 104 can be electrically connected to at least one pixel common voltage line CVL via the corresponding via hole VH. Accordingly, the third dam pattern 104f of the dam 104 can form an equivalent electric potential with the plurality of pixel common voltage lines CVL and can primarily block static electricity flowing from the outside to the inside of the display area AA, thereby preventing defects caused by static electricity. For example, the third dam pattern 104f of the dam 104 can discharge static electricity flowing from the outside to the pixel common voltage line CVL, thereby preventing defects caused by static electricity.

[0413] As mentioned above, similar to the above reference Figures 1 to 11 The light-emitting display device described, the light-emitting display device according to another embodiment of the present disclosure can prevent or minimize the non-filling phenomenon of the second encapsulation layer 106b, prevent the reliability of the self-luminous device ED caused by lateral penetration of water, and prevent the reliability of the self-luminous device ED caused by lateral penetration of water because the dam 104 is set at the peripheral portion of each outermost pixel, and therefore, the light-emitting display device according to another embodiment of the present disclosure can have an air frame structure that does not include a frame area or has a zero frame.

[0414] Figure 15 yes Figure 11 Microscope photograph of the undercut region of the passivation layer is shown in FIG.

[0415] like Figure 15 As shown in FIG, it can be seen that the end portion 102e of the planarization layer 102 according to an embodiment of the present disclosure protrudes from the side surface PASs of the passivation layer PAS and thus has an eaves structure relative to the side surface PASs of the passivation layer PAS. Accordingly, according to an embodiment of the present disclosure, the protruding tip of the planarization layer 102 having an eaves structure relative to the passivation layer PAS can be formed, and thus, the self-luminous device can be automatically isolated by the deposition process performed on the light-emitting material without a separate isolation process.

[0416] Figure 16 yes Figure 11 Microscope photograph of the undercut region of the passivation layer shown in . Figure 16 , the white layer WL is a coating layer that is experimentally coated to identify the cross-sectional structure of a deposited material, and thus, may not correspond to an element of a light-emitting display device according to an embodiment of the present disclosure.

[0417] like Figure 16 As shown in , it can be seen that the end portion of the auxiliary insulating layer 103 according to the embodiment of the present disclosure protrudes from the side surface 102s of the planarization layer 102 to form a protruding tip 103t, and therefore, the protruding tip 103t of the auxiliary insulating layer 103 has an eaves structure relative to the side surface 102s of the planarization layer 102. Accordingly, according to the embodiment of the present disclosure, the protruding tip 103t of the auxiliary insulating layer 103 having an eaves structure relative to the planarization layer 102 can be formed, and therefore, the self-luminous device can be automatically isolated by the deposition process performed on the light-emitting material without a separate isolation process.

[0418] Figure 17 is a diagram illustrating a multi-screen light-emitting display device according to an embodiment of the present disclosure, Figure 18 It is along Figure 17 A cross-sectional view taken along line III-III' shown in FIG. Figure 17 and Figure 18 Illustrated by splicing Figures 1 to 16 A multi-screen light-emitting display device is implemented by a light-emitting display device according to another embodiment of the present disclosure as shown in FIG.

[0419] Reference Figure 17 and Figure 18 , a multi-screen light-emitting display device (or a spliced ​​light-emitting display device) according to an embodiment of the present disclosure may include a plurality of display devices DM1 to DM4.

[0420] The plurality of display devices DM1 to DM4 may each display a separate image or may display one image in a divided manner. Figures 1 to 16 The light emitting display devices according to the embodiments of the present disclosure are shown in FIG, and thus, their repeated descriptions are omitted or will be briefly given.

[0421] Multiple display devices DM1 to DM4 can be spliced ​​on a separate splicing frame so as to contact each other at their sides. For example, multiple display devices DM1 to DM4 can be spliced ​​to have an N×M format, thereby realizing a multi-screen light-emitting display device with a large screen. For example, N is a positive integer of 1 or greater and M is a positive integer of 2 or greater, but embodiments of the present disclosure are not limited thereto. For example, N is a positive integer of 2 or greater and M is a positive integer of 1 or greater.

[0422] Each of the plurality of display devices DM1 to DM4 may not include a frame area (or non-display portion) surrounding the display area AA where all images are displayed, but may have an air frame structure where the display area AA is surrounded by air. For example, in each of the plurality of display devices DM1 to DM4, the first surface of all the first substrates 100 may be implemented as the display area AA.

[0423] According to an embodiment, in each of the plurality of display devices DM1 to DM4, the second interval D2 between the center portion CP of the outermost pixel Po and the outermost outer surface VL of the first substrate 100 may be implemented to be half or less of the first interval D1 (or pixel pitch) between adjacent pixels. Accordingly, in two adjacent display devices DM1 to DM4 coupled (or in contact) with each other at their sides along the first direction X and the second direction Y in a lateral coupling manner, the interval "D2+D2" between adjacent outermost pixel areas PAo may be equal to or less than the first interval D1 between two adjacent pixels. Figure 18 , in the first and third display devices DM1 and DM3 coupled (or in contact with) each other at their sides along the second direction, the interval "D2+D2" between the center portion CP of the outermost pixel Po of the first display device DM1 and the center portion CP of the outermost pixel Po of the third display device DM3 may be equal to or less than the first interval (or pixel pitch) between two adjacent pixels set at each of the first and third display devices DM1 and DM3.

[0424] Therefore, the interval "D2+D2" between the center portions CP of the outermost pixels Po of two adjacent display devices DM1 to DM4 coupled (or contacting) each other at their sides along the first direction X and the second direction Y can be less than or equal to the first interval D1 provided between two adjacent pixels provided at each of the display devices DM1 to DM4. Therefore, there can be no gap or boundary portion between the two adjacent display devices DM1 to DM4, and thus there can be no dark area caused by the boundary portion provided between the two adjacent display devices DM1 to DM4. As a result, the image displayed on the multi-screen display device in which the plurality of display devices DM1, DM2, DM3, and DM4 are each spliced ​​in an N×M form can be continuously displayed without a sense of disconnection (or discontinuity) at the boundary portion between the plurality of display devices DM1, DM2, DM3, and DM4.

[0425] exist Figure 11 and Figure 18 In the embodiment, the plurality of display devices DM1 to DM4 are shown to be spliced ​​in a 2×2 form, but the embodiments of the present disclosure are not limited thereto, and the plurality of display devices DM1 to DM4 can be spliced ​​in an x×1 form, a 1×y form, or an x×y form. For example, x and y can be natural numbers of 2 or greater, which are equal to or different from each other. For example, x can be a natural number of 2 or greater or equal to y. y can be a natural number of 2 or greater or greater than or less than x.

[0426] As described above, when the display area AA of each of the multiple display devices DM1 to DM4 is one screen and displays one image, the multi-screen display device according to an embodiment of the present disclosure can display an image that is not disconnected and continuous at the boundary portions between the multiple display devices DM1 to DM4, and thus, can enhance the sense of immersion of the user who watches the image displayed by the multi-screen light-emitting display device.

[0427] Hereinafter, a light-emitting display device according to an embodiment of the present disclosure and a multi-screen light-emitting display device including the same will be described.

[0428] According to an embodiment of the present disclosure, a light-emitting display device may include a light-emitting display device, which includes: a substrate configured to include a display area; a planarization layer arranged above the display area; a groove line arranged along a peripheral portion of the substrate and configured to surround a side of the planarization layer; a dam configured to surround the groove line; a light-emitting device layer configured to include a self-luminous device arranged above the planarization layer, the groove line, and the dam; an encapsulation layer, the encapsulation layer being configured to include an organic encapsulation layer arranged above an encapsulation area surrounded by the dam, the organic encapsulation layer being configured to fill the groove line and configured to surround a side of the light-emitting device layer and a side of the planarization layer, and the self-luminous device being configured to be isolated at each of the groove line and the dam.

[0429] According to some embodiments of the present disclosure, the light-emitting display device may further include: an interlayer insulating layer arranged above the substrate; and a passivation layer arranged between the interlayer insulating layer and the planarization layer, the groove line can be formed by removing all of the passivation layer and the planarization layer arranged above the interlayer insulating layer, and the top surface of the interlayer insulating layer can be the bottom surface of the groove line.

[0430] According to some embodiments of the present disclosure, the light-emitting display device may further include an undercut region formed between the planarization layer and the side of the passivation layer defining one side of the groove line, and the self-luminous device arranged above the planarization layer and the groove line may be isolated by the undercut region.

[0431] According to some embodiments of the present disclosure, the dam may include: a first dam pattern arranged above the interlayer insulating layer; a second dam pattern arranged above the first dam pattern; a third dam pattern arranged above the second dam pattern; and an undercut area formed between the first dam pattern and the second dam pattern, and the self-luminous device arranged above the dam may be isolated by the undercut area.

[0432] According to some embodiments of the present disclosure, the first dam pattern may include an inorganic insulating material, the second dam pattern may include an organic insulating material, and the third dam pattern may include an organic insulating material or an inorganic insulating material.

[0433] According to some embodiments of the present disclosure, the light-emitting display device may further include a blocking structure configured to include at least one blocking pattern portion surrounding the dam, and the self-luminous device disposed above the dam may be further isolated by the at least one blocking pattern portion.

[0434] According to some embodiments of the present disclosure, the at least one blocking pattern portion may include: a first blocking pattern arranged above the interlayer insulating layer; a second blocking pattern arranged above the first blocking pattern; a third blocking pattern arranged above the second blocking pattern; and an undercut region formed between the first blocking pattern and the second blocking pattern, and the self-luminous device arranged above the blocking structure may be isolated by the undercut region.

[0435] According to some embodiments of the present disclosure, the first barrier pattern may include an inorganic insulating material, the second barrier pattern may include a metal material, and the third barrier pattern may include an organic insulating material or an inorganic insulating material.

[0436] According to some embodiments of the present disclosure, the light-emitting display device may further include a pixel common voltage line electrically connected to the common electrode of the light-emitting device layer arranged in the display area, and the second blocking pattern may be electrically connected to the pixel common voltage line through a via formed at the first blocking pattern and the interlayer insulating layer.

[0437] According to some embodiments of the present disclosure, the light-emitting display device may further include: an interlayer insulating layer arranged above the substrate; a passivation layer arranged between the interlayer insulating layer and the planarization layer; and an auxiliary insulating layer arranged between the planarization layer and the light-emitting device layer. The groove line can be formed by removing all of the planarization layer and the auxiliary insulating layer arranged above the passivation layer, and the upper surface of the passivation layer can be the lower surface of the groove line.

[0438] According to some embodiments of the present disclosure, the light-emitting display device may further include an undercut region formed between the auxiliary insulating layer and the side of the planarization layer defining one side of the groove line, and the self-luminous device arranged above the auxiliary insulating layer and the groove line may be isolated by the undercut region.

[0439] According to some embodiments of the present disclosure, the dam may include: a first dam pattern arranged above the passivation layer; a second dam pattern arranged above the first dam pattern; a third dam pattern arranged above the second dam pattern; a fourth dam pattern arranged above the third dam pattern; and an undercut area formed between the first dam pattern and the second dam pattern, and the self-luminous device arranged above the dam may be isolated by the undercut area.

[0440] According to some embodiments of the present disclosure, the first dam pattern may include an inorganic insulating material, the second dam pattern may include an inorganic insulating material, the third dam pattern may include a metal material, and the fourth dam pattern may include an organic insulating material or an inorganic insulating material.

[0441] According to some embodiments of the present disclosure, the light-emitting display device may further include a blocking structure configured to include at least one blocking pattern portion surrounding the dam, and the self-luminous device disposed above the dam may be further isolated by the at least one blocking pattern portion.

[0442] According to some embodiments of the present disclosure, the at least one blocking pattern portion may include: a first blocking pattern arranged above the passivation layer; a second blocking pattern arranged above the first blocking pattern; a bottom cut area formed between the first blocking pattern and the second blocking pattern, and the self-luminous device arranged above the blocking structure may be isolated by the bottom cut area.

[0443] According to some embodiments of the present disclosure, the first barrier pattern may include an organic insulating material, and the second barrier pattern may include an inorganic insulating material.

[0444] According to some embodiments of the present disclosure, the light-emitting display device may further include: a first pad component, the first pad component being configured to include a plurality of first pads arranged at a peripheral portion of the substrate; a wiring substrate, the wiring substrate being configured to include a second pad component, the second pad component including a plurality of second pads overlapping with each of the plurality of first pads; a coupling element arranged between the substrate and the wiring substrate; and a routing portion, the routing portion being arranged at one side of each of the substrate and the wiring substrate and being configured to include a plurality of routing routes to couple the plurality of first pads to the plurality of second pads in a one-to-one relationship.

[0445] According to some embodiments of the present disclosure, the display area may be configured to include a plurality of pixels arranged above the substrate along a first direction and a second direction intersecting the first direction, the distance between the center portion of the outermost pixel among the plurality of pixels and the outermost surface of the substrate may be half of a pixel pitch or less, and the pixel pitch may be the distance between the center portions of two adjacent pixels.

[0446] According to an embodiment of the present disclosure, a multi-screen light-emitting display device may include: a plurality of display devices arranged along at least one of a first direction and a second direction intersecting the first direction, each of the plurality of display devices may include a light-emitting display device, and the light-emitting display device includes: a substrate configured to include a display area; a planarization layer arranged above the display area; a groove line arranged along a peripheral portion of the substrate and configured to surround a side of the planarization layer; a dam configured to surround the groove line; a light-emitting device layer configured to include a self-luminous device arranged above the planarization layer, the groove line, and the dam; an encapsulation layer, the encapsulation layer being configured to include an organic encapsulation layer arranged above an encapsulation area surrounded by the dam, the organic encapsulation layer being configured to fill the groove line and configured to surround a side of the light-emitting device layer and a side of the planarization layer, and the self-luminous device being configured to be isolated at each of the groove line and the dam.

[0447] According to some embodiments of the present disclosure, in the light-emitting display device of each of the multiple display devices, the display area may be configured to include a plurality of pixels, and the plurality of pixels are arranged above the substrate along a first direction and a second direction intersecting the first direction. In a first display device and a second display device adjacent to each other along the first direction and the second direction, a distance between a center portion of an outermost pixel of the first display device and a center portion of an outermost pixel of the second display device may be less than or equal to a pixel pitch, and the pixel pitch may be a distance between center portions of two adjacent pixels.

[0448] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit and scope of the present invention. Therefore, it is intended that the present disclosure cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting display device, comprising: a substrate configured to include a display area; a planarization layer disposed above the display area; a groove line provided along a peripheral portion of the substrate and configured to surround a side surface of the planarization layer; a dam configured to surround the trench line; a light emitting device layer configured to include a self-luminous device disposed above the planarization layer, the trench line, and the dam; an encapsulation layer configured to include an organic encapsulation layer disposed over an encapsulation area surrounded by the dam, wherein the organic encapsulation layer is configured to fill the groove line and is configured to surround a side surface of the light emitting device layer and a side surface of the planarization layer, and The self-luminous device is configured to be isolated at each of the trench line and the dam.

2. The light-emitting display device according to claim 1, further comprising: an interlayer insulating layer disposed above the substrate; and a passivation layer disposed between the interlayer insulating layer and the planarization layer; wherein the trench line is formed by removing all of the passivation layer and the planarization layer disposed above the interlayer insulating layer, and The top surface of the interlayer insulating layer is the bottom surface of the trench line.

3. The light emitting display device according to claim 2 , further comprising an undercut region formed between the planarization layer and a side surface of the passivation layer defining one side of the groove line, The self-luminous device disposed above the planarization layer and the groove line is isolated by the undercut region.

4. The light-emitting display device according to claim 2, The dam comprises: a first dam pattern disposed above the interlayer insulating layer; a second dam pattern disposed above the first dam pattern; a third dam pattern disposed above the second dam pattern; and forming an undercut region between the first dam pattern and the second dam pattern, and The self-luminous device disposed above the dam is isolated by the undercut region.

5. The light-emitting display device according to claim 4, wherein the first dam pattern comprises an inorganic insulating material, wherein the second dam pattern comprises an organic insulating material, and The third dam pattern includes an organic insulating material or an inorganic insulating material.

6. The light emitting display device according to claim 2 , further comprising a barrier structure configured to include at least one barrier pattern portion surrounding the dam, The self-luminous device disposed above the dam is further isolated by the at least one barrier pattern portion.

7. The light-emitting display device according to claim 6, wherein the at least one blocking pattern portion comprises: a first barrier pattern disposed above the interlayer insulating layer; a second barrier pattern disposed above the first barrier pattern; a third barrier pattern disposed above the second barrier pattern; and forming an undercut region between the first barrier pattern and the second barrier pattern, and The self-luminous device disposed above the blocking structure is isolated by the undercut region.

8. The light-emitting display device according to claim 7, wherein the first barrier pattern comprises an inorganic insulating material, wherein the second barrier pattern comprises a metal material, and The third barrier pattern comprises an organic insulating material or an inorganic insulating material.

9. The light emitting display device according to claim 8, further comprising a pixel common voltage line electrically connected to a common electrode of the light emitting device layer provided in the display area, The second barrier pattern is electrically connected to the pixel common voltage line through a via hole formed at the first barrier pattern and the interlayer insulating layer.

10. The light-emitting display device according to claim 1, further comprising: an interlayer insulating layer disposed above the substrate; a passivation layer disposed between the interlayer insulating layer and the planarization layer; an auxiliary insulating layer disposed between the planarization layer and the light emitting device layer; wherein the trench line is formed by removing all of the planarization layer and the auxiliary insulating layer disposed above the passivation layer, and The upper surface of the passivation layer is the lower surface of the trench line.

11. The light emitting display device according to claim 10 , further comprising an undercut region formed between the auxiliary insulating layer and a side surface of the planarization layer defining one side of the trench line, The self-luminous device disposed above the auxiliary insulating layer and the groove line is isolated by the undercut region.

12. The light-emitting display device according to claim 10, The dam comprises: a first dam pattern disposed above the passivation layer; a second dam pattern disposed above the first dam pattern; a third dam pattern disposed above the second dam pattern; a fourth dam pattern disposed above the third dam pattern; and forming an undercut region between the first dam pattern and the second dam pattern, and The self-luminous device disposed above the dam is isolated by the undercut region.

13. The light-emitting display device according to claim 12, wherein the first dam pattern comprises an inorganic insulating material, wherein the second dam pattern comprises an inorganic insulating material, wherein the third dam pattern comprises a metal material, and The fourth dam pattern includes an organic insulating material or an inorganic insulating material.

14. The light emitting display device according to claim 10, further comprising a barrier structure configured to include at least one barrier pattern portion surrounding the dam, The self-luminous device disposed above the dam is further isolated by the at least one barrier pattern portion.

15. The light-emitting display device according to claim 14, wherein the at least one blocking pattern portion comprises: a first barrier pattern disposed above the passivation layer; a second barrier pattern disposed above the first barrier pattern; forming an undercut region between the first barrier pattern and the second barrier pattern, and The self-luminous device disposed above the blocking structure is isolated by the undercut region.

16. The light-emitting display device according to claim 15, wherein the first barrier pattern comprises an organic insulating material, and The second barrier pattern comprises an inorganic insulating material.

17. The light-emitting display device according to claim 1, further comprising: a first pad component configured to include a plurality of first pads provided at one peripheral portion of the substrate; a wiring substrate configured to include a second pad section including a plurality of second pads overlapping each of the plurality of first pads; a coupling element disposed between the substrate and the wiring substrate; and A routing section is provided at one side surface of each of the substrate and the wiring substrate and is configured to include a plurality of routing lines to couple the plurality of first pads to the plurality of second pads in a one-to-one relationship.

18. The light-emitting display device according to any one of claims 1 to 17, wherein the display area is configured to include a plurality of pixels, the plurality of pixels being arranged above the substrate along a first direction and a second direction intersecting the first direction at right angles, wherein a distance between a center portion of an outermost pixel among the plurality of pixels and an outermost surface of the substrate is half a pixel pitch or less, and The pixel pitch is the distance between the centers of two adjacent pixels.

19. A multi-screen luminous display device comprising: a plurality of display devices arranged along at least one of a first direction and a second direction intersecting the first direction at a right angle, The plurality of display devices each include the light-emitting display device according to any one of claims 1 to 18.

20. The multi-screen light-emitting display device according to claim 19, wherein in each of the light-emitting display devices, the display area is configured to include a plurality of pixels, and the plurality of pixels are arranged above the substrate along a first direction and a second direction intersecting the first direction at a right angle, wherein in a first display device and a second display device adjacent to each other along the first direction or the second direction, a distance between a center portion of an outermost pixel of the first display device and a center portion of an outermost pixel of the second display device is less than or equal to a pixel pitch, and The pixel pitch is the distance between the centers of two adjacent pixels.

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