Flip chip packaging structure

Abstract

The present invention discloses a packaging structure of a flip chip, which includes: a semiconductor chip, a first surface of the semiconductor chip having a plurality of pads; a plurality of metal columns, respectively formed on the plurality of pads; a packaging frame, a surface of the packaging frame having a plurality of joint grooves; a plastic package body, used to package the semiconductor chip, the plurality of metal columns and the packaging frame, wherein the plurality of joint grooves correspond to the plurality of metal columns one by one, and a portion of each of the plurality of metal columns is located in the corresponding joint groove and is joined to the inner wall of the joint groove by a conductive adhesive. The present invention can improve the welding cracking problem and the extrusion deformation problem of the chip surface circuit in the temperature cycle test of the packaging structure of the flip chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a packaging structure of a flip chip. Background Art

[0002] As time goes by, semiconductor packaging structures are becoming smaller and more concentrated, and are manufactured into a variety of shapes. According to the connection method, semiconductor packaging structures are typically divided into wire bonding (WireBonding, WB) type or flip chip (Flip Chip, FC) bonding type. The wire bonding type packaging structure uses conductive bonding wires to achieve the bonding of the electrodes of the semiconductor chip (referred to as the chip in this article) with the packaging frame, while the flip chip type packaging structure uses conductive bumps placed on the electrode solder joints of the semiconductor chip to achieve the bonding of the chip circuit with the packaging frame. The flip chip bonding type packaging structure has a shorter electrical connection path and higher density interconnection requirements than the wire bonding type packaging structure, thus providing excellent thermal and electrical characteristics and a smaller packaging structure size, making it a favorable choice for modern wireless communication applications using GHz frequency ranges.

[0003] At present, in the process of forming a flip chip package, a low melting point solder is generally deposited at the interconnection position to form a pad bump on the semiconductor chip, such as Figure 1 As shown, the pad protrusion may include a metal column 6, such as a copper column, extending from the pad 4 of the semiconductor chip 1, and a solder ball 7 formed by reflow on the free end of the metal column 6. The solder ball 7 is generally made of high-lead solder. Then, the solder ball 7 on the chip and the semiconductor chip 1 are turned over and placed on the packaging frame 9. Next, the temperature is increased. When the temperature reaches a certain condition, the flip chip 1 and the packaging frame 9 are connected to each other by heat pressing at high temperature through the solder ball 7 on the surface of the copper column 6, thereby forming a connection structure such as copper-tin-copper. The final package is as shown in FIG. Figure 2 The semiconductor package structure is shown.

[0004] Currently, the flip chip is connected to the packaging frame through copper pillars and pressed solder balls. However, due to the high hardness of the copper pillars, during the temperature cycle test of the chip, the copper pillars will expand and squeeze the solder balls and the circuits on the surface of the chip under high temperature conditions, causing solder cracks and deformation of the circuits on the surface of the chip, causing many problems in the packaging structure of the flip chip after the temperature reliability test.

[0005] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a flip chip packaging structure, which improves the solder cracking problem and the extrusion deformation problem of the chip surface circuit in the flip chip packaging structure during the temperature cycle test.

[0007] According to a first aspect of the present invention, there is provided a flip chip packaging structure, comprising: a semiconductor chip, wherein a first surface of the semiconductor chip has a plurality of pads;

[0008] A plurality of metal pillars are respectively formed on the plurality of pads;

[0009] A packaging frame, wherein a surface of the packaging frame has a plurality of engagement grooves;

[0010] The plurality of joining grooves correspond to the plurality of metal pillars one by one, and a portion of each of the plurality of metal pillars is located in the corresponding joining groove and joined to the inner wall of the joining groove through conductive glue.

[0011] Optionally, each of the plurality of metal pillars is adhered to at least one of a bottom surface and a side surface of a corresponding bonding groove through the conductive adhesive.

[0012] Optionally, the flip chip packaging structure further includes:

[0013] The under bump metallization layer is disposed between the plurality of pads and the plurality of metal pillars.

[0014] Optionally, the flip chip packaging structure further includes:

[0015] an insulating layer formed on the first surface of the semiconductor chip, and having an opening therein to expose the plurality of pads; or

[0016] The insulating layer is formed between the semiconductor chip and the plurality of pads, and the insulating layer has a plurality of via holes, and the plurality of pads are connected to the semiconductor chip through the plurality of via holes.

[0017] Optionally, the flip chip packaging structure further includes:

[0018] A passivation layer is formed on a surface of the insulating layer away from the semiconductor chip, and the passivation layer covers a portion of each of the plurality of pads.

[0019] Optionally, the plurality of metal pillars include:

[0020] a plurality of first metal pillars, engaged with a plurality of first engagement grooves among the plurality of engagement grooves;

[0021] a plurality of second metal pillars, engaging with a plurality of second engaging grooves among the plurality of engaging grooves,

[0022] wherein the plurality of first bonding grooves are located in a first region of the packaging frame, and the plurality of second bonding grooves are located in a second region of the packaging frame; and

[0023] The depth of portions of the plurality of first metal pillars located in the plurality of first bonding grooves is greater than the depth of portions of the plurality of second metal pillars located in the plurality of second bonding grooves.

[0024] Optionally, the first area is an edge area of ​​the packaging frame, and the second area is a central area of ​​the packaging frame.

[0025] Optionally, a height of the plurality of first metal pillars is greater than a height of the plurality of second metal pillars.

[0026] Optionally, the depth of the plurality of first engaging grooves is greater than the depth of the plurality of second engaging grooves.

[0027] Optionally, the flip chip packaging structure further includes: a plastic package body, used to package the semiconductor chip, the plurality of metal pillars and the packaging frame.

[0028] The beneficial effects of the present invention include at least:

[0029] The flip chip packaging structure disclosed in the present invention changes the interconnection form when the packaging frame and the metal column are joined. By setting a joining groove at the position corresponding to the connection of the metal column on the packaging frame, the metal column can be directly inserted into the corresponding joining groove when the packaging frame and the metal column are interconnected, and the interconnection is achieved through conductive adhesive. Compared with the form of interconnecting the metal column and the packaging frame through solder balls in the prior art, the present invention replaces solder with conductive adhesive, which effectively improves the solder cracking problem and the extrusion deformation problem of the chip surface circuit in the flip chip packaging structure during the temperature cycle test.

[0030] Furthermore, the present invention increases the height of the metal column and the etching depth of the bonding groove in the high-risk area (such as the edge area corresponding to the packaging frame), so that after the metal column is bonded to the packaging frame, the risk of pulling and misalignment between the metal column and the bonding groove in the high-risk area can be effectively improved during the subsequent reliability verification temperature cycle process.

[0031] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram showing the structure of a conventional pad protrusion on a semiconductor chip is shown;

[0033] Figure 2 A schematic structural diagram showing an existing flip chip packaging structure;

[0034] Figure 3 A schematic structural diagram of a flip chip packaging structure provided according to an embodiment of the present invention is shown;

[0035] Figure 4 A schematic diagram showing the structure of a packaging frame provided according to an embodiment of the present invention is shown;

[0036] Figure 5a A schematic structural diagram showing the first metal pillar and the first bonding groove provided in accordance with an embodiment of the present invention are shown;

[0037] Figure 5b A schematic structural diagram is shown when a second metal column provided by an embodiment of the present invention is engaged with a second engagement groove. DETAILED DESCRIPTION

[0038] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0039] like Figure 3 As shown, the flip chip packaging structure disclosed in the embodiment of the present invention includes: a semiconductor chip 1, the first surface of which has a plurality of pads 4; a plurality of metal pillars 6, respectively formed on the plurality of pads 4; a packaging frame 9, the surface of the packaging frame 9 has a plurality of joining grooves; and a plastic package 8, which is used to package the semiconductor chip 1, the plurality of metal pillars 6 and the packaging frame 9.

[0040] In the present invention, semiconductor chip (chip for short) 1 is a general term. In order to simplify the drawings and highlight the invention, the internal structure of the semiconductor chip 1 is not illustrated in the drawings, but the internal structure of the semiconductor chip 1 can be understood based on the prior art. For example, a semiconductor device and a rewiring layer are formed in the semiconductor chip 1, and the semiconductor device and the plurality of pads 4 can be located on the same side surface of the chip 1, or on different side surfaces of the chip 1. When the semiconductor device and the plurality of pads 4 are located on different side surfaces of the chip 1, the plurality of pads 4 can be electrically connected to the semiconductor device using through holes that penetrate the chip. In the present embodiment, the semiconductor device and the plurality of pads 4 are located on the first surface of the chip 1, and the semiconductor device is electrically connected to the plurality of pads 4, and the circuit structure in the chip is electrically connected to the external circuit using the plurality of pads 4.

[0041] The plurality of metal pillars 6 can be formed on the plurality of pads 4 by electroplating, for example, and the plurality of metal pillars 6 correspond to the plurality of pads 4 one by one, that is, a corresponding metal pillar 6 is formed on each of the plurality of pads 4. The material of the plurality of pads 4 is aluminum, copper, gold or silver, etc. The semiconductor device in the chip 1 is connected to the external circuit through the plurality of pads 4, the plurality of metal pillars 6 and the conductive adhesive 10, etc.

[0042] Furthermore, the packaging structure of the flip chip in the embodiment of the present invention further includes an insulating layer 2 formed on the first surface of the chip 1, and the insulating layer 2 can be formed by depositing an oxidizing material such as silicon oxide on the first surface of the semiconductor chip. In one possible embodiment of the present invention, a plurality of pads 4 are also arranged on the first surface of the chip 1, and the plurality of pads 4 are directly connected to the semiconductor device in the chip 1 and exposed through the openings etched on the insulating layer 2. In another possible embodiment of the present invention, a plurality of pads 4 are arranged on the surface of the insulating layer 2 away from the chip 1, that is, the insulating layer 2 is formed between the semiconductor chip 1 and the plurality of pads 4, and the plurality of pads 4 are connected to the semiconductor device in the chip 1 through a plurality of vias on the insulating layer 2. Optionally, the insulating layer 2 is a stacked structure of one or more layers of a silicon oxide layer, a silicon nitride layer or a polyimide resin layer, or a benzoxazine resin layer to protect the chip 1. In this embodiment, the insulating layer 2 is a silicon oxide layer.

[0043] Furthermore, the packaging structure of the flip chip in the embodiment of the present invention also includes a plating seed layer formed on the surface of the plurality of pads 4. The material of the plating seed layer is one or a mixture of aluminum, copper, gold, and silver, and the process for forming the plating seed layer is a sputtering process or a physical vapor deposition process. When the material of the plating seed layer is aluminum, the process for forming the plating seed layer is a sputtering process, and when the material of the plating seed layer is one of copper, gold, and silver, the process for forming the plating seed layer is a physical vapor deposition process. In the present embodiment, the material of the plating seed layer is copper.

[0044] Preferably, in this embodiment, an Under Bump Metallurgy (UBM) 5 is formed on the surface of the plurality of pads 4 away from the chip 1 to serve as an electroplating seed layer.

[0045] In this embodiment, a plurality of pads 4 and an under bump metal layer 5 located on the surface of the plurality of pads 4 constitute a metal interconnection layer, and subsequently a plurality of metal pillars 6 are formed on the under bump metal layer 5. The material of the plurality of metal pillars 6 is copper or other suitable metals, and the plurality of metal pillars 6 are formed on the surface of the under bump metal layer 5 by electroplating. The under bump metal layer 5 is a metallized transition layer between the chip pads 4 and the metal pillars 6, and mainly plays the role of adhesion and diffusion barrier. The under bump metal layer 5 is usually composed of a multilayer metal film such as an adhesion layer, a diffusion barrier layer and an infiltration layer. The under bump metal layer 5 can be formed by sputtering, evaporation, chemical plating, electroplating and other methods.

[0046] Furthermore, the flip chip packaging structure in the embodiment of the present invention further includes a passivation layer 3 formed on the surface of the insulating layer 2 away from the semiconductor chip 1, an opening is formed on the passivation layer 3, and the passivation layer 3 covers a portion of each of the multiple pads 4, and even covers a portion of the under-bump metal layer 5 on each pad 4. Since the pads 4 produced by the chip manufacturing plant are often larger, the size of the columnar electrode, i.e., the metal electrode 6, formed directly on the pad 4 is also larger. Therefore, by forming another passivation layer 3 on the surface of the insulating layer 2 and using the passivation layer 3 to cover a portion of each pad 4, the exposed area of ​​each pad 4 is reduced, and the size of the metal column 6 formed subsequently is reduced, which helps to form a high-density packaging structure.

[0047] The positions of the multiple joint grooves on the packaging frame 9 correspond to the multiple metal pillars 6 one by one, and the cross-sectional dimension of each of the multiple joint grooves is larger than the cross-sectional dimension of the corresponding metal pillar 6, so that when the packaging frame 9 is joined with the multiple metal pillars 6, the multiple metal pillars 6 can be correspondingly inserted into the multiple joint grooves on the packaging frame 9, and bonded to the inner wall of the joint groove by the conductive adhesive 10. That is, in the final packaging structure, a portion of each of the multiple metal pillars 6 is located in the corresponding joint groove.

[0048] The present invention improves the bonding process between the metal pillars 6 and the packaging frame 9. On the target packaging frame to be bonded, a plurality of bonding grooves corresponding to the positions of the plurality of metal pillars 6 and having a size equivalent to or slightly larger than that of the plurality of metal pillars 6 are formed on the packaging frame 9 through photolithography and other related processes, and a suitable conductive glue 10 is then dripped into the bonding grooves. For example, a conductive glue with a certain elasticity can be selected. When the plurality of metal pillars 6 on the semiconductor chip 1 are inserted into the plurality of bonding grooves on the packaging frame 9, the gaps between the two are filled with the conductive glue 10, thereby achieving electrical adhesion between the plurality of metal pillars 6 and the plurality of bonding grooves or the plurality of metal pillars 6 and the packaging frame 9. This bonding method shown in the present invention can increase the contact area between the metal pillars 6 and the packaging frame 9, reduce the on-resistance, and meet the electrical connection properties of the chip.

[0049] Optionally, by reasonably setting the size of the multiple joint grooves and the depth of the portion of the multiple metal pillars 6 located in the corresponding joint grooves, when the multiple metal pillars 6 are inserted into the multiple joint grooves on the packaging frame 9, a gap is left between the portion of the metal pillar 6 located in the corresponding joint groove and at least one of the bottom surface and the side surface of the joint groove. Based on the conductive glue 10 pre-placed in the joint groove, when the multiple metal pillars 6 are inserted into the multiple joint grooves on the packaging frame 9, the gap between the two is filled with the conductive glue 10, thereby achieving electrical adhesion between the multiple metal pillars 6 and the multiple joint grooves or the multiple metal pillars 6 and the packaging frame 9. In a preferred embodiment of the present invention, when the multiple metal pillars 6 are inserted into the multiple joint grooves on the packaging frame 9, each of the multiple metal pillars 6 is adhered to the bottom surface and the side surface of the corresponding joint groove by the conductive glue 10.

[0050] The conductive glue 10 is an adhesive with conductive filler and resin as main components, and has good conductive properties (the resistivity is at the same order of magnitude as that of tin, and the conductivity is slightly lower than that of tin) and elasticity. Its applicable temperature range can also match the packaging temperature reliability test, and in the temperature cycle test, the conductive glue 10 can also serve as a buffer layer between the metal column 6 and the packaging frame 9 to effectively reduce the stress between the two, so the stress transmitted to the surface of the chip 1 will also be reduced, which can effectively improve the reliability of the flip chip packaging structure during use.

[0051] Furthermore, if Figure 4 As shown, the plurality of metal pillars 6 in the present invention include a plurality of first metal pillars 61 and a plurality of second metal pillars 62. The plurality of first metal pillars 61 are engaged with a plurality of first bonding grooves among the plurality of bonding grooves; the plurality of second metal pillars 62 are engaged with a plurality of second bonding grooves among the plurality of bonding grooves, and the plurality of first bonding grooves are located in a first region of the packaging frame 9 (for example, an edge region of the packaging frame 9), and the plurality of second bonding grooves are located in a second region of the packaging frame 9 (for example, a central region of the packaging frame 9).

[0052] Taking the package frame in QFN (Quad Flat No-leads Package) as an example, compared with the multiple second metal pillars 62 located in the second area of ​​the package frame 9, during the reliability test after injection molding packaging, such as TCC test or TCB test, the multiple first metal pillars 61 distributed in the first area of ​​the package frame 9 will have a larger displacement due to the thermal expansion and contraction of the package frame 9 than the multiple second metal pillars 62 located in the second area of ​​the package frame 9. Therefore, the deformation displacement between the multiple first metal pillars 61 in the multiple first bonding grooves in the first area of ​​the package frame 9 and the multiple first bonding grooves will be larger than the deformation displacement between the multiple second metal pillars 62 in the second area of ​​the package frame 9 and the multiple second bonding grooves, which will create a risk of pulling dislocation.

[0053] Furthermore, in the present invention, the depth of the portions of the plurality of first metal pillars 61 located in the plurality of first bonding grooves is greater than the depth of the portions of the plurality of second metal pillars 62 located in the plurality of second bonding grooves, thereby improving the risk of pulling and misalignment between the metal pillars and the bonding grooves in high-risk areas (such as the first area of ​​the packaging frame 9). Figure 5a and Figure 5b In the embodiment of the present invention, the height of the multiple first metal pillars 61 is set to be greater than the height of the multiple second metal pillars 62, and the depth of the multiple first bonding grooves is set to be greater than the depth of the multiple second bonding grooves, so that when the multiple metal pillars 6 are correspondingly inserted into the multiple bonding grooves on the packaging frame 9, the depth of the parts of the multiple first metal pillars 61 located in the multiple first bonding grooves can be greater than the depth of the parts of the multiple second metal pillars 62 located in the multiple second bonding grooves.

[0054] In summary, the present invention changes the interconnection form when the packaging frame and the metal column are joined, and sets a joining groove at the position corresponding to the connection of the metal column on the packaging frame, so that when the packaging frame and the metal column are interconnected, the metal column can be directly inserted into the corresponding joining groove, and the interconnection is achieved through conductive glue. Compared with the form of interconnecting the metal column and the packaging frame through solder balls in the prior art, the present invention replaces solder with conductive glue, which effectively improves the solder cracking problem, i.e., solder cracking problem, and the extrusion deformation problem of the chip surface circuit that occur in the flip chip packaging structure during the temperature cycle test.

[0055] On the other hand, the present invention increases the height of the metal column and the etching depth of the bonding groove in the high-risk area (such as the edge area corresponding to the packaging frame), so that after the metal column is bonded to the packaging frame, the risk of pulling and misalignment between the metal column and the bonding groove in the high-risk area can be effectively improved during the subsequent reliability verification temperature cycle process.

[0056] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

Claims

1. A flip chip packaging structure, wherein: include: A semiconductor chip, wherein a first surface of the semiconductor chip has a plurality of pads; A plurality of metal pillars are respectively formed on the plurality of pads; A packaging frame, wherein a surface of the packaging frame has a plurality of engagement grooves; Wherein, the plurality of joining grooves correspond to the plurality of metal pillars one by one, and a portion of each of the plurality of metal pillars is located in the corresponding joining groove and joined to the inner wall of the joining groove by means of conductive glue; The plurality of metal pillars include: a plurality of first metal pillars, engaged with a plurality of first engagement grooves among the plurality of engagement grooves; a plurality of second metal pillars, engaging with a plurality of second engaging grooves among the plurality of engaging grooves, wherein the plurality of first bonding grooves are located in a first region of the packaging frame, and the plurality of second bonding grooves are located in a second region of the packaging frame, wherein deformation displacements caused by thermal expansion and contraction of the packaging frame between the plurality of first metal pillars in the plurality of first bonding grooves in the first region and the plurality of first bonding grooves are greater than deformation displacements caused by thermal expansion and contraction of the packaging frame between the plurality of second metal pillars in the plurality of second bonding grooves in the second region and the plurality of second bonding grooves; and The depth of portions of the plurality of first metal pillars located in the plurality of first bonding grooves is greater than the depth of portions of the plurality of second metal pillars located in the plurality of second bonding grooves.

2. The flip chip packaging structure according to claim 1, wherein: Each of the plurality of metal pillars is adhered to at least one of the bottom surface and the side surface of the corresponding joining groove through the conductive adhesive.

3. The flip chip packaging structure according to claim 1, wherein: The flip chip packaging structure also includes: The under bump metallization layer is disposed between the plurality of pads and the plurality of metal pillars.

4. The flip chip packaging structure according to claim 3, wherein: The flip chip packaging structure also includes: an insulating layer formed on the first surface of the semiconductor chip, and having an opening therein to expose the plurality of pads; or The insulating layer is formed between the semiconductor chip and the plurality of pads, and the insulating layer has a plurality of via holes, and the plurality of pads are connected to the semiconductor chip through the plurality of via holes.

5. The flip chip packaging structure according to claim 4, wherein: The flip chip packaging structure also includes: A passivation layer is formed on a surface of the insulating layer away from the semiconductor chip, and the passivation layer covers a portion of each of the plurality of pads.

6. The flip chip packaging structure according to claim 1, wherein: The first area is an edge area of ​​the packaging frame, and the second area is a central area of ​​the packaging frame.

7. The flip chip packaging structure according to claim 1, wherein: The height of the plurality of first metal pillars is greater than the height of the plurality of second metal pillars.

8. The flip chip packaging structure according to claim 1, wherein: The depth of the plurality of first engaging grooves is greater than the depth of the plurality of second engaging grooves.

9. The flip chip packaging structure according to claim 1, further comprising: The plastic package is used to package the semiconductor chip, the plurality of metal pillars and the packaging frame.

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