A silicon substrate suitable for high speed laser chip packaging

Abstract

The application discloses a silicon substrate suitable for high-speed laser chip packaging, which comprises a silicon substrate, a coplanar waveguide structure is arranged on the surface of the silicon substrate, and through holes are distributed in the ground metal area on both sides of a signal line of the silicon substrate; a metal ground layer is arranged on the back surface of the silicon substrate, wherein the ground metal area is connected with the metal ground layer; and a low-resistance silicon sheet is attached to the back surface of the silicon substrate. Compared with the prior art, the high-resistance silicon of the order of kilo-ohm is avoided, when high-frequency transmission requires that the thickness of the substrate is less than 200 microns, in order to avoid that the substrate is too thin and fragile, the back low-resistance silicon sheet is attached in the application, the lower low-resistance silicon sheet is electrically conducted with the ground metal area on the back surface of the upper silicon substrate, and becomes a common ground part. The mechanical strength is guaranteed, and the ground electrical characteristics are good.

Description

Technical Field

[0001] This application belongs to the field of optoelectronic device technology, specifically relating to a silicon substrate suitable for high-speed laser chip packaging. Background Technology

[0002] In fiber optic communication technology, semiconductor lasers are primarily used as signal sources. With the continuous improvement of laser chip fabrication technology, not only has the cost of laser chips been significantly reduced, but the modulation frequency of a single laser chip has also reached 10 GHz or even tens of GHz. Currently, the key factor restricting the characteristics and cost of the signal source lies mainly in packaging technology. In the packaging process, the packaging substrate must provide the laser with a high-frequency signal. To meet the requirements of high-frequency transmission and signal coupling and decoupling, the circuit must be matched with capacitors, resistors, inductors, and other devices. Silicon is very suitable for the integration of resistors, capacitors, and other components, and can also form coplanar waveguides.

[0003] Ordinary silicon semiconductor substrates cannot be directly used to fabricate microwave coplanar waveguides due to leakage and electromagnetic coupling losses at high frequencies. Currently, there are two main solutions to this problem: The first method uses high-resistivity silicon, such as the method described in (IEEE Trans. Microwave Theory Tech., Vol. 43, P. 705, Apr. 1995). High-resistivity silicon requires a resistivity higher than 2500 Ω·cm. Microwave coplanar waveguides can be directly fabricated on this high-resistivity silicon. However, high-resistivity silicon is very expensive, which contradicts the goal of large-scale, low-cost production. The second method involves growing a layer of SiO2 insulating dielectric material several micrometers thick on a silicon substrate, and then fabricating the microwave coplanar waveguide on this thick SiO2 dielectric layer (IEEE Phtonics Technology Letters, Vol. 9, No. 3, P. 306, MARCH 1997). The addition of a SiO2 insulating layer several micrometers thick between the coplanar waveguide and the silicon substrate greatly reduces microwave transmission loss. However, growing a dense, thick SiO2 dielectric layer on the silicon surface requires a long time or expensive advanced equipment. Furthermore, the poor thermal conductivity of thick SiO2 is not conducive to heat dissipation of the laser chip. Summary of the Invention

[0004] In view of the shortcomings or deficiencies of the prior art, the technical problem to be solved by this application is to provide a silicon substrate suitable for high-speed laser chip packaging, which can support signal transmission above 50 GHz.

[0005] To solve the above-mentioned technical problems, this application provides the following technical solution:

[0006] This application proposes a silicon substrate suitable for high-speed laser chip packaging, comprising: a silicon substrate, a coplanar waveguide structure provided on the surface of the silicon substrate, and vias distributed in the ground metal regions on both sides of the signal lines of the silicon substrate; a metal ground layer provided on the back side of the silicon substrate, wherein the ground metal regions are connected to the metal ground layer; and a low-resistivity silicon wafer is also attached to the back side of the silicon substrate.

[0007] Optionally, in the above-mentioned silicon substrate suitable for high-speed laser chip packaging, the thickness of the silicon substrate is between 100 and 500 μm.

[0008] Optionally, in the aforementioned silicon substrate suitable for high-speed laser chip packaging, the coplanar waveguide structure is made of titanium, gold, aluminum, copper, silver, or platinum; and / or, the thickness of the coplanar waveguide structure is between 0.1 and 2 μm.

[0009] Optionally, in the silicon substrate described above for packaging high-speed laser chips, the grounding metal region is made of titanium, gold, aluminum, copper, silver, or platinum; and / or the thickness of the grounding metal region is 0.1 to 2 μm.

[0010] Optionally, in the aforementioned silicon substrate suitable for high-speed laser chip packaging, the metal ground layer is made of titanium, copper, aluminum, silver, or tin.

[0011] Optionally, in the silicon substrate for high-speed laser chip packaging described above, the vias are filled with a first conductive material, wherein the first conductive material includes titanium, gold, copper, or aluminum.

[0012] Optionally, in the silicon substrate for high-speed laser chip packaging described above, a layer of silicon dioxide is further provided on the sidewall of the through hole, the thickness of the silicon dioxide being 0.1 to 1 μm.

[0013] Optionally, in the silicon substrate for high-speed laser chip packaging described above, a layer of silicon dioxide is further provided between the silicon substrate and the metal ground layer, the thickness of the silicon dioxide ranging from 0.1 to 1 μm.

[0014] Optionally, in the aforementioned silicon substrate suitable for high-speed laser chip packaging, the back side of the silicon substrate is bonded to the low-resistivity silicon wafer via a second conductive material, the second conductive material including a gold-tin, copper-tin, or silver-tin eutectic film.

[0015] Optionally, in the aforementioned silicon substrate suitable for high-speed laser chip packaging, the thickness of the low-resistivity silicon wafer is 100–500 μm.

[0016] Compared with the prior art, this application has the following technical effects:

[0017] Compared with the prior art, this application avoids high-resistivity silicon at the kiloohm level. When the substrate thickness is required to be less than 200 micrometers for high-frequency transmission, in order to avoid the substrate being too thin and fragile, this application adopts back-side low-resistivity silicon wafer mounting. The lower low-resistivity silicon wafer is electrically connected to the back-side grounding metal area of ​​the upper silicon substrate, becoming a common grounding part; ensuring sufficient mechanical strength, while also having good grounding electrical characteristics. Attached Figure Description

[0018] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0019] Figure 1 This application includes a top view of a silicon substrate for packaging high-speed laser chips, according to one embodiment.

[0020] Figure 2 This application provides a cross-sectional view of a silicon substrate for packaging high-speed laser chips, according to one embodiment. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] like Figure 1 and Figure 2 As shown, in one embodiment of this application, a silicon substrate suitable for high-speed laser chip packaging includes: a silicon substrate 1, a coplanar waveguide structure 3 disposed on the surface of the silicon substrate 1, and vias 2 distributed in the ground metal regions on both sides of the signal lines of the silicon substrate 1; a metal ground layer disposed on the back side of the silicon substrate 1, wherein the ground metal regions are connected to the metal ground layer; and a low-resistivity silicon wafer 5 is also attached to the back side of the silicon substrate 1. This embodiment uses a back-side low-resistivity silicon wafer 5 for mounting, and the lower low-resistivity silicon wafer 5 is electrically connected to the back-side ground metal region of the upper silicon substrate 1, forming a common grounding part; ensuring sufficient mechanical strength while also having good grounding electrical characteristics; this embodiment can support signal transmission above 50GHz.

[0023] In this embodiment, the thickness of the silicon substrate 1 is between 100 and 500 μm. More preferably, the thickness of the silicon substrate 1 is between 100 and 450 μm; more preferably, the thickness of the silicon substrate 1 is between 150 and 450 μm; more preferably, the thickness of the silicon substrate 1 is between 150 and 400 μm; more preferably, the thickness of the silicon substrate 1 is between 200 and 400 μm; more preferably, the thickness of the silicon substrate 1 is between 200 and 350 μm; more preferably, the thickness of the silicon substrate 1 is between 250 and 350 μm; more preferably, the thickness of the silicon substrate 1 is between 250 and 300 μm.

[0024] Furthermore, the resistance of the silicon substrate 1 is above 200 Ω·cm.

[0025] In this embodiment, the coplanar waveguide structure 3 is made of one or more of titanium, gold, aluminum, copper, silver, or platinum.

[0026] The thickness of the coplanar waveguide structure 3 is 0.1–2 μm; more preferably, the thickness of the coplanar waveguide structure 3 is 0.2–1.9 μm; more preferably, the thickness of the coplanar waveguide structure 3 is 0.3–1.8 μm; more preferably, the thickness of the coplanar waveguide structure 3 is 0.4–1.6 μm; more preferably, the thickness of the coplanar waveguide structure 3 is 0.5–1.5 μm; more preferably, the thickness of the coplanar waveguide structure 3 is 0.6–1.4 μm; more preferably, the thickness of the coplanar waveguide structure 3 is 0.7–1.3 μm; more preferably, the thickness of the coplanar waveguide structure 3 is 0.8–1.2 μm; more preferably, the thickness of the coplanar waveguide structure 3 is 0.9–1.1 μm; more preferably, the thickness of the coplanar waveguide structure 3 is 0.9–1.0 μm.

[0027] The grounding metal zone is made of one or more of titanium, gold, aluminum, copper, silver, or platinum.

[0028] The thickness of the grounding metal region is 0.1–2 μm; more preferably, the thickness of the grounding metal region is 0.2–1.9 μm; more preferably, the thickness of the grounding metal region is 0.3–1.8 μm; more preferably, the thickness of the grounding metal region is 0.4–1.6 μm; more preferably, the thickness of the grounding metal region is 0.5–1.5 μm; more preferably, the thickness of the grounding metal region is 0.6–1.4 μm; more preferably, the thickness of the grounding metal region is 0.7–1.3 μm; more preferably, the thickness of the grounding metal region is 0.8–1.2 μm; more preferably, the thickness of the grounding metal region is 0.9–1.1 μm; more preferably, the thickness of the grounding metal region is 0.9–1.0 μm.

[0029] In this embodiment, the metal grounding layer is made of one or more of titanium, copper, aluminum, silver, or tin.

[0030] The through-hole 2 is filled with a first conductive material, wherein the first conductive material includes one or more combinations of titanium, gold, copper, or aluminum. The first conductive material enables conductive communication between the grounded metal region and the metal grounding layer.

[0031] It should also be noted that the distribution, number, and diameter of the through holes 2 are optimized according to product requirements.

[0032] A layer of silicon dioxide is further provided on the sidewall of the through hole 2, the thickness of which ranges from 0.1 to 1 μm. More preferably, the thickness of the silicon dioxide ranges from 0.2 to 0.8 μm; more preferably, the thickness of the silicon dioxide ranges from 0.3 to 0.7 μm; more preferably, the thickness of the silicon dioxide ranges from 0.4 to 0.6 μm; and more preferably, the thickness of the silicon dioxide ranges from 0.4 to 0.5 μm.

[0033] A layer of silicon dioxide is further disposed between the silicon substrate 1 and the metal ground layer, the thickness of the silicon dioxide ranging from 0.1 to 1 μm. More preferably, the thickness of the silicon dioxide ranges from 0.2 to 0.8 μm; more preferably, the thickness of the silicon dioxide ranges from 0.3 to 0.7 μm; more preferably, the thickness of the silicon dioxide ranges from 0.4 to 0.6 μm; and more preferably, the thickness of the silicon dioxide ranges from 0.4 to 0.5 μm.

[0034] The low-resistivity silicon wafer 5 is bonded to the back side of the silicon substrate 1 by a second conductive material 4, the second conductive material 4 including a gold-tin, copper-tin or silver-tin eutectic film.

[0035] The thickness of the low-resistivity silicon wafer 5 is 100–500 μm. More preferably, the thickness of the low-resistivity silicon wafer 5 is between 100 and 450 μm; more preferably, the thickness of the low-resistivity silicon wafer 5 is between 150 and 450 μm; more preferably, the thickness of the low-resistivity silicon wafer 5 is between 150 and 400 μm; more preferably, the thickness of the low-resistivity silicon wafer 5 is between 200 and 400 μm; more preferably, the thickness of the low-resistivity silicon wafer 5 is between 200 and 350 μm; more preferably, the thickness of the low-resistivity silicon wafer 5 is between 250 and 350 μm; more preferably, the thickness of the low-resistivity silicon wafer 5 is between 250 and 300 μm. Wherein, when the thickness of the silicon substrate 1 with a resistance of 200 Ω·cm or higher is less than 200 μm, the back-side low-resistivity silicon wafer 5 serves as a support.

[0036] In this embodiment, the resistance of the low-resistivity silicon wafer 5 is below 1 Ω·cm.

[0037] In this embodiment, the front side can be fitted with or integrated with thin-film capacitors, resistors and other devices.

[0038] By optimizing the resistance of the upper silicon substrate 1, the coplanar waveguide structure 3, and the thickness of the upper silicon substrate 1, a microwave waveguide structure with a frequency greater than 50 GHz can be obtained.

[0039] One of the manufacturing methods in this embodiment is shown below.

[0040] Using a 300 Ω·cm silicon substrate 1, via 2 is first etched to a depth of 200 micrometers, etching a 2000 angstrom length of silicon dioxide. Then, the back side is thinned to 200 micrometers until the back side of via 2 is exposed. A 10-micrometer thick copper layer is then sputtered and electroplated on the back side. A 1-um tin layer is then deposited. Simultaneously, a low-resistivity silicon wafer 5 with a resistivity of 0.01 Ω·cm and a thickness of 300 micrometers is used, with copper deposited on its surface. This wafer is then bonded to the via 2 substrate using a bonding method.

[0041] Based on this substrate structure, and using classical electromagnetic field theory calculations, a 50 GHz transmission line with a loss of less than 1.5 dB can be optimized.

[0042] After bonding, a coplanar waveguide, including transmission lines, is fabricated on the front side of the substrate using a mask. It adopts a Ti / Ni / Au structure with a thickness of 100 / 1000 / 10000 angstroms. At the same time, a tantalum nitride thin film resistor can be fabricated on the front side.

[0043] Compared with the prior art, this application avoids high-resistivity silicon at the kiloohm level. When the high-frequency transmission requires a substrate thickness of less than 200 micrometers, in order to avoid the substrate being too thin and fragile, this application uses a low-resistivity silicon wafer 5 on the back. The lower low-resistivity silicon wafer 5 is electrically connected to the back ground metal area of ​​the upper silicon substrate 1, becoming a common grounding part; ensuring sufficient mechanical strength, while also having good grounding electrical characteristics.

[0044] In the description of this application, unless otherwise expressly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0045] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0046] In the description of this embodiment, the terms "upper," "lower," "left," "right," etc., refer to the orientation or positional relationship shown in the accompanying drawings. They are used only for ease of description and simplification of operation, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first" and "second" are used only for distinction in description and have no special meaning.

[0047] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. The preferred embodiments have been described in detail. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application, and all such modifications and substitutions should be covered within the scope of the claims of this application.

Claims

1. A silicon substrate suitable for packaging high-speed laser chips, characterized in that, The silicon substrate is used for signal transmission above 50 GHz, and includes: a silicon substrate with a coplanar waveguide structure disposed on the surface of the silicon substrate. Through-holes are also distributed in the ground metal areas on both sides of the signal line on the silicon substrate; the through-holes are filled with a first conductive material, and a layer of silicon dioxide is also provided on the sidewall of the through-holes; the first conductive material includes: titanium, gold, copper or aluminum; A metal ground layer is provided on the back side of the silicon substrate, and the metal ground layer is made of titanium, copper, aluminum, silver or tin; The grounding metal area is connected to the metal grounding layer, and the grounding metal area is made of titanium, gold, aluminum, copper, silver or platinum; the back side of the silicon substrate is bonded to a low-resistivity silicon wafer through a second conductive material, the second conductive material including gold-tin, copper-tin or silver-tin eutectic thin film; The silicon substrate has a resistance of 200Ω or higher; the low-resistance silicon wafer has a resistance of 1Ω or lower.

2. The silicon substrate suitable for high-speed laser chip packaging according to claim 1, characterized in that, The thickness of the silicon substrate is between 100 and 500 μm.

3. The silicon substrate suitable for high-speed laser chip packaging according to claim 1, characterized in that, The coplanar waveguide structure is made of titanium, gold, aluminum, copper, silver or platinum; and / or, the thickness of the coplanar waveguide structure is 0.1~2μm.

4. The silicon substrate suitable for high-speed laser chip packaging according to claim 1, characterized in that, The thickness of the grounded metal region is 0.1~2μm.

5. The silicon substrate suitable for high-speed laser chip packaging according to claim 1, characterized in that, The thickness of the silicon dioxide ranges from 0.1 to 1 μm.

6. The silicon substrate suitable for high-speed laser chip packaging according to any one of claims 1 to 5, characterized in that, A layer of silicon dioxide is further disposed between the silicon substrate and the metal ground layer, the thickness of the silicon dioxide being 0.1~1μm.

7. The silicon substrate suitable for high-speed laser chip packaging according to any one of claims 1 to 5, characterized in that, The thickness of the low-resistivity silicon wafer is 100~500 μm.

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