Receiver for receiving a multi-level signal, memory device comprising the receiver and method for receiving data using the receiver

Abstract

A receiver that receives a multi-level signal includes a compensation circuit, a sampling circuit, an output circuit, and a mode selector. The compensation circuit generates a plurality of data signals and a plurality of reference voltages by compensating for intersymbol interference on an input data signal. The sampling circuit generates a plurality of sample signals based on the plurality of data signals and the plurality of reference voltages. The output circuit generates an output data based on the plurality of sample signals and selects a current value of the output data based on a previous value of the output data. The mode selector generates a mode selection signal for selecting one of a first operating mode and a second operating mode based on an operating environment. The compensation circuit and the sampling circuit are fully enabled in the first operating mode, and the compensation circuit and the sampling circuit are partially enabled in the second operating mode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0001264, filed on January 6, 2021, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] The example embodiments generally relate to semiconductor integrated circuits, and more specifically to a receiver for receiving multi-level signals, a storage device including the receiver, and a method for receiving data using the receiver. Background Technology

[0004] Semiconductor memory devices are typically classified into two categories based on whether they retain their stored data when disconnected from power. These categories include volatile memory devices and non-volatile memory devices. Volatile memory devices lose their stored data when power is off, while non-volatile memory devices retain their stored data when power is off. Volatile memory devices can perform read and write operations at high speeds, but the contents they store may be lost when power is off. Non-volatile memory devices retain their stored contents even when power is off, meaning they can be used to store data that must be retained regardless of whether they are powered on.

[0005] Recently, with the improvement of semiconductor memory device performance, the communication speed (or interface speed) between memory controllers and semiconductor memory devices has also increased. Therefore, multi-level signaling that transmits multiple bits during a unit interval (UI) has been studied. Summary of the Invention

[0006] At least one example embodiment of this disclosure provides a receiver capable of improving timing margin and reducing power consumption while receiving signals based on multi-level signaling.

[0007] At least one example embodiment of this disclosure provides a storage device including a receiver.

[0008] At least one example embodiment of this disclosure provides a method for receiving data using a receiver.

[0009] According to an example embodiment, a receiver configured to receive multilevel signals having three or more voltage levels that are different from each other includes a compensation circuit, a sampling circuit, an output circuit, and a mode selector. The compensation circuit generates multiple data signals and multiple reference voltages by compensating for inter-symbol interference (ISI) on the input data signals, which are multilevel signals. Each of the multiple reference voltages includes multiple compensated reference levels. The sampling circuit generates multiple sampled signals based on the multiple data signals and the multiple reference voltages. Each of the multiple sampled signals includes multiple decision values. The output circuit generates output data based on the multiple sampled signals and selects the current value of the output data based on previous values ​​of the output data. The output data includes two or more bits that are different from each other. The mode selector generates a mode selection signal based on the operating environment for selecting one of a first operating mode and a second operating mode. The compensation circuit and the sampling circuit are fully enabled in the first operating mode and partially enabled in the second operating mode.

[0010] According to an example embodiment, a storage device includes a receiver and a memory cell array. The receiver receives an input data signal, which is a multi-level signal having three or more voltage levels that are different from each other. The memory cell array performs a data write operation based on the input data signal. The receiver includes a compensation circuit, a sampling circuit, an output circuit, and a mode selector. The compensation circuit generates multiple data signals and multiple reference voltages by compensating for inter-symbol interference (ISI) on the input data signal. Each of the multiple reference voltages includes multiple compensated reference levels. The sampling circuit generates multiple sampled signals based on the multiple data signals and the multiple reference voltages. Each of the multiple sampled signals includes multiple decision values. The output circuit generates output data based on the multiple sampled signals and selects the current value of the output data based on a previous value of the output data. The output data includes two or more bits that are different from each other. The mode selector generates a mode selection signal based on the operating environment for selecting one of a first operating mode and a second operating mode. The compensation circuit and the sampling circuit are fully enabled in the first operating mode and partially enabled in the second operating mode.

[0011] According to an example embodiment, in a method for receiving data based on multi-level signals having three or more distinct voltage levels, a mode selection signal is generated based on the operating environment to select one of a first operating mode and a second operating mode. A compensation circuit generates multiple data signals and multiple reference voltages based on the mode selection signal by compensating for inter-symbol interference (ISI) on the input data signals, which are multi-level signals. Each of the multiple reference voltages includes multiple compensated reference levels. A sampling circuit generates multiple sampled signals based on the mode selection signal, the multiple data signals, and the multiple reference voltages. Each of the multiple sampled signals includes multiple decision values. Output data is generated based on the multiple sampled signals. The output data includes two or more distinct bits. The current value of the output data is selected based on a previous value of the output data. The compensation circuit and the sampling circuit are fully enabled in the first operating mode and partially enabled in the second operating mode.

[0012] According to an example embodiment, a receiver configured to receive a multilevel signal having three or more voltage levels that are different from each other includes a compensation circuit, a sampling circuit, and an output circuit. The compensation circuit generates multiple data signals and multiple compensation reference levels by compensating for inter-symbol interference (ISI) on the input data signals, which are multilevel signals. The sampling circuit generates multiple decision values ​​based on the multiple data signals and the multiple compensation reference levels. The output circuit generates output data based on the multiple decision values ​​and selects the current value of the output data based on a previous value of the output data. The output data includes two or more bits that are different from each other. Equalization is performed on the multiple compensation reference levels such that all the multiple compensation reference levels change by the same level. The direction of equalization is determined based on the previous value of the output data.

[0013] According to an example embodiment, a receiver configured to receive multi-level signals having first, second, third, and fourth voltage levels that are different from each other includes a compensation circuit, a sampling circuit, an output circuit, and a mode selector. The compensation circuit compensates for inter-symbol interference (ISI) on the input data signal, which is a multi-level signal, and includes a first post-verb canceller, a second post-verb canceller, a third post-verb canceller, and a fourth post-verb canceller. The first post-verb canceller generates a first data signal and first, second, and third compensated reference levels. The second post-verb canceller generates a second data signal and fourth, fifth, and sixth compensated reference levels. The third post-verb canceller generates a third data signal and seventh, eighth, and ninth compensated reference levels. The fourth post-verb canceller generates a fourth data signal and tenth, eleventh, and twelfth compensated reference levels. The sampling circuit includes a first limiter, a second limiter, a third limiter, and a fourth limiter. The first limiter generates first, second, and third determination values ​​by comparing the first data signal with the first, second, and third compensated reference levels. The second limiter generates the fourth, fifth, and sixth judgment values ​​by comparing the second data signal with the fourth, fifth, and sixth compensation reference levels. The third limiter generates the seventh, eighth, and ninth judgment values ​​by comparing the third data signal with the seventh, eighth, and ninth compensation reference levels. The fourth limiter generates the tenth, eleventh, and twelfth judgment values ​​by comparing the fourth data signal with the tenth, eleventh, and twelfth compensation reference levels. The output circuit generates output data based on the first to twelfth judgment values ​​and selects the current value of the output data based on the previous value of the output data. The output data includes the most significant bit (MSB) and the least significant bit (LSB). The mode selector selects one of the first and second operating modes based on the operating environment. The first to fourth limiters are fully enabled in the first operating mode and partially enabled in the second operating mode.

[0014] In the receiver, storage device, and method of receiving data according to the example embodiments, multi-level signals can be received, and a cyclic unrolling structure can be applied or employed. For example, the receiver can be implemented as a dual-mode cyclic unrolled DFE operating in one of a first operating mode and a second operating mode based on the operating environment. In the second operating mode, only a portion of the compensation circuitry and sampling circuitry included in the receiver can be enabled. Therefore, a cyclic unrolling structure can be used to improve or enhance timing margin issues, and power consumption can be reduced by selecting the operating mode based on the operating environment. Attached Figure Description

[0015] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0016] Figure 1This is a block diagram illustrating a receiver according to an example embodiment.

[0017] Figure 2A and Figure 2B This is a block diagram illustrating an example of a receiver according to some embodiments.

[0018] Figure 3 This is a block diagram illustrating a memory system according to an example embodiment.

[0019] Figure 4A and Figure 4B It is shown that according to some embodiments Figure 3 A block diagram of an example memory system.

[0020] Figure 5 This is a block diagram illustrating an example of a memory controller included in a memory system according to an example embodiment.

[0021] Figure 6A and Figure 6B This is a block diagram illustrating an example of a storage device included in a memory system according to an example embodiment.

[0022] Figure 7A , Figure 7B and Figure 7C It is a diagram used to describe the data signals generated according to the multi-level signaling scheme of the example embodiment.

[0023] Figure 8 It is shown that according to some embodiments Figure 1 A block diagram of an example receiver.

[0024] Figure 9 It is shown that according to some embodiments Figure 8 A block diagram of an example of a first limiter included in the receiver.

[0025] Figure 10 It is shown that according to some embodiments Figure 8 A block diagram of an example of the output circuitry included in the receiver.

[0026] Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B and Figure 12C It is used to describe according to some embodiments Figure 8 A diagram illustrating the operation of the receiver.

[0027] Figure 13 It is shown that according to some embodiments Figure 1 A block diagram of another example of a receiver.

[0028] Figure 14 It is shown that according to some embodiments Figure 13 A block diagram of an example of the output circuitry included in the receiver.

[0029] Figure 15A and Figure 15B It is used to describe according to some embodiments Figure 13 A diagram illustrating the operation of the receiver.

[0030] Figure 16 and Figure 17 This is a block diagram illustrating a receiver according to an example embodiment.

[0031] Figure 18 This is a flowchart illustrating a method for receiving data according to an example embodiment.

[0032] Figure 19 This is a block diagram illustrating a computing system according to an example embodiment.

[0033] Figure 20 This is a block diagram illustrating a communication system according to an example embodiment. Detailed Implementation

[0034] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In this application, similar reference numerals denote similar elements.

[0035] Figure 1 This is a block diagram illustrating a receiver according to an example embodiment.

[0036] Reference Figure 1 The receiver 1000 includes a compensation circuit 1100, a sampling circuit 1200, an output circuit 1300, and a mode selector 1400. The receiver 1000 may also include a data input pad (or pin) 1010.

[0037] Receiver 1000 receives an input data signal DS having three or more voltage levels as a multi-level signal, and generates output data ODAT comprising two or more bits as multi-bit data based on the input data signal DS. For example, the multi-level signal may have one of three or more voltage levels that are different from each other during a unit interval (UI), and the multi-bit data may include two or more bits that are different from each other. Receiver 1000 can be included in various communication systems and / or signal transmission systems, and may be included, for example, in storage devices and / or memory systems. The configuration of receiver 1000, storage devices, memory systems, and multi-level signals will be described in detail later.

[0038] The compensation circuit 1100 generates multiple data signals (or intermediate data signals) IDS and multiple reference voltages VREF by compensating for inter-symbol interference (ISI) on the input data signal DS, which is a multi-level signal. Each of the multiple reference voltages VREF includes multiple compensated reference levels.

[0039] The sampling circuit 1200 generates multiple sampled signals SAM based on multiple data signals IDS and multiple reference voltages VREF. Each of the multiple sampled signals SAM includes multiple decision values.

[0040] In some example embodiments, the compensation circuit 1100 and the sampling circuit 1200 can form a decision feedback equalizer (DFE) and can be implemented in a loop-unfolded structure. (See also...) Figure 8 and Figure 13 Describe the detailed configuration of the compensation circuit 1100 and the sampling circuit 1200.

[0041] In some example embodiments, the compensation circuit 1100 can generate multiple compensated reference levels by performing equalization (or equalization) techniques on multiple reference levels. For example, the compensation circuit 1100 can perform post-vernier elimination based on decision feedback equalization and can be referred to as a post-vernier elimination circuit. Multiple reference levels can be used to read out or detect the voltage levels of a multi-level signal. When equalization is performed on multiple reference levels, multiple compensated reference levels can be generated by adjusting or controlling the direction of increase and / or decrease of the multiple reference levels and the amount of change in the multiple reference levels. Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B and Figure 12C Describing equalization. For example, sampling circuit 1200 may perform a decision (or determination) based on the output of compensation circuit 1100, and may be referred to as a decision circuit or limiter circuit.

[0042] Output circuit 1300 generates output data ODAT as multi-bit data based on multiple sampled signals SAM, and selects the current value of output data ODAT based on the previous value of output data ODAT. For example, output circuit 1300 can be used to determine or identify the output in a loop unrolling structure. (See also...) Figure 10 and Figure 14 Describe the detailed configuration of the output circuit 1300.

[0043] The mode selector 1400 generates a mode selection signal MSEL based on the operating environment to select one of a first operating mode and a second operating mode. The mode selection signal MSEL can be provided to the compensation circuit 1100 and the sampling circuit 1200. The compensation circuit 1100 and the sampling circuit 1200 can be fully enabled (or activated) in the first operating mode, and the first operating mode can be referred to as full mode. The compensation circuit 1100 and the sampling circuit 1200 can be partially enabled (or activated) in the second operating mode, and the second operating mode can be referred to as half mode or partial mode. (See reference...) Figure 2A and Figure 2B Describe the detailed configuration of the mode selector 1400.

[0044] The data input pad 1010 can be connected to the compensation circuit 1100 and can receive the input data signal DS. For example, the pad can be a contact pad or a contact pin, but the example embodiment is not limited to this, and the data input pad 1010 can be a conductive terminal with other known forms.

[0045] In the receiver 1000 according to an example embodiment, an input data signal DS generated based on a multi-level signaling scheme is received. The multi-level signaling scheme can be used as a means of compressing the bandwidth required to transmit data at a given bit rate. In a simple binary scheme, two single symbols (typically two voltage levels) can be used to represent "1" and "0," so the symbol rate can be equal to the bit rate. In contrast, the principle of a multi-level signaling scheme can be to use a larger alphabet with m symbols to represent the data, such that each symbol can represent more than one bit of data. As a result, the number of symbols that need to be transmitted can be less than the number of bits (e.g., the symbol rate can be less than the bit rate), and thus the bandwidth can be compressed. The symbol alphabet can consist of many different voltage levels. For example, in a four-level scheme, a group of two data bits can be mapped to one of four symbols. Only one symbol needs to be transmitted for each pair of data bits, so the symbol rate can be half the bit rate.

[0046] Multilevel signaling schemes can be used to increase data transmission (or delivery) rates without increasing the frequency of data transmission and / or the transmission power of the communication data. An example of one type of multilevel signaling scheme is a pulse amplitude modulation (PAM) scheme, where unique symbols for multilevel signals can represent multiple bits of data. The number of possible pulse amplitudes in a digital PAM scheme can be a power of 2. For example, in 4-level PAM (e.g., in PAM4), there can be 2... 2 There are 2 possible discrete pulse amplitudes in an 8-level PAM (e.g., in PAM8). 3 There are 2 possible discrete pulse amplitudes, and in a 16-level PAM (e.g., in PAM16), there can be 2 4A possible discrete pulse amplitude. However, the example embodiments are not limited thereto, and the example embodiments can be applied or adopted to an X-level PAM (e.g., PAM(X)) having X possible pulse amplitudes, where X is a natural number greater than or equal to 3.

[0047] In a general data input / output (I / O) interface, a data signal is sent to a receiver through a channel. Recently, with the increase in data rate, interference signals caused by channel effects may increase, so the characteristics and / or quality of the received signal may decrease or deteriorate. To solve this problem or improve signal integrity (SI), equalization (or equalizing) techniques have been used to restore or recover the received signal by eliminating or compensating for interference signals. One of various equalization techniques is decision feedback equalization. In decision feedback equalization, signal integrity can be improved by eliminating interference signals (e.g., by eliminating postcursor causing intersymbol interference). However, since the current data is compensated after determining the signal compensation amount based on the result of determining the previous data, there may be a feedback delay. To reduce the feedback delay, decision feedback equalization with a loop-unrolled structure has been studied. In the loop-unrolled structure, output candidates can be generated by pre-computing compensation signals based on all possible results of decision values, and then one of the output candidates can be selected as the final output value.

[0048] The receiver 1000 according to the example embodiments can receive a multilevel signal and can be implemented with a loop-unrolled structure. For example, the receiver 1000 can be implemented as a dual-mode loop-unrolled DFE operating in one of the first operating mode and the second operating mode based on the operating environment. In the second operating mode, only a part (or portion) of the compensation circuit 1100 and the sampling circuit 1200 included in the receiver 1000 can be enabled. Therefore, the timing margin problem can be improved or enhanced using the loop-unrolled structure, and the power consumption can be reduced by selecting the operating mode based on the operating environment.

[0049] Figure 2A and Figure 2B is a block diagram showing an example of a receiver according to certain embodiments. Descriptions that are repeated with Figure 1 will be omitted.

[0050] Referring to Figure 2A , the receiver 1000a includes a compensation circuit 1100, a sampling circuit 1200, an output circuit 1300, and a mode selector 1400a. The receiver 1000a may further include a data input pad 1010 and an environment sensor 1500.

[0051] Except that the receiver 1000a further includes an environment sensor 1500 and the operation of the mode selector 1400a is partially changed, the receiver 1000a can be the same as Figure 1The receiver is basically the same as the 1000.

[0052] The environmental sensor 1500 (also described as an environmental sensor circuit) can generate a readout signal SEN by detecting changes in the operating environment (or surrounding environment) of the receiver 1000a (e.g., by detecting changes in the operating environment of the storage device and / or memory system including the receiver 1000a). For example, the environmental sensor 1500 can activate the readout signal SEN when the operating environment changes beyond a predetermined reference range.

[0053] In some example embodiments, the environmental sensor 1500 may include at least one of a temperature sensor, humidity sensor, pressure sensor, motion sensor, time sensor, space sensor, illuminance sensor, acceleration sensor, vibration sensor, mechanical stress sensor, shock sensor, frequency sensor, voltage sensor, and channel environment sensor. In other words, the operating environment may include at least one of temperature, humidity, pressure, motion, time, space, illuminance, acceleration, vibration, mechanical stress, shock, operating frequency of the storage device (or memory system), operating voltage of the storage device (or memory system), and channel environment or characteristics of the storage device (or memory system). However, the example embodiments are not limited thereto, and the environmental sensor 1500 may also include at least one sensor that collects at least one of various environmental information, such as an external force sensor, radiation sensor, dust sensor, electrical stress sensor, etc.

[0054] The mode selector 1400a can generate a mode selection signal MSEL based on the output of the environmental sensor 1500 (e.g., based on the readout signal SEN), and can set and / or change the operating mode. For example, based on a specific characteristic or set of characteristics (e.g., temperature above or below a threshold; humidity above or below a threshold; operating voltage above or below a threshold; or a combination thereof), a mode can be selected by setting the mode selection signal MSEL to a specific value that reflects the selected mode.

[0055] Reference Figure 2B The receiver 1000b includes a compensation circuit 1100, a sampling circuit 1200, an output circuit 1300, and a mode selector 1400b. The receiver 1000b may also include a data input pad 1010.

[0056] Apart from the partial change in the operation of the mode selector 1400b, the receiver 1000b can be connected with... Figure 1 The receiver is basically the same as the 1000.

[0057] During the initial operation period (or when receiver 1000b is powered on), or while receiver 1000b is operating, receiver 1000b can enter a training mode to perform training operations based on an external command (e.g., based on the training command TRCMD). Mode selector 1400b can generate a mode selection signal MSEL based on the result of the training operation. Then, after training is complete, mode selector 1400b can select a mode selection signal MSEL. Figure 1 It operates in the same way as the mode selector 1400.

[0058] although Figure 2B The example illustrates providing the training command TRCMD directly to the receiver 1000b, but the example embodiment is not limited thereto. For instance, the training command TRCMD could be decoded by a command decoder, and the decoded command could be provided to the receiver 1000b.

[0059] Figure 3 This is a block diagram illustrating a memory system according to an example embodiment.

[0060] Reference Figure 3 The memory system 10 includes a memory controller 20 and a memory device 40. The memory system 10 may also include multiple signal lines 30 that electrically connect the memory controller 20 and the memory device 40.

[0061] Storage device 40 is controlled by memory controller 20. For example, based on a request from a host (not shown), memory controller 20 can store data (e.g., write or program) into storage device 40, or retrieve data from storage device 40 (e.g., read or read out).

[0062] Multiple signal lines 30 may include control lines, command lines, address lines, data input / output (I / O) lines, and power lines. The memory controller 20 can send the command CMD, address ADDR, and control signal CTRL to the memory device 40 via the command lines, address lines, and control lines; can exchange the data signal MLDAT with the memory device 40 via the data I / O lines; and can send the power supply voltage PWR to the memory device 40 via the power lines. For example, the data signal MLDAT may be a multi-level signal received according to an example embodiment. Although... Figure 3 Not shown, but the multiple signal lines 30 may also include a data strobe (DQS) line for transmitting DQS signals.

[0063] In some example embodiments, at least a portion or all of the signal lines 30 may be referred to as a channel. As used herein, the term "channel" can mean a signal line that includes a data I / O line for transmitting the data signal MLDAT. However, example embodiments are not limited thereto, and a channel may also include a command line for transmitting the command CMD and / or an address line for transmitting the address ADDR.

[0064] Figure 4A and Figure 4B It is shown that according to some embodiments Figure 3 A block diagram of an example memory system.

[0065] Reference Figure 4A and Figure 4B The memory system 11 includes a memory controller 21, a storage device 41, and multiple channels 31a, 31b, and 31c. For example, the number of channels 31a, 31b, and 31c can be N, where N is a natural number greater than or equal to 2.

[0066] The memory controller 21 may include multiple transmitters 25a, 25b, and 25c, multiple receivers 27a, 27b, and 27c, and multiple data I / O pads 29a, 29b, and 29c. The storage device 41 may include multiple transmitters 45a, 45b, and 45c, multiple receivers 47a, 47b, and 47c, and multiple data I / O pads 49a, 49b, and 49c. The multiple data I / O pads 29a, 29b, and 29c, as well as 49a, 49b, and 49c, may be pads, pins, or other types of conductive terminals.

[0067] Each of the plurality of transmitters 25a, 25b, 25c, 45a, 45b, and 45c may be a circuit configured to generate a multi-level signal. Each of the plurality of receivers 27a, 27b, 27c, 47a, 47b, and 47c may receive the multi-level signal and may be a receiver according to an example embodiment. For example, each of the plurality of receivers 27a, 27b, 27c, 47a, 47b, and 47c may be a reference... Figure 1 The receiver is described, and can be referenced. Figures 8 to 18 The example described is used to implement this.

[0068] Each of the multiple data I / O pads 29a, 29b, 29c, 49a, 49b and 49c can be connected to a corresponding one of the multiple transmitters 25a, 25b, 25c, 45a, 45b and 45c and a corresponding one of the multiple receivers 27a, 27b, 27c, 47a, 47b and 47c.

[0069] Multiple channels 31a, 31b, and 31c can connect the memory controller 21 to the memory device 41. Each of the multiple channels 31a, 31b, and 31c can be connected to a corresponding one of the multiple transmitters 25a, 25b, and 25c and a corresponding one of the multiple receivers 27a, 27b, and 27c via a corresponding one of the multiple data I / O pads 29a, 29b, and 29c. Furthermore, each of the multiple channels 31a, 31b, and 31c can be connected to a corresponding one of the multiple transmitters 45a, 45b, and 45c and a corresponding one of the multiple receivers 47a, 47b, and 47c via a corresponding one of the multiple data I / O pads 49a, 49b, and 49c. Multilevel signals can be transmitted through each of the multiple channels 31a, 31b, and 31c.

[0070] Figure 4A The operation of transferring data from memory controller 21 to storage device 41 is illustrated. For example, transmitter 25a can generate a multi-level data signal DS11 based on input data DAT11. The data signal DS11 can be transmitted from memory controller 21 to storage device 41 via channel 31a, and receiver 47a can receive the data signal DS11 to obtain output data ODAT11 corresponding to input data DAT11. Similarly, transmitter 25b can generate a multi-level data signal DS21 based on input data DAT21. The data signal DS21 can be transmitted to storage device 41 via channel 31b, and receiver 47b can receive the data signal DS21 to obtain output data ODAT21 corresponding to input data DAT21. Transmitter 25c can generate a multi-level data signal DSN1 based on input data DATN1. The data signal DSN1 can be transmitted to storage device 41 via channel 31c, and receiver 47c can receive the data signal DSN1 to obtain output data ODATN1 corresponding to input data DATN1. For example, input data DAT11, DAT21, and DATN1 can be write data to be written to storage device 41, and write commands and write addresses can be provided to storage device 41 along with the write data.

[0071] Figure 4BThe operation of transferring data from storage device 41 to memory controller 21 is illustrated. For example, transmitter 45a can generate a multi-level data signal DS12 based on input data DAT12. The data signal DS12 can be transmitted from storage device 41 to memory controller 21 via channel 31a, and receiver 27a can receive the data signal DS12 to obtain output data ODAT12 corresponding to input data DAT12. Similarly, transmitter 45b can generate a multi-level data signal DS22 based on input data DAT22. The data signal DS22 can be transmitted to memory controller 21 via channel 31b, and receiver 27b can receive the data signal DS22 to obtain output data ODAT22 corresponding to input data DAT22. Transmitter 45c can generate a multi-level data signal DSN2 based on input data DATN2. The data signal DSN2 can be transmitted to memory controller 21 via channel 31c, and receiver 27c can receive the data signal DSN2 to obtain output data ODATN2 corresponding to input data DATN2. For example, input data DAT12, DAT22, and DATN2 can be read data retrieved from storage device 41, and read commands and read addresses for retrieving read data can be provided to storage device 41.

[0072] Figure 5 This is a block diagram illustrating an example of a memory controller included in a memory system according to an example embodiment.

[0073] Reference Figure 5 The memory controller 100 may include at least one processor 110, a buffer memory 120, a host interface 130, an error correction code (ECC) block 140, and a memory interface 150.

[0074] Processor 110 can control the operation of memory controller 100 in response to commands and / or requests received from an external host (not shown) via host interface 130. For example, processor 110 can control the operation of memory controller 100 by employing methods for operating memory devices (e.g., Figure 3 The firmware of the storage device 40 in the middle is used to control the various components.

[0075] Buffer memory 120 can store instructions and data executed and processed by processor 110. For example, buffer memory 120 can be implemented using volatile storage devices such as dynamic random access memory (DRAM), static random access memory (SRAM), cache memory, etc.

[0076] Host interface 130 provides a physical connection between the host and memory controller 100. Host interface 130 provides an interface corresponding to the host's bus format for communication between the host and memory controller 100. In some example embodiments, the host bus format may be a Small Computer System Interface (SCSI) or a Serial Attached SCSI (SAS) interface. In other example embodiments, the host bus format may be USB, Peripheral Component Interconnect (PCI) Rapid (PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Non-Volatile Memory (NVM) Rapid (NVMe), etc.

[0077] The ECC block 140 used for error correction can be encoded and modulated using Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc., or can be used to perform ECC encoding and ECC decoding using the above codes or other error correction codes.

[0078] The memory interface 150 can exchange data with the storage device. The memory interface 150 can send commands and addresses to the storage device, and can send data to the storage device or receive data read from the storage device. Although in Figure 5 Not shown, but according to the example embodiment, a transmitter or multiple transmitters that generate multi-level signals (e.g., Figure 4A The transmitter 25a) and the receiver or multiple receivers that receive multi-level signals (e.g., Figure 4A The receiver 27a) can be included in the memory interface 150.

[0079] Figure 6A and Figure 6B This is a block diagram illustrating an example of a storage device included in a memory system according to an example embodiment.

[0080] Reference Figure 6A The storage device 200 includes control logic 210, refresh control circuitry 215, address register 220, memory bank control logic 230, row address multiplexer 240, column address latch 250, row decoder, column decoder, memory cell array, sense amplifier unit, input / output (I / O) gating circuitry 290, data I / O buffer 295, and data I / O pads 299. In some example embodiments, the storage device 200 may be, for example, a volatile storage device. For example, the storage device 200 may be one of various volatile storage devices such as dynamic random access memory (DRAM).

[0081] The storage cell array may include multiple storage cells. The storage cell array may include multiple storage bank arrays, such as first storage bank arrays to fourth storage bank arrays 280a, 280b, 280c, and 280d. The row decoder may include multiple storage bank row decoders, such as first storage bank row decoders to fourth storage bank row decoders 260a, 260b, 260c, and 260d respectively connected to the first storage bank arrays to fourth storage bank arrays 280a, 280b, 280c, and 280d. The column decoder may include multiple storage bank column decoders, such as first storage bank column decoders to fourth storage bank column decoders 270a, 270b, 270c, and 270d respectively connected to the first storage bank arrays to fourth storage bank arrays 280a, 280b, 280c, and 280d. The readout amplifier unit may include multiple memory bank readout amplifiers, such as first memory bank readout amplifiers to fourth memory bank readout amplifiers 285a, 285b, 285c and 285d respectively connected to the first memory bank array to the fourth memory bank array 280a, 280b, 280c and 280d.

[0082] The first memory array to the fourth memory array 280a to 280d, the first memory row decoder to the fourth memory row decoder 260a to 260d, the first memory column decoder to the fourth memory column decoder 270a to 270d, and the first memory sense amplifier to the fourth memory sense amplifier 285a to 285d can respectively form the first memory to the fourth memory. For example, a first memory array 280a, a first memory row decoder 260a, a first memory column decoder 270a, and a first memory sense amplifier 285a can form a first memory; a second memory array 280b, a second memory row decoder 260b, a second memory column decoder 270b, and a second memory sense amplifier 285b can form a second memory; a third memory array 280c, a third memory row decoder 260c, a third memory column decoder 270c, and a third memory sense amplifier 285c can form a third memory; and a fourth memory array 280d, a fourth memory row decoder 260d, a fourth memory column decoder 270d, and a fourth memory sense amplifier 285d can form a fourth memory.

[0083] Address register 220 can be accessed from the memory controller (e.g., Figure 3The memory controller 20 receives an address ADDR that includes the bank address BANK_ADDR, the row address ROW_ADDR, and the column address COL_ADDR. The address register 220 can provide the received bank address BANK_ADDR to the bank control logic 230, the received row address ROW_ADDR to the row address multiplexer 240, and the received column address COL_ADDR to the column address latch 250.

[0084] The memory bank control logic 230 can generate a memory bank control signal in response to receiving the memory bank address BANK_ADDR. In response to the memory bank control signal generated by the memory bank control logic 230, the memory bank row decoders corresponding to the received memory bank address BANK_ADDR among the first to fourth memory bank row decoders 260a to 260d can be activated, and in response to the memory bank control signal generated by the memory bank control logic 230, the memory bank column decoders corresponding to the received memory bank address BANK_ADDR among the first to fourth memory bank column decoders 270a to 270d can be activated.

[0085] The refresh control circuit 215 can generate a refresh address REF_ADDR in response to receiving a refresh command or entering any self-refresh mode. For example, the refresh control circuit 215 may include a refresh counter configured to sequentially change the refresh address REF_ADDR from the first address of the memory cell array to the last address of the memory cell array. The refresh control circuit 215 may receive control signals from the control logic 210.

[0086] The row address multiplexer 240 can receive the row address ROW_ADDR from the address register 220 and the refresh address REF_ADDR from the refresh control circuit 215. The row address multiplexer 240 can selectively output either the row address ROW_ADDR or the refresh address REF_ADDR. The row address output from the row address multiplexer 240 (e.g., the row address ROW_ADDR or the refresh address REF_ADDR) can be applied to the first memory bank row decoder to the fourth memory bank row decoder 260a to 260d.

[0087] The activated bank row decoders in the first to fourth bank row decoders 260a to 260d can decode the row address output from the row address multiplexer 240 and can activate the word line corresponding to the row address. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address.

[0088] Column address latch 250 can receive column address COL_ADDR from address register 220 and can temporarily store the received column address COL_ADDR. Column address latch 250 can apply the temporarily stored or received column address COL_ADDR to column decoders 270a to 270d of the first to fourth memory banks.

[0089] The activated bank column decoders in the first to fourth bank column decoders 270a to 270d can decode the column address COL_ADDR output from the column address latch 250 and can control the I / O strobe circuit 290 to output data corresponding to the column address COL_ADDR.

[0090] I / O gating circuit 290 may include circuitry for gating I / O data. For example, although not shown, I / O gating circuit 290 may include: input data masking logic; read data latches for storing data output from the first memory array to the fourth memory arrays 280a-280d; and write drivers for writing data to the first memory array to the fourth memory arrays 280a-280d.

[0091] Data DQ to be read from one of the first to fourth memory arrays 280a to 280d can be read by a sense amplifier coupled to that memory array and stored in a read data latch. Data DQ stored in the read data latch can be provided to the memory controller via data I / O buffer 295 and data I / O pads 299. Data DQ to be written to one of the first to fourth memory arrays 280a to 280d, received via data I / O pads 299, can be provided from the memory controller to data I / O buffer 295. Data DQ received via data I / O pads 299 and provided to data I / O buffer 295 can be written to the memory array via a write driver in I / O strobe circuit 290. Although in Figure 6A Not shown, but according to the example embodiment, a transmitter or multiple transmitters that generate multi-level signals (e.g., Figure 4A The transmitter 45a) and the receiver or multiple receivers (e.g., in the middle) receive multi-level signals. Figure 4A The receiver 47a) can be included in the data I / O buffer 295.

[0092] Control logic 210 can control the operation of storage device 200. For example, control logic 210 can generate control signals for causing storage device 200 to perform data write or data read operations. Control logic 210 may include a command decoder 211 for decoding commands (CMD) received from the memory controller and a mode register 212 for setting the operating mode of storage device 200.

[0093] Reference Figure 6B The storage device 300 may include a storage cell array 310, an address decoder 320, a page buffer circuit 330, a data input / output (I / O) circuit 340, a voltage generator 350, and a control circuit 360. For example, the storage device 300 may be one of various non-volatile storage devices such as NAND flash memory devices.

[0094] The memory cell array 310 is connected to the address decoder 320 via multiple serial select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). The memory cell array 310 is also connected to the page buffer circuit 330 via multiple bit lines (BL). The memory cell array 310 may include multiple memory cells (e.g., multiple non-volatile memory cells) connected to the multiple word lines (WL) and the multiple bit lines (BL). The memory cell array 310 may be divided into multiple memory blocks BLK1, BLK2, ..., BLKz, where each memory block includes memory cells.

[0095] In some example embodiments, multiple memory cells may be arranged in a two-dimensional (2D) array structure or a three-dimensional (3D) vertical array structure. A three-dimensional vertical array structure may include vertically oriented strings of cells such that at least one memory cell is positioned above another memory cell. This at least one memory cell may include a charge trapping layer. The following patent documents (incorporated herein by reference in their entirety) describe suitable constructions for memory cell arrays including 3D vertical array structures, wherein the 3D memory array is configured as multiple levels and shares word lines and / or bit lines between levels: U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0096] The control circuit 360 is controlled from the outside (e.g., from...). Figure 3The memory controller 20 receives commands CMD and address ADDR, and controls the erase, program, and read operations of the storage device 300 based on the commands CMD and address ADDR. Erasing operations may include executing a series of erase cycles, and programming operations may include executing a series of programming cycles. Each programming cycle may include a programming operation and a programming verification operation. Each erase cycle may include an erase operation and an erase verification operation. Read operations may include normal read operations and data recovery read operations.

[0097] For example, based on the command CMD, the control circuit 360 can generate a control signal CON for controlling the voltage generator 350 and a control signal PBC for controlling the page buffer circuit 330. Furthermore, the control circuit 360 can generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuit 360 can provide the row address R_ADDR to the address decoder 320 and the column address C_ADDR to the data I / O circuit 340.

[0098] Address decoder 320 can be connected to memory cell array 310 via multiple string select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). For example, during data erase / write / read operations, address decoder 320 can determine at least one of the multiple word lines (WL) as the selected word line, at least one of the multiple string select lines (SSL) as the selected string select line, and at least one of the multiple ground select lines (GSL) as the selected ground select line based on the row address R_ADDR.

[0099] Voltage generator 350 can generate the voltage VS used or required for the operation of storage device 300 based on power PWR and control signal CON. Voltage VS can be applied to multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL via address decoder 320. Furthermore, voltage generator 350 can generate the erase voltage VERS required for data erase operations based on power PWR and control signal CON.

[0100] Page buffer circuit 330 can be connected to memory cell array 310 via multiple bit lines BL. Page buffer circuit 330 may include multiple page buffers. Page buffer circuit 330 can store data DAT to be programmed into memory cell array 310, or can read data DAT read from memory cell array 310. For example, page buffer circuit 330 can operate as a write driver or a sense amplifier depending on the operating mode of memory device 300.

[0101] Data I / O circuit 340 can be connected to page buffer circuit 330 via data line DL. Data I / O circuit 340 can provide data DAT from outside the memory device 300 to the memory cell array 310 via page buffer circuit 330 based on column address C_ADDR, or it can provide data DAT from memory cell array 310 to outside the memory device 300. Although in Figure 6B Not shown, but according to the example embodiment, a transmitter or multiple transmitters that generate multi-level signals (e.g., Figure 4A The transmitter 45a) and the receiver or multiple receivers (e.g., in the middle) receive multi-level signals. Figure 4A The receiver 47a) can be included in the data I / O circuit 340.

[0102] Although the memory devices included in the memory system according to the example embodiments are described based on DRAM and NAND flash memory, the memory devices according to the example embodiments can be any volatile memory device and / or any non-volatile memory device, such as static random access memory (SRAM), phase random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), thyristor random access memory (TRAM), etc.

[0103] Figure 7A , Figure 7B and Figure 7C It is a diagram used to describe the data signals generated according to the multi-level signaling scheme of the example embodiment.

[0104] Figure 7A An ideal eye diagram of a data signal (e.g., a PAM4 signal) generated based on a 4-level scheme (e.g., a PAM4 scheme) is shown, where the 4-level scheme is an example of a multi-level signaling scheme (e.g., a PAM scheme). Figure 7B By simplifying Figure 7A The diagram shown is based on the ideal eye diagram. Figure 7C This is a diagram shown by simplifying the ideal eye diagram of a data signal (e.g., a PAM8 signal) generated based on an 8-level scheme (e.g., a PAM8 scheme).

[0105] Reference Figure 7AEye diagrams can be used to indicate the quality of signals in high-speed transmissions. For example, an eye diagram can represent four symbols of a signal (e.g., "00", "01", "10", and "11"), and each of these four symbols can be represented by a corresponding one of different voltage levels (e.g., voltage amplitudes) VL11, VL21, VL31, and VL41. Eye diagrams can be used to provide a visual indication of the health of signal integrity and can indicate the noise margin of a data signal. For example, when using Gray code, voltage levels VL11, VL21, VL31, and VL41 can be mapped to "00", "01", "11", and "10", respectively.

[0106] To generate an eye diagram, an oscilloscope or other computing device can sample a digital signal according to a sampling period SP (e.g., a unit interval or bit period). The sampling period SP can be defined by a clock associated with the transmission of the measured signal. The oscilloscope or other computing device can measure the voltage level of the signal during the sampling period SP to form multiple traces TRC. Various characteristics associated with the measured signal can be determined by superimposing multiple traces TRC.

[0107] Eye diagrams can be used to identify various characteristics of communication signals, such as jitter, crosstalk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof. For example, the eye width W in an eye diagram can be used to indicate timing synchronization or jitter effects in a measurement signal. For example, an eye diagram can indicate eye opening OP, which represents the peak-to-peak voltage difference between various voltage levels VL11, VL21, VL31, and VL41. Eye opening OP can be related to the voltage margin used to distinguish the different voltage levels VL11, VL21, VL31, and VL41 of the measurement signal. For example, an eye diagram can be used to identify the rise time RT and / or fall time FT from a first amplitude to a second amplitude. The rise time RT or fall time FT can indicate the time required to transition from one voltage level to another and can be related to or associated with the rising and falling edges, respectively. For example, an eye diagram can be used to identify the amount of jitter JT in a measurement signal. Jitter JT can refer to timing errors caused by misalignment of rise and fall times. Jitter (JT) can occur when the rising or falling edge occurs at a time different from the ideal time defined by the data clock. Jitter can be caused by signal reflection, inter-symbol interference, crosstalk, process voltage-temperature (PVT) variations, random jitter, additional noise, or a combination thereof.

[0108] Reference Figure 7BThe diagram illustrates different first voltage levels VL11, second voltage level VL21, third voltage level VL31, and fourth voltage level VL41 for the data signal of the PAM4 signal, and also shows different first reference level VREF_H, second reference level VREF_M, and third reference level VREF_L for reading out or detecting the data signal. For example, the number of reference levels may be one less than the number of voltage levels for the data signal.

[0109] The first voltage level VL11, being the lowest voltage level among voltage levels VL11 to VL41, can be lower than the second voltage level VL21. The second voltage level VL21 can be lower than the third voltage level VL31, and the third voltage level VL31 can be lower than the fourth voltage level VL41, which is the highest voltage level among voltage levels VL11 to VL41. Furthermore, the first reference level VREF_H can be a level between the third voltage level VL31 and the fourth voltage level VL41, the second reference level VREF_M can be a level between the second voltage level VL21 and the third voltage level VL31, and the third reference level VREF_L can be a level between the first voltage level VL11 and the second voltage level VL21. The voltage level (e.g., symbol) of the data signal can be determined or specified based on the result of comparing the data signal with the reference levels VREF_H, VREF_M, and VREF_L. Therefore, the determined voltage level can actually be a level between two reference levels.

[0110] Reference Figure 7C The diagram shows different first voltage levels VL12, second voltage level VL22, third voltage level VL32, fourth voltage level VL42, fifth voltage level VL52, sixth voltage level VL62, seventh voltage level VL72, and eighth voltage level VL82 for the data signal of the PAM8 signal. It also shows different first reference level VREF_A, second reference level VREF_B, third reference level VREF_C, fourth reference level VREF_D, fifth reference level VREF_E, sixth reference level VREF_F, and seventh reference level VREF_G for reading out or detecting the data signal.

[0111] In the following sections, example embodiments will be described in detail based on the PAM4 scheme. However, the example embodiments are not limited thereto, and the example embodiments can be applied to or adopted by PAM(K) schemes with K possible pulse amplitudes.

[0112] Figure 8 It shows the receiver (such as Figure 1 A block diagram of an example receiver in an embodiment.

[0113] Reference Figure 8 The receiver 1002 includes a compensation circuit 1102, a sampling circuit 1202, an output circuit 1302, and a mode selector 1400. The receiver 1002 may also include a data input pad 1010, a first buffer 1020, and a second buffer 1030.

[0114] The data input pad 1010 can receive an input data signal DS1 having one of a first voltage level VL11, a second voltage level VL21, a third voltage level VL311, and a fourth voltage level VL41 during a UI.

[0115] The compensation circuit 1102 may include a first rear vernier eliminator 1110, a second rear vernier eliminator 1120, a third rear vernier eliminator 1130, and a fourth rear vernier eliminator 1140.

[0116] The first post-vernier canceller 1110 can generate a first data signal IDS1 and a first reference voltage VREF1 based on a previous value DATA_PRE of the output data ODAT1 being "10" (e.g., corresponding to the fourth voltage level VL41). The second post-vernier canceller 1120 can generate a second data signal IDS2 and a second reference voltage VREF2 based on a previous value DATA_PRE of the output data ODAT1 being "11" (e.g., corresponding to the third voltage level VL31). The third post-vernier canceller 1130 can generate a third data signal IDS3 and a third reference voltage VREF3 based on a previous value DATA_PRE of the output data ODAT1 being "01" (e.g., corresponding to the second voltage level VL21). The fourth post-vernier canceller 1140 can generate a fourth data signal IDS4 and a fourth reference voltage VREF4 based on a previous value DATA_PRE of the output data ODAT1 being "00" (e.g., corresponding to the first voltage level VL11). For example, each post-vernier canceller may include a feedback filter with an n-tap structure, where n is a natural number.

[0117] The first reference voltage VREF1 may include a first compensated reference level VREF_H1, a second compensated reference level VREF_M1, and a third compensated reference level VREF_L1. The second reference voltage VREF2 may include a fourth compensated reference level VREF_H2, a fifth compensated reference level VREF_M2, and a sixth compensated reference level VREF_L2. The third reference voltage VREF3 may include a seventh compensated reference level VREF_H3, an eighth compensated reference level VREF_M3, and a ninth compensated reference level VREF_L3. The fourth reference voltage VREF4 may include a tenth compensated reference level VREF_H4, an eleventh compensated reference level VREF_M4, and a twelfth compensated reference level VREF_L4. Each of the first, fourth, seventh, and tenth compensation reference levels VREF_H1, VREF_H2, VREF_H3, and VREF_H4 can correspond to the first reference level VREF_H, and each of these levels can be generated by increasing or decreasing the first reference level VREF_H by a specific level (or amount) based on equalization. Similarly, each of the second, fifth, eighth, and eleventh compensation reference levels VREF_M1, VREF_M2, VREF_M3, and VREF_M4 can correspond to the second reference level VREF_M, and each of these levels can be generated by increasing or decreasing the second reference level VREF_M by a specific level (or amount) based on equalization. Each of the third, sixth, ninth, and twelfth compensation reference levels VREF_L1, VREF_L2, VREF_L3, and VREF_L4 can correspond to the third reference level VREF_L, and the third, sixth, ninth, and twelfth compensation reference levels VREF_L1, VREF_L2, VREF_L3, and VREF_L4 can be generated by increasing or decreasing the third reference level VREF_L by a specific level (or amount) based on equalization.

[0118] In some example embodiments, data signals IDS1 to IDS4 may be substantially the same as each other. In other example embodiments, the first data signal IDS1 and the first reference voltage VREF1 may be provided as a pair of differential signals, and another data signal and the corresponding reference voltage may also be provided as a pair of differential signals, so data signals IDS1 to IDS4 may be different from each other.

[0119] The sampling circuit 1202 may include a first limiter 1210, a second limiter 1220, a third limiter 1230, and a fourth limiter 1240. Each limiter may also be described as a limiter circuit.

[0120] The first limiter 1210 generates a first sampled signal SAM1 by comparing the first data signal IDS1 with the first, second, and third compensation reference levels VREF_H1, VREF_M1, and VREF_L1. The second limiter 1220 generates a second sampled signal SAM2 by comparing the second data signal IDS2 with the fourth, fifth, and sixth compensation reference levels VREF_H2, VREF_M2, and VREF_L2. The third limiter 1230 generates a third sampled signal SAM3 by comparing the third data signal IDS3 with the seventh, eighth, and ninth compensation reference levels VREF_H3, VREF_M3, and VREF_L3. The fourth limiter 1240 generates a fourth sampled signal SAM4 by comparing the fourth data signal IDS4 with the tenth, eleventh, and twelfth compensation reference levels VREF_H4, VREF_M4, and VREF_L4. For example, if the reference... Figure 9 Each limiter may include multiple comparators.

[0121] The first sampling signal SAM1 may include first, second, and third decision values ​​VOH1, VOM1, and VOL1. The second sampling signal SAM2 may include fourth, fifth, and sixth decision values ​​VOH2, VOM2, and VOL2. The third sampling signal SAM3 may include seventh, eighth, and ninth decision values ​​VOH3, VOM3, and VOL3. The fourth sampling signal SAM4 may include tenth, eleventh, and twelfth decision values ​​VOH4, VOM4, and VOL4. Each of the first, fourth, seventh, and tenth decision values ​​VOH1, VOH2, VOH3, and VOH4 may represent a decision result obtained by comparing the input data signal DS1 with a corresponding one of the first reference levels equalized by the compensation circuit 1102. Similarly, each of the second, fifth, eighth, and eleventh decision values ​​VOM1, VOM2, VOM3, and VOM4 may represent a decision result obtained by comparing the input data signal DS1 with a corresponding one of the second reference levels equalized by the compensation circuit 1102. Each of the third, sixth, ninth, and twelfth decision values ​​VOL1, VOL2, VOL3, and VOL4 can represent a decision result obtained by comparing the input data signal DS1 with a corresponding one of the third reference levels equalized by the compensation circuit 1102.

[0122] The output circuit 1302 can generate output data ODAT1, including the first MSB1 and the second LSB1, based on the first to twelfth determination values ​​VOH1 to VOH4, VOM1 to VOM4, and VOL1 to VOL4. The first MSB1 and the second LSB1 can be the most significant bit (MSB) and the least significant bit (LSB) of the output data ODAT1, respectively. For example, when the output data ODAT1 is "10", the first MSB1 can be "1" and the second LSB1 can be "0".

[0123] The first buffer 1020 buffers the input data signal DS1 and provides the buffered input data signal to the first post-vernier eliminator 1110 and the fourth post-vernier eliminator 1140. The second buffer 1030 buffers the input data signal DS1 and provides the buffered input data signal to the second post-vernier eliminator 1120 and the third post-vernier eliminator 1130. The mode selector 1400 can generate a mode selection signal MSEL for selecting one of a first operating mode and a second operating mode based on the operating environment (e.g., output from an environmental sensor). Figure 8 In the example, the mode selection signal MSEL can be provided to the second buffer 1030, and a portion of the compensation circuit 1102 and the sampling circuit 1202 can be disabled or deactivated in the second operating mode by disabling or turning off the second buffer 1030.

[0124] As described above, receiver 1002 can be implemented in a loop-expanded structure, such that compensation circuit 1102 and sampling circuit 1202 pre-calculate all possible decision results and generate output candidates based on them, and output circuit 1302 selects one of the output candidates as the final output value.

[0125] In some example embodiments, such as referring to Figure 10 The output circuit 1302 can select or determine the output value of the loop unrolling structure based on the first MSB1 and the second LSB1. In this example, the number of multiplexers and flip-flops can be reduced, and the load on the input terminals viewed through the buffer can be reduced.

[0126] Figure 9 It shows Figure 8 A block diagram of an example of a first limiter included in the receiver.

[0127] Reference Figure 9 The first limiter 1210a may include comparators 1212, 1214 and 1216, each of which operates based on a clock signal CLK.

[0128] Comparator 1212 generates a first decision value VOH1 by comparing the first data signal IDS1 with a first compensation reference level VREF_H1. Comparator 1214 generates a second decision value VOM1 by comparing the first data signal IDS1 with a second compensation reference level VREF_M1. Comparator 1216 generates a third decision value VOL1 by comparing the first data signal IDS1 with a third compensation reference level VREF_L1. (The last sentence appears to be incomplete and possibly refers to a different context.) Figure 15A The structure of each of the remaining limiters 1220, 1230 and 1240 can be substantially the same as that of the first limiter 1210a.

[0129] Figure 10 It shows Figure 8 A block diagram of an example of the output circuitry included in the receiver.

[0130] Reference Figure 10 The output circuit 1302a may include a first decoder 1312, a second decoder 1314, a third decoder 1316, a fourth decoder 1318, a first multiplexer 1322, and a second multiplexer 1324. The output circuit 1302a may also include flip-flops (FFs) 1332 and 1334, each of which operates based on a clock signal CLK.

[0131] The first decoder 1312 can generate a first MSB MSB_10 and a first LSB LSB_10 based on a first decision value VOH1, a second decision value VOM1, and a third decision value VOL1. The second decoder 1314 can generate a second MSB MSB_11 and a second LSB LSB_11 based on a fourth decision value VOH2, a fifth decision value VOM2, and a sixth decision value VOL2. The third decoder 1316 can generate a third MSB MSB_01 and a third LSB LSB_01 based on a seventh decision value VOH3, an eighth decision value VOM3, and a ninth decision value VOL3. The fourth decoder 1318 can generate a fourth MSB MSB_00 and a fourth LSB LSB_00 based on a tenth decision value VOH4, an eleventh decision value VOM4, and a twelfth decision value VOL4. For example, each of decoders 1312, 1314, 1316, and 1318 can be a PAM4 decoder.

[0132] The first multiplexer 1322 can output the first bit (e.g., MSB) of the output data ODAT1 by selecting one of the first MSB MSB_10, the second MSB MSB_11, the third MSB MSB_01, and the fourth MSB MSB_00. The second multiplexer 1324 can output the second bit (e.g., LSB) of the output data ODAT1 by selecting one of the first LSB LSB_10, the second LSB LSB_11, the third LSB LSB_01, and the fourth LSB LSB_00. The first bit MSB1 and the second bit LSB1 of the output data ODAT1 can be synchronized with the clock signal CLK by flip-flops 1332 and 1334.

[0133] Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B and Figure 12C It is used to describe Figure 8 A diagram illustrating the operation of the receiver.

[0134] Reference Figure 11A and Figure 11B This shows the equalization of the third reference level VREF_L.

[0135] like Figure 11A As shown, when the previous data (e.g., the previous value DATA_PRE of output data ODAT1) is “00”, equalization can be performed to form a lower compensation reference level VREF_L(-) by reducing the third reference level VREF_L, thus increasing or improving the read margin of the limiter used to read the current data (e.g., the current value DATA_CUR of output data ODAT1).

[0136] like Figure 11B As shown, when the previous value DATA_PRE of the output data ODAT1 is "10", "11" or "01", equalization can be performed to form a higher compensation reference level VREF_L(+) by increasing the third reference level VREF_L. Therefore, the read margin of the limiter used to read the current value DATA_CUR of the output data ODAT1 can be increased or improved.

[0137] Reference Figure 11C This shows the operation of receiver 1002 in the first operation mode MODE1 and the change of reference level VREF_CHANGE in the first operation mode MODE1.

[0138] In the first operating mode MODE1, all of the post-cursor cancellers 1110 to 1140 and limiters 1210 to 1240 can be enabled, and each of the multiplexers 1322 and 1324 can select one of all input values ​​based on both the first MSB1 and the second LSB1. For example, when the previous value DATA_PRE of the output data ODAT1 is "10", multiplexers 1322 and 1324 can select and output the first MSB MSB_10 and the first LSB LSB_10, respectively.

[0139] In the first operating mode, MODE1, equalization can be performed so that the direction of increase and / or decrease of the reference level, as well as the amount of change in the reference level, are different in all possible cases. Figure 11C In the diagram, the determination results obtained by comparing the previous value DATA_PRE of the output data ODAT1 with the reference levels VREF_H, VREF_M, and VREF_L are represented by VOH, VOM, and VOL, respectively. The changes in the reference levels VREF_H, VREF_M, and VREF_L obtained by performing equalization based on the previous value DATA_PRE are also shown. Figure 11C In the table, the symbols "+" and "-" indicate the direction of increase and decrease of the reference level, and the number of symbols indicates the amount of change in the reference level. For example, when the previous value DATA_PRE is "10", the first reference level VREF_H can increase to a first level, as shown by "+". When the previous value DATA_PRE is "11", the first reference level VREF_H can decrease to a second level different from the first level, as shown by "-". When the previous value DATA_PRE is "01", the first reference level VREF_H can decrease to a third level greater than the second level, as shown by "--". When the previous value DATA_PRE is "00", the first reference level VREF_H can decrease to a fourth level greater than the third level, as shown by "---". As mentioned above, the direction of increase and / or decrease of the reference level and the amount of change in the reference level can be different in all cases.

[0140] As a result, in the first operating mode MODE1, equalization can be performed on a reference level of the same voltage level used to read out multi-level signals by different levels and / or directions based on the previous value DATA_PRE (for example, VREF_H can be changed differently by "---", "--", "-", and "+" when DATA_PRE is "00", "01", "11", and "10" respectively). Additionally, in the first operating mode MODE1, equalization can be performed on different reference levels used when the previous value DATA_PRE corresponds to the same value by different levels and / or directions (for example, VREF_H, VREF_M, and VREF_L can be changed differently by "---", "--", and "-" when DATA_PRE is "00").

[0141] In some embodiments, the change in the reference level can be determined as four cases in the PAM4 scheme based on previous data. Each of the three limiters should perform calculations for all four cases in the cyclic expansion structure, and thus a total of twelve (=4*3) calculations can be performed in the first operating mode MODE1.

[0142] Reference Figure 12A , Figure 12B and Figure 12C This illustrates the operation of receiver 1002 in the second operation mode MODE2 and the change of reference level VREF_CHANGE in the second operation mode MODE2.

[0143] like Figure 12A and Figure 12B As shown, in the second operating mode MODE2, the second buffer 1030 can be disabled based on the mode selection signal MSEL. Therefore, the post-verb cancellers 1120 and 1130, limiters 1220 and 1230, and decoders 1314 and 1316 can be disabled, and only the post-verb cancellers 1110 and 1140, limiters 1210 and 1240, and decoders 1312 and 1318 can be enabled. Figure 12A and Figure 12B In the diagram, disabled components are shown by dashed lines. Multiplexer 1322 can select one of the first MSB (MSB_10) and the fourth MSB (MSB_00) based on the first MSB1, and multiplexer 1324 can select one of the first LSB (LSB_10) and the fourth LSB (LSB_00) based on the first MSB1. For example, when the first MSB1 is "0", multiplexers 1322 and 1324 can select and output the fourth MSB (MSB_00) and the fourth LSB (LSB_00), respectively.

[0144] like Figure 12CAs shown, in the second operating mode MODE2, equalization can be performed so that the direction of increase and / or decrease of the reference level and the amount of change of the reference level are the same in at least some of all possible cases. (The remaining text is omitted.) Figure 11C Repeating description. For example, when the previous value DATA_PRE is "10", the first reference level VREF_H can increase to a first level, as shown by "+". When the previous value DATA_PRE is "11", "01", and "00", the first reference level VREF_H can decrease to a second level, as shown by "-". For example, when the first and second levels are the same, the amount of change in the reference level can be the same in all cases, and only the direction of increase and / or decrease in the reference level can be different in some cases. When the previous value DATA_PRE is "11", "01", and "00", the amount of change in the first reference level VREF_H can be different in the first operating mode MODE1, as shown by "-", "--", and "---", however, the amount of change in the first reference level VREF_H can be the same in the second operating mode MODE2, as shown by "-".

[0145] As a result, in the second operating mode MODE2, equalization can be performed on a reference level of the same voltage level used to read out multi-level signals using the same level and direction based on the previous value DATA_PRE (e.g., VREF_H can be changed by "-" when DATA_PRE is "11", "01", and "00"). Furthermore, in the second operating mode MODE2, equalization can be performed on different reference levels used when the previous value DATA_PRE corresponds to the same value using the same level and direction (e.g., VREF_H, VREF_M, and VREF_L can be changed by "-" when DATA_PRE is "00").

[0146] For example, if the desired equalization performance is achieved by controlling or adjusting only the direction of increase and / or decrease of the reference level without controlling or adjusting the amount of change in the reference level, then calculations can be performed only for the direction of increase and / or decrease, and therefore only six (=2*3) calculations can be performed in the second operating mode MODE2.

[0147] Although the example embodiment has been described with the rear vernier cancellers 1110 and 1140 and the limiters 1210 and 1240 enabled in the second operating mode MODE2, the example embodiment is not limited thereto. For example, in the second operating mode MODE2, any two of the rear vernier cancellers 1110 to 1140 and any two of the limiters 1210 to 1240 can be enabled.

[0148] Figure 13 It shows Figure 1 A block diagram of another example of a receiver. (The text will be omitted.) Figure 8 Repeated description.

[0149] Reference Figure 13 The receiver 1004 includes a compensation circuit 1102, a sampling circuit 1202, an output circuit 1304, and a mode selector 1400. The receiver 1004 may also include a data input pad 1010.

[0150] The data input pad 1010, compensation circuit 1102, sampling circuit 1202, and mode selector 1400 can be connected to the reference. Figure 8 and Figure 9 The components described are basically the same.

[0151] The output circuit 1304 can generate output data ODAT1, including the first MSB1 and the second LSB1, based on the first to twelfth determination values ​​VOH1 to VOH4, VOM1 to VOM4 and VOL1 to VOL4.

[0152] In some example embodiments, such as referring to Figure 14 The output circuit 1304 can select or determine the output value of the loop unrolling structure based on some of the decision values ​​VOH1 to VOH4, VOM1 to VOM4, and VOL1 to VOL4. In this example, the number of decoders can be reduced, and the DFE delay can be reduced or minimized.

[0153] The mode selector 1400 can generate a mode selection signal MSEL based on the operating environment to select one of a first operating mode and a second operating mode. Figure 13 In the example, the mode selection signal MSEL can be directly provided to the compensation circuit 1102 and the sampling circuit 1202, and a portion of the compensation circuit 1102 and the sampling circuit 1202 can be disabled or deactivated in the second operating mode.

[0154] Figure 14 It shows Figure 13 A block diagram of an example of the output circuitry included in the receiver.

[0155] Reference Figure 14 The output circuit 1304a may include a first multiplexer 1342, a second multiplexer 1344, a third multiplexer 1346, and a decoder 1362. The output circuit 1304a may also include flip-flops 1352, 1354, and 1356, each of which operates based on a clock signal CLK.

[0156] The first multiplexer 1342 can output a first final decision value VOH_F by selecting one of the first, fourth, seventh, and tenth decision values ​​VOH1 to VOH4. The second multiplexer 1344 can output a second final decision value VOM_F by selecting one of the second, fifth, eighth, and eleventh decision values ​​VOM1 to VOM4. The third multiplexer 1346 can output a third final decision value VOL_F by selecting one of the third, sixth, ninth, and twelfth decision values ​​VOL1 to VOL4. The first final decision value VOH_F, the second final decision value VOM_F, and the third final decision value VOL_F can be synchronized with the clock signal CLK using flip-flops 1352, 1354, and 1356. The decoder 1362 can generate the first MSB1 and the second LSB1 of the output data ODAT1 based on the first final decision value VOH_F, the second final decision value VOM_F, and the third final decision value VOL_F. For example, the decoder 1362 can be a PAM4 decoder.

[0157] Figure 15A and Figure 15B It is used to describe Figure 13 A diagram illustrating the operation of the receiver.

[0158] In the first operating mode MODE1, all of the post-cursor cancellers 1110 to 1140 and the limiters 1210 to 1240 can be enabled, and each of the multiplexers 1342, 1344, and 1346 can select one of all input values ​​based on all of the first final decision value VOH_F, the second final decision value VOM_F, and the third final decision value VOL_F. For example, when the previous value DATA_PRE of the output data ODAT1 is "10" and when the first final decision value VOH_F, the second final decision value VOM_F, and the third final decision value VOL_F are all "1", multiplexers 1342, 1344, and 1346 can respectively select and output the first decision value VOH1, the second decision value VOM1, and the third decision value VOL1.

[0159] Reference Figure 15A and Figure 15B In the second operating mode MODE2, based on the mode selection signal MSEL, only a portion of the rear vernier cancellers 1110 to 1140 and the limiters 1210 to 1240 can be enabled, and other portions of the rear vernier cancellers 1110 to 1140 and the limiters 1210 to 1240 can be disabled, and some paths included in the output circuit 1304a can be disabled.

[0160] For example, such as Figure 15AAs shown, in comparators 1212, 1214, and 1216 included in limiter 1210, only comparator 1212 can be enabled. In comparators 1222, 1224, and 1226 included in limiter 1220, only comparators 1222 and 1224 can be enabled. In comparators 1232, 1234, and 1236 included in limiter 1230, only comparators 1234 and 1236 can be enabled. In comparators 1242, 1244, and 1246 included in limiter 1240, only comparator 1246 can be enabled. In some example embodiments, some components of postcursor eliminators 1110 to 1140 that generate inputs for disabled comparators 1214, 1216, 1226, 1232, 1242, and 1244 may also be disabled.

[0161] In addition, as Figure 15B shown, multiplexer 1342 can select one of first decision value VOH1 and fourth decision value VOH2 based on first final decision value VOH_F. Multiplexer 1344 can select one of fifth decision value VOM2 and eighth decision value VOM3 based on second final decision value VOM_F. Multiplexer 1346 can select one of ninth decision value VOL3 and twelfth decision value VOL4 based on third final decision value VOL_F. For example, when the previous value DATA_PRE of output data ODAT1 is "00" and when the first final decision value VOH_F, the second final decision value VOM_F, and the third final decision value VOL_F are all "0", multiplexers 1342, 1344, and 1346 can respectively select and output fourth decision value VOH2, eighth decision value VOM3, and twelfth decision value VOL4.

[0162] In the second operation mode MODE2, the change based on the reference level of the equalization of receiver 1004 can be substantially the same as that described Figure 12C above.

[0163] Although not shown in detail, in the PAM8 scheme, the compensation circuit can include 8 postcursor eliminators, the sampling circuit can include 8 limiters, each limiter can include seven comparators, and the output circuit can select or determine the output value based on the bits or decision values of the output data.

[0164] Figure 16 and Figure 17 are block diagrams showing a receiver according to an example embodiment. Details related to Figure 8 , Figure 9 , Figure 10 , Figure 12A , Figure 12B , Figure 12C , Figure 13 , Figure 14 , Figure 15A and Figure 15B Repeated description.

[0165] Reference Figure 16 The receiver 1006 may include a data input pad 1010, a buffer 1020, post-cursor cancellers 1110 and 1140, comparators 1212, 1214, 1216, 1242, 1244 and 1246, decoders 1312 and 1318, multiplexers 1322b and 1324b, and triggers 1332 and 1334.

[0166] Receiver 1006 may include only Figure 8 The receiver 1002 includes components that are enabled in the second operating mode. For example, post-vernier cancellers 1110 and 1140 can form a compensation circuit, comparators 1212, 1214, 1216, 1242, 1244, and 1246 can form a sampling circuit, and decoders 1312 and 1318, multiplexers 1322b and 1324b, and flip-flops 1332 and 1334 can form an output circuit. The operation of these components can be compared with reference to... Figure 8 , Figure 9 , Figure 10 , Figure 12A , Figure 12B and Figure 12C The components described operate in basically the same way.

[0167] Reference Figure 17 The receiver 1008 may include a data input pad 1010, a back cursor canceller 1110, 1120, 1130 and 1140, comparators 1212, 1222, 1224, 1234, 1236 and 1246, multiplexers 1342c, 1344c and 1346c, triggers 1352, 1354 and 1356 and a decoder 1362.

[0168] Receiver 1008 may include only Figure 13 The receiver 1004 includes components that are enabled in the second operating mode. For example, post-vernier cancellers 1110, 1120, 1130, and 1140 can form a compensation circuit, comparators 1212, 1222, 1224, 1234, 1236, and 1246 can form a sampling circuit, and multiplexers 1342c, 1344c, and 1346c, flip-flops 1352, 1354, and 1356, and decoder 1362 can form an output circuit. The operation of these components can be compared with reference to... Figure 13 , Figure 14 , Figure 15A and Figure 15B The components described operate in basically the same way.

[0169] If a cyclic unrolled structure is required for timing margin but higher equalization performance is not needed, the receiver according to the example embodiment can be implemented as a cyclic unrolled DFE (where only the second operating mode is applied), such as... Figure 16 and Figure 17 As shown, this reduces circuit size and power consumption. In this example, as referenced... Figure 12C As shown, equalization can be performed on multiple compensation reference levels, so that all multiple compensation reference levels change by the same level, and the direction of equalization can be determined based on the previous value of the output data.

[0170] Figure 18 This is a flowchart illustrating a method for receiving data according to an example embodiment.

[0171] Reference Figure 1 and Figure 18 The method for receiving data according to the example embodiment is performed by the receiver 1000 according to the example embodiment.

[0172] In the method for receiving data according to the example embodiment, a mode selection signal MSEL is generated based on the operating environment (step S100). The mode selection signal MSEL is used to select one of a first operating mode and a second operating mode based on the operating environment. A compensation circuit 1100 generates multiple data signals IDS and multiple reference voltages VREF by compensating for inter-symbol interference on the input data signal DS, which is a multi-level signal, based on the mode selection signal MSEL (step S200). A sampling circuit 1200 generates multiple sampling signals SAM based on the mode selection signal MSEL, the multiple data signals IDS, and the multiple reference voltages VREF (step S300). Output data ODAT, comprising two or more bits, is generated based on the multiple sampling signals SAM (step S400). The current value of the output data is selected based on the previous value of the output data. The compensation circuit 1100 and the sampling circuit 1200 are fully enabled in the first operating mode and partially enabled in the second operating mode.

[0173] Figure 19 This is a block diagram illustrating a computing system according to an example embodiment.

[0174] Reference Figure 19 The computing system 4000 includes a processor 4010, a system controller 4020, and a memory system 4030. The computing system 4000 may also include an input device 4050, an output device 4060, and a storage device 4070.

[0175] The memory system 4030 includes a plurality of storage devices 4034 and a memory controller 4032 for controlling the storage devices 4034. The memory controller 4032 may be included in the system controller 4020. The memory system 4030 may be a memory system according to an example embodiment and may include a receiver according to an example embodiment.

[0176] Processor 4010 can perform various computing functions, such as executing specific software instructions for performing specific calculations or tasks. Processor 4010 can be connected to system controller 4020 via a processor bus. System controller 4020 can be connected to input device 4050, output device 4060, and storage device 4070 via an expansion bus. In this way, processor 4010 can use system controller 4020 to control input device 4050, output device 4060, and storage device 4070.

[0177] Figure 20 This is a block diagram illustrating a communication system according to an example embodiment.

[0178] Reference Figure 20 The communication system 5000 includes a first communication device 5100, a second communication device 5200, and a channel 5300.

[0179] The first communication device 5100 includes a first transmitter 5110 and a first receiver 5120. The second communication device 5200 includes a second transmitter 5210 and a second receiver 5220. The first transmitter 5110 and the first receiver 5120 are connected to the second transmitter 5210 and the second receiver 5220 via a channel 5300. Receivers 5120 and 5220 may be receivers according to an example embodiment. In some example embodiments, each of the first communication device 5100 and the second communication device 5200 may include multiple transmitters and multiple receivers, and the communication system 5000 may include multiple channels for connecting the multiple transmitters and multiple receivers.

[0180] The inventive concept can be applied to a wide range of electronic devices and systems, including storage devices and memory systems. For example, the inventive concept can be applied to systems such as: personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0181] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that various modifications can be made to the exemplary embodiments without substantially departing from the novel doctrine and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments as defined in the claims. Accordingly, it should be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims.

Claims

1. A receiver configured to receive a multilevel signal having three or more voltage levels that are different from each other, the receiver comprising: The compensation circuit is configured to generate multiple data signals and multiple reference voltages by compensating for inter-symbol interference (ISI) on the input data signals, which are said multi-level signals, each of the multiple reference voltages including multiple compensated reference levels. A sampling circuit is configured to generate a plurality of sampling signals based on the plurality of data signals and the plurality of reference voltages, each of the plurality of sampling signals including a plurality of determination values; An output circuit is configured to generate output data based on the plurality of sampled signals and select a current value of the output data based on a previous value of the output data, the output data comprising two or more bits that are different from each other; as well as The mode selector is configured to generate a mode selection signal based on the operating environment for selecting one of a first operating mode and a second operating mode. In the first operating mode, the compensation circuit and the sampling circuit are fully enabled, and in the second operating mode, the compensation circuit and the sampling circuit are partially enabled.

2. The receiver according to claim 1, wherein: In the first operating mode, equalization is performed on the first compensation reference level among the plurality of compensation reference levels, such that all the first compensation reference levels are changed by different amounts. In the second operating mode, equalization is performed on the first compensation reference level such that at least two of the first compensation reference levels change by the same amount, and The first compensation reference level is used to read out the first voltage level among the three or more voltage levels of the multi-level signal.

3. The receiver according to claim 2, wherein: In the first operating mode, equalization is performed on the second compensation reference level among the plurality of compensation reference levels, such that all the second compensation reference levels are changed by different amounts. In the second operating mode, equalization is performed on the second compensation reference level such that at least two of the second compensation reference levels change by the same amount, and The second compensation reference level is used when the previous value of the output data corresponds to the first value.

4. The receiver according to claim 1, further comprising: An environmental sensor is configured to detect changes in the operating environment, and The mode selector is configured to generate the mode selection signal based on the output of the environmental sensor.

5. The receiver according to claim 4, wherein, The environmental sensor includes at least one of a temperature sensor, humidity sensor, pressure sensor, motion sensor, time sensor, space sensor, illuminance sensor, vibration sensor, mechanical stress sensor, impact sensor, frequency sensor, voltage sensor, and channel environment sensor, and the motion sensor includes an acceleration sensor.

6. The receiver according to claim 1, wherein, The mode selector is configured to generate the mode selection signal based on the result of the training operation when the receiver enters the training mode for performing training operations based on an external command.

7. The receiver according to claim 1, wherein: The three or more voltage levels include a first voltage level, a second voltage level, a third voltage level, and a fourth voltage level that are different from each other, and The two or more bits include the first and second bits that are different from each other.

8. The receiver according to claim 7, wherein: The first voltage level is the lowest voltage level among the first voltage level, the second voltage level, the third voltage level, and the fourth voltage level. The second voltage level is higher than the first voltage level. The third voltage level is higher than the second voltage level, and The fourth voltage level is higher than the third voltage level and is the highest voltage level among the first voltage level, the second voltage level, the third voltage level, and the fourth voltage level.

9. The receiver according to claim 7, wherein, The compensation circuit includes: A first post-vernier canceller is configured to generate a first data signal and a first reference voltage when a previous value of the output data corresponds to the fourth voltage level, the first reference voltage including a first compensation reference level, a second compensation reference level and a third compensation reference level. The second post-vernier canceller is configured to generate a second data signal and a second reference voltage when the previous value of the output data corresponds to the third voltage level, the second reference voltage including a fourth compensation reference level, a fifth compensation reference level and a sixth compensation reference level; A third post-vernier canceller is configured to generate a third data signal and a third reference voltage when a previous value of the output data corresponds to the second voltage level, the third reference voltage including a seventh compensation reference level, an eighth compensation reference level, and a ninth compensation reference level; and The fourth post-vernier canceller is configured to generate a fourth data signal and a fourth reference voltage when the previous value of the output data corresponds to the first voltage level, the fourth reference voltage including a tenth compensation reference level, an eleventh compensation reference level and a twelfth compensation reference level.

10. The receiver according to claim 9, wherein, The sampling circuit includes: A first limiter is configured to generate a first sampling signal by comparing the first data signal with a first compensation reference level, a second compensation reference level and a third compensation reference level, the first sampling signal including a first determination value, a second determination value and a third determination value; The second limiter is configured to generate a second sampling signal by comparing the second data signal with the fourth compensation reference level, the fifth compensation reference level and the sixth compensation reference level, the second sampling signal including a fourth determination value, a fifth determination value and a sixth determination value; A third limiter is configured to generate a third sampling signal by comparing the third data signal with the seventh compensation reference level, the eighth compensation reference level, and the ninth compensation reference level, the third sampling signal including a seventh determination value, an eighth determination value, and a ninth determination value; and The fourth limiter is configured to generate a fourth sampling signal by comparing the fourth data signal with the tenth compensation reference level, the eleventh compensation reference level and the twelfth compensation reference level, the fourth sampling signal including the tenth determination value, the eleventh determination value and the twelfth determination value.

11. The receiver according to claim 10, wherein, The output circuit includes: A first decoder is configured to generate a first most significant bit (MSB) and a first least significant bit (LSB) based on the first determination value, the second determination value, and the third determination value. The second decoder is configured to generate a second MSB and a second LSB based on the fourth determination value, the fifth determination value, and the sixth determination value; The third decoder is configured to generate a third MSB and a third LSB based on the seventh determination value, the eighth determination value, and the ninth determination value; The fourth decoder is configured to generate a fourth MSB and a fourth LSB based on the tenth decision value, the eleventh decision value, and the twelfth decision value; A first multiplexer is configured to output the MSB of the output data by selecting one of a first MSB, a second MSB, a third MSB, and a fourth MSB; and The second multiplexer is configured to output the LSB of the output data by selecting one of the first LSB, the second LSB, the third LSB, and the fourth LSB.

12. The receiver according to claim 11, wherein: In the first operating mode, the first, second, third, and fourth rear vernier eliminates, as well as the first, second, third, and fourth limiters, are all enabled. In the second operating mode, only the first and fourth rear vernier eliminates, the third and fourth rear vernier eliminates, and the first and fourth limiters are enabled.

13. The receiver according to claim 12, further comprising: The first buffer is configured to buffer the input data signal and provide the buffered input data signal to the first and fourth post-verb cancellers; as well as The second buffer is configured to buffer the input data signal and provide the buffered input data signal to the second and third post-verb cancellers. The second buffer is disabled in the second operating mode.

14. The receiver according to claim 12, wherein: The first multiplexer is configured to select one of the first MSB, the second MSB, the third MSB, and the fourth MSB based on both the MSB and LSB of the output data in the first operating mode, and to select one of the first MSB and the fourth MSB based on the MSB of the output data in the second operating mode. The second multiplexer is configured to select one of the first LSB, the second LSB, the third LSB, and the fourth LSB based on both the MSB and LSB of the output data in the first operating mode, and to select one of the first LSB and the fourth LSB based on the MSB of the output data in the second operating mode.

15. The receiver according to claim 10, wherein, The output circuit includes: The first multiplexer is configured to output a first final decision value by selecting one of the first decision value, the fourth decision value, the seventh decision value, and the tenth decision value; The second multiplexer is configured to output a second final decision value by selecting one of the second decision value, the fifth decision value, the eighth decision value, and the eleventh decision value; A third multiplexer is configured to output a third final decision value by selecting one of the third decision value, the sixth decision value, the ninth decision value, and the twelfth decision value; and The decoder is configured to generate the MSB and LSB of the output data based on the first final decision value, the second final decision value, and the third final decision value.

16. The receiver according to claim 15, wherein: In the first operating mode, the first, second, third, and fourth rear vernier eliminates, as well as the first, second, third, and fourth limiters, are fully enabled. In the second operating mode, the first rear vernier eliminator, the second rear vernier eliminator, the third rear vernier eliminator, and the fourth rear vernier eliminator, as well as the first limiter, the second limiter, the third limiter, and the fourth limiter, are partially enabled.

17. The receiver according to claim 16, wherein: The first multiplexer is configured to select one of the first determination value, the fourth determination value, the seventh determination value, and the tenth determination value based on all of the first final determination value, the second final determination value, and the third final determination value in the first operating mode, and to select one of the first determination value and the fourth determination value based on the first final determination value in the second operating mode. The second multiplexer is configured to select one of the second decision value, the fifth decision value, the eighth decision value, and the eleventh decision value based on all of the first final decision value, the second final decision value, and the third final decision value in the first operating mode, and to select one of the fifth decision value and the eighth decision value based on the second final decision value in the second operating mode. The third multiplexer is configured to select one of the third, sixth, ninth, and twelfth determination values ​​based on all of the first, second, and third final determination values ​​in the first operating mode, and to select one of the ninth and twelfth determination values ​​based on the third final determination value in the second operating mode.

18. The receiver according to claim 1, wherein: The three or more voltage levels include a first voltage level, a second voltage level, a third voltage level, a fourth voltage level, a fifth voltage level, a sixth voltage level, a seventh voltage level, and an eighth voltage level, all of which are different from each other. The two or more bits include a first, second, and third bit that are different from each other.

19. A storage device comprising: The receiver is configured to receive an input data signal, which is a multi-level signal having three or more voltage levels that are different from each other. as well as The storage cell array is configured to perform a data write operation based on the input data signal. The receiver includes: The compensation circuit is configured to generate a plurality of data signals and a plurality of reference voltages by compensating for inter-symbol interference (ISI) on the input data signals, each of the plurality of reference voltages including a plurality of compensation reference levels. A sampling circuit is configured to generate a plurality of sampling signals based on the plurality of data signals and the plurality of reference voltages, each of the plurality of sampling signals including a plurality of determination values; An output circuit is configured to generate output data based on the plurality of sampled signals, and to select a current value of the output data based on a previous value of the output data, the output data comprising two or more bits that are distinct from each other; and The mode selector is configured to generate a mode selection signal based on the operating environment for selecting one of a first operating mode and a second operating mode. In the first operating mode, the compensation circuit and the sampling circuit are fully enabled, and in the second operating mode, the compensation circuit and the sampling circuit are partially enabled.

20. A method for receiving data based on a multilevel signal having three or more voltage levels that are different from each other, the method comprising: A mode selection signal is generated based on the operating environment to select one of the first operating mode and the second operating mode; The compensation circuit generates multiple data signals and multiple reference voltages based on the mode selection signal by compensating for inter-symbol interference (ISI) on the input data signal, which is the multi-level signal. Each of the multiple reference voltages includes multiple compensated reference levels. The sampling circuit generates multiple sampling signals based on the mode selection signal, the multiple data signals, and the multiple reference voltages, each of the multiple sampling signals including multiple determination values; as well as Output data is generated based on the multiple sampled signals, and the output data includes two or more bits that are different from each other. The current value of the output data is selected based on the previous value of the output data, and In the first operating mode, the compensation circuit and the sampling circuit are fully enabled, and in the second operating mode, the compensation circuit and the sampling circuit are partially enabled.

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