Resource access method and device, computer device and storage medium

Abstract

A resource access method is disclosed in the embodiments of the present application, which comprises: receiving a first access request of a first device for a shared resource, determining occupation state information of the shared resource; and sending the occupation state information to the first device, so that the first device performs a first operation on the shared resource when the occupation state information indicates that the shared resource is not occupied. A resource access device, a computer device and a storage medium are also disclosed in the embodiments of the present application.

Description

Technical Field

[0001] This application relates to the field of computer application technology, and more specifically, to a resource access method, apparatus, computer device, and storage medium. Background Technology

[0002] Today, with the increasing integration of chips, chip computing power has become one of the most important indicators for evaluating a System-on-Chip (SoC). The CPU (Central Processing Unit) has also officially entered the multi-core era from traditional single-core operation. With the development of multi-core applications, the resources within SoC chips are becoming increasingly abundant. Generally speaking, in slightly more complex application scenarios, how to efficiently occupy and release hardware resources (e.g., bus, memory, interrupts) or software resources (e.g., processes) among multiple cores becomes a problem that must be solved in high-performance SoC design. Summary of the Invention

[0003] This application provides a resource access method, apparatus, computer device, and storage medium.

[0004] A first aspect of the embodiments of this application provides a resource access method, the method comprising:

[0005] Receive a first access request from a first device for a shared resource, and determine the occupancy status information of the shared resource;

[0006] The occupancy status information is sent to the first device so that the first device can perform a first operation on the shared resource when the occupancy status information indicates that the shared resource is not occupied.

[0007] In an optional embodiment of this application, determining the occupancy status information of the shared resource includes:

[0008] Obtain the current state value and initial state value of the shared resource;

[0009] Based on the current state value and the initial state value, the occupancy status information of the shared resource is determined.

[0010] In an optional embodiment of this application, the method further includes:

[0011] If the occupancy status information indicates that the shared resource is occupied by the second device, then the first queue information is sent to the first device so that the first device can perform the first operation on the shared resource after the second device finishes accessing the shared resource.

[0012] In an optional embodiment of this application, the method further includes:

[0013] If, while the first device is performing the first operation on the shared resource, it receives a third access request for the shared resource from the third device, then it sends third queue information to the third device so that the third device can perform the third operation on the shared resource after the first device finishes accessing the shared resource.

[0014] In an optional embodiment of this application, the method further includes:

[0015] Receive the first release request from the first device for the shared resource;

[0016] Based on the first release request, the occupancy status information of the shared resource is updated.

[0017] In an optional embodiment of this application, updating the occupancy status information of the shared resource includes:

[0018] Update the read status value to the initial status value.

[0019] In an optional embodiment of this application, the bit width of the initial state value and the bit width of the read state value are consistent with the number of devices accessing the shared resource.

[0020] A second aspect of the present application provides a resource access device, the device comprising: a first determining module and a first sending module;

[0021] The first determining module is used to receive a first access request from the first device for the shared resource and determine the occupancy status information of the shared resource;

[0022] The first sending module is configured to send the occupancy status information to the first device, so that the first device can perform a first operation on the shared resource when the occupancy status information indicates that the shared resource is not occupied.

[0023] A third aspect of this application provides a computer device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above methods.

[0024] A fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the steps of the method as described in any of the above.

[0025] The resource access method provided in this application receives a first access request from a first device for a shared resource and determines the occupancy status information of the shared resource. It then sends the occupancy status information to the first device, enabling the first device to perform a first operation on the shared resource when the occupancy status information indicates that the shared resource is not occupied. Thus, by receiving the device's access request through hardware and determining the occupancy status of the shared resource, access to the shared resource is only permitted when it is not occupied. This achieves exclusive access to the shared resource by the device, overcoming the problem of existing technologies that can only resolve shared resource occupancy conflicts through software intervention, and improving the efficiency of shared resource access. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0027] Figure 1 This application provides a schematic diagram illustrating the principle of a processor core executing atomic operation instructions in a resource access method according to an embodiment of the present application.

[0028] Figure 2 This is a schematic diagram illustrating the principle of resource access by the processor core through atomic operation instructions in a resource access method provided in one embodiment of this application.

[0029] Figure 3 A flowchart illustrating a resource access method provided in one embodiment of this application;

[0030] Figure 4 This is a schematic diagram illustrating the working principle of a resource access method provided in one embodiment of this application;

[0031] Figure 5 Another schematic diagram illustrating the working principle of a resource access method provided in one embodiment of this application;

[0032] Figure 6 This is a schematic diagram of the structure of a resource access device provided in one embodiment of this application;

[0033] Figure 7 A schematic diagram of an atomic operation control circuit and its application environment provided in one embodiment of this application;

[0034] Figure 8 This is a schematic diagram of an atomic operation control circuit provided in one embodiment of this application;

[0035] Figure 9 This is a partial schematic diagram of an atomic operation control circuit provided in one embodiment of this application;

[0036] Figure 10This is a schematic diagram of a computer device structure provided in one embodiment of this application. Detailed Implementation

[0037] In the process of developing this application, the inventors discovered that in slightly complex SoC application scenarios, how to efficiently occupy and release shared resources among multiple processor cores has become a problem that must be solved in high-performance SoC design.

[0038] SoC, often referred to as a system-on-a-chip, is an integrated circuit with a specific purpose, containing a complete system and embedded software. SoC is also a technology used to implement the entire design process, from defining system functions to software / hardware partitioning.

[0039] Here, we take the SMP (Symmetrical Multi-Processing) system, which is common in SoC, as an example. Since SMP systems have multiple processor cores occupying and releasing shared resources at the same time, it is necessary to determine the priority of occupation. That is, when one processor core is performing an operation on data in a certain address space of memory, other processor cores must stop operating on the data in that address space in order to avoid data race problems.

[0040] Due to potential interruptions and preemption issues during the load-update-write (read-modify-write) process, atomic operation instructions such as LDREX (exclusive load) / STREX (exclusive store) can be added to the instruction set of each processor core to achieve exclusive access. Figure 1 As shown. Figure 1 This is a schematic diagram illustrating the principle of a processor core executing atomic operation instructions. The processor core uses the LDREX instruction to read raw data from a segment of the address space of a shared resource it wants to access, and marks that segment of the address space (physical address) as exclusively accessible. At this point, the read access is complete. When the processor core wants to modify the data in that address space, it uses the STREX instruction. When updating the data corresponding to that address space, the STREX instruction checks whether the address space has been marked as exclusively accessible, and uses this status to determine whether to update the value in memory. In this way, the processor core can achieve exclusive access to shared resources, avoiding data race issues. The process of the processor core executing atomic operation instructions is broken down and explained below:

[0041] Instruction A: LDREX Rx, [Ry];

[0042] Here, instruction A reads the data value stored in the address space pointed to by the Ry register, saves the data value to the Rx register (similar to a cache), and marks the address space pointed to by the Ry register as Exclusive Access State. If the LDREX instruction finds that the address space is already marked as Exclusive Access State, it sets the value of the Rx register to 1, indicating that the cache failed, that is, the LDREX instruction execution failed.

[0043] Command B: STREX Rx,Ry,[Rz]

[0044] Here, when executing the STREX instruction, if it is found that the address space is not marked as exclusive access, it means that the LDREX instruction has failed to execute. The processor core cannot update the data in the Rz register through the STREX instruction. At this time, the value of the Rx register is set to 1 to indicate that the STREX instruction has failed to execute.

[0045] Here, when executing instruction B, if the address space pointed to by the Ry register is found to be marked as exclusive access, meaning the LDREX instruction executed successfully, the processor core can now update the data in the Rz register using the STREX instruction. The value of the Ry register is updated in the address space pointed to by the Rz register, and the value of the Rx register is set to 0, indicating that the STREX instruction executed successfully. At this point, the Rx register can be considered a status register for determining whether the instruction executed successfully. After successful instruction execution, the exclusive access state of the Ry register is cleared, and the address space pointed to by the Rz register is marked as Open Access State.

[0046] Once the STREX instruction executes successfully, other registers, such as the R1 register, will find that the exclusive access state of the Ry register has been cleared if they try to use the STREX instruction to update the value in the address space pointed to by the Ry register to the address space pointed to by the R1 register. Therefore, the mechanism of the Rz register accessing the Ry register is realized.

[0047] However, if it is found that the address space pointed to by the Ry register is not marked as exclusive access when executing instruction B, the value of the Ry register will not be updated to the address space pointed to by the Rz register. Instead, the value of the Rx register will be set to 1, indicating that the STREX instruction has failed to execute.

[0048] For example, in a multi-core SoC system, there are two processor cores, CPU0 and CPU1. Figure 2 As shown, Figure 2This is a schematic diagram illustrating the principle of how a processor core accesses resources via atomic operation instructions in an embodiment of this application. If CPU0 wants to initiate a load or store operation on a segment of on-chip memory and does not want other cores (CPU1) to interfere, hoping to exclusively occupy this address space, then CPU0 will initiate an atomic load or atomic store operation on this address space. In this case, CPU1 can only begin executing a load or store operation on the same address space after CPU0's atomic store operation has finished, thus ensuring data consistency in memory, similar to the meaning of cache consistency. This is based on the premise that the processor core's supported instruction set contains atomic instructions such as exclusive load and exclusive store. However, if a processor core's supported instruction set does not contain atomic instructions such as exclusive load and exclusive store, then exclusive access to shared resources cannot be achieved in this situation.

[0049] To address the above problems, this application provides a resource access method, such as... Figure 3 As shown, to solve the aforementioned problems in the prior art, the method may include the following steps:

[0050] S301. Receive the first access request from the first device for the shared resource and determine the occupancy status information of the shared resource;

[0051] S302. Send occupancy status information to the first device so that the first device can perform the first operation on the shared resource when the occupancy status information indicates that the shared resource is not occupied.

[0052] Specifically, in conjunction with the appendix Figure 4 and attached Figure 5The embodiments of this application will be described below. Here, the first device can be a processor core. When the atomic operation module receives a first access request from the first device for a shared resource, it determines the occupancy status information of the shared resource based on the address space of the shared resource. Since multiple cores in an SMP system may simultaneously occupy and release shared resources, there may be situations where multiple cores want to occupy a certain resource at the same time. Assuming that in a certain SMP system, there are two processor cores (CPU0 and CPU1), and the instruction sets supported by CPU0 and CPU1 do not contain atomic operation instructions such as exclusive load and exclusive store, when CPU0 wants to initiate an operation on a shared resource in memory, CPU0 can read the current status value of the shared resource through the AXI bus via the atomic operation module. If the current status value indicates that the shared resource is not occupied, it means that no processor core in the current system is occupying this part of the shared resource, and at this time CPU0 can access the shared resource; at the same time, the atomic operation module configures the current status value of the shared resource as the ID number of CPU0 (assuming that the ID number of CPU0 is 01).

[0053] It should be noted that the atomic operation module can be a semaphore register. A semaphore, often called a signal, is used to control the number of threads accessing a specific resource simultaneously, coordinating these threads to ensure the rational use of resources. Here, the bit width of the initial state value is the same as the number of processor cores; that is, the bit width of the semaphore register is the same as the number of devices accessing the shared resource.

[0054] Here, determining whether a shared resource is occupied can be understood as setting a resource lock for the shared resource. The usage of the shared resource is managed through the resource lock. The resource lock receives a request to access the shared resource, reads the value of the specified position corresponding to the shared resource in the resource lock, and determines whether the shared resource is currently occupied based on the value of the specified position. This provides a reliable shared resource management mechanism, achieving high-efficiency and high-reliability shared resource management without adding software management, and solving the problem of lacking a suitable way to handle shared device access conflicts.

[0055] In an optional embodiment of this application, the method may further include:

[0056] S303. If the occupancy status information indicates that the shared resource is occupied by the second device, then send the first queue information to the first device so that the first device can perform the first operation on the shared resource when the second device ends its access to the shared resource.

[0057] Here, assuming a certain SMP system has two processor cores (CPU0 and CPU1), and the instruction sets supported by CPU0 and CPU1 do not contain atomic operation instructions such as exclusive load and exclusive store, when CPU0 wants to initiate an operation on a shared memory resource, CPU0 can use the atomic operation module via the AXI bus to read the current status value of the shared resource. The current status value indicates that CPU1 is currently occupying the shared resource and has not yet released it, so CPU0 must wait. At this time, the atomic operation module sends a first queue information to CPU0, indicating how many CPUs are currently waiting for CPU1 to finish accessing the shared resource, and CPU0's access position. After CPU1 finishes accessing the shared resource, other CPUs and CPU0 can access the shared resource one by one according to the order of the first queue information. In this way, it can be ensured that each device can access the shared resource in sequence, avoiding access omissions and access conflicts, and achieving efficient access to shared resources.

[0058] In an optional embodiment of this application, the method may further include:

[0059] S304. If a third access request for a shared resource is received from a third device when the first device performs a first operation on the shared resource, then a third queue information is sent to the third device so that the third device performs the third operation on the shared resource when the first device finishes accessing the shared resource.

[0060] Here, assuming a certain SMP system with two processor cores (CPU0 and CPU2), and the instruction sets supported by CPU0 and CPU2 do not contain atomic operation instructions such as exclusive load and exclusive store, when CPU0 wants to initiate an operation on a shared memory resource, CPU0 can use the atomic operation module via the AXI bus to read the current status value of the shared resource. If the current status value indicates that the shared resource is not occupied, it means that no processor core in the current system is occupying this shared resource, and CPU0 can access the shared resource. At the same time, the atomic operation module configures the current status value of the shared resource to the ID number of CPU0 (assuming the ID number of CPU0 is 01). Meanwhile, CPU2 sends an access request to the atomic operation module. The atomic operation module reads the current status value of the shared resource, which indicates that CPU0 is currently occupying the shared resource and has not yet released it, so CPU2 must wait. At this point, the atomic operation module sends a third queue message to CPU2, indicating how many CPUs are currently waiting for CPU0 to finish accessing the shared resource, and CPU2's position in the queue. Only after CPU0 finishes accessing the shared resource can the other CPUs and CPU2 access the shared resource sequentially according to the order in the third queue message. This ensures that each device can access the shared resource in order, avoiding access omissions and conflicts, and achieving efficient access to the shared resource.

[0061] In an optional embodiment of this application, the method may further include:

[0062] S305, Receive the first release request from the first device for the shared resource;

[0063] S306. Based on the first release request, update the occupancy status information of the shared resource.

[0064] Here, again assuming a SoC chip with two processor cores (CPU0 and CPU1), and neither CPU0 nor CPU1 supports atomic instructions such as exclusive load and exclusive store, when CPU0 completes access to the shared resource through the atomic operation module, it sends a first release request to the atomic operation module to inform it that CPU0 has completed access to the shared resource. At this time, the atomic operation module updates the occupancy status of the shared resource based on the first release request, updating the current status value to the initial status value. When the current status value indicates that the shared resource is not occupied, it means that no processor core in the current system is occupying this shared resource. At this time, CPU1 can directly access the shared resource. Simultaneously, CPU1 can configure the current status value of the shared resource using its own CPU1 ID number (assuming CPU0's ID number is 01) through the atomic operation module. After the status register value is configured to 01, if CPU0 or another CPU wants to initiate a read / modify / write operation on the shared resource, CPU0 or other CPUs will read the current status value of the shared resource in the status register and find that the current status value indicates that CPU1 is currently occupying this shared resource and has not yet released it. Therefore, CPU0 or other CPUs must wait. This ensures that each device can access the shared resource sequentially, avoiding access omissions and conflicts, and achieving efficient access to shared resources.

[0065] In one optional embodiment of this application, updating the occupancy status information of the shared resource in S305 may include updating the read status value to the initial status value.

[0066] Here, after a CPU finishes accessing a shared resource, it updates the resource's occupancy status information, resetting the read status value to the initial status value. This ensures that when other CPUs obtain the current status value of the shared resource, they know that the current status value is the same as the initial status value, meaning the shared resource is currently in an open access state, and any CPU can access it. Thus, resetting the shared resource's status value after access ends provides a reliable shared resource management mechanism. It achieves highly efficient and reliable shared resource management without adding software management, solving the problem of lacking suitable methods for handling shared device access conflicts.

[0067] In one optional embodiment of this application, the bit width of the initial state value is consistent with the number of devices accessing the shared resource.

[0068] Here, the bit width of the initial state value is consistent with the number of devices accessing the shared resource. That is, the initial state value is set to m bits, where bit 0 corresponds to device 0, bit 1 corresponds to device 1, and so on, with bit m-1 corresponding to device m-1. By setting the bits of the initial state value, the device accessing the shared resource can be identified. For example, in a SoC chip with three devices (CPU0, CPU1, CPU2), the bit width of the initial state value is the same as the number of processor cores in the system. This means the initial state value is 3 bits wide, and the reset value is all 1s. In other words, only when the initial state value for a shared resource is 111 does it indicate that the shared resource is in open access mode, meaning any device can access it. If the initial state value for a shared resource is not 111, then to rewrite it, the initial state value for that shared resource must first be changed to all 1s before it can be rewritten.

[0069] It should be noted that the bit width of the initial state value is defined here to be consistent with the number of processor cores accessing the shared resource. Furthermore, the processor core number is consistent with the number of bits in the initial state value. That is, assuming the initial state value has a bit width of m bits, bit 0 corresponds to processor core 0, bit 1 corresponds to processor core 1, and so on, with bit m-1 corresponding to processor core m-1. By setting the bits of the initial state value, a shared resource can be bound to a specific processor core.

[0070] It should also be noted that the initial state value is preset to all 1s, meaning that when all bits are 1, it indicates that the shared resource is in an open access state, and all processor cores can access the shared resource. However, when a processor core accesses the shared resource, the value of the corresponding bit for that processor core is updated to 0. For example, when CPU0 accesses the shared resource, and the total number of processor cores is 3, then CPU0 will update the read status value to 110, indicating that CPU0 is accessing the shared resource.

[0071] When the read status value is 10, it indicates that there are a total of 2 processor cores and the shared resource is being accessed by CPU0. If CPU1 wants to initiate a read-modify-write operation on this shared resource, it will find that the current status value indicates that the shared resource is being accessed by CPU0. Therefore, CPU1 knows that CPU0 is currently occupying this shared resource and has not yet released it, so CPU1 must wait. In this way, resource access can be achieved even when the processor core's instruction set does not support atomic operations such as exclusive load and exclusive store.

[0072] It's also important to note that the semaphore register's bit width must match the number of devices accessing the shared resource. For example, if there are four devices in the system, logically their IDs could be 0, 1, 2, and 3. Since the binary representation of 3 is 11, if device 3 writes its ID to the semaphore register, it can still write to the semaphore register even if another device (like device 1) is already using the shared resource. This interrupts device 1's atomic operation, leading to multiple devices accessing the shared resource simultaneously. Later, after device 3 writes 11 and begins an atomic operation, the semaphore register also shows a value of 11. When another device reads the semaphore register as 11, it mistakenly assumes no atomic operation is in progress and initiates a rewrite of the semaphore register, interrupting device 3's atomic operation and again causing multiple devices to access the shared resource simultaneously. Therefore, for these two reasons, the semaphore register bit width needs to be consistent with the number of devices accessing the shared resource, and different bits of the semaphore register represent different device IDs.

[0073] The resource access method provided in this application receives a first access request from a first device for a shared resource and determines the occupancy status information of the shared resource. It then sends the occupancy status information to the first device, enabling the first device to perform a first operation on the shared resource when the occupancy status information indicates that the shared resource is not occupied. Thus, by receiving the device's access request in hardware and determining the occupancy status of the shared resource, access to the shared resource is only permitted when it is not occupied. This achieves exclusive access to the shared resource by the device, overcoming the problem of existing technologies that can only resolve shared resource occupancy conflicts through software intervention, and improving the efficiency of shared resource access. Simultaneously, this mechanism can also add a secure operating mode to the SoC chip. When a processor core wants to occupy certain IP (Intellectual Property) resources in the system, such as UART, I2C, GPIO, SPI, and DDR, an atomic operation module can be used to maintain the atomic operation performance of the system. In this scenario, even if existing processor cores internally support atomic instruction operations, they cannot resolve this exclusive access to a certain IP resource and can only resolve it through software intervention.

[0074] Please see Figure 6 One embodiment of this application provides a resource access device 60, which includes: a first determining module 601 and a first sending module 602, wherein...

[0075] The first determining module 601 is used to receive a first access request from the first device for the shared resource and determine the occupancy status information of the shared resource;

[0076] The first sending module 602 is used to send the occupancy status information to the first device, so that the first device can perform a first operation on the shared resource when the occupancy status information indicates that the shared resource is not occupied.

[0077] In an optional embodiment of this application, the determining module 601 may include: an acquisition submodule 6011 and a determining submodule 6012; wherein,

[0078] The acquisition submodule 6011 is used to acquire the current state value and the initial state value of the shared resource;

[0079] The determining submodule 6012 is used to determine the occupancy status information of the shared resource based on the current status value and the initial status value.

[0080] In an optional embodiment of this application, the device 60 may further include: a second sending module 603, configured to send first queue information to the first device if the occupancy status information indicates that the shared resource is occupied by a second device, so that the first device performs the first operation on the shared resource after the second device finishes accessing the shared resource.

[0081] In an optional embodiment of this application, the device 60 may further include: a third sending module 604, configured to send the third queue information to the third device if, when the first device performs the first operation on the shared resource, it receives a third access request for the shared resource from the third device, so that the third device performs the third operation on the shared resource after the first device finishes accessing the shared resource.

[0082] In an optional embodiment of this application, the first receiving module 601 is further configured to receive a first release request from the first device for the shared resource; and update the occupancy status information of the shared resource based on the first release request.

[0083] For specific limitations regarding the aforementioned resource access device, please refer to the limitations of the resource access method described above, which will not be repeated here. Each module in the aforementioned resource access device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0084] In one embodiment, the above-described resource access method and apparatus can be applied to the atomic operation control circuit 10, such as... Figure 7 As shown, the control circuit 10 can be applied to a multi-core system 20, which may include multiple processors 210, each processor 210 acting as a core to collectively constitute the multi-core system 20. The multi-core system 20 can be any system, such as a SoC system; this embodiment does not impose specific limitations. In application, the atomic operation control circuit 10 provided in this embodiment is signal-connected to each processor 210 in the multi-core system 20, used to control each processor 210 to exclusively load or exclusively write hardware resources (e.g., IP resources, memory resources) or software resources (e.g., processes), i.e., to execute atomic operations on the target resource. It should be explained that the atomic operation in this embodiment refers to an operation that will not be interrupted by the thread scheduling mechanism; once started, this operation runs continuously until completion without any thread interference.

[0085] like Figure 8 As shown, the control circuit 10 may further include: a control module 100 and an atomic operation module 200, wherein:

[0086] The control module 100 is connected to multiple processors 210 via signals. The control module 100 receives data read / write signals from each processor 210 for target resources. For example, if the first processor CPU1 needs to access the target resource I2C interface (one of the three IP resources: I2C, UART, and SPI) for data reading or writing, the first processor CPU1 generates a data read / write request for the target resource's I2C interface, i.e., generates a data read / write signal, and sends it to the control module 100. The control module 100 also controls the multiple processors 210 to perform atomic operations on the target resource based on resource occupancy status signals. This means initiating an exclusive access mechanism for the target resource to avoid interference from other processors in the multi-core system 20, such as CPU2 and CPU3. It should be noted that the processors 210 refer to the individual cores in the multi-core system 20, and the control module 100 is the central medium controlling the access of each processor 210 to various resources, such as loading or writing operations, within the multi-core system 20. The form in which the control module 100 exists varies in different multi-core systems 20. For example, in a SoC system, the control module 100 is a data bus, while in other multi-core systems it exists in other forms.

[0087] The atomic operation module 200 is signal-connected to the control module 100. The atomic operation module 200 generates a resource status signal for the target resource based on the data read / write signals sent by the control module 100, and sends the resource status signal to the control module 100. The resource status signal indicates whether the target resource is currently occupied. The atomic operation module 200 can be configured based on registers, address memory, address control chips, etc. This application embodiment does not impose specific limitations; it only needs to be able to determine whether the target resource is currently occupied and generate the corresponding resource status signal.

[0088] The working principle of the atomic operation control circuit 10 provided in the embodiments of this application is briefly described below:

[0089] The current multi-core system 20 includes multiple processors 210. In this embodiment, the atomic operation control circuit 10 includes a control module 100 and an atomic operation module 200. During operation, each processor 210 sends a data read / write request for a target resource to the control module 100, i.e., the aforementioned data read / write signal. Upon receiving the data read / write signal, the control module 100 triggers the atomic operation module 200 to determine the current resource status of the target resource, generates a resource status signal characterizing whether the target resource is currently occupied, and feeds this resource status signal back to the control module 100. Based on this resource status signal, the control module 100 determines whether the target resource is currently occupied and, based on the determination result, controls whether other processors 210 can access the target resource, thereby ensuring that the current loading or writing operation of the target resource is not interfered with. For example, if the first processor CPU1 wants to read the target resource I2C, but the target resource I2C is currently occupied by the second processor CPU2, the atomic operation module 200 generates a resource status signal indicating that the target resource I2C is occupied or occupied by the second processor CPU2 and feeds it back to the control module 100. Based on the obtained resource status signal, the control module 100 prohibits the first processor CPU1 from accessing the target resource I2C, so as to maintain the exclusive loading or exclusive writing of the target resource I2C by the second processor CPU2 and prevent interference from CPU1, that is, to perform atomic operations on the target resource I2C.

[0090] The atomic operation control circuit 10 provided in this application embodiment includes a control module 100 and an atomic operation module 200. Upon receiving the data read / write signal, the control module 100 triggers the atomic operation module 200 to determine the current resource status of the target resource, generates a resource status signal characterizing whether the target resource is currently occupied, and feeds this resource status signal back to the control module 100. Firstly, the control module 100 determines whether the target resource is currently occupied based on the resource status signal, and controls whether other processors 210 can access the target resource based on the determined result, ensuring that the current loading or writing operation of the target resource is not interfered with. This achieves an atomic operation mechanism for the target resource, thereby solving the technical problem of poor reliability of atomic operations in the current multi-core system 20, and achieving the technical effect of improving the stability and reliability of atomic operations. Secondly, regardless of whether each processor 210 in the multi-core system 20 has atomic operation instructions, the atomic operation control circuit 10 provided in this application embodiment can realize atomic operations for each resource, thereby greatly improving the applicability of atomic operations and the stability and reliability of the multi-core system 20.

[0091] Please see also Figure 8 In an optional embodiment of this application, the atomic operation module 200 includes: a judgment unit 310 and a register unit D0, wherein:

[0092] The first input terminal of the judgment unit 310 is connected to the data read / write interface signal of the control module 100, and the output terminal of the judgment unit 310 is connected to the switch terminal signal of the register unit D0. The judgment unit 310 is used to determine the current occupancy status of the target resource based on the data read / write signal sent by the control module 100 from the data read / write interface and the resource status signal of the target resource generated internally by the register unit D0. The resource status signal can be a level signal, where high and low levels only indicate whether the target resource is currently occupied, resulting in a simple circuit and high efficiency in determining the target resource occupancy status. Alternatively, the resource status signal can be a digital signal, where a specific digital signal carrying information indicates whether the target resource is currently occupied and the processor identifier of the occupied processor 210, making it convenient for the control module 100 and other processors 210 to know which processor 210 is currently occupying the target resource. Of course, the form of the resource status signal includes, but is not limited to, the two forms mentioned above. This embodiment does not impose any limitations and can be specifically set according to the actual situation.

[0093] The switch EN terminal of register unit D0 is connected to the output signal of judgment unit 310, the input terminals D[2:0] of register unit D0 are connected to the data read / write interface signal of control module 100, and the output terminals Q[2:0] of register unit D0 are connected to the second input terminal of judgment unit 310 and the feedback interface signal of control module 100, respectively. The resource identifiers or resource addresses of each hardware and software resource in multi-core system 20 are stored in register unit D0. Register unit D0 determines the occupancy status of each resource according to the update status of the current resource identifier or resource address, generates a resource status signal to characterize whether the target resource is currently occupied, and feeds back the resource status signal to control module 100.

[0094] This embodiment of the application includes a judgment unit 310 and a register unit D0. The input terminals D[2:0] of the register unit D0 are connected to the data read / write interface signal of the control module 100, and the output terminals Q[2:0] of the register unit D0 are connected to the second input terminal of the judgment unit 310 and the feedback interface signal of the control module 100, respectively. During operation, the register unit D0 updates the status of each hardware or software resource, such as the resource identifier or resource address, in real time, generates the corresponding resource occupancy signal, and feeds it back to the control module 100. The control module 100 can then determine the current occupancy status of the target resource to be accessed through the resource status signal sent by the register unit D0, thereby avoiding interference from access operations of other processors when the target resource is accessed by one processor, and further improving the stability and reliability of atomic operations on the target resource.

[0095] Please continue reading Figure 9 In an optional embodiment of this application, the determination unit 310 includes a comparator component 211 and a gate circuit 212.

[0096] The first input terminal of the comparator component 211 is connected to the data read / write interface signal of the control module 100, and the second input terminal of the comparator component 211 is connected to the output terminal Q[2:0] signal of the register unit D0. The comparator component 211 stores a preset duty cycle signal in advance. After receiving the data read / write signal based on the data read / write interface, the comparator component 211 compares the received data read / write signal with the preset duty cycle signal. If the two match, a high-level signal "1" is generated and output; if the two do not match, a low-level signal "0" is generated and output. Correspondingly, if the resource status signal output by the register unit D0 matches the preset duty cycle signal, a high-level signal "1" is output; if the two do not match, a low-level signal "0" is generated and output.

[0097] The input terminals of gate circuit 212 are connected to the output terminal of comparator component 211 and the data read / write interface signal of control module 100, respectively. The output terminal of gate circuit 212 is connected to the EN signal of the switch terminal of register unit D0. Gate circuit 212 is used to control the opening and closing of the EN signal of register unit D0 according to the input signal, thereby controlling the access of register unit D0 by control module 100 and other processors 210. For example, if both signals output by comparator component 211 are high level "1", it means that the target resource is in a duty cycle and a processor 210 needs to access the target resource, or has just initiated an access request but has not yet officially accessed it. At this time, gate circuit 212 performs a logical AND operation on the two high-level "1" signals, and gate circuit 212 opens and outputs a high-level "1" to open the EN switch of register unit D0. Otherwise, if one of the two signals output by comparator component 211 is a low-level signal, the signal output by gate circuit 212 will also be a low-level "0", and the EN switch of register unit D0 cannot be opened. Therefore, control module 100 cannot update or rewrite the status of each resource in register unit D0, that is, it cannot update or rewrite the generated resource status signal.

[0098] This application embodiment includes a comparator component 211 and a gate circuit 212. The comparator component 211 compares a preset occupancy signal stored internally with a data read / write signal received from the data read / write interface of the control module 100 and a resource status signal output from the register unit D0, thereby determining whether the target resource is currently occupied. The determination method is simple and quick, without the need for complex logic processing, thus greatly improving the execution efficiency of atomic operations.

[0099] Please see also Figure 8 and Figure 9 In an optional embodiment of this application, the comparator component 211 includes a first comparator U0 and a second comparator U1:

[0100] The input terminal B of the first comparator U0 is connected to the data read / write interface signal of the control module 100, and the output terminal Y of the first comparator U0 is connected to the first input terminal signal of the gate circuit 212. The first comparator U0 compares the data read / write signal output by the control module 100 with the internally preset duty cycle signal (e.g., 3b'111). If the data read signal icb-wdata[2:0] in the data read / write signal is also 3b'111, then the output terminal Y of the first comparator U0 outputs a high level "1"; if the data read signal icb-wdata[2:0] is not 3b'111, for example, 3b'101, then the output terminal Y of the first comparator U0 outputs a low level "0".

[0101] The input terminal Y of the second comparator U1 is connected to the output terminal Q[2:0] of the register unit D0, and the output terminal Y of the second comparator U1 is connected to the second input terminal of the gate circuit 212. For example, a high level "1" indicates that the target resource is occupied by a certain processor 210, and "0" indicates that it is not occupied. If the multi-core system 20 contains three processors: CPU1, CPU2 and CPU3, and the target resource in register unit D0 is not accessed or occupied by any processor 210, then the output resource status signal is 3b'111; if the target resource in register unit D0 is occupied by the second processor CPU2, then the output resource status signal is 3b'101; if the target resource is occupied by the third processor CPU3, then the output resource status signal is 3b'110.

[0102] The comparator component 211 in the atomic operation control circuit 10 provided in this application embodiment includes a first comparator U0 and a second comparator U1. The first comparator U0 compares the data read / write signal input by the control module 100 with a preset duty cycle signal to determine whether a processor 210 needs to access the target resource. The second comparator U1 compares the resource occupancy signal output by the register unit D0 with the preset duty cycle signal to determine whether the target resource is occupied and which processor 210 occupies it. The determination of the occupancy status of each resource is more accurate, further improving the reliability of atomic operations on the target resource.

[0103] In an optional embodiment of this application, the gate circuit 212 includes an OR gate circuit B0 and an AND gate circuit A0:

[0104] The first input terminal of the OR gate circuit B0 is connected to the output terminal Y signal of the first comparator U0, and the second input terminal of the OR gate circuit B0 is connected to the output terminal Y signal of the second comparator U1.

[0105] If the first comparator U0 outputs a high level "1", it means that a processor 210 needs to access the target resource. If the second comparator U1 outputs a high level "1", it means that the resource status signal output by the register unit D0 matches the preset duty cycle signal, both being 3b'111, indicating that the target resource is not currently occupied by any processor 210. Therefore, as long as the target resource in register unit D0 is not occupied (the resource occupancy signal output by the output terminal Y of the second comparator U1 is all high level "1"), or a processor 210 needs to access the target resource (the output terminal Y of the first comparator U0 is high level "1"), then the OR gate circuit B0 will be turned on and output a high level "1"; if the target resource in register unit D0 is occupied (the resource occupancy signal output by the output terminal Y of the second comparator U1 is not all high level "1"), and no processor 210 needs to access the target resource (the output terminal Y of the first comparator U0 is low level "0"), then the OR gate circuit B0 will output a low level "0".

[0106] The first input terminal of the AND gate circuit A0 is connected to the output terminal of the OR gate circuit B0, the second input terminal of the AND gate circuit A0 is connected to the data read / write interface signal of the control module 100, and the output terminal of the AND gate circuit A0 is connected to the switch terminal signal of the register unit D0. For example, the data read / write signal output by the control module 100 includes a data write signal. The data write signal icb-semaphore-sel-ena is high level "1", indicating that a processor 210 needs to access the target resource. At the same time, the output terminal Y of the OR gate circuit B0 outputs a high level "1", so the first output terminal of the AND gate circuit A0 will generate a high level "1", which turns on the switch terminal EN of the register unit D0. The controller identifies the processor 210 that needs to access the target resource based on the data read signal icb-wdata[2:0], for example, the processor ID is written to the input terminal D[2:0] of the register unit D0. During the period when CLK is high, the state of the Q terminal of register unit D0 changes with the state of the D terminal; after CLK goes low, the Q terminal will retain the state of the D terminal when CLK went low. Therefore, after the next clock cycle or a preset clock cycle, the processor ID will be written to the output terminal Q[2:0] of register unit D0, and register unit D0 can update the resource occupancy signal according to the identifier of the processor 210. For example, if the first processor CPU1 needs to access the target resource, its counter semaphore is modified to 3b'011 to feed back to the control module 100 that the first processor CPU1 is currently exclusively accessing the target resource, and so on, without exhaustive examples.

[0107] In this embodiment of the application, by setting OR gate circuit B0 and AND gate circuit A0 in gate circuit 212, the resource occupancy signal in register unit D0 can be updated or rewritten by the received data read and write signals, so as to facilitate the determination of which processor 210 occupies the target resource, and the atomic operation execution efficiency and reliability are higher.

[0108] In an optional embodiment of this application, the atomic operation control circuit 10 further includes an address selector M0:

[0109] The input of the address selector M0 is connected to the input of the second comparator U1 and the output of the register unit D0, respectively. The output of the address selector M0 is connected to the feedback interface of the control module 100. The address selector M0 is used to determine the processor 210 identifier of the target processor 210 currently occupied by the target resource according to the resource status signal, and return the processor identifier of the first processor 210 to the control module 100 so that the control module 100 can provide feedback to the processor 210 that needs to access the target resource, indicating which specific processor is currently occupying the target resource.

[0110] In an optional embodiment of this application, the control module 100 includes at least a data bus. The data bus is signal-connected to multiple processors 210 and the atomic operation module 200. The data bus is used to receive data read / write signals for target resources sent by each processor 210, and to control the multiple processors 210 to perform atomic operations on the target resources according to resource occupancy status signals. This embodiment of the application does not require additional central mediating; it directly uses the data bus as the central mediating medium between each processor 210 and the atomic operation module 200 in the multi-core system 20, resulting in high reliability and significantly reducing the cost of atomic operation execution.

[0111] In one optional embodiment of this application, the target resource includes at least one of protocol resources and memory resources. The protocol resource is an IP resource, and different protocol interfaces are used, such as I2C, UART, and SPI interfaces. The memory resource can be physical memory or virtual memory; this embodiment does not impose a specific limitation, and the appropriate option can be selected based on the actual situation. Of course, the atomic operation control circuit 10 provided in this embodiment can control atomic operations corresponding to the hardware resources of the protocol resources and memory resources, and can also control atomic operations corresponding to software resources such as processes; this is not limited here.

[0112] Another embodiment of this application provides an atomic operation control system, including: an atomic operation control circuit 10 as described in any of the previous embodiments, and a plurality of processors 210, all of which are signal-connected to the control module 100 in the atomic control circuit.

[0113] The beneficial effects of the atomic operation control circuit 10 have been described in detail in the above embodiments and will not be repeated here.

[0114] In one embodiment, a computer device is provided, the internal structure of which can be as follows: Figure 10 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements one of the resource access methods described above. This includes: memory and a processor; the memory stores a computer program; and the processor executes the computer program to implement any step of the resource access method described above.

[0115] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, can perform any of the steps in the resource access method described above.

[0116] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0117] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0118] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0119] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0120] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0121] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A resource access method, characterized in that, It is applied to an atomic operation control circuit, the atomic operation control circuit comprising: A control module is connected to multiple processors via signals, and the control module is used to receive data read / write signals for target resources sent by each of the processors. An atomic operation module, signal-connected to the control module, is used to generate a resource status signal for the target resource based on the data read / write signal sent by the control module, and send the resource status signal to the control module; wherein, the resource status signal is used to characterize whether the target resource is currently occupied; the atomic operation module includes: a judgment unit, the first input terminal of which is signal-connected to the data read / write interface of the control module; a register unit, the switch terminal of which is signal-connected to the output terminal of the judgment unit, the input terminal of which is signal-connected to the data read / write interface of the control module, and the output terminal of which is signal-connected to the second input terminal of the judgment unit and the feedback interface of the control module; wherein, the judgment unit includes: a comparator component, the first input terminal of which is signal-connected to the data read / write interface of the control module, and the second input terminal of which is signal-connected to the output terminal of the register unit; a gate circuit, the input terminal of which is signal-connected to the output terminal of the comparator component and the data read / write interface of the control module, and the output terminal of which is signal-connected to the switch terminal of the register unit; The control module is also used to control multiple processors to perform atomic operations on the target resource according to the resource status signal; The method includes: Receive a first access request from a first device for a shared resource, and determine the occupancy status information of the shared resource; The occupancy status information is sent to the first device so that the first device can perform a first operation on the shared resource when the occupancy status information indicates that the shared resource is not occupied.

2. The method according to claim 1, characterized in that, Determining the occupancy status information of the shared resource includes: Obtain the current state value and initial state value of the shared resource; Based on the current state value and the initial state value, the occupancy status information of the shared resource is determined.

3. The method according to claim 1 or 2, characterized in that, The method further includes: If the occupancy status information indicates that the shared resource is occupied by the second device, then the first queue information is sent to the first device so that the first device can perform the first operation on the shared resource after the second device finishes accessing the shared resource.

4. The method according to claim 3, characterized in that, The method further includes: If, while the first device is performing the first operation on the shared resource, it receives a third access request for the shared resource from the third device, then it sends third queue information to the third device so that the third device can perform the third operation on the shared resource after the first device finishes accessing the shared resource.

5. The method according to claim 1 or 2, characterized in that, The method further includes: Receive the first release request from the first device for the shared resource; Based on the first release request, the occupancy status information of the shared resource is updated.

6. The method according to claim 5, characterized in that, Updating the occupancy status information of the shared resources includes: Update the read status value to the initial status value.

7. The method according to claim 6, characterized in that, The bit width of the initial state value and the bit width of the read state value are consistent with the number of devices accessing the shared resource.

8. A resource access device, characterized in that, An atomic operation control circuit is applied to an atomic operation control circuit, comprising: a control module, which is signal-connected to multiple processors and receives data read / write signals for a target resource from each processor; and an atomic operation module, signal-connected to the control module, which generates a resource status signal for the target resource based on the data read / write signals sent by the control module and sends the resource status signal to the control module; wherein the resource status signal indicates whether the target resource is currently occupied; the atomic operation module includes: a judgment unit, the first input of which is signal-connected to the data read / write interface of the control module; and a register unit, the switch of which is signal-connected to the output of the judgment unit. The register unit is connected to the data read / write interface of the control module, and its output is connected to the second input of the judgment unit and the feedback interface of the control module. The judgment unit includes: a comparator component, whose first input is connected to the data read / write interface of the control module, and whose second input is connected to the output of the register unit; and a gate circuit, whose inputs are connected to the output of the comparator component and the data read / write interface of the control module, and whose output is connected to the switch of the register unit. The control module is further configured to control multiple processors to perform atomic operations on the target resource based on the resource status signal. The device includes: a first determining module and a first transmitting module; wherein... The first determining module is used to receive a first access request from the first device for the shared resource and determine the occupancy status information of the shared resource; The first sending module is configured to send the occupancy status information to the first device, so that the first device can perform a first operation on the shared resource when the occupancy status information indicates that the shared resource is not occupied.

9. A computer device, comprising: The method includes a memory and a processor, the memory storing a computer program, characterized in that the processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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