A solar charger with integrated load output control

Abstract

The application relates to a solar cell charger, in particular to a solar charger integrated with load output control. The charger comprises a storage battery, a solar panel, a synchronous Buck rectifier circuit, a processor, a flyback power supply and a load output control circuit, wherein the flyback power supply provides multiple isolated voltages for the chip and the circuit, the control end of the synchronous Buck rectifier circuit is connected with the first output end of the processor, and the control end of the load output control circuit is connected with the second output end of the processor. The purpose is to design a solar charger integrated with load output control, which can automatically drive other loads to work while charging the battery, reduce the power loss, and has the advantages of stable system operation, safety, etc. Compared with the prior art, the system has the advantages of good stability, remote monitoring of the battery charging state, effective protection of the solar panel and the storage battery, reliable storage of operation data, etc.

Description

A solar charger with integrated load output control Technical Field

[0001] This invention relates to solar cell chargers, and more particularly to a solar cell charger with integrated load output control. Background Technology

[0002] Solar cell chargers use solar energy as their power source, converting light energy into electrical energy and storing it in a battery through a control circuit. Currently, solar cell chargers include a solar panel, a battery, a synchronous Buck rectifier circuit, as well as charging current sampling circuits, battery voltage sampling circuits, and solar panel output voltage sampling circuits. Their shortcomings include the following:

[0003] 1. Because the output voltage of a solar cell charger is relatively unstable, it is difficult to start up smoothly when the voltage is very low; and under high voltage conditions, the circuit cannot be guaranteed to withstand high voltage surges. The system itself has poor operating voltage stability and poor safety.

[0004] 2. While the battery is charging, it should not be connected to any load (such as an electric fan, mobile phone, or computer charger), as this can easily lead to significant energy loss. If no load is connected, because the battery's safe charging current is relatively small, if the charging voltage is too high during charging, the current will also increase, leading to increased heat generation at the battery electrodes. Simultaneously, because the solar panel has a high power output, it will switch to a constant voltage charging state when the charging voltage reaches the battery's maximum voltage, preventing the solar panel from operating at its maximum power point and causing some energy loss.

[0005] 3. When the voltage of the solar panel is lower than that of the battery, especially at night or on cloudy or rainy days, the battery's electrical energy will flow to the solar panel, causing power loss or even damage to the solar panel, leaving the solar panel unprotected.

[0006] 4. Existing solar chargers cannot monitor the charging process in real time, so users are not notified promptly when the battery is fully charged. If the battery continues to charge even when it is already fully charged, it may lead to overcharging or even damage the battery. Summary of the Invention

[0007] The purpose of this invention is to design a solar charger that can automatically drive other loads to work while charging the battery, thereby reducing power loss, and has integrated load output control with stable system operation and good safety.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: a solar charger with integrated load output control, comprising a battery, a solar panel, a synchronous Buck rectifier circuit, a charging current sampling circuit, a battery voltage sampling circuit, and a solar panel output voltage sampling circuit, characterized in that it further includes a processor U10 with chip model TMS320F28021, and a flyback power supply and load output control circuit based on model UC2845 control chip U4, wherein:

[0009] The power input terminal of the flyback power supply is connected to the output terminal of the battery. The output terminal of the flyback power supply outputs analog power supply voltage AVCC, digital circuit power supply voltage VCC, positive digital power supply voltage DVCC, and positive and negative power supply voltages VDD and VEE, respectively.

[0010] The synchronous Buck rectifier circuit is a synchronous Buck rectifier circuit based on the IR2110S driver chip U8. The power output terminal of the solar panel is connected to the input terminal of the synchronous Buck rectifier circuit, and the output terminal of the synchronous Buck rectifier circuit is connected to the two power terminals of the battery. Pins 12 and 14 of the driver chip U8 in the synchronous Buck rectifier circuit are connected to pins 28 and 37 of the processor U10, respectively.

[0011] The load output control circuit includes an N-channel MOSFET Q7, an optocoupler U5, and an NPN transistor Q8. The positive terminal of the battery is connected to the drain of the N-channel MOSFET Q7 through the load output interface CN3. The source of the N-channel MOSFET Q7 is connected to the negative terminal of the battery. The gate of the N-channel MOSFET Q7 is connected to the emitter of the optocoupler U5. The collector of the optocoupler U5 is connected to the analog power supply voltage AVCC through a resistor R18. The anode of the optocoupler U5 is connected to the digital circuit power supply voltage VCC through a resistor R19. The cathode of the optocoupler U5 is connected to the collector of the NPN transistor Q8. The emitter of the NPN transistor Q8 is connected to the negative terminal PV- of the solar panel. The base of the NPN transistor Q8 is connected to pin 37 of the processor U10.

[0012] To further improve the stability of the system's operating voltage and provide multiple system operating voltages, the present invention makes the following modifications to the technical solution:

[0013] The transformer T in the flyback power supply has 4 output windings. The output terminal of the first winding T1 is connected to the first rectifier and filter circuit 1. The negative terminal of the first rectifier and filter circuit is connected to the negative terminal PV- of the solar panel. The digital circuit power supply voltage VCC is output from both ends of the first rectifier and filter circuit.

[0014] The output terminal of the second winding T2 is connected to the second rectifier and filter circuit. The two ends of the second rectifier and filter circuit are connected to a series voltage divider branch composed of the first voltage divider resistor R10 and the second voltage divider resistor R16. The connection point of the first voltage divider resistor R10 and the second voltage divider resistor R16 is connected to the negative terminal PV- of the solar panel. The positive power supply voltage VDD is output from the two ends of the first voltage divider resistor R10, and the negative power supply voltage VEE is output from the two ends of the second voltage divider resistor R16.

[0015] The output terminal of the third winding T3 is connected to the third rectifier and filter circuit. The negative terminal of the third rectifier and filter circuit is grounded, and the positive digital power supply voltage DVCC is output from both ends of the third rectifier and filter circuit.

[0016] The output terminal of the fourth winding T4 is connected to the fourth rectifier and filter circuit. The negative terminal of the fourth rectifier and filter circuit is connected to the negative terminal PV- of the solar panel. The analog power supply voltage AVCC is output from both ends of the fourth rectifier and filter circuit.

[0017] To prevent the battery current from flowing back into the solar panel and effectively protect the solar panel, the present invention makes the following modifications to the technical solution:

[0018] The charging current sampling circuit includes a current sampling resistor LR1 and a first voltage amplifier circuit U3 with chip model OP07CDR. The two ends of the current sampling resistor LR1 are connected to the input terminal of the first voltage amplifier circuit U3, and the output of the first voltage amplifier circuit U3 is connected to pin 7 of the processor U10. The charging current sampling circuit also includes a reverse current protection circuit for the battery, which includes a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a fourth PNP transistor Q6, and a fifth NMOS transistor Q5. One end of the current sampling resistor LR1 is connected to the negative terminal PV of the solar panel. The other end is connected to the drain of the fifth NMOS transistor Q5 and the cathode of diode D3. The anode of diode D3 is connected to the emitter of the first NPN transistor Q1. The positive terminal of the analog power supply voltage AVCC is connected to the collector and base of the first NPN transistor Q1 and the base of the third NPN transistor Q3 through resistor R3. The collector of the third NPN transistor Q3 is connected to the positive terminal of the analog power supply voltage AVCC through resistor R9. The emitters of the second NPN transistor Q2 and the fourth PNP transistor Q6 are connected to form a push-pull circuit. The output is connected to the fifth NMOS transistor Q5 through resistor R17. The gate of MOSFET Q5, the collector of the second NPN transistor Q2, and the positive terminal of the analog power supply voltage AVCC are connected. The base of the second NPN transistor Q2, the base of the fourth PNP transistor Q6, and the collector of the third NPN transistor Q3 are connected. The emitter of the third NPN transistor Q3 is connected to the anode of diode D4. The cathode of diode D4, the collector of the fourth PNP transistor Q6, and the source of the fifth NMOS transistor Q5 are connected to the negative terminal BAT- of the battery.

[0019] To improve electrical safety by remotely monitoring the battery's charging status and controlling the status of other electrical appliances on the load, this invention provides the following configuration for the technical solution: A 485 data communication circuit is also included. This circuit comprises three optocouplers U11, U13, and U14, and a signal conversion chip SU1 of model SP485. Pin 1 of the signal conversion chip SU1 is connected to the cathode of optocoupler U11, and pins 2 and 3 of the signal conversion chip SU1 are connected to the collector of optocoupler U13. Pin 4 of the signal conversion chip SU1 is connected to the collector of the optocoupler U14. The collector of the optocoupler U11 is connected to pin 6 of the processor U10. The cathode of the optocoupler U13 is connected to pin 36 of the processor U10. The cathode of the optocoupler U14 is connected to pin 6 of the processor U10. The anode of the optocoupler U11 is connected to the positive terminal of the positive digital power supply voltage DVCC. Pin 5 of the signal conversion chip SU1, the cathodes of the optocouplers U13 and U14 are all connected to the ground terminal of the positive digital power supply voltage DVCC.

[0020] To store important variables required during operation and ensure the writing and reading of stored data, this invention makes the following settings to the technical solution: Pins 1 and 48 of the processor U10 are connected to pins 6 and 5 of the AT24C64 data storage chip U9, respectively, and communicate with the processor U10 via an IIC interface. Pins 1, 2, 3, and 4 of the data storage chip U9 are connected to the negative terminal PV- of the solar panel, and pin 7 of the data storage chip U9 is connected to the solar panel via a pull-down resistor R46. The negative terminal PV- of the solar panel, pins 6 and 5 of the data storage chip U9 are also connected to pins 6 and 5 of the clock chip U12 (model PCF8563). Pin 8 of the data storage chip U9 is connected to the 3.3V positive power supply voltage VDD through diode D11, and is also connected to the positive terminal of the supercapacitor WC1 through current limiting resistor R53. Pins 1 and 2 of the clock chip U12 are connected to an external crystal oscillator circuit to provide the operating frequency. Pins 45 and 46 of the processor U10 are connected to an external 16MHz crystal oscillator circuit to ensure normal operation. Attached Figure Description

[0021] Figure 1 is a block diagram illustrating the working principle of this embodiment.

[0022] Figure 2 is a circuit diagram of the flyback power supply in this embodiment.

[0023] Figure 3 is a circuit diagram of the core system processor in this embodiment.

[0024] Figure 4 is a synchronous Buck rectifier circuit diagram in this embodiment.

[0025] Figure 5 is a diagram of the load output control circuit in this embodiment.

[0026] Figure 6 shows the charging current sampling circuit and the anti-battery current reverse flow protection circuit in this embodiment.

[0027] Figure 7 is a circuit diagram of the 485 data communication circuit in this embodiment.

[0028] Figure 8 is a circuit diagram of the operational amplifier for acquiring voltage signals from the battery and solar panel in this embodiment. Detailed Implementation

[0029] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0030] As shown in Figure 1, this embodiment includes a battery, a solar panel, a flyback power supply based on a UC2845 control chip U4, a processor U10 with a TMS320F28021 chip, a synchronous Buck rectifier circuit based on an IR2110S driver chip U8, a load output control circuit, a 485 data communication circuit, a charging current sampling circuit, a battery voltage sampling circuit, and a solar panel output voltage sampling circuit, wherein:

[0031] (1) As shown in Figure 2, the power input terminal of the flyback power supply is connected to the output terminal of the battery. The output terminal of the flyback power supply outputs analog power supply voltage AVCC, digital circuit power supply voltage VCC, positive digital power supply voltage DVCC, and positive and negative power supply voltages VDD and VEE, respectively, as follows:

[0032] The transformer T in the flyback power supply has 4 output windings. The output terminal of the first winding T1 is connected to the first rectifier and filter circuit 1. The negative terminal of the first rectifier and filter circuit 1 is connected to the negative terminal PV- of the solar panel. The digital circuit power supply voltage VCC is output from both ends of the first rectifier and filter circuit 1.

[0033] The output terminal of the second winding T2 is connected to the second rectifier and filter circuit 2. The two ends of the second rectifier and filter circuit 2 are connected to a series voltage divider branch composed of the first voltage divider resistor R10 and the second voltage divider resistor R16. The connection point of the first voltage divider resistor R10 and the second voltage divider resistor R16 is connected to the negative terminal PV- of the solar panel. The positive power supply voltage VDD is output from the two ends of the first voltage divider resistor R10, and the negative power supply voltage VEE is output from the two ends of the second voltage divider resistor R16.

[0034] The output terminal of the third winding T3 is connected to the third rectifier and filter circuit 3. The negative terminal of the third rectifier and filter circuit 3 is grounded, and the positive digital power supply voltage DVCC is output from both ends of the third rectifier and filter circuit 3.

[0035] The output terminal of the fourth winding T4 is connected to the fourth rectifier and filter circuit 4. The negative terminal of the fourth rectifier and filter circuit 4 is connected to the negative terminal PV- of the solar panel. The analog power supply voltage AVCC is output from both ends of the fourth rectifier and filter circuit 4.

[0036] (2) As shown in Figures 4 and 3, the synchronous BUCK rectifier circuit includes a driver chip (U8), an NMOS transistor Q9, an NMOS transistor Q10, an inductor L1, and a capacitor C6. Pin 8 of the driver chip U8 is connected to the gate of the NMOS transistor Q9, pin 1 is connected to the gate of the NMOS transistor Q10, pin 6 is connected to the source of the NMOS transistor Q9, the drain of the NMOS transistor Q10, and one end of the high-frequency inductor L1, pins 12 and 14 are connected to pins 28 and 37 of the processor U10, respectively. The drain of the NMOS transistor Q9 is connected to the positive terminal PV+ of the photovoltaic panel, and the source of the NMOS transistor Q10 is connected to the negative terminal PV- of the photovoltaic panel. The other end of the inductor L1 is connected to the positive terminal of the capacitor C6 and the positive terminal of the battery. The negative terminal of the battery is connected to the negative terminal of the capacitor C6 and the negative terminal PV- of the photovoltaic panel through a charging current detection circuit.

[0037] (3) As shown in Figures 1, 5, and 3, the load output control circuit includes an N-channel MOSFET Q7, an optocoupler U5, and an NPN transistor Q8. The positive terminal of the battery is connected to the drain of the N-channel MOSFET Q7 through the load output interface CN3. The source of the N-channel MOSFET Q7 is connected to the negative terminal of the battery. The gate of the N-channel MOSFET Q7 is connected to the emitter of the optocoupler U5. The collector of the optocoupler U5 is connected to the analog power supply voltage AVCC through a resistor R18. The anode of the optocoupler U5 is connected to the digital circuit power supply voltage VCC through a resistor R19. The cathode of the optocoupler U5 is connected to the collector of the NPN transistor Q8. The emitter of the NPN transistor Q8 is connected to the negative terminal PV- of the solar panel. The base of the NPN transistor Q8 is connected to pin 37 of the processor U10.

[0038] (4) As shown in Figures 1, 6, and 3, the charging current sampling circuit includes a current sampling resistor LR1 and a first voltage amplifier circuit U3 with a chip model of OP07CDR. The two ends of the current sampling resistor LR1 are connected to the input terminal of the first voltage amplifier circuit U3. Pin 6 of the first voltage amplifier circuit U3 is connected to pin 7 of the processor U10. The charging current sampling circuit is also provided with a reverse current protection circuit for the battery, which includes a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a fourth PNP transistor Q6, and a fifth NMOS transistor Q5. One end of the current sampling resistor LR1 is connected to the solar panel. The negative terminal of the transistor is connected to the PV-terminal, and the other end is connected to the drain of the fifth NMOS transistor Q5 and the cathode of the diode D3. The anode of the diode D3 is connected to the emitter of the first NPN transistor Q1. The positive terminal of the analog power supply voltage AVCC is connected to the collector and base of the first NPN transistor Q1 and the base of the third NPN transistor Q3 through resistor R3. The collector of the third NPN transistor Q3 is connected to the positive terminal of the analog power supply voltage AVCC through resistor R9. The emitters of the second NPN transistor Q2 and the fourth PNP transistor Q6 are connected to form a push-pull circuit. The output is connected to the fifth NMOS transistor Q5 through resistor R17. The gate of MOSFET Q5, the collector of the second NPN transistor Q2, and the positive terminal of the analog power supply voltage AVCC are connected. The base of the second NPN transistor Q2, the base of the fourth PNP transistor Q6, and the collector of the third NPN transistor Q3 are connected. The emitter of the third NPN transistor Q3 is connected to the anode of diode D4. The cathode of diode D4, the collector of the fourth PNP transistor Q6, and the source of the fifth NMOS transistor Q5 are connected to the negative terminal BAT- of the battery.

[0039] (4) As shown in Figures 1, 7, and 4, the data communication circuit includes three optocouplers U11, U13, and U14 and a signal conversion chip SU1 of model SP485. Pin 1 of the signal conversion chip SU1 is connected to the cathode of the optocoupler U11. Pins 2 and 3 of the signal conversion chip SU1 are connected to the collector of the optocoupler U13. Pin 4 of the signal conversion chip SU1 is connected to the collector of the optocoupler U14. The collector of the optocoupler U11 is connected to pin 6 of the processor U10. The cathode of the optocoupler U13 is connected to pin 36 of the processor U10. The cathode of the optocoupler U14 is connected to pin 6 of the processor U10. The anode of the optocoupler U11 is connected to the positive terminal of the positive digital power supply voltage DVCC. Pin 5 of the signal conversion chip SU1 and the cathodes of the optocouplers U13 and U14 are connected to the ground terminal of the positive digital power supply voltage DVCC.

[0040] (5) As shown in Figures 1, 8, and 3, the sampling data operational amplifier circuit of the battery voltage sampling circuit and the solar panel output voltage sampling circuit adopts the TL074IDR operational amplifier U1. Pins 9 and 10 of the operational amplifier U1 are connected to the two ends of the battery through corresponding resistors. Pins 13 and 12 of the operational amplifier U1 are connected to the two ends of the solar panel through corresponding resistors. Pin 2 of the operational amplifier U1 is connected to one end of the internal temperature acquisition circuit through interface CN5. The other end of the internal temperature acquisition circuit is connected to +3.3V through resistor R26. Pin 6 of the operational amplifier U1 is connected to one end of the external temperature acquisition circuit through interface CN6. The other end of the external temperature acquisition circuit is connected to +3.3V through resistor R36. Pins 1, 7, 8, and 14 of the operational amplifier U1 are connected to pins 6, 10, 9, and 8 of the processor U10, respectively.

[0041] (6) As shown in Figure 3, in order to store important variables required during operation, pins 1 and 48 of the processor U10 are connected to pins 6 and 5 of the data storage chip U9 with model number AT24C64, respectively, and communicate with the processor U10 through the IIC interface. Pins 1, 2, 3 and 4 of the data storage chip U9 are connected to the negative terminal PV- of the solar panel to ensure that the data storage chip U9 can write and read data. Pin 7 of the data storage chip U9 is connected to the negative terminal PV- of the solar panel via pull-down resistor R46. Pins 6 and 5 of the data storage chip U9 are also connected to pins 6 and 5 of the clock chip U12 (model PCF8563). Pin 8 of the data storage chip U9 is connected to the 3.3V positive power supply voltage VDD via diode D11, and is also connected to the positive terminal of the supercapacitor WC1 via current-limiting resistor R53. Under external power supply, supercapacitor WC1 can be charged. When power is off, the clock chip U12 can operate normally by being powered by supercapacitor WC1. Pins 1 and 2 of the clock chip U12 are connected to an external crystal oscillator circuit to provide the operating frequency. Pins 45 and 46 of the processor U10 are connected to an external 16MHz crystal oscillator circuit to ensure normal operation.

[0042] During operation, the battery first provides power to the system, and then the flyback power supply starts working. The output of the flyback power supply outputs analog power supply voltage AVCC, digital circuit power supply voltage VCC, positive digital power supply voltage DVCC, and positive and negative power supply voltages VDD and VEE, respectively, to provide working power to the relevant circuits and chips.

[0043] Afterwards, the system initializes and reads system parameters from the AT24C64 data storage chip U9 for basic configuration. Then, the battery voltage sampling circuit, solar panel output voltage sampling circuit, and charging current sampling circuit send the collected voltage and current information to the processor U10. The processor U10 processes the collected data as follows:

[0044] If the battery voltage is greater than the open-circuit voltage of the solar panel, it will not charge. Furthermore, the anti-reverse current circuit (as shown in Figures 4 and 6) can prevent electricity from flowing to the solar panel and causing energy loss, while effectively protecting the solar panel.

[0045] If the solar panel voltage is higher than the battery voltage, charging begins. Once charging starts, signals are output from pins 28 and 29 of the processor U10 to pins 12 and 14 of the driver chip U8 in the synchronous Buck rectifier circuit. The processor U10 controls different charging modes by issuing square wave signals with different duty cycles. When the battery charge is too low, the processor issues a very low duty cycle, allowing only a portion of the current to pass through, using trickle charging to activate the battery. If the battery charge is slightly low, the processor issues a higher duty cycle, using constant current fast charging. If the battery charge is high, the processor issues a lower duty cycle square wave signal for constant voltage charging to prevent damage from excessive voltage. If the battery charge is close to saturation, the processor issues a very low duty cycle, allowing only a portion of the current to pass through, entering a float charging phase to stabilize the voltage.

[0046] At the same time, when the battery starts charging, when pin 37 of the processor U10 sends a high-level signal, the N-channel MOSFET Q7 in the load output control circuit is turned on. The load output control circuit connects the power output line of the battery, and the battery power can provide working power to the load through the output interface CN3, avoiding energy loss during charging.

[0047] When the 485 data communication circuit is connected to an external source and receives commands, it sends system operating parameters and status information to the 485 data communication circuit for feedback, depending on the specific commands. Therefore, administrators can use a host computer to remotely monitor the battery charging status and control the status of other electrical appliances on the load, improving electrical safety.

[0048] In summary, the present invention has the following advantages compared with the prior art:

[0049] 1. The system boasts excellent operational stability. Because the processor demands high stability from the power supply system, severe interference can affect accuracy and lead to malfunctions. The system provides multiple isolated operating voltages with independent control and protection, significantly improving operational stability.

[0050] 2. The solar panels are effectively protected and prevent power loss. Because of the built-in backflow protection circuit, when the solar panel voltage is lower than the battery voltage, especially at night or on cloudy or rainy days, the battery's power will not flow to the solar panels, preventing power loss or even damage to the solar panels and effectively protecting them.

[0051] 3. It allows for remote monitoring of the battery charging status, effectively preventing overcharging and damage to the battery. Equipped with a data communication circuit, management personnel can use a host computer to remotely monitor the battery charging status and control the status of other electrical appliances on the load, improving electrical safety.

[0052] 4. Reliable data storage. The inclusion of data storage chips and power outage protection measures ensures the reliability of data writing and reading.

Claims

1. A solar charger with integrated load output control, comprising a battery, a solar panel, a synchronous Buck rectifier circuit, a charging current sampling circuit, a battery voltage sampling circuit, and a solar panel output voltage sampling circuit, characterized in that... It also includes a processor U10 with chip model TMS320F28021, and a flyback power supply and load output control circuit based on model UC2845 control chip U4. The flyback power supply's input terminal is connected to the output terminal of the battery. The flyback power supply's output terminal outputs analog power supply voltage AVCC, digital circuit power supply voltage VCC, positive digital power supply voltage DVCC, and positive and negative power supply voltages VDD and VEE, respectively. The synchronous Buck rectifier circuit is based on model IR2110S driver chip U8. The power output terminal of the solar panel is connected to the input terminal of the synchronous Buck rectifier circuit, and the output terminal of the synchronous Buck rectifier circuit is connected to the two power terminals of the battery. Pins 12 and 14 of the driver chip U8 in the synchronous Buck rectifier circuit are respectively connected to the input terminal of the battery. The processor U10 has pins 28 and 37 connected together. The load output control circuit includes an N-channel MOSFET Q7, an optocoupler U5, and an NPN transistor Q8. The positive terminal of the battery is connected to the drain of the N-channel MOSFET Q7 through the load output interface CN3. The source of the N-channel MOSFET Q7 is connected to the negative terminal of the battery. The gate of the N-channel MOSFET Q7 is connected to the emitter of the optocoupler U5. The collector of the optocoupler U5 is connected to the analog power supply voltage AVCC through a resistor R18. The anode of the optocoupler U5 is connected to the digital circuit power supply voltage VCC through a resistor R19. The cathode of the optocoupler U5 is connected to the collector of the NPN transistor Q8. The emitter of the NPN transistor Q8 is connected to the negative terminal PV- of the solar panel. The base of the NPN transistor Q8 is connected to pin 37 of the processor U10.

2. A solar charger with integrated load output control according to claim 1, characterized in that... The transformer T in the flyback power supply has four output windings. The output terminal of the first winding T1 is connected to the first rectifier filter circuit (1), and the negative terminal of the first rectifier filter circuit (1) is connected to the negative terminal PV- of the solar panel. The first rectifier filter circuit (1) outputs the digital circuit power supply voltage VCC. The output terminal of the second winding T2 is connected to the second rectifier filter circuit (2), and the two ends of the second rectifier filter circuit (2) are connected to a series voltage divider branch composed of the first voltage divider resistor R10 and the second voltage divider resistor R16. The connection point of the first voltage divider resistor R10 and the second voltage divider resistor R16 is connected to the negative terminal P of the solar panel. V-, the positive power supply voltage VDD is output across the first voltage divider resistor R10, and the negative power supply voltage VEE is output across the second voltage divider resistor R16; the output terminal of the third winding T3 is connected to the third rectifier filter circuit (3), the negative terminal of the third rectifier filter circuit (3) is grounded, and the positive digital power supply voltage DVCC is output across the third rectifier filter circuit (3); the output terminal of the fourth winding T4 is connected to the fourth rectifier filter circuit (4), the negative terminal of the fourth rectifier filter circuit (4) is connected to the negative terminal PV- of the solar panel, and the analog power supply voltage AVCC is output across the fourth rectifier filter circuit (4).

3. A solar charger with integrated load output control according to claim 2, characterized in that... The charging current sampling circuit includes a current sampling resistor LR1 and a first voltage amplifier circuit U3 with chip model OP07CDR. The two ends of the current sampling resistor LR1 are connected to the input terminal of the first voltage amplifier circuit U3, and the output of the first voltage amplifier circuit U3 is connected to pin 7 of the processor U10. The charging current sampling circuit also includes a reverse current protection circuit for the battery, which includes a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a fourth PNP transistor Q6, and a fifth NMOS transistor Q5. One end of the current sampling resistor LR1 is connected to the negative terminal PV of the solar panel. The other end is connected to the drain of the fifth NMOS transistor Q5 and the cathode of diode D3. The anode of diode D3 is connected to the emitter of the first NPN transistor Q1. The positive terminal of the analog power supply voltage AVCC is connected to the collector and base of the first NPN transistor Q1 and the base of the third NPN transistor Q3 through resistor R3. The collector of the third NPN transistor Q3 is connected to the positive terminal of the analog power supply voltage AVCC through resistor R9. The emitters of the second NPN transistor Q2 and the fourth PNP transistor Q6 are connected to form a push-pull circuit. The output is connected to the fifth NMOS transistor Q5 through resistor R17. The gate of MOSFET Q5, the collector of the second NPN transistor Q2, and the positive terminal of the analog power supply voltage AVCC are connected. The base of the second NPN transistor Q2, the base of the fourth PNP transistor Q6, and the collector of the third NPN transistor Q3 are connected. The emitter of the third NPN transistor Q3 is connected to the anode of diode D4. The cathode of diode D4, the collector of the fourth PNP transistor Q6, and the source of the fifth NMOS transistor Q5 are connected to the negative terminal BAT- of the battery.

4. A solar charger with integrated load output control according to claim 3, characterized in that... The system also includes a 485 data communication circuit, which comprises three optocouplers U11, U13, and U14, and a signal conversion chip SU1 of model SP485. Pin 1 of the signal conversion chip SU1 is connected to the cathode of optocoupler U11, pins 2 and 3 of the signal conversion chip SU1 are connected to the collector of optocoupler U13, pin 4 of the signal conversion chip SU1 is connected to the collector of optocoupler U14, the collector of optocoupler U11 is connected to pin 6 of processor U10, the cathode of optocoupler U13 is connected to pin 36 of processor U10, the cathode of optocoupler U14 is connected to pin 6 of processor U10, the anode of optocoupler U11 is connected to the positive terminal of the positive digital power supply voltage DVCC, and pin 5 of the signal conversion chip SU1, the cathodes of optocouplers U13 and U14 are connected to the ground terminal of the positive digital power supply voltage DVCC.

5. A solar charger with integrated load output control according to claim 4, characterized in that... Pins 1 and 48 of the processor U10 are connected to pins 6 and 5 of the AT24C64 data storage chip U9, respectively, and communicate with the processor U10 via an IIC interface. Pins 1, 2, 3, and 4 of the data storage chip U9 are connected to the negative terminal PV- of the solar panel. Pin 7 of the data storage chip U9 is connected to the negative terminal PV- of the solar panel via a pull-down resistor R46. Pins 6 and 5 of the data storage chip U9 are also connected to pins 6 and 5 of the PCF8563 clock chip U12. Pin 8 of the data storage chip U9 is connected to the 3.3V positive power supply voltage VDD via diode D11, and is also connected to the positive terminal of the supercapacitor WC1 via a current-limiting resistor R53. Pins 1 and 2 of the clock chip U12 are connected to an external crystal oscillator circuit to provide the operating frequency. Pins 45 and 46 of the processor U10 are connected to an external 16MHz crystal oscillator circuit to ensure normal operation.

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