Analog-to-digital converter with positive input operational amplifier structure

Abstract

The application discloses an analog-digital converter with a positive input type operational amplifier structure, which comprises N-stage integrators, a quantizer and a DAC unit; the integrators, the quantizer and the DAC unit are sequentially connected; the DAC unit is used for establishing signal connection between an output end of the quantizer and an input end of a corresponding stage integrator; the first stage integrator is designed as a positive input type operational amplifier structure, wherein an analog signal inputted into the analog-digital converter from outside is configured to flow through a positive input end of an operational amplifier in the first stage integrator; thus, the input signal is allowed to firstly enter a transistor in the first stage integrator, so that the input impedance of the analog-digital converter is improved.

Description

Technical Field

[0001] This invention belongs to the technical field of analog-to-digital converters (ADCs) and differential amplifiers, and particularly relates to an analog-to-digital converter with a positive input operational amplifier structure. Background Technology

[0002] Sigma-Delta analog-to-digital converters, also known as Sigma Delta analog-to-digital converters, are frequently used in high-precision audio signal processing. The basic structure of a Sigma-Delta ADC includes a loop filter, a quantizer, and a feedback DAC, which together form a feedback loop. Generally, in a Sigma-Delta ADC, the analog input is differentially compared with the feedback signal (error signal). The resulting difference signal is fed into the loop filter. The Sigma-Delta ADC then uses feedback to bring this difference closer to zero, reducing the nonlinearity of the feedback DAC. This structure allows the Sigma-Delta ADC to achieve extremely high precision, making it very popular in high-precision applications such as audio.

[0003] The low-pass filter built into a continuous-mode Sigma-Delta analog-to-digital converter (EMB) places lower performance requirements on the operational amplifier within the EDB, allowing for higher sampling rates and lower sensitivity to switched-capacitor circuitry. However, in existing technologies, the input of a continuous-mode Sigma-Delta EDB is designed with a resistor, resulting in a relatively low input impedance. This limits its application in fields requiring high input impedance, such as audio and sensor technology. Summary of the Invention

[0004] To overcome the low operating gain of the integrator in existing Sigma-Delta analog-to-digital converters (ADCs), this invention improves the connection method of the operational amplifier structure to introduce higher input impedance within the ADC. This invention discloses an ADC with a positive-input operational amplifier structure. The specific technical solution is as follows:

[0005] An analog-to-digital converter (ADC) with a positive-input operational amplifier structure is disclosed. The ADC includes an N-stage integrator, a quantizer, and a DAC unit. The integrator, quantizer, and DAC unit are connected in sequence. The DAC unit is used to establish a signal connection between the output of the quantizer and the input of the corresponding stage integrator. The first-stage integrator is designed as a positive-input operational amplifier structure, wherein the analog signal externally input to the ADC is configured to flow through the positive input of the operational amplifier in the first-stage integrator.

[0006] Furthermore, the first-stage integrator is the positive-input operational amplifier structure, and at least one of the integrators from the second-stage to the Nth-stage integrator is an inverting-input operational amplifier structure.

[0007] Furthermore, the first-stage integrator is the positive-input operational amplifier structure, and at least one of the integrators from the second-stage to the Nth-stage integrator is the positive-input operational amplifier structure.

[0008] Furthermore, the first-stage integrator includes a first operational amplifier, a first resistor, and a first capacitor; the positive input terminal of the first operational amplifier is used to receive the input signal to be integrated, wherein the input signal to be integrated is an analog signal from the externally input analog-to-digital converter; the negative input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier through the first capacitor, and the negative input terminal of the first operational amplifier is grounded through the first resistor, thus the first operational amplifier, the first resistor, and the first capacitor constitute the positive input type operational amplifier structure.

[0009] Furthermore, the first-stage integrator also includes a first chopper and a second chopper; the positive-input operational amplifier structure formed by the first-stage integrator is specifically as follows: the first input terminal of the first chopper is connected to one end of the first resistor, and the other end of the first resistor is grounded; the first output terminal of the first chopper is connected to the negative input terminal of the first operational amplifier; the second input terminal of the first chopper is used to receive the analog signal from the external input analog-to-digital converter, so that the input terminal of the first chopper becomes the input terminal of the first-stage integrator; the second output terminal of the first chopper is connected to the positive input terminal of the first operational amplifier; the output terminal of the first operational amplifier is connected to one end of the first capacitor through the second chopper, and the other end of the first capacitor is connected to the first input terminal of the first chopper; the DAC unit is connected to the first input terminal of the first chopper and the output terminal of the quantizer; wherein, the output terminal of the second chopper is configured as the output terminal of the first-stage integrator.

[0010] Furthermore, the negative output terminal of the first operational amplifier is connected to the first input terminal of the second chopper, and the positive output terminal of the first operational amplifier is connected to the second input terminal of the second chopper; the positive output terminal or the negative output terminal of the second chopper is connected to the first input terminal of the first chopper through the first capacitor.

[0011] Furthermore, the inverting input operational amplifier structure formed by the first-stage integrator is specifically as follows: the integrator includes a pre-configured operational amplifier, a resistor, and a capacitor; the negative input terminal of the pre-configured operational amplifier receives the input signal to be integrated through a resistor, and the input signal to be integrated is the analog signal summed from the previous stage; the negative input terminal of the pre-configured operational amplifier is connected to the output terminal of the pre-configured operational amplifier through a capacitor, and the positive input terminal of the pre-configured operational amplifier is grounded through a resistor.

[0012] Furthermore, each integrator stage includes a pre-configured operational amplifier, the input of which is configured to be connected to the output of the corresponding first-stage summing node. When the first-stage integrator forms the positive input operational amplifier structure, the first-stage summing node corresponding to the positive input of the pre-configured operational amplifier does not receive external analog signals through a branch resistor. When the first-stage integrator forms the inverting input operational amplifier structure, the first-stage summing node corresponding to the negative input of the pre-configured operational amplifier receives external analog signals through a branch resistor.

[0013] Furthermore, the integrators exist in the analog-to-digital converter in a cascaded manner, with each integrator's input terminal corresponding to a summing node, and each integrator corresponding to a summing node. The DAC unit includes a first DAC unit and a second DAC unit. The first DAC unit is connected between the input terminal of the summing node corresponding to the first-stage integrator and the output terminal of the quantizer. The first DAC unit is used to convert the quantized output signal output by the quantizer into a first feedback signal, and then transmit the first feedback signal to the input terminal of the summing node corresponding to the first-stage integrator. The second DAC unit is connected between the summing node corresponding to the last-stage integrator and the output terminal of the quantizer. The second DAC unit is used to compensate the N-stage integrator.

[0014] Furthermore, the first-stage summing node corresponding to the first-stage integrator is provided with a first input terminal and a second input terminal; the first input terminal of the first-stage summing node is used to receive the analog signal from the external input analog-to-digital converter and transmit it to the positive input terminal of the first operational amplifier through a chopper; the second input terminal of the first-stage summing node is used to receive the first feedback signal output by the first DAC unit and transmit it to the negative input terminal of the first operational amplifier through a chopper.

[0015] Furthermore, in the analog-to-digital converter, the second-stage integrator to the Nth-stage integrator are sequentially configured with second-stage summing nodes to the Nth-stage summing nodes; wherein, the Nth-stage integrator is the last stage integrator; each stage summing node has a first input terminal, a second input terminal, and an output terminal; the first input terminal of the i-th stage summing node is connected to the output terminal of the (i-1)th stage integrator, and the first input terminal of the i-th stage summing node is used to receive the (i-1)th stage integrated analog signal output by the (i-1)th stage integrator; the second input terminal of the i-th stage summing node is connected to the output terminal of the Nth stage integrator, and the second input terminal of the i-th stage summing node is used to receive the integrated analog signal output by the Nth stage integrator, wherein, the integrated analog signal output by the Nth stage integrator is a pre-feedback analog signal; The output of the i-th stage summing node is connected to the input of the i-th stage integrator. The output of the i-th stage summing node is used to output the i-th stage summing analog signal to the input of the i-th stage integrator. The i-th stage integrator is used to integrate the i-th stage summing analog signal and output the i-th stage integrated analog signal. The i-th stage summing analog signal is the sum of the (i-1)-th stage integrated analog signal and the pre-feedback analog signal. The (i-1)-th stage integrator is used to integrate the output signal of the (i-1)-th stage summing node to obtain the (i-1)-th stage integrated analog signal. N is a positive integer; i is an integer greater than 1 and less than or equal to N-1. Each stage integrator is a continuous-time structure used to integrate the input signal through a continuous-time structure.

[0016] Furthermore, in addition to the first and second input terminals, the Nth-level summing node also has N-1 preset input terminals; in the first to N-1th level summing nodes, the signal input to the first input terminal of each level summing node is also configured to be input to the corresponding preset input terminal in the Nth-level summing node; the first input terminal of the Nth-level summing node is connected to the output terminal of the N-1th-level integrator, and the first input terminal of the Nth-level summing node is used to receive the N-1th-level integrated analog signal output by the N-1th-level integrator; the second input terminal of the i-th-level summing node... The input terminal is used to receive the feedback signal for compensating the N-stage cascaded integrator; the output terminal of the Nth stage summing node is used to output the Nth stage summing analog signal to the Nth stage integrator; wherein, the Nth stage summing node is used to sum the N-1 stage integral analog signal, the feedback signal for compensating the N-stage cascaded integrator, and the signal input by each preset input terminal, and the sum value is configured as the Nth stage summing analog signal; wherein, the Nth stage integrator is used to receive the integration of the Nth stage summing analog signal to obtain the Nth stage integral analog signal.

[0017] Furthermore, the operational amplifier within the first-stage integrator is connected to a first gain amplifier to meet the gain requirements of the analog signal input to the external analog-to-digital converter; the last-stage integrator is connected to the quantizer via a second gain amplifier, so that the N-stage integrator, the second gain amplifier, the quantizer, and the DAC unit are connected to form a feedback loop; wherein, the DAC unit is a digital-to-analog converter with interpolation filtering function.

[0018] Furthermore, the first operational amplifier is a four-input operational amplifier, wherein the positive input terminal of the first operational amplifier includes a first positive input terminal and a second positive input terminal, and the negative input terminal of the first operational amplifier includes a first negative input terminal and a second negative input terminal; the first positive input terminal of the first operational amplifier is connected to the first output terminal of the first chopper, and the second negative input terminal of the first operational amplifier is connected to the second output terminal of the first chopper; both the first negative input terminal and the second positive input terminal of the first operational amplifier are connected to a common-mode reference voltage.

[0019] Further, the first operational amplifier includes a current mirror circuit, a first-stage amplifier circuit, a second-stage amplifier circuit, a first common-mode feedback circuit, and a second common-mode feedback circuit; wherein, the current mirror circuit, the first-stage amplifier circuit, and the second-stage amplifier circuit all support differential input and differential output; the differential output terminal of the first-stage amplifier circuit is correspondingly connected to the differential input terminal of the second-stage amplifier circuit; the differential output terminal of the first-stage amplifier circuit is also connected to the feedback terminal of the current mirror circuit through the first common-mode feedback circuit; the differential output terminal of the second-stage amplifier circuit is connected to the feedback terminal of the second-stage amplifier circuit through the second common-mode feedback circuit; the differential output terminal of the second-stage amplifier circuit is the output terminal of the first operational amplifier; the first positive input terminal, the first negative input terminal, the second positive input terminal, and the second negative input terminal of the first operational amplifier are all input terminals of the current mirror circuit; the output terminal of the current mirror circuit is connected to the power supply terminal of the first-stage amplifier circuit; wherein, the power supply connected to the power supply terminal of the second-stage amplifier circuit is the same as the power supply connected to the power supply terminal of the current mirror circuit.

[0020] Further, the current mirror circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor; the gate of the third PMOS transistor is the first positive input terminal of the first operational amplifier, the gate of the fifth PMOS transistor is the second positive input terminal of the first operational amplifier, the gate of the fourth PMOS transistor is the first negative input terminal of the first operational amplifier, and the gate of the sixth PMOS transistor is the second negative input terminal of the first operational amplifier; the drain of the third PMOS transistor is connected to the drain of the fifth PMOS transistor, and the connection node between the drains of the third and fifth PMOS transistors is the first output terminal of the current mirror circuit; the drain of the fourth PMOS transistor is connected to the drain of the sixth PMOS transistor, and the connection node between the drains of the fourth and sixth PMOS transistors is the second output terminal of the current mirror circuit; wherein, the current mirror circuit... The output terminals of the circuit include a first output terminal and a second output terminal of the current mirror circuit; the sources of the third and fourth PMOS transistors are both connected to the drain of the first PMOS transistor, and the sources of the fifth and sixth PMOS transistors are both connected to the drain of the second PMOS transistor; the gate of the first PMOS transistor is the first feedback terminal of the current mirror circuit, and the gate of the second PMOS transistor is the second feedback terminal of the current mirror circuit; both the gates of the first and second PMOS transistors are connected to the output terminal of the first common-mode feedback circuit; the feedback terminals of the current mirror circuit include a first feedback terminal and a second feedback terminal; the source of the first PMOS transistor is the first power supply terminal of the current mirror circuit, and the source of the second PMOS transistor is the second power supply terminal of the current mirror circuit; the power supply terminals of the current mirror circuit include a first power supply terminal and a second power supply terminal.

[0021] Further, the first-stage amplifier circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the source of the seventh PMOS transistor is the first power supply terminal of the first-stage amplifier circuit, and the first power supply terminal of the first-stage amplifier circuit is connected to the first output terminal of the current mirror circuit; the source of the eighth PMOS transistor is the second power supply terminal of the first-stage amplifier circuit, and the second power supply terminal of the first-stage amplifier circuit is connected to the second output terminal of the current mirror circuit; the gate of the seventh PMOS transistor is connected to a first bias voltage provided externally; the gate of the eighth PMOS transistor is connected to a first bias voltage provided externally; wherein, the power supply terminal of the first-stage amplifier circuit includes the first power supply terminal and the second power supply terminal of the first-stage amplifier circuit; the output terminal of the current mirror circuit includes the first output terminal and the second output terminal of the current mirror circuit; the drain of the seventh PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor is connected to a second bias voltage provided externally, the source of the first NMOS transistor is connected to the drain of the third NMOS transistor, and the gate of the third NMOS transistor is connected to a third bias voltage provided externally; the... The sources of the three NMOS transistors are grounded; the drain of the eighth PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to a second bias voltage provided externally, the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to a third bias voltage provided externally, and the source of the fourth NMOS transistor is grounded; the connection point between the drain of the seventh PMOS transistor and the drain of the first NMOS transistor is the positive output terminal of the first-stage amplifier circuit, and the connection point between the drain of the eighth PMOS transistor and the drain of the second NMOS transistor is the negative output terminal of the first-stage amplifier circuit. The output terminal; wherein, the differential output terminal of the first stage amplifier circuit includes the positive output terminal and the negative output terminal of the first stage amplifier circuit; the positive output terminal and the negative output terminal of the first stage amplifier circuit are respectively connected to the differential input terminal of the first common-mode feedback circuit, and the first feedback terminal and the second feedback terminal of the current mirror circuit are both connected to the output terminal of the first common-mode feedback circuit to adjust the differential output result of the first stage amplifier circuit; wherein, the feedback terminal of the current mirror circuit includes the first feedback terminal and the second feedback terminal of the current mirror circuit.

[0022] Further, the second-stage amplifier circuit includes a ninth PMOS transistor, a tenth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the source of the ninth PMOS transistor is connected to the first power supply terminal of the current mirror circuit, the drain of the ninth PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the ninth PMOS transistor is the positive input terminal of the second-stage amplifier circuit, the gate of the ninth PMOS transistor is connected to the positive output terminal of the first-stage amplifier circuit, and the source of the fifth NMOS transistor is grounded; the connection point between the drains of the ninth and fifth NMOS transistors is the positive output terminal of the second-stage amplifier circuit; the source of the tenth PMOS transistor is connected to the second power supply terminal of the current mirror circuit, the drain of the tenth PMOS transistor is connected to the drain of the sixth NMOS transistor, the gate of the tenth PMOS transistor is the negative input terminal of the second-stage amplifier circuit, the gate of the tenth PMOS transistor is connected to the negative output terminal of the first-stage amplifier circuit, and the source of the sixth NMOS transistor is grounded; the connection point between the drains of the tenth and sixth NMOS transistors is the negative output terminal of the second-stage amplifier circuit; the second-stage amplifier... The positive output terminal of the circuit and the negative output terminal of the second-stage amplifier circuit are respectively connected to the differential input terminal of the second common-mode feedback circuit; the gate of the fifth NMOS transistor is the first feedback terminal of the second-stage amplifier circuit, and the gate of the fourth NMOS transistor is the second feedback terminal of the second-stage amplifier circuit. Both the first and second feedback terminals of the second-stage amplifier circuit are connected to the output terminal of the second common-mode feedback circuit to adjust the differential output result of the second-stage amplifier circuit; wherein, the differential input terminal of the second-stage amplifier circuit includes the positive and negative input terminals of the second-stage amplifier circuit; the differential output terminal of the second-stage amplifier circuit includes the positive and negative output terminals of the second-stage amplifier circuit; the differential output terminal of the first-stage amplifier circuit includes the positive and negative output terminals of the first-stage amplifier circuit; the power supply terminal of the current mirror circuit includes the first and second power supply terminals of the current mirror circuit; the feedback terminal of the second-stage amplifier circuit includes the first and second feedback terminals of the second-stage amplifier circuit.

[0023] Furthermore, the first bias voltage, the second bias voltage, and the third bias voltage are not equal to each other, so as to form a voltage difference between different pairs of MOSFETs; wherein, the voltage difference between any two of the first bias voltage, the second bias voltage, and the third bias voltage remains constant; the first bias voltage, the second bias voltage, and the third bias voltage are all provided by corresponding bias voltage sources.

[0024] Furthermore, the first common-mode feedback circuit and the second common-mode feedback circuit are of the same type, and both are connected to the same common-mode reference voltage. The first common-mode feedback circuit compares the differential signal output from the first-stage amplifier circuit with the common-mode reference voltage, generating a feedback control signal for the feedback terminal of the current mirror circuit, thereby stabilizing the differential signal output from the first-stage amplifier circuit at the common-mode reference voltage. The second common-mode feedback circuit compares the differential signal output from the second-stage amplifier circuit with the common-mode reference voltage, generating a feedback control signal for the feedback terminal of the second-stage amplifier circuit, thereby stabilizing the differential signal output from the second-stage amplifier circuit at the common-mode reference voltage.

[0025] Compared with existing technologies, this invention improves the first-stage integrator in the Sigma-Delta analog-to-digital converter from an inverting input operational amplifier structure to a non-inverting input operational amplifier structure. This allows the input signal to enter the transistor in the first-stage integrator first, increasing the input impedance of the analog-to-digital converter and also increasing the input impedance of the first-stage integrator (or the first-stage operational amplifier). This increases the gain of the input stage of the analog-to-digital converter or the first-stage operational amplifier, which helps to reduce the noise contribution of the integrator or amplifier output and better meets the application requirements of high precision.

[0026] This invention also designs the operational amplifier in the first-stage integrator as an operational amplifier with four input terminals, supporting two pairs of differential inputs and one pair of differential outputs. It has both a current mirror load structure and is connected to a common-mode feedback circuit, which can form a working loop of the first-stage amplifier circuit, the second-stage amplifier circuit, and their common-mode feedback circuit. While ensuring that the circuit complexity is not high, the input impedance of the operational amplifier is increased, thereby improving the driving capability of the first-stage integrator and ensuring the transmission quality of the signal to be integrated. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of an analog-to-digital converter with a positive input operational amplifier structure disclosed in an embodiment of the present invention. The analog-to-digital converter is an N-order continuous Sigma-Delta analog-to-digital converter, where N is greater than or equal to 2.

[0028] Figure 2 This is a schematic diagram of a positive input operational amplifier structure disclosed in an embodiment of the present invention.

[0029] Figure 3 This is a schematic diagram of an analog-to-digital converter with a positive input operational amplifier structure disclosed in an embodiment of the present invention.

[0030] Figure 4 This is a schematic diagram of the structure of a four-input differential operational amplifier disclosed in an embodiment of the present invention.

[0031] Figure 5 Is with Figure 4 The schematic diagram shows the structure of a common-mode feedback circuit connected to a two-stage amplifier circuit, where CMFB1 is connected to... Figure 4 The first common-mode feedback circuit, CMFB2, is connected to the first-stage amplifier circuit and the current mirror circuit. Figure 4 The second common-mode feedback circuit is connected to the second-stage amplifier circuit. Detailed Implementation

[0032] The technical solutions of the present invention will now be described in detail with reference to the accompanying drawings.

[0033] It is understandable that the equivalent impedance at the input terminal of an analog-to-digital converter (ADC) is the input impedance of the ADC. Specifically, if a voltage source is applied to the input terminal of the ADC and the measured current flowing through that input terminal is I, then the input impedance is equal to the ratio of U to I. Generally, an ADC contains multiple cascaded operational amplifiers. The magnitude of the input resistance (differential input impedance) within the first-stage operational amplifier (which can be considered the input stage of the ADC) has a significant, even decisive, impact on the magnitude of the ADC's input impedance, and also determines the ADC's signal gain and output noise level.

[0034] As one embodiment, the present invention discloses an analog-to-digital converter with a positive input operational amplifier structure, such as... Figure 1 As shown, the analog-to-digital converter includes an N-stage integrator, a quantizer, and a DAC unit; Figure 1As seen from left to right, the N-stage integrator and quantizer are connected in series. Preferably, the input of the first-stage integrator is connected to an amplifier for configuring gain parameters, and the output of the Nth-stage integrator is also connected to another amplifier for configuring gain parameters to meet the accuracy requirements of the analog-to-digital converter. In this analog-to-digital converter, all cascaded integrators, quantizers, and DAC units are connected in series to form a feedback loop. The DAC unit is used to establish a signal connection between the output of the quantizer and the input of the corresponding stage integrator, providing feedback processing for aliasing phenomena within the N-stage cascaded integrators. This allows the N-stage cascaded integrators to filter effective analog signals and quantize and encode them for output even in the presence of aliasing, thus constructing a continuous Sigma-Delta analog-to-digital converter. In the analog-to-digital converter (ADC), the first-stage integrator is designed as a positive-input operational amplifier (OPA) structure. The analog signal input to the ADC is configured to flow through the positive input terminal of the OPA in the first-stage integrator. In this embodiment, the positive input terminal of the OPA constituting the first-stage integrator can directly receive the analog signal or amplified analog signal. Since the field-effect transistors (FETs) or transistors constituting the OPA have high input impedance, using FETs or transistors to form the differential input stage of the OPA can increase the input impedance of the ADC. Specifically, this is achieved by not connecting an external resistor to the positive input terminal of the first-stage integrator but receiving the analog input signal input to the ADC. Therefore, this embodiment increases the input impedance of the first-stage integrator (or the first-stage operational amplifier), thereby increasing the gain of the input stage or the first-stage integrator of the ADC.

[0035] In some embodiments, the first-stage integrator is the positive-input operational amplifier structure, which is understood to be located in the pre-stage of the analog-to-digital converter. At least one integrator from the second to the Nth stage is an inverting operational amplifier structure. The operational amplifier constituting the first-stage integrator has the most significant driving effect in the analog-to-digital converter. Since the integrators in existing continuous-mode Sigma-Delta analog-to-digital converters all employ inverting operational amplifier structures, meaning all operational amplifiers use negative input terminals to receive externally supplied analog input signals, the analog-to-digital converter disclosed in this embodiment differs from existing continuous-mode Sigma-Delta analog-to-digital converters, where at least one integrator is modified from an inverting operational amplifier structure to a positive-input operational amplifier structure. However, in this embodiment, the first-stage integrator must be designed as the positive-input operational amplifier structure to ensure higher input impedance.

[0036] In other embodiments, the first-stage integrator is the positive-input operational amplifier structure, which is understood to be located in the pre-stage of the analog-to-digital converter. At least one integrator from the second to the Nth stage is the positive-input operational amplifier structure. The operational amplifier constituting the first-stage integrator has the most significant driving effect in the analog-to-digital converter. Since the integrators in existing continuous-mode Sigma-Delta analog-to-digital converters all use inverting operational amplifier structures, meaning all operational amplifiers use negative input terminals to receive externally supplied analog input signals, the analog-to-digital converter disclosed in this embodiment differs from existing continuous-mode Sigma-Delta analog-to-digital converters, where at least two integrators are modified from inverting operational amplifier structures to positive-input operational amplifier structures. However, in this embodiment, the first-stage integrator must be designed as the positive-input operational amplifier structure to ensure higher input impedance.

[0037] As one embodiment, the inverting input operational amplifier structure formed by the first-stage integrator is specifically as follows: This integrator includes a pre-configured operational amplifier, resistors, and capacitors; the negative input terminal of the pre-configured operational amplifier receives the input signal to be integrated through a resistor, and the input signal to be integrated is the analog signal summed from the previous stage; the negative input terminal of the pre-configured operational amplifier is connected to the output terminal of the pre-configured operational amplifier through a first capacitor, and the positive input terminal of the pre-configured operational amplifier is grounded through a resistor. Correspondingly, the voltage gain parameter generated by this integrator is equal to the reciprocal of the product of the resistance value and the capacitance value, that is, equal to the reciprocal of the product of the integrating capacitor and the integrating resistor. Corresponding to... Figure 3 The Nth stage integrator is the inverting input operational amplifier structure. The pre-configured operational amplifier is the Nth stage operational amplifier. The negative input terminal of the Nth stage operational amplifier is connected to the output terminal of the Nth stage operational amplifier through the first capacitor Cn. The positive input terminal of the pre-configured operational amplifier is grounded through the resistor Rn. The negative input terminal of the Nth stage operational amplifier is connected to one end of the resistor Rn, and the other end of the resistor Rn is connected to the output terminal of the circuit module of the N-2 stage integrator cascade. The circuit module of the N-2 stage integrator cascade is formed by connecting the second stage integrator to the N-1 stage integrator in sequence. The output terminal of the circuit module outputs the integration result of the N-1 stage integrator. The integration result of the N-1 stage integrator first passes through the resistor and then enters the negative input terminal of the Nth stage operational amplifier.

[0038] As one embodiment, the first-stage integrator includes a first operational amplifier, a first resistor, and a first capacitor; corresponding to Figure 2The positive input terminal of the first operational amplifier (+) is used to receive the input signal to be integrated, which is an analog signal from the externally input analog-to-digital converter (ADC). The negative input terminal of the first operational amplifier (-) is connected to the output terminal of the first operational amplifier through the first capacitor C1, and the negative input terminal of the first operational amplifier (-) is grounded through the first resistor R1. Optionally, the output terminal of the first-stage integrator is connected to the input terminal of the second-stage integrator. In this embodiment, the first operational amplifier, the first resistor R1, and the first capacitor C1 constitute the positive input operational amplifier structure. The voltage gain generated by the first-stage integrator forming the positive input operational amplifier structure is equal to the sum of the reciprocal of the product of the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 and the value 1, which is equal to the sum of the reciprocal of the product of the integrating capacitor and the integrating resistor and the value 1. This is greater than the voltage gain parameter generated by the integrator forming the inverting input operational amplifier structure. Therefore, the input impedance generated by the first-stage integrator designed as the positive input operational amplifier structure is greater than the input impedance generated by the first-stage integrator designed as the inverting input operational amplifier structure. Therefore, it is evident that the input resistance of the first-stage integrator or its internal operational amplifier (first-stage amplifier) ​​plays a major determining role. The higher the input impedance in the first-stage integrator, the higher the input impedance that the analog-to-digital converter (ADC) can achieve, resulting in higher gain. Then, by setting appropriate resistor and capacitor ratios, the sensor associated with the ADC can meet the application requirements of higher gain and higher precision. Compared to existing technologies, this embodiment improves the first-stage integrator in the Sigma-Delta ADC from an inverting input op-amp structure to a non-inverting input op-amp structure. This allows the input signal to first enter the transistor in the first-stage integrator, increasing the input impedance of the ADC and also increasing the input impedance of the first-stage integrator (or first-stage operational amplifier). This increases the gain of the input stage of the ADC or the first-stage operational amplifier, which helps reduce the noise contribution of the integrator or amplifier output and better meets the requirements of high-precision applications.

[0039] As one embodiment, the first-stage integrator further includes a first chopper and a second chopper; such as Figure 3As shown, the positive input operational amplifier structure formed by the first-stage integrator is specifically as follows: the first input terminal of the first chopper is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded; the first output terminal of the first chopper is connected to the negative input terminal- of the first operational amplifier, wherein the negative input terminal- of the first operational amplifier receives the differential input signal VIN2; the second input terminal of the first chopper is used to receive the analog signal X input from the external analog-to-digital converter, making the input terminal of the first chopper the input terminal of the first-stage integrator, and thus, in some embodiments, the input terminal of the analog-to-digital converter; the second output terminal of the first chopper is connected to the positive input terminal+ of the first operational amplifier, wherein the positive input terminal+ of the first operational amplifier receives another differential input signal VIP1. The output terminal of the first operational amplifier is connected to one end of the first capacitor C1 through the second chopper, and the other end of the first capacitor C1 is connected to the first input terminal of the first chopper. The DAC unit is connected to the first input terminal of the first chopper and the output terminal of the quantizer, corresponding to... Figure 3 The first DAC unit is connected between the first input terminal of the first chopper and the output terminal of the quantizer; wherein the output terminal of the second chopper is configured as the output terminal of the first-stage integrator.

[0040] Preferably, such as Figure 3 As shown, the positive output terminal of the first operational amplifier is connected to the first input terminal of the second chopper. The negative output terminal of the first operational amplifier outputs a differential output signal VON2 to the first input terminal of the second chopper. The positive output terminal of the first operational amplifier is connected to the second input terminal of the second chopper. The positive output terminal of the first operational amplifier outputs a differential output signal VOP2 to the second input terminal of the second chopper. Both the first and second choppers are differential structures, with their first input terminal being a negative input terminal, their second input terminal being a positive input terminal, their first output terminal being a negative output terminal, and their second output terminal being a positive output terminal. The second chopper can support differential input and single-ended output; therefore, either the positive or negative output terminal of the second chopper is connected to the first input terminal of the first chopper through the first capacitor C1. The first operational amplifier is a differential operational amplifier, and the first chopper supports differential input and differential output.

[0041] In summary, applying chopping technology in the first-stage integrator effectively suppresses noise from the operational amplifier itself. Generally, after the chopper is connected to the first-stage operational amplifier, it performs chopping at a specific chopping frequency. In some embodiments, since all poles of the transfer function of the first DAC unit are located at the aliasing points introduced by the chopper, signals on even-order harmonics of the chopping frequency are canceled and / or signals on odd-order harmonics of the chopping frequency are canceled. This reduces flicker noise in the low-frequency region and suppresses aliasing introduced by the chopper.

[0042] As one embodiment, the analog-to-digital converter is a Sigma-Delta analog-to-digital converter, particularly a continuous Sigma-Delta analog-to-digital converter. Each integrator stage includes a pre-configured operational amplifier, the input of which is configured to connect to the output of the corresponding first-stage summing node. When the first-stage integrator forms the positive input operational amplifier structure, the first-stage summing node corresponding to the positive input of the pre-configured operational amplifier does not receive external analog signals through branch resistors. When the first-stage integrator forms the inverting input operational amplifier structure, the first-stage summing node corresponding to the negative input of the pre-configured operational amplifier receives external analog signals through branch resistors, specifically feedback signals transmitted back by capacitors and DAC units.

[0043] Specifically, in combination Figure 1 and Figure 3 It can be seen that the first-level summation node corresponding to the first-level integrator ( Figure 1 The first circled "+" on the left has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first-stage summing node is used to receive the analog input signal, i.e., the analog signal from the external analog-to-digital converter. The second input terminal of the first-stage summing node is used to receive the first feedback signal output by the first DAC unit. The output terminal of the first-stage summing node is used to output the first-stage summing analog signal to the first chopper. Specifically, the first-stage summing node sums the analog signal and the first feedback signal provided by the first DAC unit, and configures this sum as the first-stage summing analog signal. The first-stage integrator also includes a branch resistor, the input terminal of which is configured as the second input terminal of the first-stage summing node. The first feedback signal output by the first DAC unit passes through the branch resistor (corresponding to...). Figure 3 The resistor R1 is transmitted to the first chopper, and then to the negative input terminal of the first operational amplifier. The output terminal of the branch resistor is configured as the output terminal of the first-stage summing node. However, the first input terminal of the first-stage summing node directly receives the analog signal from the external input analog-to-digital converter and transmits it to the positive input terminal of the first operational amplifier through the chopper. It does not need to receive the analog signal through the branch resistor, allowing the analog signal to flow directly into the gate of the MOS transistor or the base of the transistor that makes up the first operational amplifier.

[0044] In the above embodiments, the integrators exist in the analog-to-digital converter in a cascaded manner, with each integrator's input terminal corresponding to a summing node, and each integrator corresponding to a summing node; for example Figure 3As shown, the DAC unit includes a first DAC unit and a second DAC unit. Both the first and second DAC units belong to the DAC circuit and can serve as signal feedback. However, when the DAC circuit is a unit DAC, the quantizer is a unit quantizer. The first DAC unit is connected between the input terminal of the summing node corresponding to the first-stage integrator and the output terminal of the quantizer. The first DAC unit is used to convert the quantized output signal of the quantizer into a first feedback signal, and then transmit the first feedback signal to the input terminal of the summing node corresponding to the first-stage integrator, specifically the second input terminal of the first-stage summing node. The second DAC unit is connected between the summing node corresponding to the last-stage integrator (specifically the second input terminal of the Nth-stage summing node) and the output terminal of the quantizer. The second DAC unit is used to compensate the Nth-stage integrator, so that the noise transfer function of the Nth-stage integrator is automatically restored.

[0045] As one example, combined with Figure 1 As can be seen, in the analog-to-digital converter, the second-stage integrator to the Nth-stage integrator are sequentially configured with second-stage summing nodes to the Nth-stage summing nodes; wherein, the Nth-stage integrator is the last stage integrator; each stage summing node has a first input terminal, a second input terminal, and an output terminal; the first input terminal of the i-th stage summing node is connected to the output terminal of the (i-1)th stage integrator, and the first input terminal of the i-th stage summing node is used to receive the (i-1)th stage integrated analog signal output by the (i-1)th stage integrator; the second input terminal of the i-th stage summing node is connected to the output terminal of the Nth stage integrator, and the second input terminal of the i-th stage summing node is used to receive the integrated analog signal output by the Nth stage integrator, wherein, the integrated analog signal output by the Nth stage integrator is a pre-feedback analog signal, which is processed by the Nth stage integrator through chopping and integrating the analog signal input to the analog-to-digital converter, and receiving the feedback signal output by the DAC unit, thus playing a signal repair role. The output of the i-th stage summing node is connected to the input of the i-th stage integrator. The output of the i-th stage summing node is used to output the i-th stage summing analog signal to the input of the i-th stage integrator. This makes the pre-feedback analog signal the analog feedback signal of each stage integrator except the first stage integrator and the last stage integrator. This helps to overcome the imbalance problem inside the integrator and ensure the linearity of the signal.

[0046] It should be noted that the i-th stage integrator is used to integrate the i-th stage summed analog signal and output the i-th stage integrated analog signal; the i-th stage summed analog signal is the sum of the (i-1)-th stage integrated analog signal and the pre-feedback analog signal; the (i-1)-th stage integrator is used to integrate the output signal of the (i-1)-th stage summing node to obtain the (i-1)-th stage integrated analog signal; N is a positive integer; i is an integer greater than 1, and if i is less than or equal to N-1, then N is an integer greater than 2; correspondingly, when i equals 2, the (i-1)-th stage integrator is Figure 2 The first-stage integrator shown is the i-th-stage integrator. Figure 2 The second-stage integrator is shown. Each integrator stage is a continuous-time structure used to integrate the input signal through a continuous-time structure.

[0047] It should be noted that the integrators exist in the analog-to-digital converter in a cascaded manner. The input of each integrator stage is connected to a corresponding summing node, so that one integrator stage corresponds to one summing node. Therefore, the input of each integrator stage is connected to a summing node, and each summing node corresponds to one integrator stage, thus forming a first-level summing node corresponding to one integrator stage. Each level of summing node corresponds to... Figure 1 The circled "+" indicates that the input of the first-stage integrator is connected to the first-stage summing node, the input of the second-stage integrator is connected to the second-stage summing node, the input of the third-stage integrator is connected to the third-stage summing node, and so on, with the input of the (N-1)th-stage integrator connected to the (N-1)th-stage summing node, and the input of the Nth-stage integrator connected to the Nth-stage summing node.

[0048] As one embodiment, the analog-to-digital converter (ADC) is a differential circuit, supporting differential input and differential output. Specifically, in the second to Nth stage integrators, when each stage integrator is the inverting input operational amplifier structure, the integrator includes branch resistors and pre-configured operational amplifiers. The output terminal of the branch resistor is connected to the input terminal of the pre-configured operational amplifier. The input terminal of the branch resistor is configured as the input terminal of the corresponding first-stage summing node, and the output terminal of the branch resistor is configured as the output terminal of the corresponding first-stage summing node. The input terminal of the pre-configured operational amplifier is the input terminal of its respective integrator. The first input terminal of each stage summing node is the input terminal of a branch resistor inside the corresponding first-stage integrator, and the second input terminal of each stage summing node is the input terminal of another branch resistor inside the corresponding first-stage integrator. The cascade number of the corresponding first-stage integrator is equal to the cascade number of the summing node in the same ADC. In addition, each preset input terminal of the last stage summing node is the input terminal of the corresponding branch resistor inside the last stage integrator. Therefore, the more input terminals of the pre-configured operational amplifiers, the more input branches are provided for summation. This addresses the nonlinearity issues introduced by the mismatch of the internal current source, while minimizing the increase in the input impedance of the analog-to-digital converter.

[0049] Specifically, in the second to Nth stage integrators, the branch resistors can be divided into a first preset resistor and a second preset resistor. The input terminal of the first preset resistor in the second stage integrator is configured as the second input terminal of the second stage summation node. The output terminal of the first preset resistor in the second stage integrator is connected to the input terminal of a pre-configured operational amplifier in the second stage integrator. The input terminal of the second preset resistor in the second stage integrator is configured as the second input terminal of the second stage summation node. The output terminal of the second preset resistor in the second stage integrator is connected to the input terminal of a pre-configured operational amplifier in the second stage integrator. Both the output terminals of the first and second preset resistors in the second stage integrator are connected to the same input terminal of the pre-configured operational amplifier in the second stage integrator, including the operational... The positive or negative input terminal of the amplifier; similarly, the input terminal of the first preset resistor in the last stage integrator is configured as the first input terminal of the last stage summing node, the output terminal of the first preset resistor in the last stage integrator is connected to the input terminal of the pre-configured operational amplifier in the last stage integrator, the input terminal of the second preset resistor in the last stage integrator is configured as the second input terminal of the last stage summing node, and the output terminal of the second preset resistor in the last stage integrator is connected to the input terminal of the pre-configured operational amplifier in the last stage integrator, wherein the output terminals of the first and second preset resistors in the last stage integrator are both input terminals with the same electrode attribute as the pre-configured operational amplifier in the last stage integrator, including the positive or negative input terminal of the operational amplifier.

[0050] Based on the above embodiments, the Nth-level summing node, in addition to having a first input terminal and a second input terminal, also has N-1 preset input terminals; wherein, the Nth-level summing node is Figure 2The rightmost circled "+"; in the first to N-1th level summation nodes, the signal input to the first input terminal of each level summation node is also configured to be input to the corresponding preset input terminal in the Nth level summation node; the first input terminal of the Nth level summation node is connected to the output terminal of the N-1th level integrator, and the first input terminal of the Nth level summation node is used to receive the N-1th level integral analog signal output by the N-1th level integrator; the second input terminal of the i-th level summation node is used to receive the feedback signal used to compensate the N-level cascaded integrators; the output terminal of the Nth level summation node is used to output the Nth level summation analog signal to the Nth level integrator; wherein, the Nth level summation node is used to sum the N-1th level integral analog signal, the feedback signal used to compensate the N-level cascaded integrators, and the signal input to each preset input terminal, and the sum value is configured as the Nth level summation analog signal; wherein, the Nth level integrator is used to receive the integration of the Nth level summation analog signal to obtain the Nth level integral analog signal. In summary, for the integrator forming the aforementioned inverting input operational amplifier structure, for each stage of the summing node of each channel of the input analog differential signal, each input terminal of each stage of the summing node is connected to a branch resistor. The input terminal of the branch resistor is configured as an input terminal of the summing node, and the output terminal of the branch resistor is connected to the same input terminal of the pre-configured operational amplifier. The output terminal of the branch resistor is configured as the output terminal of the summing node.

[0051] Preferably, the operational amplifier within the first-stage integrator is connected to a first gain amplifier. This first gain amplifier can output a single-ended signal or a differential signal. The product of the resistance of the first resistor and the capacitance of the first capacitor is related to the gain parameter of the first gain amplifier to meet the amplification requirements of the first-stage integrator for the input analog signal. In some embodiments, the negative input terminal of the operational amplifier within the first-stage integrator is connected to a first gain amplifier to meet the gain requirements of the analog signal input to the external analog-to-digital converter. In other embodiments, the positive input terminal of the operational amplifier within the first-stage integrator is connected to a first gain amplifier, which is equivalent to receiving the analog signal input to the external analog-to-digital converter through the first gain amplifier. Here, the first gain amplifier is equivalent to a preamplifier, used to amplify the signal to be integrated according to the gain parameter of the first gain amplifier before the first-stage integrator performs the integration operation. This improves the driving capability of the analog signal.

[0052] Preferably, the last stage integrator ( Figure 3The Nth-stage integrator is connected to the quantizer via a second gain amplifier. Specifically, the positive and negative outputs of the last-stage integrator are connected to the positive and negative inputs of the second gain amplifier, and the output of the second gain amplifier is connected to the input of the quantizer. This connects the Nth-stage integrator, the second gain amplifier, the quantizer, and the DAC unit into a feedback loop. The DAC unit is a digital-to-analog converter with interpolation filtering capabilities and supports continuous analog-to-digital conversion. The addition of the second gain amplifier improves the accuracy of chopping and integration processing in the feedback loop.

[0053] In one embodiment, the first DAC unit is connected between the negative input of the first-stage integrator and the output of the quantizer. This unit performs periodic extension processing on the quantized output signal from the quantizer and converts it into a first feedback signal, which is then transmitted to the negative input of the first-stage integrator. Specifically, the DAC unit (including the first DAC unit and the second DAC unit) extends the quantized output signal from the quantizer in the discrete-time domain. Mathematically, this is equivalent to processing the quantized output signal according to a relevant Z-function, which is essentially a delay processing. It can be understood that each time the DAC unit performs periodic extension processing, it performs multiple delay processing operations, and the DAC unit converts the digital signal generated by each delay processing into an analog signal in real time, i.e., the first feedback signal. When the number of quantization bits in the quantizer is 1, whenever a delay processing is performed on a 1-bit quantized output signal, the DAC unit feeds back an analog signal to the input of the corresponding first-stage integrator. It should be noted that the signal input to the analog-to-digital converter (ADC) is an analog signal. After feedback processing by the DAC unit and integration processing by the cascaded integrators, the overall effect is equivalent to filtering the analog signal input to each integrator stage. Furthermore, the quantizer quantizes the output signal of the last integrator stage, outputting a bit stream with a value of +1 or -1, corresponding to a high or low level, converting it into a digital code stream represented using "1 / 0". Therefore, the quantized output signal is a digital signal. Quantizers can be divided into one-bit quantizers and multi-bit quantizers. Using a multi-bit quantizer can increase the signal-to-noise ratio, making the ADC easier to stabilize, generating fewer harmonic components, and ensuring sufficient accuracy for the DAC unit to guarantee the accuracy of the final feedback analog signal.

[0054] It should be noted that each integrator stage is a continuous-time structure used to integrate the input signal through a continuous-time structure. Therefore, the Sigma-Delta analog-to-digital converter is configured as a continuous-time Sigma-Delta analog-to-digital converter. Based on this, when N is 3, a third-order Sigma-Delta analog-to-digital converter is formed.

[0055] As one example, combined with Figure 3 and Figure 4 It can be seen that the first operational amplifier is a four-input operational amplifier, wherein the positive input terminal of the first operational amplifier includes the first positive input terminal and the second positive input terminal, and the negative input terminal of the first operational amplifier includes the first negative input terminal and the second negative input terminal; optionally, in Figure 3 In this embodiment, the first positive input terminal of the first operational amplifier is connected to the first output terminal of the first chopper, wherein the first positive input terminal of the first operational amplifier is used to receive the differential signal VIP1 output from the first output terminal of the first chopper; the second negative input terminal of the first operational amplifier is connected to the second output terminal of the first chopper, wherein the second negative input terminal of the first operational amplifier is used to receive the differential signal VIN2 output from the second output terminal of the first chopper; both the first negative input terminal and the second positive input terminal of the first operational amplifier are connected to a common-mode reference voltage. This embodiment designs the operational amplifier in the aforementioned first-stage integrator as a differential operational amplifier with four input terminals, supporting two pairs of differential inputs and one pair of differential outputs, to meet the stability requirements of the positive input type operational amplifier structure for its input and output; thereby, while ensuring low circuit complexity, it increases the input impedance of the first-stage integrator where the first operational amplifier is located, thereby improving the driving capability of the first-stage integrator and ensuring the transmission quality of the signal to be integrated.

[0056] In one embodiment, the first operational amplifier includes a current mirror circuit, a first-stage amplifier circuit, a second-stage amplifier circuit, a first common-mode feedback circuit, and a second common-mode feedback circuit. The current mirror circuit, the first-stage amplifier circuit, and the second-stage amplifier circuit all support differential input and differential output. The differential output terminal of the first-stage amplifier circuit is connected to the differential input terminal of the second-stage amplifier circuit, thus cascading the first-stage and second-stage amplifier circuits. The differential output terminal of the first-stage amplifier circuit is also connected to the feedback terminal of the current mirror circuit through the first common-mode feedback circuit to stabilize the output level of this stage. Therefore, the current mirror circuit and the first-stage amplifier circuit constitute a complete amplifier stage. The differential output of the second-stage amplifier circuit is connected to the feedback terminal of the second-stage amplifier circuit through a second common-mode feedback circuit. The differential output of the second-stage amplifier circuit is the output terminal of the first operational amplifier. The first positive input terminal, the first negative input terminal, the second positive input terminal, and the second negative input terminal of the first operational amplifier are all input terminals of the current mirror circuit, corresponding to two pairs of differential input terminals. The output terminal of the current mirror circuit is connected to the power supply terminal of the first-stage amplifier circuit, providing a drive signal source for the first-stage amplifier circuit. The power supply connected to the power supply terminal of the second-stage amplifier circuit is the same as that connected to the power supply terminal of the current mirror circuit. The ground terminal of the second-stage amplifier circuit and the ground terminal of the first-stage amplifier circuit share a ground wire, specifically the source of the relevant NMOS transistor is grounded. This forms a first loop of the first-stage amplifier circuit and the first common-mode feedback circuit, and a second loop of the second-stage amplifier circuit and the second common-mode feedback circuit. The first loop and the second loop together maintain the stability of the differential signal output by the first operational amplifier and provide a high input impedance for the differential input signal.

[0057] In the above embodiments, the first common-mode feedback circuit and the second common-mode feedback circuit can be regarded as two independent common-mode feedback circuits, or they can be combined into an integrated circuit module to form a common-mode feedback circuit. The differential input terminal of the first common-mode feedback circuit is connected to the differential output terminal of the first amplifier circuit, and the output terminal of the first common-mode feedback circuit is connected to the current mirror circuit to form the first loop. The differential input terminal of the second common-mode feedback circuit is connected to the differential output terminal of the second amplifier circuit, and the output terminal of the second common-mode feedback circuit is connected to the second amplifier circuit to form the second loop.

[0058] It should be noted that the common-mode feedback circuits can be classified into continuous-time common-mode feedback circuits and switched-capacitor common-mode feedback circuits. Continuous-time common-mode feedback circuits perform continuous calibration of the output common-mode voltage offset. However, switched-capacitor common-mode feedback circuits provide discrete feedback control of the output common-mode voltage, completing the calibration within half a clock cycle of each charge transfer. Continuous-time common-mode feedback circuits are mainly used in continuous-time circuits, but they have disadvantages such as limiting the differential-mode output signal swing, increasing differential-mode load, increasing static power consumption, and nonlinearity in common-mode voltage detection. Switched-capacitor common-mode feedback circuits have advantages in these aspects, but they are unsuitable for continuous-time circuits because they introduce clock coupling and discrete operating states that cause glitches in the differential output signal. Switched-capacitor common-mode feedback circuits have been successfully applied in data sampling systems, especially in fully differential switched-capacitor circuits. Specifically, a common-mode feedback circuit is generally divided into two parts: a common-mode detection circuit and a comparator amplifier circuit. The common-mode detection circuit detects the output common-mode voltage, which is then input to the comparator amplifier circuit and compared with a pre-specified common-mode reference voltage. The difference between them is amplified and returned to the original circuit to correct the offset of the output common-mode voltage.

[0059] In some embodiments, the current mirror circuit can be a MOS-type current mirror circuit, where the first and second stage amplifier circuits are connected by MOS transistors, particularly using an inverter structure to construct the two-stage amplifier circuit. Alternatively, the current mirror circuit can be a transistor-type current mirror, where the first and second stage amplifier circuits are connected by transistors. When the current mirror circuit is a MOS-type current mirror circuit, the channel length modulation effect is suppressed. In this case, the substrates of the relevant PMOS transistors in the current mirror circuit, the first stage amplifier circuit, and the second stage amplifier circuit are all connected to the power supply VDD, and the substrates of the relevant NMOS transistors are all connected to the ground line GND. When the current mirror circuit is a transistor-type current mirror circuit, the base width modulation effect is suppressed.

[0060] As one example, such as Figure 4As shown, the current mirror circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6. The gate of the third PMOS transistor MP3 is the first positive input terminal of the first operational amplifier, used to input the differential analog signal VIP1. The gate of the fifth PMOS transistor MP5 is the second positive input terminal of the first operational amplifier, used to input the differential analog signal VIP2. The gate of the fourth PMOS transistor MP4 is the first negative input terminal of the first operational amplifier, used to input the differential analog signal VIN1. The gate of the sixth PMOS transistor is the second negative input terminal of the first operational amplifier, used to input the differential analog signal VIN2. It should be noted that the source of the first PMOS transistor MP1 is the first power supply terminal of the current mirror circuit, and the source of the second PMOS transistor MP2 is the second power supply terminal of the current mirror circuit. The power supply terminals of the current mirror circuit include both the first and second power supply terminals. The drain of the third PMOS transistor MP3 is connected to the drain of the fifth PMOS transistor MP5. The connection point between the drains of the third PMOS transistor MP3 and the fifth PMOS transistor MP5 is the first output terminal of the current mirror circuit, providing a current source for the pair of differential MOS transistors set up inside the first-stage amplifier circuit. The drain of the fourth PMOS transistor MP4 is connected to the drain of the sixth PMOS transistor MP6. The connection point between the drains of the fourth PMOS transistor MP4 and the sixth PMOS transistor MP6 is the second output terminal of the current mirror circuit, providing a current source for the other pair of differential MOS transistors in the first-stage amplifier circuit, thus forming a current mirror load structure and improving the driving capability of the first-stage amplifier circuit. The output terminals of the current mirror circuit include the first output terminal and the second output terminal of the current mirror circuit. The sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the drain of the first PMOS transistor MP1, and the sources of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are both connected to the drain of the second PMOS transistor MP2. The gate of the first PMOS transistor MP1 is the first feedback terminal of the current mirror circuit, used to receive the common-mode feedback control signal Vfb1; the gate of the second PMOS transistor MP2 is the second feedback terminal of the current mirror circuit, used to receive the common-mode feedback control signal Vfb1. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the output terminal of the first common-mode feedback circuit. The feedback terminal of the current mirror circuit includes the first feedback terminal and the second feedback terminal of the current mirror circuit, thus forming the working loop of the current mirror circuit, the first-stage amplifier circuit, and the first common-mode feedback circuit. As long as the loop is stable, the average voltage (common-mode voltage) of the differential signal output by the first-stage amplifier circuit is equal to the common-mode reference voltage.

[0061] As one example, such as Figure 4As shown, the first-stage amplifier circuit includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM4. The source of the seventh PMOS transistor MP7 is the first power supply terminal of the first-stage amplifier circuit, which is connected to the first output terminal of the aforementioned current mirror circuit. The source of the eighth PMOS transistor MP8 is the second power supply terminal of the first-stage amplifier circuit, which is connected to the second output terminal of the current mirror circuit. The gate of the seventh PMOS transistor MP7 is connected to a first bias voltage Vb1 provided externally. MOSFET MP7 provides bias current. When the first bias voltage Vb1 is constant, a constant bias current is generated in the branch where the seventh PMOS transistor MP7 is located. The gate of the eighth PMOS transistor MP8 is connected to the first bias voltage Vb1 provided externally, providing bias current for the eighth PMOS transistor MP8. When the first bias voltage Vb1 is constant, a constant bias current is generated in the branch where the eighth PMOS transistor MP8 is located. The power supply terminals of the first stage amplifier circuit include a first power supply terminal and a second power supply terminal. The output terminals of the current mirror circuit include a first output terminal and a second output terminal. The drain of the seventh PMOS transistor MP7 is connected to the drain of the first NMOS transistor NM1. The gate of the first NMOS transistor NM1 is connected to the second bias voltage Vb2 provided by the outside, which provides bias current for the first NMOS transistor NM1. The source of the first NMOS transistor NM1 is connected to the drain of the third NMOS transistor NM3. The gate of the third NMOS transistor NM3 is connected to the third bias voltage Vb3 provided by the outside, which provides bias current for the third NMOS transistor NM3. The source of the third NMOS transistor NM3 is grounded to GND. If necessary, the substrates of the first NMOS transistor NM1 and the substrates of the third NMOS transistor NM3 are both grounded to GND. The drain of the eighth PMOS transistor MP8 is connected to the drain of the second NMOS transistor NM2; the gate of the second NMOS transistor NM2 is connected to a second bias voltage Vb2 provided externally, providing bias current for the second NMOS transistor NM2; the source of the second NMOS transistor NM2 is connected to the drain of the fourth NMOS transistor NM4; the gate of the fourth NMOS transistor NM4 is connected to a third bias voltage Vb3 provided externally, providing bias current for the fourth NMOS transistor NM4; the source of the fourth NMOS transistor NM4 is grounded to GND. Necessarily, the substrates of both the second NMOS transistor NM2 and the fourth NMOS transistor NM4 are grounded to GND.The connection node 41 between the drain of the seventh PMOS transistor MP7 and the drain of the first NMOS transistor NM1 is the positive output terminal of the first-stage amplifier circuit, used to output the differential output signal VOP1; the connection node 42 between the drain of the eighth PMOS transistor MP8 and the drain of the second NMOS transistor NM2 is the negative output terminal of the first-stage amplifier circuit, used to output the differential output signal VON1; wherein, the differential output terminal of the first-stage amplifier circuit includes both the positive and negative output terminals. The average values ​​of the differential output signals VON1 and VOP1, i.e., the common-mode voltages of the differential output signals VON1 and VOP1, are both adjusted and stabilized to the common-mode reference voltage under the action of the first common-mode feedback circuit.

[0062] As one example, such as Figure 4 As shown, the first bias voltage Vb1, the second bias voltage Vb2, and the third bias voltage Vb3 are not equal to each other, so as to form a voltage difference between different pairs of MOSFETs. The voltage difference between any two of the first, second, and third bias voltages remains constant, ensuring a constant voltage difference and helping to suppress channel length modulation effects. It should be noted that the first, second, and third bias voltages are all provided by corresponding bias voltage sources. It should also be noted that the above bias voltage sources can also be implemented using voltage regulator devices or voltage regulator circuits. This embodiment does not limit this. For input power supply circuits, the aforementioned bias voltages can be designed to be stable relative to ground.

[0063] Combination Figure 5It is known that the positive and negative output terminals of the first-stage amplifier circuit are respectively connected to the differential input terminals (including the positive and negative input terminals) of the first common-mode feedback circuit. The positive input terminal of the first common-mode feedback circuit CMFB1 is used to receive the differential output signal VOP1 output from the positive output terminal of the first-stage amplifier circuit, and the negative input terminal of the first common-mode feedback circuit CMFB1 is used to receive the differential output signal VON1 output from the negative output terminal of the first-stage amplifier circuit. The first feedback terminal and the second feedback terminal of the current mirror circuit are both connected to the output terminal of the first common-mode feedback circuit CMFB1. The first common-mode feedback circuit CMFB1 provides a feedback control signal Vfb1 to the first and second feedback terminals of the current mirror circuit to adjust the differential output result of the first-stage amplifier circuit, specifically making the common-mode voltage of the first-stage amplifier circuit output equal to the common-mode reference voltage Vcom. It should be noted that the feedback terminals of the current mirror circuit include the first and second feedback terminals of the current mirror circuit. When the working loop of the current mirror circuit, the first-stage amplifier circuit, and the first common-mode feedback circuit is stable, the differential output of the first-stage amplifier circuit is stabilized at the common-mode reference voltage, which can realize that the voltage of the differential output signal VOP1 is equal to the common-mode reference voltage, and the voltage of the differential output signal VON1 is equal to the common-mode reference voltage.

[0064] As one example, such as Figure 4As shown, the second-stage amplifier circuit includes a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6. The source of the ninth PMOS transistor MP9 is connected to the first power supply terminal of the current mirror circuit, which is used to connect to the power supply VDD. The gate of the ninth PMOS transistor MP9 is the positive input terminal of the second-stage amplifier circuit, and the gate of the ninth PMOS transistor MP9 is connected to the positive output terminal of the first-stage amplifier circuit, which is used to receive the differential signal VOP1 output from the positive output terminal of the first-stage amplifier circuit or the common-mode reference voltage Vcom adjusted by the first common-mode feedback circuit. This allows the second-stage amplifier circuit to be cascaded with the first-stage amplifier circuit, and the input impedance of the first operational amplifier is improved due to the cascaded structure of the multi-stage amplifier circuit. The source of the fifth NMOS transistor NM5 is grounded to GND. The drain of the ninth PMOS transistor MP9 is connected to the drain of the fifth NMOS transistor NM5. The connection point between the drains of the ninth PMOS transistor MP9 and the fifth NMOS transistor NM5 is the positive output terminal of the second-stage amplifier circuit, used to output the differential output signal VOP2, which serves as the differential signal output from the positive output terminal of the first operational amplifier. The source of the tenth PMOS transistor MP10 is connected to the second power supply terminal of the current mirror circuit, used to connect to the power supply VDD. The gate of the tenth PMOS transistor MP10 is the negative input terminal of the second-stage amplifier circuit. The gate of the tenth PMOS transistor MP10 is connected to the negative output terminal of the first-stage amplifier circuit, used to receive the differential signal VON1 output from the negative output terminal of the first-stage amplifier circuit or the common-mode reference voltage Vcom adjusted by the first common-mode feedback circuit. This allows the second-stage amplifier circuit to be cascaded with the first-stage amplifier circuit, thus increasing the input impedance of the first operational amplifier due to the cascaded structure of the two amplifier stages. The source of the sixth NMOS transistor NM6 is grounded; the drain of the tenth PMOS transistor MP10 is connected to the drain of the sixth NMOS transistor NM6. The connection point between the drains of the tenth PMOS transistor MP10 and the sixth NMOS transistor NM6 is the negative output terminal of the second-stage amplifier circuit, used to output the differential output signal VON2, which serves as the differential signal output from the negative output terminal of the first operational amplifier. Figure 4 and Figure 5It can be seen that the positive output terminal and the negative output terminal of the second-stage amplifier circuit are respectively connected to the differential input terminal (including the positive input terminal and the negative input terminal) of the second common-mode feedback circuit; the positive input terminal of the second common-mode feedback circuit CMFB2 is used to receive the differential output signal VOP2 output from the positive output terminal of the second-stage amplifier circuit, and the negative input terminal of the second common-mode feedback circuit CMFB2 is used to receive the differential output signal VON2 output from the negative output terminal of the second-stage amplifier circuit. The gate of the fifth NMOS transistor NM5 is the first feedback terminal of the second-stage amplifier circuit, and the gate of the fourth NMOS transistor NM4 is the second feedback terminal of the second-stage amplifier circuit. Both the first and second feedback terminals of the second-stage amplifier circuit are connected to the output terminal of the second common-mode feedback circuit. The second common-mode feedback circuit CMFB2 provides a feedback control signal Vfb2 to the first and second feedback terminals of the second-stage amplifier circuit to adjust the differential output of the second-stage amplifier circuit. Specifically, it ensures that the common-mode voltage of the second-stage amplifier circuit output (the average voltage of the differential output signals VON2 and VOP2) is equal to the common-mode reference voltage Vcom. When the working loop formed by the current mirror circuit, the first-stage amplifier circuit, the first common-mode feedback circuit, the second-stage amplifier circuit, and the second common-mode feedback circuit is stable, the differential output of the second-stage amplifier circuit stabilizes at the common-mode reference voltage. This allows the voltage of the differential output signal VOP2 to be equal to the common-mode reference voltage, and the voltage of the differential output signal VON2 to be equal to the common-mode reference voltage. In summary, in the aforementioned embodiments, the output of the first-stage amplifier circuit provides bias for the input of the second-stage amplifier circuit, and both stages of the amplifier circuit have their own independent common-mode feedback circuits to adjust the differential signal output by the operational amplifier of this stage, so that the corresponding common-mode voltage is equal to the common-mode reference voltage. In this way, the two stages of the amplifier circuit can share the current of the current mirror circuit, increase the input impedance of the first operational amplifier, thereby increasing the overall gain and expanding the output range.

[0065] It should be noted that the feedback terminals of the current mirror circuit include the first feedback terminal and the second feedback terminal of the current mirror circuit; the differential input terminals of the second-stage amplifier circuit include the positive input terminal and the negative input terminal of the second-stage amplifier circuit; the differential output terminals of the second-stage amplifier circuit include the positive output terminal and the negative output terminal of the second-stage amplifier circuit; the differential output terminals of the first-stage amplifier circuit include the positive output terminal and the negative output terminal of the first-stage amplifier circuit; the power supply terminals of the current mirror circuit include the first power supply terminal and the second power supply terminal of the current mirror circuit; the feedback terminals of the second-stage amplifier circuit include the first feedback terminal and the second feedback terminal of the second-stage amplifier circuit. Therefore, the differential input terminals of the second-stage amplifier circuit are the output of the first-stage amplifier circuit and the feedback control signal Vfb2 provided by the second common-mode feedback circuit CMFB2.

[0066] Combination Figure 5 It can be seen that the first common-mode feedback circuit CMFB1 and the second common-mode feedback circuit CMFB2 are of the same type of common-mode feedback circuit. Both the first common-mode feedback circuit CMFB1 and the second common-mode feedback circuit CMFB2 are connected to the same common-mode reference voltage Vcom. The first common-mode feedback circuit CMFB1 is used to compare the differential signal output by the first-stage amplifier circuit with the common-mode reference voltage, and generate a feedback control signal to the feedback terminal of the current mirror circuit, so that the differential signal output by the first-stage amplifier circuit is stabilized at the common-mode reference voltage Vcom, at least making the average voltage of the differential signal output by the first-stage amplifier circuit equal to the common-mode reference voltage Vcom. The second common-mode feedback circuit CMFB2 is used to compare the differential signal output by the second-stage amplifier circuit with the common-mode reference voltage, and generate a feedback control signal to the feedback terminal of the second-stage amplifier circuit, so that the differential signal output by the second-stage amplifier circuit is stabilized at the common-mode reference voltage Vcom, at least making the average voltage of the differential signal output by the second-stage amplifier circuit equal to the common-mode reference voltage Vcom.

[0067] In one implementation, when the average voltage of the differential signal output from the differential output terminal of the first-stage amplifier circuit is greater than the common-mode reference voltage, the first common-mode feedback circuit generates a corresponding feedback control signal to lower the average voltage of the differential signal output from the first-stage amplifier circuit to reach the common-mode reference voltage, and to stably equal the common-mode reference voltage. When the average voltage of the differential signal output from the first-stage amplifier circuit is less than the common-mode reference voltage, the first common-mode feedback circuit generates a corresponding feedback control signal to raise the average voltage of the differential signal output from the first-stage amplifier circuit to reach the common-mode reference voltage, and to stably equal the common-mode reference voltage. Therefore, in this embodiment, the voltage of the differential input to the first-stage amplifier circuit often cannot reach the expected voltage value during production due to process deviations or other factors. The common-mode feedback circuit is needed to adjust the average voltage of the output differential signal, i.e., the common-mode voltage, to the expected voltage, i.e., the common-mode reference voltage.

[0068] In one implementation, when the voltage of the first differential signal output from the differential output terminal of the first-stage amplifier circuit is greater than the common-mode reference voltage, and the voltage of the second differential signal output from the first-stage amplifier circuit is less than the common-mode reference voltage, the first common-mode feedback circuit generates a corresponding feedback control signal to pull down the voltage of the first differential signal output from the first-stage amplifier circuit to reach the common-mode reference voltage, and simultaneously pull up the voltage of the second differential signal output from the first-stage amplifier circuit to reach the common-mode reference voltage, and ensures that the adjusted voltages of the first and second differential signals are both equal to the common-mode reference voltage, and remains stable at the common-mode reference voltage.

[0069] In one implementation, when the average voltage of the differential signal output from the differential output terminal of the second-stage amplifier circuit is greater than the common-mode reference voltage, the second common-mode feedback circuit generates a corresponding feedback control signal to lower the average voltage of the differential signal output from the second-stage amplifier circuit to reach the common-mode reference voltage, and ensures that the average voltage is stably equal to the common-mode reference voltage. When the average voltage of the differential signal output from the second-stage amplifier circuit is less than the common-mode reference voltage, the second common-mode feedback circuit generates a corresponding feedback control signal to raise the average voltage of the differential signal output from the second-stage amplifier circuit to reach the common-mode reference voltage, and ensures that the average voltage is stably equal to the common-mode reference voltage. Therefore, in this embodiment, the voltage of the differential input second-stage amplifier circuit often cannot reach the expected voltage value during production due to process deviations or other factors. The common-mode feedback circuit is needed to adjust the average voltage of the output differential signal, i.e., the common-mode voltage, to the expected voltage, i.e., the common-mode reference voltage.

[0070] In one implementation, when the voltage of the first differential signal output from the differential output terminal of the second-stage amplifier circuit is greater than the common-mode reference voltage, and the voltage of the second differential signal output from the second-stage amplifier circuit is less than the common-mode reference voltage, the second common-mode feedback circuit generates a corresponding feedback control signal to pull down the voltage of the first differential signal output from the second-stage amplifier circuit to reach the common-mode reference voltage, and simultaneously pull up the voltage of the second differential signal output from the second-stage amplifier circuit to reach the common-mode reference voltage. Then, the adjusted voltages of the first and second differential signals are both equal to the common-mode reference voltage and kept stable at the common-mode reference voltage.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. An analog-to-digital converter with a positive input operational amplifier structure, characterized in that, The analog-to-digital converter includes an N-stage integrator, a quantizer, and a DAC unit; The integrator, quantizer, and DAC unit are connected in sequence. The DAC unit is used to establish a signal connection between the output of the quantizer and the input of the corresponding integrator. The first-stage integrator is designed as a positive-input operational amplifier structure, wherein the analog signal of the external input analog-to-digital converter is configured to flow through the positive input terminal of the operational amplifier in the first-stage integrator; The first-stage integrator includes a first operational amplifier, a first resistor, and a first capacitor; The positive input terminal of the first operational amplifier is used to receive the input signal to be integrated, wherein the input signal to be integrated is an analog signal from the externally input analog-to-digital converter; The negative input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier through the first capacitor, and the negative input terminal of the first operational amplifier is grounded through the first resistor. Thus, the first operational amplifier, the first resistor, and the first capacitor constitute the positive input type operational amplifier structure.

2. The analog-to-digital converter according to claim 1, characterized in that, The first-stage integrator is the positive-input operational amplifier structure, and at least one of the integrators from the second-stage to the Nth-stage integrator is an inverting-input operational amplifier structure.

3. The analog-to-digital converter according to claim 1, characterized in that, The first-stage integrator is the positive-input operational amplifier structure, and at least one of the integrators from the second-stage to the Nth-stage integrator is the positive-input operational amplifier structure.

4. The analog-to-digital converter according to claim 2 or 3, characterized in that, The first-stage integrator also includes a first chopper and a second chopper; The positive input operational amplifier structure formed by the first-stage integrator is specifically as follows: The first input terminal of the first chopper is connected to one end of the first resistor, and the other end of the first resistor is grounded; the first output terminal of the first chopper is connected to the negative input terminal of the first operational amplifier. The second input terminal of the first chopper is used to receive the analog signal from the external input analog-to-digital converter, so that the input terminal of the first chopper becomes the input terminal of the first stage integrator; the second output terminal of the first chopper is connected to the positive input terminal of the first operational amplifier. The output of the first operational amplifier is connected to one end of the first capacitor via a second chopper, and the other end of the first capacitor is connected to the first input of the first chopper. The DAC unit is connected to the first input of the first chopper and the output of the quantizer. The output of the second chopper is configured as the output of the first-stage integrator.

5. The analog-to-digital converter according to claim 4, characterized in that, The negative output terminal of the first operational amplifier is connected to the first input terminal of the second chopper, and the positive output terminal of the first operational amplifier is connected to the second input terminal of the second chopper. The positive or negative output terminal of the second chopper is connected to the first input terminal of the first chopper through the first capacitor.

6. The analog-to-digital converter according to claim 2, characterized in that, The inverting input operational amplifier structure formed by the first-stage integrator is specifically as follows: This integrator stage includes pre-configured operational amplifiers, resistors, and capacitors; The negative input terminal of the pre-configured operational amplifier receives the input signal to be integrated through a resistor. The input signal to be integrated is the analog signal summed in the previous stage. The negative input terminal of the pre-configured operational amplifier is connected to the output terminal of the pre-configured operational amplifier through a capacitor, and the positive input terminal of the pre-configured operational amplifier is grounded through a resistor.

7. The analog-to-digital converter according to claim 2, characterized in that, Each stage of the integrator includes a pre-configured operational amplifier, whose input is set to connect to the output of the corresponding stage summing node. When the first-stage integrator forms the positive input operational amplifier structure, the first-stage summing node corresponding to the positive input terminal of the pre-configured operational amplifier does not receive external analog signals through the branch resistor. When the first-stage integrator forms the inverting input operational amplifier structure, the first-stage summing node corresponding to the negative input terminal of the pre-configured operational amplifier receives external analog signals through the branch resistor.

8. The analog-to-digital converter according to claim 7, characterized in that, The integrators exist in the analog-to-digital converter in a cascaded manner. Each integrator has a summing node configured at its input terminal, and each integrator corresponds to a summing node. The DAC unit includes a first DAC unit and a second DAC unit; The first DAC unit is connected between the input terminal of the summing node corresponding to the first-stage integrator and the output terminal of the quantizer. The first DAC unit is used to convert the quantized output signal output by the quantizer into a first feedback signal, and then transmit the first feedback signal to the input terminal of the summing node corresponding to the first-stage integrator. The second DAC unit is connected between the summing node corresponding to the last stage integrator and the output of the quantizer. The second DAC unit is used to compensate the N-stage integrator.

9. The analog-to-digital converter according to claim 8, characterized in that, The first-stage summing node corresponding to the first-stage integrator is provided with a first input terminal and a second input terminal; The first input terminal of the first-stage summing node is used to receive the analog signal from the external input analog-to-digital converter and transmit it to the positive input terminal of the first operational amplifier through a chopper; The second input of the first-stage summing node is used to receive the first feedback signal output by the first DAC unit and transmit it to the negative input of the first operational amplifier through a chopper.

10. The analog-to-digital converter according to claim 8, characterized in that, In the analog-to-digital converter, the second-stage integrator to the Nth-stage integrator are respectively configured with the second-stage summing node to the Nth-stage summing node; wherein, the Nth-stage integrator is the last stage integrator; each stage summing node has a first input terminal, a second input terminal, and an output terminal; The first input of the i-th stage summing node is connected to the output of the (i-1)-th stage integrator, and the first input of the i-th stage summing node is used to receive the (i-1)-th stage integral analog signal output by the (i-1)-th stage integrator; the second input of the i-th stage summing node is connected to the output of the N-th stage integrator, and the second input of the i-th stage summing node is used to receive the integral analog signal output by the N-th stage integrator, wherein the integral analog signal output by the N-th stage integrator is a pre-feedback analog signal; The output of the i-th stage summing node is connected to the input of the i-th stage integrator. The output of the i-th stage summing node is used to output the i-th stage summing analog signal to the input of the i-th stage integrator. The i-th stage integrator is used to integrate the i-th stage summed analog signal and output the i-th stage integrated analog signal; Wherein, the i-th level summation analog signal is the sum of the (i-1)-th level integral analog signal and the pre-feedback analog signal; The (i-1)th stage integrator is used to integrate the output signal of the (i-1)th stage summing node to obtain the (i-1)th stage integrated analog signal. Where N is a positive integer; i is an integer greater than 1, and i is an integer less than or equal to N-1; Each integrator stage is a continuous-time structure used to integrate the input signal through a continuous-time structure.

11. The analog-to-digital converter according to claim 9, characterized in that, In addition to the first and second input terminals, the Nth level summation node also has N-1 preset input terminals; In the first-level summing node to the (N-1)th-level summing node, the signal input to the first input terminal of each level summing node is also configured to be input to the corresponding preset input terminal in the Nth-level summing node; The first input of the Nth stage summing node is connected to the output of the (N-1)th stage integrator. The first input of the Nth stage summing node is used to receive the (N-1)th stage integrated analog signal output by the (N-1)th stage integrator. The second input of the i-th stage summing node is used to receive the feedback signal used to compensate the N-stage cascaded integrator. The output of the Nth-level summing node is used to output the Nth-level summing analog signal to the Nth-level integrator; wherein, the Nth-level summing node is used to sum the N-1th-level integral analog signal, the feedback signal used to compensate the Nth-level cascaded integrator, and the signal input by each preset input terminal, and the sum value is configured as the Nth-level summing analog signal. The Nth-stage integrator is used to receive and integrate the Nth-stage summed analog signal to obtain the Nth-stage integrated analog signal.

12. The analog-to-digital converter according to claim 7, characterized in that, The operational amplifier built into the first-stage integrator is connected to a first gain amplifier to meet the gain requirements of the analog signal input to the external analog-to-digital converter. The final integrator is connected to the quantizer via a second gain amplifier, so that the N-stage integrator, the second gain amplifier, the quantizer and the DAC unit are connected to form a feedback loop; The DAC unit is a digital-to-analog converter with interpolation filtering function.

13. The analog-to-digital converter according to claim 4, characterized in that, The first operational amplifier is a four-input operational amplifier, wherein the positive input terminal of the first operational amplifier includes a first positive input terminal and a second positive input terminal, and the negative input terminal of the first operational amplifier includes a first negative input terminal and a second negative input terminal. The first positive input terminal of the first operational amplifier is connected to the first output terminal of the first chopper, and the second negative input terminal of the first operational amplifier is connected to the second output terminal of the first chopper. Both the first negative input terminal and the second positive input terminal of the first operational amplifier are connected to a common-mode reference voltage.

14. The analog-to-digital converter according to claim 13, characterized in that, The first operational amplifier includes a current mirror circuit, a first-stage amplifier circuit, a second-stage amplifier circuit, a first common-mode feedback circuit, and a second common-mode feedback circuit; wherein, the current mirror circuit, the first-stage amplifier circuit, and the second-stage amplifier circuit all support differential input and differential output; The differential output terminal of the first-stage amplifier circuit is connected to the differential input terminal of the second-stage amplifier circuit; the differential output terminal of the first-stage amplifier circuit is also connected to the feedback terminal of the current mirror circuit through the first common-mode feedback circuit. The differential output of the second-stage amplifier circuit is connected to the feedback terminal of the second-stage amplifier circuit through the second common-mode feedback circuit; the differential output of the second-stage amplifier circuit is the output terminal of the first operational amplifier. The first positive input terminal, the first negative input terminal, the second positive input terminal, and the second negative input terminal of the first operational amplifier are all input terminals of the current mirror circuit; the output terminal of the current mirror circuit is connected to the power supply terminal of the first stage amplifier circuit. In this circuit, the power supply connected to the power supply terminal of the second-stage amplifier circuit is the same as the power supply connected to the power supply terminal of the current mirror circuit.

15. The analog-to-digital converter according to claim 14, characterized in that, The current mirror circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor; The gate of the third PMOS transistor is the first positive input terminal of the first operational amplifier, the gate of the fifth PMOS transistor is the second positive input terminal of the first operational amplifier, the gate of the fourth PMOS transistor is the first negative input terminal of the first operational amplifier, and the gate of the sixth PMOS transistor is the second negative input terminal of the first operational amplifier. The drain of the third PMOS transistor is connected to the drain of the fifth PMOS transistor, and the connection point between the drains of the third PMOS transistor and the drain of the fifth PMOS transistor is the first output terminal of the current mirror circuit; the drain of the fourth PMOS transistor is connected to the drain of the sixth PMOS transistor, and the connection point between the drains of the fourth PMOS transistor and the drain of the sixth PMOS transistor is the second output terminal of the current mirror circuit; wherein, the output terminal of the current mirror circuit includes the first output terminal and the second output terminal of the current mirror circuit. The source of the third PMOS transistor and the source of the fourth PMOS transistor are both connected to the drain of the first PMOS transistor, and the source of the fifth PMOS transistor and the source of the sixth PMOS transistor are both connected to the drain of the second PMOS transistor. The gate of the first PMOS transistor is the first feedback terminal of the current mirror circuit, and the gate of the second PMOS transistor is the second feedback terminal of the current mirror circuit. Both the gates of the first PMOS transistor and the gate of the second PMOS transistor are connected to the output terminal of the first common-mode feedback circuit. The feedback terminal of the current mirror circuit includes the first feedback terminal and the second feedback terminal of the current mirror circuit. The source of the first PMOS transistor is the first power supply terminal of the current mirror circuit, and the source of the second PMOS transistor is the second power supply terminal of the current mirror circuit; the power supply terminals of the current mirror circuit include the first power supply terminal and the second power supply terminal of the current mirror circuit.

16. The analog-to-digital converter according to claim 14, characterized in that, The first-stage amplifier circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The source of the seventh PMOS transistor is the first power supply terminal of the first-stage amplifier circuit, which is connected to the first output terminal of the current mirror circuit. The source of the eighth PMOS transistor is the second power supply terminal of the first-stage amplifier circuit, which is connected to the second output terminal of the current mirror circuit. The gate of the seventh PMOS transistor is connected to a first bias voltage provided externally. The gate of the eighth PMOS transistor is also connected to a first bias voltage provided externally. The power supply terminals of the first-stage amplifier circuit include both the first and second power supply terminals. The output terminals of the current mirror circuit include both the first and second output terminals. The drain of the seventh PMOS transistor is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to a second bias voltage provided by the outside. The source of the first NMOS transistor is connected to the drain of the third NMOS transistor. The gate of the third NMOS transistor is connected to a third bias voltage provided by the outside. The source of the third NMOS transistor is grounded. The drain of the eighth PMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to a second bias voltage provided by the outside. The source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the fourth NMOS transistor is connected to a third bias voltage provided by the outside. The source of the fourth NMOS transistor is grounded. The connection point between the drain of the seventh PMOS transistor and the drain of the first NMOS transistor is the positive output terminal of the first-stage amplifier circuit, and the connection point between the drain of the eighth PMOS transistor and the drain of the second NMOS transistor is the negative output terminal of the first-stage amplifier circuit; wherein, the differential output terminal of the first-stage amplifier circuit includes the positive output terminal and the negative output terminal of the first-stage amplifier circuit. The positive and negative output terminals of the first-stage amplifier circuit are respectively connected to the differential input terminal of the first common-mode feedback circuit. The first feedback terminal and the second feedback terminal of the current mirror circuit are both connected to the output terminal of the first common-mode feedback circuit to adjust the differential output result of the first-stage amplifier circuit. The feedback terminal of the current mirror circuit includes the first feedback terminal and the second feedback terminal of the current mirror circuit.

17. The analog-to-digital converter according to claim 14, characterized in that, The second-stage amplifier circuit includes a ninth PMOS transistor, a tenth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The source of the ninth PMOS transistor is connected to the first power supply terminal of the current mirror circuit, the drain of the ninth PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the ninth PMOS transistor is the positive input terminal of the second stage amplifier circuit, the gate of the ninth PMOS transistor is connected to the positive output terminal of the first stage amplifier circuit, and the source of the fifth NMOS transistor is grounded; the connection node between the drain of the ninth PMOS transistor and the drain of the fifth NMOS transistor is the positive output terminal of the second stage amplifier circuit. The source of the tenth PMOS transistor is connected to the second power supply terminal of the current mirror circuit, the drain of the tenth PMOS transistor is connected to the drain of the sixth NMOS transistor, the gate of the tenth PMOS transistor is the negative input terminal of the second stage amplifier circuit, the gate of the tenth PMOS transistor is connected to the negative output terminal of the first stage amplifier circuit, and the source of the sixth NMOS transistor is grounded. The connection point between the drain of the tenth PMOS transistor and the drain of the sixth NMOS transistor is the negative output terminal of the second-stage amplifier circuit. The positive output terminal of the second-stage amplifier circuit and the negative output terminal of the second-stage amplifier circuit are respectively connected to the differential input terminal of the second common-mode feedback circuit. The gate of the fifth NMOS transistor is the first feedback terminal of the second-stage amplifier circuit, and the gate of the fourth NMOS transistor is the second feedback terminal of the second-stage amplifier circuit. Both the first feedback terminal and the second feedback terminal of the second-stage amplifier circuit are connected to the output terminal of the second common-mode feedback circuit to adjust the differential output result of the second-stage amplifier circuit. The differential input terminals of the second-stage amplifier circuit include the positive input terminal and the negative input terminal of the second-stage amplifier circuit; the differential output terminals of the second-stage amplifier circuit include the positive output terminal and the negative output terminal of the second-stage amplifier circuit; the differential output terminals of the first-stage amplifier circuit include the positive output terminal and the negative output terminal of the first-stage amplifier circuit; the power supply terminals of the current mirror circuit include the first power supply terminal and the second power supply terminal of the current mirror circuit; and the feedback terminals of the second-stage amplifier circuit include the first feedback terminal and the second feedback terminal of the second-stage amplifier circuit.

18. The analog-to-digital converter according to claim 16, characterized in that, The first bias voltage, the second bias voltage, and the third bias voltage are not equal to each other, so as to form a voltage difference between different pairs of MOSFETs; Among the first bias voltage, the second bias voltage, and the third bias voltage, the voltage difference between any two bias voltages remains constant; the first bias voltage, the second bias voltage, and the third bias voltage are all provided by corresponding bias voltage sources.

19. The analog-to-digital converter according to claim 14, characterized in that, The first common-mode feedback circuit and the second common-mode feedback circuit are of the same type of common-mode feedback circuit, and the first common-mode feedback circuit and the second common-mode feedback circuit are connected to the same common-mode reference voltage.

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