Display device and video wall display system including the same

Abstract

A display device and a video wall display system including the display device are provided. The display device includes: a pixel circuit layer including a plurality of transistors; a first electrode and a second electrode formed on the same layer on the pixel circuit layer; a light emitting element arranged between the first electrode and the second electrode; and an antenna pattern arranged on the light emitting element.

Description

Technical Field

[0001] The present disclosure relates to a display device and a video wall display system including the display device. Background Art

[0002] As interest in information display increases and demand for using portable information media increases, demand and commercialization of display devices come into focus. Summary of the invention

[0003] Technical issues

[0004] An object to be solved by the present disclosure is to provide a video wall display system including a plurality of display devices connected to a wireless network through an antenna pattern.

[0005] Another object to be solved by the present disclosure is to provide a video wall display system in which each of the display devices includes a nano-scale to micro-scale light emitting element.

[0006] Still another object to be solved by the present disclosure is to provide a video wall display system in which each of the display devices includes a wireless power transmission antenna for wireless charging.

[0007] The objects of the present disclosure are not limited to the objects described above, and other technical objects not described will be clearly understood by those skilled in the art from the following description.

[0008] Technical Solution

[0009] According to an embodiment of the present disclosure for solving the purpose described above, a display device includes: a pixel circuit layer, including a plurality of transistors; a first electrode and a second electrode, formed on the same layer on the pixel circuit layer; a light-emitting element, arranged between the first electrode and the second electrode; and an antenna pattern, arranged on the light-emitting element.

[0010] The display device may further include a first contact electrode electrically connecting one end of the light emitting element and the first electrode.

[0011] The antenna pattern may be formed at the same layer as the first contact electrode.

[0012] The antenna pattern and the first contact electrode may be electrically separated from each other.

[0013] The display device may further include a second contact electrode electrically connecting the other end of the light emitting element and the second electrode.

[0014] The first contact electrode may be disposed on the second contact electrode.

[0015] The antenna pattern may overlap the second contact electrode, and the display device may further include an insulating layer disposed between the antenna pattern and the second contact electrode.

[0016] The display device may further include a first bridge pattern formed at the same layer as the second contact electrode, and the antenna pattern may be connected to the first bridge pattern through a first contact hole formed in the insulating layer.

[0017] The first contact electrode, the second contact electrode, and the antenna pattern may be disposed at the same layer and may be electrically separated from each other.

[0018] The display device may further include a touch electrode pattern formed at the same layer as the antenna pattern.

[0019] The display device may further include a first contact electrode disposed on the same layer as the antenna pattern and the touch electrode pattern, and the first contact electrode may electrically connect one end of the light emitting element and the first electrode.

[0020] The transmission / reception frequency of the antenna pattern may be 28 GHz to 39 GHz.

[0021] The antenna pattern may include a transparent conductive material.

[0022] The display device may further include: a first contact electrode electrically connecting one end of the light emitting element to the first electrode; and a second contact electrode electrically connecting the other end of the light emitting element to the second electrode. The first contact electrode may be disposed on the second contact electrode, and the antenna pattern may be disposed under the second contact electrode.

[0023] The display device may further include: a first contact electrode electrically connecting one end of the light emitting element to the first electrode; and a second contact electrode electrically connecting the other end of the light emitting element to the second electrode, and the antenna pattern may be provided on the first contact electrode and the second contact electrode.

[0024] The display device may further include an encapsulation layer disposed on the first contact electrode and the second contact electrode, the antenna pattern may be disposed on the encapsulation layer, and the encapsulation layer may include at least one inorganic layer and an organic layer.

[0025] In addition, according to another embodiment of the present disclosure for solving the purpose described above, a video wall display system includes multiple display devices, each of the multiple display devices includes a display substrate and an antenna pattern arranged on the display substrate, the display substrate includes: a pixel circuit layer, including multiple transistors; a first electrode and a second electrode, formed on the same layer on the pixel circuit layer; and a light-emitting element, arranged between the first electrode and the second electrode.

[0026] Multiple display devices can be connected via a wireless network.

[0027] The display substrate may include a curved region.

[0028] The display substrate of the video wall display system may further include a wireless power transfer antenna disposed below the display substrate.

[0029] The display substrate of the video wall display system may further include a speaker module disposed below the display substrate.

[0030] The speaker module may include a first speaker electrode, a second speaker electrode, and a vibration layer disposed between the first speaker electrode and the second speaker electrode.

[0031] The vibration layer may include at least one of polyvinylidene fluoride (PVDF), lead zirconate titanate ceramic (PZT), and an electroactive polymer.

[0032] In addition, according to another embodiment of the present disclosure for solving the purpose described above, a video wall display system includes multiple display devices, each of the multiple display devices includes: a display substrate, including multiple transistors and multiple light-emitting elements; an antenna pattern, arranged on the display substrate; and a network communication unit, which sends wireless signals to other display devices in the video wall display system through the antenna pattern and receives wireless signals from other display devices in the video wall display system.

[0033] Each of the plurality of light emitting elements may have a diameter and a length ranging from a few hundred nanometers to a few micrometers.

[0034] The video wall display system may further include a control unit connected to at least one of the plurality of display devices through a wireless network, and a user's instruction may be input to the control unit.

[0035] Details of other embodiments are included in the detailed description and accompanying drawings.

[0036] Beneficial Effects

[0037] According to an embodiment of the present disclosure, a plurality of display devices in a video wall display system are connected through a wireless network, and the delay time between the display devices can be minimized.

[0038] Additionally, power can be supplied wirelessly to the video wall display system without separate code.

[0039] Additionally, the durability and efficiency of the video wall display system may be excellent.

[0040] The effects according to the embodiments are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1is a perspective view of a video wall display system according to an embodiment of the present disclosure.

[0042] Figure 2 is a control block diagram of a first display device according to an embodiment of the present disclosure.

[0043] Figure 3 and Figure 4 are a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0044] Figure 5 and Figure 6 are a perspective view and a cross-sectional view illustrating a light emitting element according to another embodiment of the present disclosure.

[0045] Figure 7 and Figure 8 are a perspective view and a cross-sectional view showing a light emitting element according to still another embodiment of the present disclosure.

[0046] Fig. 9 is a plan view showing a first display device according to an embodiment of the present disclosure.

[0047] Fig.10 is with Fig. 9 A schematic cross-sectional view of the first display device corresponding to line I1-I1'.

[0048] Fig.11 It is shown that the Fig. 9 A circuit diagram of an example of a sub-pixel in a first display device.

[0049] Figures 12 to 18 It is shown that it can be applied to include Fig.11 A circuit diagram of an example of a unit pixel in a sub-pixel.

[0050] Fig.19 It is schematically shown that the Fig. 9 A plan layout diagram of a sub-pixel arrangement in a first display device.

[0051] Fig. 20 It is schematically shown that the Fig. 9 A plan layout diagram of the arrangement of another sub-pixel in the first display device.

[0052] Fig.21 is in the first display device and Fig.19 The line I2 - I2 ′ corresponds to a cross-sectional view from the display substrate to the encapsulation layer.

[0053] Fig. 22 is in the first display device and Fig. 20 The line I3 - I3 ′ corresponds to a cross-sectional view from the display substrate to the encapsulation layer.

[0054] Fig.23 is a conceptual diagram illustrating a driving signal of each display device of a video wall display system according to an embodiment of the present disclosure.

[0055] Fig.24 is a perspective view of a video wall display system according to another embodiment of the present disclosure.

[0056] Fig.25 and Fig.26 is a cross-sectional view from a display substrate to an encapsulation layer of a first display device of a video wall display system according to yet another embodiment of the present disclosure.

[0057] Fig. 27 is a plan layout diagram schematically showing the arrangement of one sub-pixel included in a first display device of a video wall display system according to yet another embodiment of the present disclosure.

[0058] Fig.28 is in the first display device and Fig. 27 The line II2-II2' corresponds to a cross-sectional view from the display substrate to the encapsulation layer.

[0059] Fig.29 is a plan layout diagram schematically showing the arrangement of one sub-pixel included in a first display device of a video wall display system according to yet another embodiment of the present disclosure.

[0060] Fig.30 is in the first display device and Fig.29 The line III2-III2' corresponds to a cross-sectional view from the display substrate to the encapsulation layer.

[0061] Fig.31 is a plan layout diagram schematically showing the arrangement of one sub-pixel included in a first display device of a video wall display system according to yet another embodiment of the present disclosure.

[0062] Fig.32 is a cross-sectional view from a display substrate to an encapsulation layer in a first display device of a video wall display system according to yet another embodiment of the present disclosure.

[0063] Fig.33 yes Fig.32 's modified example.

[0064] Fig.34 is a plan layout diagram schematically showing the arrangement of one sub-pixel included in a first display device of a video wall display system according to yet another embodiment of the present disclosure.

[0065] Fig.35 is in the first display device and Fig.34 The line IV2-IV2' corresponds to a cross-sectional view from the display substrate to the encapsulation layer.

[0066] Fig.36 yes Fig.34 's modified example.

[0067] Fig.37 is a plan layout diagram schematically showing the arrangement of one sub-pixel included in a first display device of a video wall display system according to yet another embodiment of the present disclosure.

[0068] Fig.38 is in the first display device and Fig.37 The line V-V' corresponds to a cross-sectional view from the display substrate to the encapsulation layer.

[0069] Fig.39 is a perspective view of a first display device of a video wall display system according to yet another embodiment of the present disclosure.

[0070] Fig.40 yes Fig.39 Schematic cross-sectional view of a first display device shown in .

[0071] Fig.41 yes Fig.40 A magnified view of area AA.

[0072] Fig.42 yes Figure 1 's modified example. DETAILED DESCRIPTION

[0073] Refer to the following and attached Figure 1 The advantages and features of the present disclosure and methods for achieving them will become apparent from the embodiments described in detail below. However, the present disclosure is not limited to the embodiments disclosed below and can be implemented in various different forms. The current embodiments are provided so that the disclosure will be thorough and complete, and the technical personnel in the field of disclosure can fully understand the scope of the present disclosure. The present disclosure is limited only by the scope of the claims.

[0074] The case where an element or a layer is referred to as being 'on' another element or layer includes the case where another layer or another element is disposed directly on another element or between other layers. The same reference numerals denote the same components.

[0075] Although the first, second, etc. are used to describe various components, these components are not limited to these terms. These terms are only used to distinguish one component from another component. Therefore, within the disclosed technical spirit, the first component mentioned below may be the second component. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0076] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same components in the drawings.

[0077] Figure 1 is a perspective view of a video wall display system according to an embodiment of the present disclosure.

[0078] refer to Figure 1 As an embodiment, the video wall display system 1 may include a plurality of display devices DV1 to DV4 arranged in a predetermined order and a control unit MC connected to the display devices DV1 to DV4 through a wireless network. Each of the display devices DV1 to DV4 may receive a signal from the control unit MC and / or an adjacent display device DV1 to DV4 through an antenna pattern provided inside the display device DV1 to DV4, and may transmit the signal again to other adjacent display devices DV1 to DV4. That is, when at least one of the plurality of display devices DV1 to DV4 receives an image signal, the at least one display device may transmit the image signal to all the display devices DV1 to DV4 in a method of bypassing the image signal. Although the position of each of the display devices DV1 to DV4 is not determined, it is preferred to indicate the position in a matrix form. Figure 1 It is constructed in the form of a 2×2 matrix of width×length. Here, at least one of the width and length may be increased or decreased. In the present embodiment, the plurality of display devices DV1 to DV4 include a first display device DV1 to a fourth display device DV4, and based on the first display device DV1, the second display device DV2 is arranged on the lower side, the third display device DV3 is arranged on the left side, and the fourth display device DV4 is arranged on the lower left side.

[0079] The control unit MC may be used as a host system. For example, the control unit MC may be implemented as any one of a television system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a mobile phone system, and a tablet computer.

[0080] As an embodiment, the user's instructions may be input to the control unit MC in various formats. For example, the control unit MC may include a touch input unit, and the instructions input by the user's touch may be input to the control unit MC. However, the present disclosure is not limited thereto, and the user's instructions may be input to the control unit MC through an input method, a button input method, etc. through a remote control unit.

[0081] As examples, the display devices DV1 to DV4 may be used as large electronic devices such as televisions and monitors, and small and medium-sized electronic devices such as mobile phones, tablet computers, car navigation systems, game consoles, and smart watches.

[0082] The video wall display system 1 includes a display area DA and a non-display area NDA. The display devices DV1 to DV4 include display areas DA1 to DA4 and non-display areas NDA1 to NDA4, respectively.

[0083] Each of the display areas DA1 to DA4 is defined as an area in which a corresponding image is displayed. The non-display areas NDA1 to NDA4 are defined as areas in which no image is displayed. Each of the non-display areas NDA1 to NDA4 may be adjacent to each of the display areas DA1 to DA4. The display areas DA1 to DA4 may have a quadrilateral shape. The non-display areas NDA1 to NDA4 may have a shape surrounding the display areas DA1 to DA4. For example, the first display area DA1 may have a shape surrounded by the first non-display area NDA1, the second display area DA2 may have a shape surrounded by the second non-display area NDA2, the third display area DA3 may have a shape surrounded by the third non-display area NDA3, and the fourth display area DA4 may have a shape surrounded by the fourth non-display area NDA4. However, the present disclosure is not limited thereto, and the shape of each of the display areas DA1 to DA4 and the shape of each of the non-display areas NDA1 to NDA4 may be relatively changed.

[0084] Each of the display areas DA1 to DA4 is parallel to a plane defined by the first direction DR1 and the second direction DR2. A thickness direction of each of the display devices DV1 to DV4 may be defined as a normal direction of each of the display areas DA1 to DA4, for example, a third direction DR3 may indicate a thickness direction.

[0085] As an example, an image in which images displayed on each of the display devices DV1 to DV4 are merged may be displayed on the control unit MC, but the present disclosure is not limited thereto.

[0086] Each of the display devices DV1 to DV4 can display an image corresponding to its unique ID. For example, the control unit MC can divide the data corresponding to the first image IM1 to be displayed by the number of display devices DV1 to DV4, send a part to the first display device DV1, send another part to the second display device DV2, send another part to the third display device DV3, and send another part to the fourth display device DV4. The first display device DV1 can display a first sub-image IM21 corresponding to the transmitted data, the second display device DV2 can display a second sub-image IM22 corresponding to the transmitted data, the third display device DV3 can display a third sub-image IM23 corresponding to the transmitted data, and the fourth display device DV4 can display a fourth sub-image IM24 corresponding to the transmitted data.

[0087] The user can see each of the sub-images IM21 to IM24 displayed on the first to fourth display devices DV1 to DV4 and can recognize it as a new second image IM2 in which the first to fourth sub-images IM21 to IM24 are merged. For the user, the second image IM2 can be recognized as an image having a shape substantially the same as that of the first image IM1 and having a size different from that of the first image IM1.

[0088] Figure 2 1 is a control block diagram of a first display device according to an embodiment of the present disclosure. Since the description of the control block diagram of the first display device DV1 can be substantially identically applied to the second to fourth display devices DV2 to DV4, overlapping descriptions are omitted.

[0089] refer to Figure 2 , the first display device DV1 may include a broadcast tuner unit 210 , a signal processing unit 220 , a display unit 230 , a speaker 240 , a user input unit 250 , an HDD 260 , a network communication unit 270 , a UI generating unit 280 , and a control unit 290 .

[0090] The broadcast tuner unit 210 tunes a predetermined channel frequency under the control of the control unit 290 to be described later, receives a broadcast signal of a corresponding channel through an antenna, and includes a channel detection module (not shown) and an RF demodulation module (not shown).

[0091] The broadcast signal demodulated by the broadcast tuner unit 210 is processed by the signal processing unit 220 and output to the display unit 230 and the speaker 240. Here, the signal processing unit 220 may include a demultiplexer 221, a video decoder 222, a video processing unit 223, an audio decoder 224, and an additional data processing unit 225.

[0092] The demodulated broadcast signal is divided into a video signal, an audio signal and additional data by the demultiplexer 221. The divided video signal, audio signal and additional data are restored by the video decoder 222, the audio decoder 224 and the additional data processing unit 225, respectively. At this time, the video decoder 222, the audio decoder 224 and the additional data processing unit 225 are restored to a decoding format corresponding to the encoding format when the broadcast signal is transmitted.

[0093] Meanwhile, the decoded video signal is converted by the video processing unit 223 to adapt to a vertical frequency, a resolution, a screen ratio, etc. corresponding to an output standard of the display unit 230 , and the decoded audio signal is output to the speaker 240 .

[0094] The display unit 230 includes a panel (not shown) provided with a first display area DA1 on which an image is displayed, and a panel driving unit (not shown) which controls driving of the panel.

[0095] The user input unit 250 may receive a signal transmitted from the control unit MC. The user input unit 250 may be provided to allow a user to receive instructions related to communication with other display devices DV2 to DV4, and to input data for input and data related to selection of a channel transmitted through the control unit MC, selection and manipulation of a UI menu.

[0096] The HDD 260 stores various software programs including an OS program, recorded broadcast programs, moving pictures, photos, and other data, and may be implemented by another storage medium.

[0097] The network communication unit 270 is used for short-range communication with the control unit MC and other display devices DV2 to DV4 and may be implemented with a communication module including an antenna pattern that may implement mobile communication, data communication, Bluetooth, RF, Ethernet, and the like.

[0098] The network communication unit 270 can send and receive wireless signals with at least one of a base station, an external terminal and a server on a mobile communication network constructed according to a technical standard or communication method for mobile communication (for example, Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Code Division Multiple Access (CDMA2000), Enhanced Voice Data Optimization or Enhanced Voice Data Only (EV-DO), Wideband CDMA (WCDMA), High Speed ​​Downlink Packet Access (HSDPA), High Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), Advanced Long Term Evolution (LTE-A), 5G, etc.) through an antenna pattern to be described later.

[0099] In addition, the network communication unit 270 can send and receive wireless signals in a communication network according to wireless Internet technology through an antenna pattern to be described later. The wireless Internet technology may include, for example, wireless LAN (WLAN), wireless fidelity (Wi-Fi), wireless fidelity (Wi-Fi) direct connection, digital living network alliance (DLNA), wireless broadband access service (WiBro), world microwave access interoperability (WIMAX), high speed downlink packet access (HSDPA), high speed uplink packet access (HSUPA), long term evolution (LTE), advanced long term evolution (LTE-A), etc., and the antenna pattern sends and receives data according to at least one wireless Internet technology within the range including Internet technologies not listed above.

[0100] The UI generation unit 280 generates a UI menu for communicating with the control unit MC and other display devices DV2 to DV4, and can be implemented by an algorithm code and an OSD IC. The UI menu for communicating with the control unit MC and other display devices DV2 to DV4 is a menu for specifying a counterpart digital TV and selecting a desired function, and the UI menu according to an embodiment of the present disclosure may include "power on / off", "channel switching", "recent channels", "transmit channels", "quality settings", "audio settings", "data transmission", "data update", etc., but is not limited thereto.

[0101] The control unit 290 is responsible for the overall control of the first display device DV1, and is responsible for the communication control of the control unit MC and other display devices DV2 to DV4, and the corresponding algorithm code for control is stored, and the control unit 290 can be implemented by a microcontroller unit (MCU) in which the stored algorithm code is executed. The control unit 290 uses another digital TV within the communicable network to send the channel information and other data currently being watched. At this time, each digital TV sends and receives various data regardless of the power-on / power-off state, and sends the power-off state instead of the channel information in the case of the power-off state.

[0102] The control unit 290 controls according to the input and selection of the user input unit 250 to send corresponding control instructions and data to the control unit MC and other display devices DV2 to DV4 through the network communication unit 270. Of course, when predetermined control instructions and data are input from the control unit MC and other display devices DV2 to DV4, operations are performed according to the corresponding control instructions.

[0103] Hereinafter, elements constituting each of the display devices DV1 to DV4 are described based on the first display device DV1. Since the description of the elements of the first display device DV1 may be substantially identically applied to the second to fourth display devices DV2 to DV4, overlapping descriptions are omitted.

[0104] Figure 3 and Figure 4 are a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0105] exist Figure 3 and Figure 4 , a bar-shaped light emitting element LD having a cylindrical shape is shown, but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0106] refer to Figure 3 and Figure 4, the light emitting element LD may include a first conductive electrode layer 11, a second conductive electrode layer 13, and an active layer 12 disposed between the first conductive electrode layer 11 and the second conductive electrode layer 13. For example, the light emitting element LD may be configured as a stacked body in which the first conductive electrode layer 11, the active layer 12, and the second conductive electrode layer 13 are sequentially stacked in one direction.

[0107] According to the embodiment, the light emitting element LD may be provided in a stripe shape extending in one direction. The light emitting element LD may have one side end and another side end along the one direction.

[0108] According to an embodiment, one of the first conductive electrode layer 11 and the second conductive electrode layer 13 may be disposed at one side end of the light emitting element LD, and the remaining one of the first conductive electrode layer 11 and the second conductive electrode layer 13 may be disposed at the other side end of the light emitting element LD.

[0109] According to an embodiment, the light emitting element LD may be a strip-shaped light emitting diode manufactured in a strip shape. Here, the strip shape includes a rod-like shape or a strip-like shape that is longer in the longitudinal direction than in the width direction (i.e., having an aspect ratio greater than 1), such as a cylinder or a polygonal column, and the shape of its cross section is not particularly limited. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of the cross section).

[0110] According to an embodiment, the light emitting element LD may have a diameter D and / or a length L as small as nanometer level to micrometer level (e.g., a range of several hundred nanometer level to several micrometer level). However, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be variously changed according to the design conditions of various devices using a light emitting device (e.g., display devices DV1 to DV4) using the light emitting element LD as a light emitting unit.

[0111] The first conductive electrode layer 11 may include at least one n-type semiconductor material. For example, the first conductive electrode layer 11 may include one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor layer doped with a first conductive dopant such as Si, Ge, or Sn. However, the material constituting the first conductive electrode layer 11 is not limited thereto, and various materials other than the materials described above may constitute the first conductive electrode layer 11.

[0112] The active layer 12 may be disposed on the first conductive electrode layer 11, and may be formed in a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. According to an embodiment, the active layer 12 may be formed using materials such as AlGaN, AlInGaN, and the like, and various materials other than the materials described above may constitute the active layer 12.

[0113] When a voltage equal to or greater than a threshold voltage is applied to both ends of the light emitting element LD, the light emitting element LD may emit light while electron-hole pairs are recombined in the active layer 12. By controlling light emission of the light emitting element LD using this principle, the light emitting element LD may be used as a light emitting unit of various light emitting devices including pixels of the display devices DV1 to DV4.

[0114] The second conductive electrode layer 13 may be disposed on the active layer 12, and may include a semiconductor material of a type different from that of the first conductive electrode layer 11. For example, the second conductive electrode layer 13 may include at least one p-type semiconductor layer. For example, the second conductive electrode layer 13 may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor material doped with a second conductive dopant such as Mg. However, the material constituting the second conductive electrode layer 13 is not limited thereto, and various materials other than the materials described above may constitute the second conductive electrode layer 13.

[0115] According to an embodiment, the light emitting element LD may further include an insulating film INF disposed on the surface. The insulating film INF may be formed on the surface of the light emitting element LD so as to surround at least the outer peripheral surface of the active layer 12, and may also surround a region of the first conductive electrode layer 11 and the second conductive electrode layer 13. However, the insulating film INF may expose both ends of the light emitting element LD having different polarities. For example, the insulating film INF may not cover and expose one end of each of the first conductive electrode layer 11 and the second conductive electrode layer 13 located at both ends of the light emitting element LD in the longitudinal direction, for example, two planes (i.e., the upper surface and the lower surface) of a cylinder.

[0116] According to an embodiment, the insulating film INF may include silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ) and titanium dioxide (TiO 2) at least one insulating material, but is not limited thereto. That is, the constituent material of the insulating film INF is not particularly limited, and the insulating film INF can be composed of various insulating materials currently known.

[0117] In an embodiment, in addition to the first conductive electrode layer 11, the active layer 12, the second conductive electrode layer 13 and / or the insulating film INF, the light emitting element LD may further include additional components. For example, the light emitting element LD may further include at least one phosphor layer, an active layer, a semiconductor material and / or an electrode layer disposed on one end side of the first conductive electrode layer 11, the active layer 12 and / or the second conductive electrode layer 13.

[0118] Figure 5 and Figure 6 are a perspective view and a cross-sectional view illustrating a light emitting element according to another embodiment of the present disclosure. Figure 7 and Figure 8 are a perspective view and a cross-sectional view showing a light emitting element according to still another embodiment of the present disclosure.

[0119] refer to Figure 5 and Figure 6 The light emitting element LD may further include at least one electrode layer 14 disposed on one end side of the second conductive electrode layer 13 .

[0120] refer to Figure 7 and Figure 8 The light emitting element LD may further include at least another electrode layer 15 provided on one end side of the first conductive electrode layer 11 .

[0121] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal or a conductive metal oxide, for example, each of the electrode layers 14 and 15 may be formed of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, transparent electrode materials (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO) alone or in combination). The electrode layers 14 and 15 may be substantially transparent or translucent. Therefore, the light generated in the light emitting element LD may pass through the electrode layers 14 and 15 and may be emitted to the outside of the light emitting element LD.

[0122] According to an embodiment, the insulating film INF may or may not at least partially surround the outer peripheral surface of the electrode layers 14 and 15. That is, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose both ends of the light emitting element LD having different polarities, for example, the insulating film INF may expose at least one region of the electrode layers 14 and 15. However, the present disclosure is not limited thereto, and the insulating film INF may not be provided.

[0123] Since the insulating film INF is provided on the surface of the light emitting element LD (e.g., the surface of the active layer 12), the active layer 12 can be prevented from being short-circuited with at least one electrode (e.g., at least one contact electrode among the contact electrodes connected to both ends of the light emitting element LD). Therefore, the electrical stability of the light emitting element LD can be ensured.

[0124] In addition, since the insulating film INF is formed on the surface of the light emitting element LD, surface defects of the light emitting element LD can be minimized, and the life and efficiency of the light emitting element LD can be improved. In addition, since the insulating film INF is formed on the surface of the light emitting element LD, even if a plurality of light emitting elements LD are closely arranged, an undesirable short circuit between the light emitting elements LD can be prevented.

[0125] In an embodiment, the light emitting element LD may be manufactured by a surface treatment process (e.g., coating). For example, when a plurality of light emitting elements LD are mixed in a fluid solution (or solvent) and supplied to each emission region (e.g., the emission region of each pixel), the light emitting element LD may be uniformly dispersed in the solution and unevenly aggregated. Here, the emission region is an area where light is emitted by the light emitting element LD and can be distinguished from a non-emission region that does not emit light.

[0126] According to an embodiment, the insulating film INF itself may be formed as a hydrophobic film using a hydrophobic material, or a hydrophobic film formed of a hydrophobic material may be additionally formed on the insulating film INF. According to an embodiment, the hydrophobic material may be a fluorine-containing material to exhibit hydrophobicity. In addition, according to an embodiment, the hydrophobic material may be applied to the light-emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. In addition, the hydrophobic material may be a commercially available material such as Teflon. TM or Cytop TM Fluorine-containing material or a corresponding material.

[0127] The light-emitting device including the light-emitting element LD can be used in various types of devices that require a light-emitting unit and include the display devices DV1 to DV4 according to the present embodiment. For example, at least one ultra-small light-emitting element LD, for example, a plurality of ultra-small light-emitting elements LD each having a size from nanometer level to micrometer level can be arranged in each pixel region in the display devices DV1 to DV4, and the light-emitting unit of each pixel can be constituted using the ultra-small light-emitting element LD. However, the application field of the light-emitting element LD is not limited to the display devices DV1 to DV4 in the present disclosure. For example, the light-emitting element LD can be used in other types of devices such as lighting devices that require a light source.

[0128] Fig. 9 is a plan view showing a first display device according to an embodiment of the present disclosure. According to the embodiment, Fig. 9 Shows that you can use Figures 3 to 8 The light emitting element LD described in the first display device DV1 is used as a light emitting unit.

[0129] The first display device DV1 may include a base layer SUB1 (or substrate) and pixels PXL disposed on the base layer SUB1. Specifically, as described above, the first display device DV1 and the base layer SUB1 may include a first display area DA1 in which an image is displayed and a first non-display area NDA1 other than the first display area DA1. That is, the first display area DA1 and the first non-display area NDA1 may be defined in the base layer SUB1.

[0130] As an embodiment, the first display area DA1 may include a first sub-display area DA11 in which an antenna pattern is disposed and a second sub-display area DA12 in which no antenna pattern is disposed. For example, the second sub-display area DA12 may include a touch electrode pattern for sensing a user's touch input and / or a piezoelectric sensor pattern for sensing a user's press. However, the present disclosure is not limited thereto, and according to an embodiment, the first display area DA1 may be formed only of the first sub-display area DA11 in which an antenna pattern is disposed.

[0131] As an embodiment, the first sub display area DA11 may be located at an edge of the first display area DA1, and the second sub display area DA12 may be located inside the first sub display area DA11.

[0132] The base layer SUB1 may constitute a base member of the first display device DV1. For example, the base layer SUB1 may constitute a base member of a lower panel (eg, a lower plate of the display device DV1).

[0133] According to an embodiment, the base layer SUB1 may be a rigid substrate or a flexible substrate, and the material or physical properties of the base layer SUB1 are not particularly limited. For example, the base layer SUB1 may be a rigid substrate composed of glass or tempered glass, or a flexible substrate composed of a thin film of a plastic or metal material. In addition, the base layer SUB1 may be a transparent substrate, but is not limited thereto. For example, the base layer SUB1 may be a translucent substrate, an opaque substrate, or a reflective substrate. As an example, the present embodiment describes that the base layer SUB1 is a flexible substrate.

[0134] One area of ​​the base layer SUB1 is defined as a first display area DA1 and the pixels PXL are disposed, and the remaining area is defined as a first non-display area NDA1. For example, the base layer SUB1 may include: a first display area DA1 including a plurality of emission areas in which the pixels PXL are formed; and a first non-display area NDA1 disposed outside the first display area DA1. Various lines and / or built-in circuits connected to the pixels PXL of the first display area DA1 may be disposed in the first non-display area NDA1.

[0135] The pixel PXL may include at least one light emitting element LD driven by corresponding scan signals and data signals, for example, according to Figures 3 to 8 At least one strip-shaped light emitting diode of any one of the embodiments of the present invention. For example, the pixel PXL may include a plurality of strip-shaped light emitting diodes having a size as small as nanometer to micrometer and connected in parallel to each other. The plurality of strip-shaped light emitting diodes may constitute a light emitting unit of the pixel PXL.

[0136] In addition, the pixel PXL may include a plurality of sub-pixels. For example, the pixel PXL may include a first sub-pixel SPX11, a second sub-pixel SPX12, a third sub-pixel SPX13, a fourth sub-pixel SPX21, a fifth sub-pixel SPX22, and a sixth sub-pixel SPX23. The plurality of sub-pixels may be arranged in a matrix form. For example, the first sub-pixel SPX11 may be arranged in the first row and the first column, the second sub-pixel SPX12 may be arranged in the first row and the second column, the third sub-pixel SPX13 may be arranged in the first row and the third column, the fourth sub-pixel SPX21 may be arranged in the second row and the first column, the fifth sub-pixel SPX22 may be arranged in the second row and the second column, and the sixth sub-pixel SPX23 may be arranged in the second row and the third column. Here, the column direction may be indicated by the first direction DR1, and the row direction may be indicated by the second direction DR2.

[0137] As an embodiment, the first subpixel SPX11, the second subpixel SPX12, the third subpixel SPX13, and the fourth subpixel SPX21 may be located in the first sub-display area DA11. The fifth subpixel SPX22 and the sixth subpixel SPX23 may be located in the second sub-display area DA12. The antenna pattern may be provided in the first subpixel SPX11, the second subpixel SPX12, the third subpixel SPX13, and the fourth subpixel SPX21 located in the first sub-display area DA11. The antenna pattern may not be provided, and the touch electrode pattern and / or the piezoelectric sensor pattern may be provided in the fifth subpixel SPX22 and the sixth subpixel SPX23 located in the second sub-display area DA12.

[0138] According to an embodiment, the first sub-pixel SPX11 to the sixth sub-pixel SPX23 may emit light of the same or different colors. For example, the first sub-pixel SPX11 and the fourth sub-pixel SPX21 may be red sub-pixels that emit red light, the second sub-pixel SPX12 and the fifth sub-pixel SPX22 may be green sub-pixels that emit green light, and the third sub-pixel SPX13 and the sixth sub-pixel SPX23 may be blue sub-pixels that emit blue light. However, the color, type, number, etc. of the sub-pixels constituting the pixel PXL are not particularly limited, for example, the color of the light emitted by each of the sub-pixels may be variously changed. In addition, although Fig. 9 An embodiment in which the pixels PXL are arranged in a matrix form in the first display area DA1 is shown, but the present disclosure is not limited thereto. For example, the pixels PXL may be provided in various currently known pixel arrangement shapes.

[0139] Fig.10 is with Fig. 9 A schematic cross-sectional view of the first display device corresponding to line I1-I1'.

[0140] refer to Fig.10 , the display substrate SUB_DA is a flexible substrate and may be formed of a plastic material or a metal foil. That is, since the display substrate SUB_DA is formed of a flexible material, the display substrate SUB_DA may be bent as shown.

[0141] For example, the display substrate SUB_DA of plastic material may include any one of polyimide (PI), polycarbonate (PC), polynorbornene (PNB), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). A first display area DA1 including a first sub-display area DA11 and a second sub-display area DA12 and a first non-display area NDA1 may be defined in the display substrate SUB_DA.

[0142] A plurality of transistors and light emitting elements may be disposed in the first display area DA1 of the display substrate SUB_DA. A description of the plurality of transistors and light emitting elements is described later. At least a portion of the first non-display area NDA1 of the display substrate SUB_DA may be a bending area BA, and a pad (not shown) may be disposed in the first non-display area NDA1 of the display substrate SUB_DA.

[0143] In the display substrate SUB_DA, two areas divided by a curved shape based on the curved area BA may face each other. The two areas may overlap each other. In this specification, unless otherwise specified, the expression "overlap" means that two structures overlap in the thickness direction (third direction DR3) of the first display device DV1.

[0144] Therefore, the antenna pattern ANTE, the touch electrode pattern TS, the piezoelectric sensor pattern FS and the driving integrated circuit DIC can all be set on the display substrate SUB_DA, but based on the cross-section of the first display device DV1, the antenna pattern ANTE, the touch electrode pattern TS and the piezoelectric sensor pattern FS can be located on the display substrate SUB_DA, and the driving integrated circuit DIC can be located under the display substrate SUB_DA.

[0145] Although not clearly shown, the antenna pattern ANTE may be connected to a corresponding feeder line through a contact hole. Therefore, the antenna pattern ANTE may be connected to an RF driving unit or the like provided on the first flexible circuit board FPC1 through a feeder line. Therefore, the antenna pattern ANTE may be used as a patch antenna for mobile communication or as an antenna for an RFID tag for short-range communication.

[0146] The buffer member ADH may be disposed between the curved display substrate SUB_DA. The buffer member ADH may be formed of various materials having a buffer. For example, the buffer member ADH may be formed of latex, sponge, polyurethane foam as a foamable resin, EVA, silicone resin, etc. In addition, the buffer member ADH may be formed in a belt shape having a buffer. In addition, the buffer member ADH may be an adhesive member.

[0147] The first protection film PF1 and the second protection film PF2 may be disposed between the buffer member ADH and the display substrate SUB_DA. For example, the first protection film PF1 may be disposed between the buffer member ADH and a relatively upper region of the display substrate SUB_DA, and the second protection film PF2 may be disposed between the buffer member ADH and another relatively lower region of the display substrate SUB_DA.

[0148] Each of the first protection film PF1 and the second protection film PF2 may be formed of a plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), and polyethersulfone (PES), but is not limited thereto. The first protection film PF1 and the second protection film PF2 are disposed to completely cover the rear surface of the display substrate SUB_DA. However, in order to reduce the bending stress of the bending area BA, they may not be disposed on the rear surface of the portion forming the bending area BA.

[0149] The antenna pattern ANTE, the touch electrode pattern TS and / or the piezoelectric sensor pattern FS may be disposed in the first display area DA1 of the display substrate SUB_DA. As an embodiment, the antenna pattern ANTE, the touch electrode pattern TS and / or the piezoelectric sensor pattern FS may be simultaneously formed by the same process.

[0150] The encapsulation layer TFE may be disposed on the antenna pattern ANTE, the touch electrode pattern TS and / or the piezoelectric sensor pattern FS. The encapsulation layer TFE may be formed to cover the antenna pattern ANTE, the touch electrode pattern TS and / or the piezoelectric sensor pattern FS, the transistor and the light emitting element to protect them from external moisture or air.

[0151] The polarizing layer POL may be disposed on the encapsulation layer TFE. The polarizing layer POL may overlap the encapsulation layer TFE.

[0152] The polarization layer POL may transmit light parallel to the polarization axis in one direction among the light output from the light emitting element. In addition, the polarization layer POL may reduce external light reflection. The polarization layer POL may be a coating type polarization layer POL or a polarization layer POL formed by deposition. The polarization layer POL may be formed by coating a material including a dichroic dye and a liquid crystal compound.

[0153] The bending stress relief member BFL may be disposed on the bending area BA of the display substrate SUB_DA. The bending stress relief member BFL may reduce bending stress of the substrate generated in the bending area BA.

[0154] The bending stress relief member BFL may include an adhesive formed of a resin. Since the bending stress relief member BFL is cured in a state in which the bending stress relief member BFL is attached to the outer surface of the bending area BA, the shape of the curved substrate can be more stably maintained. The bending stress relief member BFL may be formed of a thermosetting resin, an ultraviolet curable resin, or the like.

[0155] The driving integrated circuit DIC may be disposed on a region of the display substrate SUB_DA in a relatively lower portion. The driving integrated circuit DIC is mounted on the display substrate SUB_DA through a chip bonding process or a surface mounting process and bonded to a plurality of signal supply terminals and a plurality of signal input terminals.

[0156] The driving integrated circuit DIC generates data signals and gate signals based on image data and timing synchronization signals supplied from the outside through multiple signal input terminals, and supplies the generated data signals and gate signals to corresponding signal supply terminals to drive each pixel PXL, thereby displaying a first sub-image IM21 corresponding to the image data in the first display area DA1.

[0157] The first flexible circuit board FPC1 may be disposed on another area of ​​the display substrate SUB_DA located in a relatively lower portion. A flexible printed circuit (FPC) may be applied to the first flexible circuit board FPC1, and a driving element for supplying image data and a timing synchronization signal input from the outside to the driving integrated circuit DIC may be formed in a surface mounting method, and a protective cover for protecting the driving element may be formed.

[0158] The driving integrated circuit DIC may be electrically connected to the battery BAT. As an embodiment, the battery BAT may be disposed on the driving integrated circuit DIC, but is not limited to the disposition position. That is, the battery BAT may be located in a portion lower than the driving integrated circuit DIC.

[0159] The battery BAT may supply power required to drive the first display device DV1. The battery BAT may be charged by external power.

[0160] The battery BAT may be electrically connected to the first antenna member WPT 1. As an embodiment, the first antenna member WPT 1 may correspond to a wireless power transfer (hereinafter referred to as WPT) antenna for wireless charging.

[0161] The first antenna member WPT1 may be located in a portion lower than the battery BAT.

[0162] The second flexible circuit board FPC2 may be disposed on the first antenna member WPT1. A flexible printed circuit (FPC) may be applied to the second flexible circuit board FPC2, a wiring for supplying a power signal may be formed in a surface mounting method, and a protection cover for protecting the wiring may be formed.

[0163] The connection member CN may be provided between the battery BAT and the first antenna member WPT1. The connection member CN may be a flexible printed circuit (FPC) or a chip on film (COF).

[0164] Although not clearly shown, the connection member CN may be connected between the upper surface of the display substrate SUB_DA, the battery BAT, and the first antenna member WPT1.

[0165] The second antenna member WPT2 may be disposed on the connection member CN. The second antenna member WPT2 may be disposed on the connection member CN such that an upper surface of the second antenna member WPT2 faces a side surface of the first display device DV1.

[0166] The second antenna member WPT2 may be one of a WPT antenna, a magnetic secure transmission (MST) antenna, a near field communication (NFC) antenna, and an RFID antenna for wireless charging, or may be a 3-in-1 (3-combo) antenna in which a WPT antenna, an MST antenna, and an NFC antenna are formed in combination. Here, when the second antenna member WPT2 is a WPT antenna, the frequency band may be 100kHz to 300kHz, and when the second antenna member WPT2 is an NFC antenna, the frequency band may be 10MHz to 20MHz.

[0167] The window member WD may be disposed on the first display device DV1 and may be located on the polarization layer POL. For example, the window member WD may be formed of glass, sapphire, plastic, etc. The window member WD may overlap both the first display area DA1 and the first non-display area NDA1 defined above.

[0168] In addition, although the window member WD is shown as a single layer, the window member WD may include a plurality of layers.

[0169] The black matrix BM may be disposed on the rear surface of the window member WD to overlap the first non-display area NDA1. The black matrix BM may include a light absorbing material or a light reflecting material. For example, the black matrix BM may include a black resin or a reflective metal such as chrome (Cr).

[0170] The black matrix BM may be positioned adjacent to the polarization layer POL.

[0171] The case member FU may mount the above-described members, and may be coupled to the window member WD.

[0172] When the case member FU and the window member WD are combined, the first buffer member BF1 may be disposed between the black matrix BM and the case member FU in order to reduce a step difference or facilitate combining.

[0173] In some embodiments, the second buffer member BF2 may be disposed between the battery BAT, the first antenna member WPT1, and the second flexible circuit board FPC2. As an embodiment, the first buffer member BFL and the second buffer member BF2 may include resin.

[0174] Fig.11It is shown that the Fig. 9 A circuit diagram of an example of a sub-pixel in a first display device. Fig.11 Shown included in Fig. 9 The first sub-pixel SPX11 to the sixth sub-pixel SPX23 in the first display device DV1.

[0175] refer to Fig.11 , as an embodiment, each of the sub-pixels SPX11 to SPX23 may include a plurality of unit pixels SSPX11 , SSPX12 , and SSPX13 .

[0176] Since the first subpixel SPX11 to the sixth subpixel SPX23 are substantially identical to one another except that they are respectively connected to the corresponding data lines Dj, Dj+1 and Dj+2 and the corresponding scan lines Si and Si+1, the first subpixel SPX11 to the sixth subpixel SPX23 are described inclusively based on the first subpixel SPX11.

[0177] The first subpixel SPX11 to the sixth subpixel SPX23 may be arranged in regions separated by scan lines Si-1, Si and Si+1 (where i is a positive integer) and data lines Dj, Dj+1 and Dj+2 (where j is a positive integer), respectively. For example, the first subpixel SPX11 may be arranged in a region separated by the (i-1)th scan line Si-1 and the i-th scan line Si and the j-th data line Dj and the (j+1)th data line Dj+1. However, the arrangement of the first subpixel SPX11 to the sixth subpixel SPX23 is not limited thereto.

[0178] The first sub-pixel SPX11 may be connected to the scan line Si and the data line Dj, and may also be connected to a first power line and a second power line. Here, a first power source VDD may be applied to the first power line, a second power source VSS may be applied to the second power line, and each of the first power line and the second power line may be a common line connected to a plurality of sub-pixels. The first power source VDD and the second power source VSS may have different potentials so that the first sub-pixel SPX11 emits light, and the first power source VDD may have a voltage level higher than that of the second power source VSS.

[0179] As an embodiment, the first subpixel SPX11 may include at least one unit pixel SSPX1 to SSPXk (where k is a positive integer).

[0180] Each of the unit pixels SSPX1 to SSPXk may be connected to a scan line Si and a data line Dj, and may also be connected to a first power line and a second power line. Each of the unit pixels SSPX1 to SSPXk may emit light having a brightness corresponding to a data signal transmitted through the data line Dj in response to a scan signal transmitted through the scan line Si. The unit pixels SSPX1 to SSPXk may include substantially the same pixel structure or pixel circuit.

[0181] That is, the first subpixel SPX11 may include unit pixels SSPX1 to SSPXk that independently emit light in response to one scan signal and one data signal.

[0182] As an embodiment, each of the unit pixels SSPX1 to SSPXk (or sub-pixels SPX11 to SPX23) may be configured as an active pixel. However, the type, structure and / or driving method of the unit pixel applicable to the first display device DV1 of the present disclosure are not particularly limited. For example, the unit pixel may be configured as a pixel of the first display device DV1 having various currently known passive or active structures.

[0183] Figures 12 to 18 It is shown that it can be applied to include Fig.11 A circuit diagram of an example of a unit pixel in a sub-pixel.

[0184] The description is based on one unit pixel in each drawing, and similar contents can be applied to Fig.12 The first unit pixel SSPX1 to the kth unit pixel SSPXk shown in FIG. 1 are shown in FIG. 1 , and thus similar contents are omitted. That is, Fig.11 The first to k-th unit pixels SSPX1 to SSPXk shown in FIG. 1 may have substantially the same or similar structures. Figures 12 to 18 The first unit pixel SSPX1 shown in FIG. 1 may be an example and may be applied to Fig.11 Any one of the first to k-th unit pixels SSPX1 to SSPXk.

[0185] First, refer to Fig.12 , the first unit pixel SSPX1 may include a light source unit LSU that emits light having brightness corresponding to the data signal. In addition, the first unit pixel SSPX1 may further selectively include a pixel circuit PXC for driving the light source unit LSU.

[0186] According to an embodiment, the light source unit LSU may include a plurality of light emitting elements LD electrically connected between a first power source VDD and a second power source VSS. In an embodiment, the light emitting elements LD may be connected to each other in a parallel structure, but are not limited thereto. For example, the plurality of light emitting elements LD may be connected between the first power source VDD and the second power source VSS in a parallel structure.

[0187] The first power supply VDD and the second power supply VSS may have different potentials so that the light emitting element LD can emit light. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. Here, during the emission period of the first unit pixel SSPX1 (or the first sub-pixel SPX11), the potential difference between the first power supply VDD and the second power supply VSS may be set to be equal to or greater than the threshold voltage of the light emitting element LD.

[0188] At the same time, despite Fig.12 An embodiment in which the light emitting elements LD are connected in parallel with each other in the same direction (e.g., the forward direction) between the first power supply VDD and the second power supply VSS is shown, but the present disclosure is not limited thereto. For example, some of the light emitting elements LD may be connected in the forward direction between the first power supply VDD and the second power supply VSS to form a corresponding effective light source, and another part may be connected in the reverse direction. As another example, the first unit pixel SSPX1 may include only a single light emitting element LD (e.g., a single effective light source connected in the forward direction between the first power supply VDD and the second power supply VSS).

[0189] According to an embodiment, one end of each of the light emitting elements LD may be commonly connected to the corresponding pixel circuit PXC through the first electrode, and may be connected to the first power supply VDD through the pixel circuit PXC and the first power supply line. The other end of each of the light emitting elements LD may be commonly connected to the second power supply VSS through the second electrode and the second power supply line.

[0190] The light source unit LSU may emit light having a brightness corresponding to the driving current supplied through the corresponding pixel circuit PXC. Thus, a predetermined image may be displayed in the first display area DA1 (refer to Figure 1 and Fig. 9 ).

[0191] The pixel circuit PXC can be connected to the scan line Si and the data line Dj of the corresponding sub-pixel (i.e., the first sub-pixel SPX11). For example, when the first sub-pixel SPX11 is arranged in the i-th row and j-th column of the first display area DA1, the pixel circuit PXC of the unit pixel SSPX can be connected to the i-th scan line Si and the j-th data line Dj of the first display area DA1.

[0192] The pixel circuit PXC may include first and second transistors T1 and T2 and a storage capacitor Cst.

[0193] The first transistor T1 (or driving transistor) may be connected between the first power source VDD and the light source unit LSU. A gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control a driving current supplied to the light source unit LSU in response to a voltage of the first node N1.

[0194] The second transistor T2 (or the switching transistor) may be connected between the data line Dj and the first node N1. A gate electrode of the second transistor T2 may be connected to the scan line Si.

[0195] The second transistor T2 may be turned on in response to a scan signal of a gate-on voltage (eg, a low voltage) from the scan line Si to electrically connect the data line Dj and the first node N1 to each other.

[0196] A data signal of a corresponding frame may be supplied to the data line Dj for each frame period, and the data signal may be transmitted to the first node N1 via the second transistor T2. Therefore, a voltage corresponding to the data signal may be charged in the storage capacitor Cst.

[0197] One electrode of the storage capacitor Cst may be connected to the first power source VDD and the other electrode may be connected to the first node N1. The storage capacitor Cst may charge a voltage corresponding to a data signal supplied to the first node N1 during each frame period and maintain the charged voltage until a data signal of a next frame is supplied.

[0198] At the same time, Fig.12 , the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are shown as P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0199] For example, Fig.13 As shown in FIG. 1 , both the first transistor T1 and the second transistor T2 may be N-type transistors. In this case, the gate-on voltage of the scanning signal for writing the data signal supplied to the data line Dj into the first unit pixel SSPX1_1 during each frame period may be a high-level voltage. Similarly, the voltage of the data signal for turning on the first transistor T1 may be a voltage of Fig.12 The waveform of the embodiment is opposite to the waveform of the voltage. For example, in Fig.13 In the embodiment, as the grayscale value to be expressed increases, a data signal having a higher voltage level may be supplied.

[0200] In addition to the connection positions of some circuit elements and the voltage levels of control signals (e.g., scan signals and data signals) being changed according to the transistor types, Fig.13 The configuration and operation of the first unit pixel SSPX1_1 shown in FIG. 1 are substantially the same as those of FIG. Fig.12 The configuration and operation of the first unit pixel SSPX1 are similar. Therefore, the Fig.13 Detailed description of the first unit pixel SSPX1_1.

[0201] Meanwhile, the structure of the pixel circuit PXC is not limited to Fig.12 and Fig.13 That is, the pixel circuit PXC can be constructed as a pixel circuit of various currently known structures and / or driving methods. For example, the pixel circuit PXC can be as follows Fig.14 The embodiment shown in FIG.

[0202] refer to Fig.14 , in addition to the corresponding scan line Si, the pixel circuit PXC in the first unit pixel SSPX1_2 can also be connected to at least another scan line (or control line). For example, the pixel circuit PXC of the sub-pixel SPX (or the unit pixel SSPX included therein) arranged in the i-th row of the first display area DA1 can also be connected to the (i-1)th scan line Si-1 and / or the (i+1)th scan line Si+1. In addition, according to an embodiment, the pixel circuit PXC can also be connected to another power supply other than the first power supply VDD and the second power supply VSS. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint.

[0203] According to an embodiment, the pixel circuit PXC may include seven transistors T1 to T7. The pixel circuit PXC may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0204] The first transistor T1 may be connected between the first power supply VDD and the light source unit LSU. One electrode (e.g., source electrode) of the first transistor T1 may be connected to the first power supply VDD through the fifth transistor T5, and the other electrode (e.g., drain electrode) of the first transistor T1 may be connected to one electrode of the light source unit LSU (e.g., first electrode of the corresponding sub-pixel SPX) via the sixth transistor T6. The gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control the driving current supplied to the light source unit LSU in response to the voltage of the first node N1.

[0205] The second transistor T2 may be connected between the data line Dj and the one electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the corresponding scan line Si. The second transistor T2 may be turned on when a scan signal of a gate-on voltage is supplied from the scan line Si to electrically connect the data line Dj and the one electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the data line Dj may be transmitted to the first transistor T1.

[0206] The third transistor T3 may be connected between the other electrode (e.g., drain electrode) of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be connected to the corresponding scan line Si. The third transistor T3 may be turned on when a scan signal of a gate-on voltage is supplied from the scan line Si to connect the first transistor T1 in a diode form.

[0207] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be connected to a previous scan line, for example, the (i-1)th scan line Si-1. The fourth transistor T4 may be turned on when a scan signal of a gate-on voltage is supplied to the (i-1)th scan line Si-1 to transfer the voltage of the initialization power supply Vint to the first node N1. Here, the voltage of the initialization power supply Vint may be equal to or less than the lowest voltage of the data signal.

[0208] The fifth transistor T5 may be connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 may be connected to a corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal of a gate-off voltage (for example, a high voltage) is supplied to the emission control line Ei, and may be turned on in other cases.

[0209] The sixth transistor T6 may be connected between the first transistor T1 and the first electrode of the light source unit LSU. The gate electrode of the sixth transistor T6 may be connected to a corresponding emission control line, for example, the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal of a gate-off voltage is supplied to the emission control line Ei, and may be turned on in other cases.

[0210] The seventh transistor T7 may be connected between the first electrode of the light source unit LSU and the initialization power supply Vint (or a third power supply line that transmits the initialization power supply). The gate electrode of the seventh transistor T7 may be connected to any one of the next scan lines, for example, the (i+1)th scan line Si+1. The seventh transistor T7 may be turned on when a scan signal of a gate-on voltage is supplied to the (i+1)th scan line Si+1 to supply the voltage of the initialization power supply Vint to the first electrode of the light source unit LSU. In this case, the voltage of the first electrode of the light source unit LSU may be initialized during each initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU.

[0211] The control signal for controlling the operation of the seventh transistor T7 may be variously changed. For example, the gate electrode of the seventh transistor T7 may be connected to the scan line of the corresponding horizontal line, that is, the i-th scan line Si. In this case, the seventh transistor T7 may be turned on when the scan signal of the gate-on voltage is supplied to the i-th scan line Si to supply the voltage of the initialization power supply Vint to one electrode of the light source unit LSU.

[0212] The storage capacitor Cst may be connected between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal supplied to the first node N1 and a threshold voltage of the first transistor T1 in each frame period.

[0213] At the same time, Fig.14 , all transistors (eg, first to seventh transistors T1 to T7) included in the pixel circuit PXC are shown as P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0214] According to an embodiment, the pixel circuit PXC may also be connected to a line other than the data line Dj.

[0215] refer to Fig.15 , the pixel circuit PXC in the first unit pixel SSPX1_3 may be connected to the sensing line SENj. The pixel circuit PXC may include first to third transistors T1 to T3 and a storage capacitor Cst. Since the first transistor T1 and the second transistor T2 and the storage capacitor Cst are respectively connected to the reference Fig.13 The described first and second transistors T1 and T2 and the storage capacitor Cst are substantially the same or similar, and thus overlapping descriptions are not repeated.

[0216] The third transistor T3 may be connected between the sensing line SENj and the second node N2. A gate electrode of the third transistor T3 may be connected to a second scan line S2 different from the first scan line S1 (eg, an (i+1)th scan line Si+1 different from the i-th scan line Si).

[0217] The light source unit LSU may be connected between the second node N2 and a second power line (ie, a power line to which the second power source VSS is applied).

[0218] The third transistor T3 may be turned on in response to a scan signal of a gate-on voltage transmitted from the second scan line S2 to electrically connect the sensing line SENj and the second node N2 .

[0219] For example, when the third transistor T3 is turned on in a state in which a driving current corresponding to a reference voltage flows through the first transistor T1, the driving current flowing through the first transistor T1 can be supplied to an external sensing device through the third transistor T3 and the sensing line SENj, and a signal corresponding to a characteristic (e.g., Vth) of the first transistor T1 can be output to the outside based on the driving current through the sensing line SENj.

[0220] refer to Fig.16 , the pixel circuit PXC in the first unit pixel SSPX1_4 may be connected to an initialization voltage line to which an initialization power source Vint is supplied. The pixel circuit PXC may include first to fourth transistors T1 to T4 and a storage capacitor Cst. Since the first to fourth transistors T1 to T4 and the storage capacitor Cst are respectively connected to the reference Fig.12 The first transistor T1 and the second transistor T2 described in reference Fig.14 The seventh transistor T7 and the sixth transistor T6 and the storage capacitor Cst are described to be substantially the same or similar, and thus overlapping descriptions are not repeated.

[0221] refer to Fig.17 , the first unit pixel SSPX1_5 can be connected with Fig.16 The first unit pixel SSPX1_4 is similarly applied, and the second transistor T2 may be an N-type transistor.

[0222] refer to Fig.18 , the first unit pixel SSPX1_6 can be connected with Fig.16 The first unit pixel SSPX1_4 is similarly applied, the second transistor T2 can be an N-type transistor, and the fourth transistor T4 can be connected to the reference Fig.14 The fifth transistor T5 described is used identically or similarly.

[0223] In addition, the structure of the first unit pixel SSPX1 applicable to the present disclosure is not limited to Figures 12 to 18, and the first unit pixel SSPX1 may have various currently known structures. For example, the pixel circuit PXC included in the first unit pixel SSPX1 may be configured as a pixel circuit having various currently known structures and / or driving methods. In addition, the first unit pixel SSPX1 may be configured as in a passive light emitting panel or the like. In this case, the pixel circuit PXC may be omitted, and each of the first electrode and the second electrode of the light source unit LSU may be directly connected to the scan line Si, the data line Dj, the power line, the control line, etc.

[0224] Fig.19 It is schematically shown that the Fig. 9 A plan layout diagram of a sub-pixel arrangement in a first display device. Fig. 20 It is schematically shown that the Fig. 9 A plan layout diagram of the arrangement of another sub-pixel in the first display device. Fig.19 The second sub-pixel SPX12 is shown among the sub-pixels arranged in the first sub-display area DA11. Fig. 20 A fifth sub-pixel SPX22 among the sub-pixels disposed in the second sub display area DA12 is illustrated.

[0225] exist Fig.19 and Fig. 20 In the example, based on the light source unit LSU (reference Figures 12 to 18 ) (or light emitting element layer), the structure of the unit pixels SSPX1 to SSPX3 is shown. Since the first to third unit pixels SSPX1 to SSPX3 are substantially the same as each other, the light source unit LSU is described based on the first unit pixel SSPX1.

[0226] refer to Fig.19 The first unit pixel SSPX1 of the second subpixel SPX12 may include first and second electrodes ETL1, ETL21, ETL22, and ETL23 disposed to be spaced apart from each other and at least one light emitting element LD connected between the first and second electrodes ETL1, ETL21, ETL22, and ETL23.

[0227] According to an embodiment, the light emitting elements LD included in the same unit pixel SSPX1 to SSPX3 may emit light of the same color. According to an embodiment, the first unit pixel SSPX1 to the third unit pixel SSPX3 may define an emission area that emits light of different colors. For example, the first unit pixel SSPX1 may include a light emitting element LD that emits red light, the second unit pixel SSPX2 may include a light emitting element LD that emits green light, and the third unit pixel SSPX3 may include a light emitting element LD that emits blue light. As another example, all of the first unit pixels SSPX1 to the third unit pixels SSPX3 may include a light emitting element LD that emits blue light. In this case, in order to construct a full-color pixel PXL, a light conversion layer and / or a color filter for converting the color of light emitted from the corresponding unit pixel may be provided on at least a portion of the first unit pixel SSPX1 to the third unit pixel SSPX3.

[0228] As an embodiment, the first electrode ETL1 may be an electrode shared by the first to third unit pixels SSPX1 to SSPX3 In this case, the first to third unit pixels SSPX1 to SSPX3 may be disposed along the first direction DR1.

[0229] The second electrodes ETL21, ETL22, and ETL23 may be disposed to be spaced apart from the first electrode ETL1 at one side in the second direction DR2. The second electrodes ETL21, ETL22, and ETL23 in the first to third unit pixels SSPX1 to SSPX3 may be arranged in the first direction DR1.

[0230] The first electrode ETL1 and the second electrodes ETL21 , ETL22 , and ETL23 may be spaced apart from each other by a predetermined distance and disposed side by side (in parallel).

[0231] As an embodiment, the first electrode ETL1 may be a cathode electrode electrically connected to the second power source VSS. The second electrodes ETL21, ETL22, and ETL23 may be anode electrodes electrically connected to the first power source VDD. A light emitting element LD having one end and the other end electrically connected to the first electrode ETL1 and the second electrodes ETL21, ETL22, and ETL23, respectively, is provided, so that each of the second electrodes ETL21, ETL22, and ETL23 and the first electrode ETL1 may be electrically connected.

[0232] As an embodiment, one emission region may define each unit pixel (e.g., SSPX1). The emission region may be divided by a non-emission region. Although not clearly shown, a pixel defining layer (or embankment, light blocking pattern) or the like that blocks light emitted from the light emitting element LD from being transmitted to another region may be arranged to overlap in the non-emission region.

[0233] As an embodiment, the second subpixel SPX12 may include a first contact electrode CNE1 electrically connecting the first electrode ETL1 with one end of the light emitting element LD. The first contact electrode CNE1 may overlap at least a partial region of the first electrode ETL1.

[0234] The second subpixel SPX12 may include an antenna pattern ANTE formed simultaneously with the first contact electrode CNE1 through the same process as the first contact electrode CNE1. The antenna pattern ANTE may be electrically separated and insulated from the first contact electrode CNE1. The antenna pattern ANTE may have a shape surrounding the first contact electrode CNE1 formed for each unit pixel. The antenna pattern ANTE shown in this figure may be Fig.10 The antenna pattern ANTE corresponds to.

[0235] The antenna pattern ANTE may overlap each of the unit pixels SSPX1 to SSPX3. The antenna pattern ANTE may be formed for each sub-pixel (eg, SPX11, SPX12, SPX13, and SPX21, see reference numeral 23) in the first sub-display area DA11. Fig. 9 ). The antenna pattern ANTE may be an electrode pattern formed for each sub-pixel. Although not clearly shown, the antenna patterns ANTE located in adjacent sub-pixels may be electrically connected to each other. However, the shape of the antenna pattern ANTE is not limited thereto, and the antenna pattern ANTE may be formed for each unit pixel SSPX1 to SSPX3, and in this case, the antenna patterns ANTE may be electrically connected to each other through a separate connection pattern (not shown).

[0236] refer to Fig. 20 In the fifth sub-pixel SPX22, the touch electrode pattern TS may be formed instead of Fig.19 The antenna pattern ANTE in the second sub-pixel SPX12 is formed at a position corresponding to the antenna pattern ANTE.

[0237] The touch electrode pattern TS may be formed to be respectively directed to each sub-pixel (eg, SPX23 and SPX22, see FIG. 1 ) in the second sub-display area DA12. Fig. 9 ). The touch electrode pattern TS may be formed for each unit pixel SSPX1 to SSPX3, respectively, and adjacent touch electrode patterns TS may be electrically separated and insulated. In the present drawing, the touch electrode pattern TS may be Fig.10 The touch electrode pattern TS corresponds to.

[0238] As an embodiment, some of the touch electrode patterns TS may correspond to driving electrodes TE through which driving signals flow, and the remaining portions of the touch electrode patterns TS may correspond to sensing electrodes RE through which sensing signals flow. The driving electrodes TE and the sensing electrodes RE may sense external input using a mutual capacitance method or a self capacitance method.

[0239] However, the arrangement shape of the touch electrode pattern TS is not limited thereto and may be formed for each sub-pixel. In addition, in another embodiment, the touch electrode pattern TS in at least some sub-pixels in the second sub-display area DA12 may be changed to a piezoelectric sensor pattern FS (see Fig.10 ).

[0240] Since the arrangement structure of the first and second electrodes ETL1 , ETL21 , ETL22 , and ETL23 and the first contact electrode CNE1 of the fifth subpixel SPX22 is the same as that of the second subpixel SPX12 , overlapping descriptions are omitted.

[0241] Fig.21 is in the first display device and Fig.19 The line I2 - I2 ′ corresponds to a cross-sectional view from the display substrate to the encapsulation layer. Fig. 22 is in the first display device and Fig. 20 The line I3 - I3 ′ corresponds to a cross-sectional view from the display substrate to the encapsulation layer.

[0242] refer to Fig.21 and Fig. 22 , the first display device DV1 may include a base layer SUB1 disposed under the display substrate SUB_DA. Fig. 9 The description of the base layer SUB1 is described, and thus an overlapping description thereof is omitted.

[0243] The first buffer layer 111 is disposed on the base layer SUB1. The first buffer layer 111 is used to smooth the surface of the base layer SUB1 and prevent the penetration of moisture or external air. The first buffer layer 111 may be an inorganic layer. The first buffer layer 111 may be a single layer or a multi-layer.

[0244] A plurality of transistors Tdr and Tsw are disposed on the first buffer layer 111. Here, each of the transistors Tdr and Tsw may be a thin film transistor. The two transistors Tdr and Tsw shown in the drawing correspond to a driving transistor and a switching transistor, respectively.

[0245] Each of the transistors Tdr and Tsw may include semiconductor patterns ACT1 and ACT2, gate electrodes GE1 and GE2, source electrodes SDE2 and SDE4, and drain electrodes SDE1 and SDE3, respectively. For example, the first transistor Tdr as a driving transistor may include a first semiconductor pattern ACT1, a first gate electrode GE1, a first source electrode SDE2, and a first drain electrode SDE1. The second transistor Tsw as a switching transistor may include a second semiconductor pattern ACT2, a second gate electrode GE2, a second source electrode SDE4, and a second drain electrode SDE3.

[0246] Specifically, the semiconductor layer is disposed on the first buffer layer 111. The semiconductor layer may include the first and second semiconductor patterns ACT1 and ACT2 described above. In addition, the semiconductor layer may further include a third semiconductor pattern ACT3.

[0247] The semiconductor layer may include amorphous silicon, polycrystalline silicon, low temperature polycrystalline silicon, and an organic semiconductor. In another embodiment, the semiconductor layer may be an oxide semiconductor. Although not clearly shown, the semiconductor layer may include a channel region and a source region and a drain region disposed at both sides of the channel region and doped with impurities.

[0248] The first gate insulating layer 112 is disposed on the semiconductor layer. The first gate insulating layer 112 may be an inorganic layer. The first gate insulating layer 112 may be a single layer or multiple layers.

[0249] The first conductive layer is disposed on the first gate insulating layer 112. The first conductive layer may include the first gate electrode GE1 and the second gate electrode GE2 described above. In addition, the first conductive layer may further include a first low power pattern VSSL1. The first conductive layer may be formed of a metal material having conductivity. For example, the first conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The first conductive layer may be a single layer or a multilayer.

[0250] The first low power pattern VSSL1 may be electrically connected to the second power line. The first low power pattern VSSL1 may be disposed in the first display area DA1 and may overlap the third semiconductor pattern ACT3.

[0251] The second gate insulating layer 113 is disposed on the first conductive layer. The second gate insulating layer 113 may be an inorganic layer. The second gate insulating layer 113 may be a single layer or multiple layers.

[0252] The second conductive layer is disposed on the second gate insulating layer 113. The second conductive layer may include a third gate electrode GE4. The third gate electrode GE4 may be a gate electrode of another transistor not shown, but is not limited thereto. The second conductive layer may be formed of a metal material having conductivity. For example, the second conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The second conductive layer may be a single layer or a multilayer.

[0253] The interlayer insulating layer 114 is disposed on the second conductive layer. The interlayer insulating layer 114 may be an organic layer or an inorganic layer. The interlayer insulating layer 114 may be a single layer or a multilayer.

[0254] The third conductive layer is disposed on the interlayer insulating layer 114. The third conductive layer may include the source electrodes SDE2 and SDE4 and the drain electrodes SDE1 and SDE3 described above. In addition, the third conductive layer may further include a second low power pattern VSSL2. The third conductive layer is formed of a metal material having conductivity. For example, the source electrodes SDE2 and SDE4, the drain electrodes SDE1 and SDE3, and the second low power pattern VSSL2 may include aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo).

[0255] The second low power pattern VSSL2 may be electrically connected to the second power line. The second low power pattern VSSL2 may contact the first low power pattern VSSL1 through a contact hole passing through the second gate insulating layer 113 and the interlayer insulating layer 114. The second low power pattern VSSL2 may be disposed in the first display area DA1 and may overlap the first low power pattern VSSL1 and the third semiconductor pattern ACT3.

[0256] The source electrodes SDE2 and SDE4 and the drain electrodes SDE1 and SDE3 are not limited to the names. Fig.21 and Fig. 22 The source electrodes SDE2 and SDE4 shown in FIG. 1 may perform the function of drain electrodes, and Fig.21 and Fig. 22 The drain electrodes SDE1 and SDE3 shown in FIG. 4 may perform the function of source electrodes.

[0257] The source electrodes SDE2 and SDE4 and the drain electrodes SDE1 and SDE3 may be respectively connected to the source and drain regions of each of the corresponding semiconductor patterns ACT1 and ACT2 through contact holes passing through the interlayer insulating layer 114 , the second gate insulating layer 113 , and the first gate insulating layer 112 .

[0258] Although not separately shown, the first display device DV1 may further include a storage capacitor disposed on the base layer SUB1.

[0259] The first protective layer 121 is disposed on the third conductive layer. Here, the first protective layer 121 is disposed to cover the circuit portion including the transistors Tdr and Tsw. The first protective layer 121 may also be disposed in at least a portion of the first non-display area NDA1. The first protective layer 121 may be a passivation layer or a planarization layer. The passivation layer may include SiO 2 、SiN x The first protective layer 121 may include a passivation layer and a planarization layer. In this case, the passivation layer may be disposed on the third conductive layer and the interlayer insulating layer 114, and the planarization layer may be disposed on the passivation layer. The upper surface of the first protective layer 121 may be flat.

[0260] The fourth conductive layer may be disposed on the first protective layer 121. The fourth conductive layer may include various conductive patterns such as power lines, signal lines, and connection electrodes. In the drawings, it is illustrated that the fourth conductive layer includes the first connection pattern CE1 disposed in the first display area DA1. The fourth conductive layer is formed of a metal material having conductivity. For example, the fourth conductive layer may include aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo).

[0261] The first connection pattern CE1 may contact any one of the source electrode SDE2 and the drain electrode SDE1 of the first transistor Tdr through a contact hole passing through the first protective layer 121 .

[0262] The second protective layer 122 is disposed on the fourth conductive layer. The second protective layer 122 may be a passivation layer or a planarization layer. The passivation layer may include SiO 2 、SiN x The second protective layer 122 may include both a passivation layer and a planarization layer.

[0263] Meanwhile, the second protective layer 122 may include an opening exposing an upper portion of a portion of a portion of the fourth conductive layer included in the fourth conductive layer. For example, the second protective layer 122 may include an opening exposing at least a portion of the first connection pattern CE1.

[0264] In this specification, the base layer SUB1 to the second protective layer 122 are referred to as a pixel circuit layer. That is, the pixel circuit layer corresponds to a layer including a plurality of transistors in the display substrate SUB_DA.

[0265] The first display device DV1 may include first and second partition walls PW1 and PW2, first and second electrodes ETL1 and ETL21, a first insulating layer 131, a light emitting element LD, a second insulating layer 132, first and second contact electrodes CNE1 and CNE21, a third insulating layer 133, and a thin film encapsulation layer 141 sequentially disposed on the second protective layer 122.

[0266] The first partition wall PW1 and the second partition wall PW2 may be disposed on the pixel circuit layer (i.e., the second protective layer 122). The first partition wall PW1 and the second partition wall PW2 may protrude in the thickness direction (e.g., the third direction DR3) on the pixel circuit layer. According to an embodiment, the first partition wall PW1 and the second partition wall PW2 may have substantially the same height, but are not limited thereto. For example, the protrusion heights of the first partition wall PW1 and the second partition wall PW2 may be approximately 1.0 μm to 1.5 μm, respectively.

[0267] As an embodiment, the first partition wall PW1 may be disposed between the pixel circuit layer and the first electrode ETL1 . The second partition wall PW2 may be disposed between the pixel circuit layer and each of the second electrodes ETL21 , ETL22 , and ETL23 .

[0268] According to the embodiment, the first partition wall PW1 and the second partition wall PW2 may have various shapes. As an example, the first partition wall PW1 and the second partition wall PW2 may have a trapezoidal cross-sectional shape in which the width narrows toward the upper portion as shown in the drawings. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have an inclined surface on at least one side surface.

[0269] Although not shown, as another example, the first partition wall PW1 and the second partition wall PW2 may have a semicircular or semi-elliptical cross-section in which the width narrows toward the upper portion. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have a curved surface on at least one side surface. That is, in the present disclosure, the shapes of the first partition wall PW1 and the second partition wall PW2 are not particularly limited and may be variously changed. In addition, according to the embodiment, at least one of the first partition wall PW1 and the second partition wall PW2 may be omitted, or its position may be changed.

[0270] The first partition wall PW1 and the second partition wall PW2 may include an insulating material including an inorganic material and / or an organic material. For example, the first partition wall PW1 and the second partition wall PW2 may include at least one inorganic layer including SiN x 、SiO xAlternatively, the first partition wall PW1 and the second partition wall PW2 may include at least one organic layer (including various currently known organic insulating materials, photoresist layers, etc.), or may be composed of a single-layer or multi-layer insulator including a combination of organic / inorganic materials. That is, the construction materials of the first partition wall PW1 and the second partition wall PW2 may be variously changed.

[0271] In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be used as a reflective member. As an example, the first partition wall PW1 and the second partition wall PW2 may be used together with the first electrode ETL1 and the second electrode ETL21 disposed thereon as a reflective member to guide the light emitted from each light emitting element LD in a desired direction to improve the light efficiency of the pixel PXL.

[0272] The first electrode ETL1 and the second electrode ETL21 may be disposed on the first partition wall PW1 and the second partition wall PW2, respectively. The first electrode ETL1 and the second electrode ETL21 may be disposed to be spaced apart from each other. The first electrode ETL1 and the second electrode ETL21 may be formed at the same layer.

[0273] As an embodiment, the first electrode ETL1 and the second electrode ETL21, etc., respectively disposed on the first partition wall PW1 and the second partition wall PW2 may have a shape corresponding to the shape of each of the first partition wall PW1 and the second partition wall PW2. For example, each of the first electrode ETL1 and the second electrode ETL21 may have an inclined surface or a curved surface corresponding to the first partition wall PW1 and the second partition wall PW2, and may protrude in the thickness direction of the first display device DV1.

[0274] Each of the first electrode ETL1 and the second electrode ETL21 may include at least one conductive material. For example, each of the first electrode ETL1 and the second electrode ETL21 may include a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and alloys thereof, a conductive oxide such as ITO, IZO, ZnO, and ITZO, and a conductive polymer such as PEDOT, but is not limited thereto.

[0275] In addition, each of the first electrode ETL1 and the second electrode ETL21 may be configured as a single layer or multiple layers. For example, each of the first electrode ETL1 and the second electrode ETL21 may include at least one reflective electrode layer. In addition, each of the first electrode ETL1 and the second electrode ETL21 may further selectively include at least one of at least one transparent electrode layer disposed on and / or below the reflective electrode layer and at least one conductive cap layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0276] According to an embodiment, the reflective electrode layer of each of the first electrode ETL1 and the second electrode ETL21 may be formed of an electrode material having uniform reflectivity. As an example, the reflective electrode layer may include at least one of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and alloys thereof, but is not limited thereto. That is, the reflective electrode layer may be formed of various reflective electrode materials. When each of the first electrode ETL1 and the second electrode ETL21 includes a reflective electrode layer, light emitted from both ends (i.e., one end and the other end) of each of the light emitting elements LD may be allowed to further advance in the direction of displaying an image (e.g., the third direction DR3, the front direction). In particular, when the first electrode ETL1 and the second electrode ETL21 have inclined surfaces or curved surfaces corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2 and are disposed to face one end and the other end of each of the light emitting elements LD, light emitted from one end and the other end of each of the light emitting elements LD may be reflected by the first electrode ETL1 and the second electrode ETL21 and may further advance in a front direction of the first display device DV1 (e.g., a third direction DR3 that is an upper direction of the base layer SUB1). Therefore, the efficiency of light emitted from the light emitting element LD may be improved.

[0277] In addition, the transparent electrode layer of each of the first electrode ETL1 and the second electrode ETL21 may be formed of various transparent electrode materials. As an example, the transparent electrode layer may include ITO, IZO or ITZO, but is not limited thereto. In an embodiment, each of the first electrode ETL1 and the second electrode ETL21 may be constructed as a three-layer stacked structure having ITO / Ag / ITO. As described above, when the first electrode ETL1 and the second electrode ETL21 are constructed as at least two or more layers, the voltage drop caused by the signal delay (RC delay) may be minimized. Therefore, the desired voltage may be effectively delivered to the light emitting element LD.

[0278] Additionally, when each of the first electrode ETL1 and the second electrode ETL21 includes a conductive cover layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer, etc. of the first electrode ETL1 and the second electrode ETL21 can be prevented from being damaged due to defects occurring in the manufacturing process of the pixel PXL, etc. However, according to an embodiment, the conductive cover layer may be selectively included in the first electrode ETL1 and the second electrode ETL21, and may be omitted. In addition, the conductive cover layer may be considered as a component of each of the first electrode ETL1 and the second electrode ETL21, or as a separate component disposed on the first electrode ETL1 and the second electrode ETL21.

[0279] As an embodiment, the second electrodes ETL21 , ETL22 , and ETL23 may overlap the first connection pattern CE1 in at least a partial region. The second electrodes ETL21 , ETL22 , and ETL23 may contact the first connection pattern CE1 through the contact holes CH passing through the second protective layer 122 .

[0280] The first insulating layer 131 may be disposed on one region of the first and second electrodes ETL1 and ETL21 in the first display area DA1. For example, the first insulating layer 131 may include an opening formed to cover one region of the first and second electrodes ETL1 and ETL21 and expose another region of the first and second electrodes ETL1 and ETL21.

[0281] In an embodiment, the first insulating layer 131 may be formed to completely cover the first electrode ETL1 and the second electrode ETL21 first. After the light emitting element LD is supplied and aligned on the first insulating layer 131, the first insulating layer 131 may be partially opened to expose the first electrode ETL1 and the second electrode ETL21. Alternatively, after the supply and alignment of the light emitting element LD are completed, the first insulating layer 131 may be patterned in the form of an individual pattern partially disposed under the light emitting element LD.

[0282] That is, the first insulating layer 131 may be interposed between the first and second electrodes ETL1 and ETL21 and the light emitting element LD, and may expose at least one region of each of the first and second electrodes ETL1 and ETL21. After forming the first and second electrodes ETL1 and ETL21, the first insulating layer 131 may be formed to cover the first and second electrodes ETL1 and ETL21 to prevent damage to the first and second electrodes ETL1 and ETL21 or precipitation of metal. In addition, the first insulating layer 131 may stably support each light emitting element LD. According to an embodiment, the first insulating layer 131 may be omitted.

[0283] The light emitting element LD may be supplied and aligned in the region of the first insulating layer 131. For example, the light emitting element LD may be supplied by an inkjet method or the like, and the light emitting element LD may be aligned between the first electrode ETL1 and the second electrode ETL21 by a predetermined alignment voltage (or alignment signal) applied to the first electrode ETL1 and the second electrode ETL21.

[0284] As an example, the thickness of the first insulating layer 131 may be about (Angstrom) to

[0285] The bank BNK may be disposed on the first insulating layer 131. For example, the bank BNK may be formed between other sub-pixels to surround the sub-pixel ( Fig.11Each of SPX11 to SPX23) and can constitute a pixel defining layer that separates the emission areas.

[0286] According to an embodiment, the bank BNK may not be disposed between the unit pixels SSPX1 to SSPXk in the same sub-pixels SPX11 to SPX23 , but is not limited thereto.

[0287] The second insulating layer 132 may be disposed on the light emitting element LD, in particular, on the light emitting element LD aligned between the first electrode ETL1 and the second electrode ETL21, and may expose one end and the other end of the light emitting element LD. For example, the second insulating layer 132 may be partially disposed on only one region of the light emitting element LD without covering one end and the other end of the light emitting element LD. The second insulating layer 132 may be formed in an independent pattern on each emission region, but is not limited thereto. In addition, as Fig.21 and Fig. 22 As shown in FIG. 1 , when there is a space between the first insulating layer 131 and the light emitting element LD before forming the second insulating layer 132, the space may be filled with the second insulating layer 132. Therefore, the light emitting element LD may be supported more stably.

[0288] As an example, the thickness of the second insulating layer 132 may be about to

[0289] The first and second contact electrodes CNE1 and CNE21 may be disposed on the first and second electrodes ETL1 and ETL21 and one and the other ends of the light emitting element LD.

[0290] In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE21 may be disposed in different layers, such as Fig.21 and Fig. 22 shown.

[0291] The second contact electrode CNE21 may be disposed on the second electrodes ETL21, ETL22, and ETL23 to contact the second electrodes ETL21, ETL22, and ETL23. As an example, the second contact electrode CNE21 may be disposed to contact the second electrode ETL21 on an area of ​​the second electrode ETL21 that is not covered by the first insulating layer 131. In addition, the second contact electrode CNE21 may be disposed on an end of the light emitting element LD adjacent to the second electrode ETL21 to contact one end of the light emitting element. That is, the second contact electrode CNE21 may be disposed to cover one end of the light emitting element LD and at least one area of ​​the second electrode ETL21 corresponding thereto. Therefore, one end of the light emitting element LD may be electrically connected to each second electrode ETL21.

[0292] Meanwhile, the first bridge pattern BE1 and the second bridge pattern BE2 may be disposed at the same layer as the second contact electrode CNE21. The first bridge pattern BE1, the second bridge pattern BE2, and the second contact electrode CNE21 may be simultaneously formed by the same process.

[0293] The first bridge pattern BE1 may electrically connect adjacent antenna patterns ANTE. The first bridge pattern BE1 may be disposed on the first insulating layer 131 and the bank BNK, and may be formed to cross adjacent sub-pixels beyond the bank BNK.

[0294] The second bridge pattern BE2 may electrically connect adjacent touch electrode patterns TS. The second bridge pattern BE2 may be disposed on the first insulating layer 131 and the bank BNK, and may be formed to cross adjacent sub-pixels beyond the bank BNK.

[0295] The third insulating layer 133 may be disposed on the first partition wall PW1 and the second partition wall PW2, the first electrode ETL1 and the second electrode ETL21, the light emitting element LD, the second contact electrode CNE21, the first bridge pattern BE1 and the second bridge pattern BE2, and the embankment BNK to cover the first partition wall PW1 and the second partition wall PW2, the first electrode ETL1 and the second electrode ETL21, the light emitting element LD, the second contact electrode CNE21, the first bridge pattern BE1 and the second bridge pattern BE2, and the embankment BNK.

[0296] As an example, the thickness of the third insulating layer 133 may be about (Angstrom) to A first contact hole CNT1 exposing at least a portion of the first bridge pattern BE1 and a second contact hole CNT2 exposing at least a portion of the second bridge pattern BE2 may be formed in the third insulating layer 133 .

[0297] According to an embodiment, each of the first insulating layer 131, the second insulating layer 132, and the third insulating layer 133 may be configured as a single layer or a multilayer, and may include at least one inorganic insulating material and / or an organic insulating material. For example, each of the first insulating layer 131, the second insulating layer 132, and the third insulating layer 133 may include various types of currently known SiN x The organic / inorganic insulating material of the first insulating layer 131, the second insulating layer 132, and the third insulating layer 133 are not particularly limited in terms of the constituent material of each. In addition, the first insulating layer 131, the second insulating layer 132, and the third insulating layer 133 may include different insulating materials, or at least some of the first insulating layer 131, the second insulating layer 132, and the third insulating layer 133 may have the same insulating material.

[0298] The first contact electrode CNE1 may be disposed on the third insulating layer 133. As an example, the first contact electrode CNE1 may be disposed to contact the first electrode ETL1 on one region of the first electrode ETL1 that is not covered by the first insulating layer 131. In addition, the first contact electrode CNE1 may be disposed on the other end of the light emitting element adjacent to the first electrode ETL1 to contact the other end. That is, the first contact electrode CNE1 may be disposed to cover the other end of the light emitting element LD and at least one region of the first electrode ETL1 corresponding thereto. Therefore, the other end of the light emitting element LD may be electrically connected to each of the first electrodes ETL1.

[0299] Meanwhile, the antenna pattern ANTE and the touch electrode pattern TS may be disposed at the same layer as the first contact electrode CNE1. The antenna pattern ANTE, the touch electrode pattern TS, and the first contact electrode CNE1 may be simultaneously formed through the same process.

[0300] As an embodiment, the first contact electrode CNE1 and the second contact electrode CNE21 may be formed of a transparent conductive material such as ITO, IZO, and ITZO so that light emitted from the light emitting element LD can pass therethrough. Similarly, the antenna pattern ANTE and the touch electrode pattern TS may be formed of a transparent conductive material such as ITO, IZO, and ITZO.

[0301] The antenna pattern ANTE may make contact with the first bridge pattern BE1 through the first contact hole CNT1 , and the touch electrode pattern TS may make contact with the second bridge pattern BE2 through the second contact hole CNT2 .

[0302] The encapsulation layer 141 including at least one inorganic layer and / or organic layer may be disposed on the antenna pattern ANTE, the touch electrode pattern TS, and the first contact electrode CNE1. The encapsulation layer 141 may be another insulating layer. Fig.10 According to an embodiment, the encapsulation layer 141 may be omitted.

[0303] In this specification, the first partition wall PW1 and the second partition wall PW2 to the first contact electrode CNE1 are referred to as a light emitting element layer. That is, the light emitting element layer corresponds to a layer including a light emitting element in the display substrate SUB_DA.

[0304] The electromagnetic waves of the antenna pattern ANTE can be radiated to the front surface or rear surface of the first display device DV1. Specifically, since another conductive material is not provided on the antenna pattern ANTE, the first display device DV1 can perform communication by minimizing the loss in the 5G frequency band (eg, 28 GHz to 39 GHz frequency band).

[0305] The description of the antenna pattern ANTE of the first display device DV1 may be similarly applied to the second to fourth display devices DV2 to DV4 .

[0306] Fig.23 is a conceptual diagram illustrating a driving signal of each display device of a video wall display system according to an embodiment of the present disclosure.

[0307] refer to Fig.23 , each of the display devices DV1 to DV4 of the video wall display system 1 includes the antenna pattern ANTE described above, and communication of the 5G frequency band with a minimum loss rate is possible.

[0308] Therefore, the wireless signal SG_MC may be provided from the control unit MC to each of the display devices DV1 to DV4, and a delay time (latency) between the signals SG1 to SG4 received by the display devices DV1 to DV4 may be extremely short or may not actually occur.

[0309] Therefore, the user may feel the first to fourth sub images IM21 to IM24 as one image by viewing each of the display devices DV1 to DV4 of the video wall display system 1 .

[0310] Next, a video wall display system according to another embodiment is described. Figures 1 to 23 The same components as in the accompanying drawings are described below and the same or similar reference numerals are used.

[0311] Fig.24 is a perspective view of a video wall display system according to another embodiment of the present disclosure.

[0312] refer to Fig.24 According to the video wall display system 2 of this embodiment, Figure 1 The video wall display system 1 differs in that the functionality of the control unit MC is merged into the first display device DV1_MC.

[0313] The first display device DV1_MC may have the above reference Figure 1 and Figure 2 The functions of the first display device DV1 and the control unit MC are described. Figures 3 to 23 The description of the first display device DV1_MC and the second to fourth display devices DV2 to DV4 may be similarly applied to the description of the first display device DV1_MC and the second to fourth display devices DV2 to DV4, and thus overlapping descriptions are omitted.

[0314] Fig.25 and Fig.26 is a cross-sectional view from a display substrate to an encapsulation layer of a first display device of a video wall display system according to yet another embodiment of the present disclosure. Fig.25 and Fig.26 Respectively Fig.21 and Fig. 22 The modified example corresponds to .

[0315] refer to Fig.25 and Fig.26 According to the first display device of the video wall display system 3 of this embodiment, Fig.21 and Fig. 22 The embodiment is different in that, in each sub-pixel (eg, the second sub-pixel SPX12_1, the fifth sub-pixel SPX22_1, etc.), the first and second bridge patterns BE1_1 and BE2_1 are formed at the same layer as the first and second electrodes ETL1 and ETL21.

[0316] The antenna pattern ANTE may contact the second connection pattern CE2 formed at the same layer as the second contact electrode CNE21 through the first contact hole CNT1, and the second connection pattern CE2 may contact the first bridge pattern BE1_1. The first bridge pattern BE1_1 may pass under the bank BNK and may be electrically connected to the antenna pattern ANTE of an adjacent subpixel.

[0317] The touch electrode pattern TS (eg, the driving electrode TE) may contact the third connection pattern CE3 formed at the same layer as the second contact electrode CNE21 through the second contact hole CNT2, and the third connection pattern CE3 may contact the second bridge pattern BE2_1. The second bridge pattern BE2_1 may pass under the bank BNK and may be electrically connected to the touch electrode pattern TS of the adjacent sub-pixel.

[0318] Fig. 27 is a plan layout diagram schematically showing the arrangement of one sub-pixel included in a first display device of a video wall display system according to yet another embodiment of the present disclosure. Fig.28 is in the first display device and Fig. 27 A cross-sectional view of the display substrate to the encapsulation layer corresponding to line II2-II2'. Hereinafter, since the touch electrode pattern included in the fifth subpixel has the same shape as the antenna pattern ANTE included in the second subpixel SPX12_2 and only has different functions, overlapping descriptions are omitted.

[0319] refer to Fig. 27 and Fig.28 According to the first display device of the video wall display system 4 of this embodiment, Fig.19 and Fig.21 The embodiment of FIG. 2 is different in that the antenna pattern ANTE and the touch electrode pattern are formed on the same layer as the second contact electrodes CNE21 , CNE22 , and CNE23 .

[0320] The antenna pattern ANTE and the touch electrode pattern may be formed in the same layer as the second contact electrode CNE21. The antenna pattern ANTE and the touch electrode pattern may not overlap the first contact electrode CNE1 and the second contact electrode CNE21, respectively, and may be electrically separated from each other. The first contact electrode CNE1 and the second contact electrode CNE21 may be surrounded by the antenna pattern ANTE and the touch electrode pattern on a plane.

[0321] The first bridge pattern BE1_2 may be formed at the same layer as the first contact electrode CNE1. The first bridge pattern BE1_2 may be connected to the antenna pattern ANTE through the first contact hole CNT1. The first bridge pattern BE1_2 may electrically connect the antenna pattern ANTE between adjacent pixels beyond the bank BNK.

[0322] Fig.29 1 is a plan layout diagram schematically illustrating the arrangement of a sub-pixel (eg, a second sub-pixel SPX12_3 ) included in a first display device of a video wall display system according to yet another embodiment of the present disclosure. Fig.30 is in the first display device and Fig.29 The line III2-III2' corresponds to a cross-sectional view from the display substrate to the encapsulation layer.

[0323] refer to Fig.29 and Fig.30 According to the first display device of the video wall display system 5 of this embodiment, Fig.19 and Fig.21 The embodiment of FIG. 1 is different in that the antenna pattern ANTE, the touch electrode pattern, the first contact electrode CNE1 and the second contact electrode CNE21 are all formed on the same layer.

[0324] The antenna pattern ANTE, the touch electrode pattern, the first contact electrode CNE1 and the second contact electrode CNE21 may be formed simultaneously by the same process. The antenna pattern ANTE, the touch electrode pattern, the first contact electrode CNE1 and the second contact electrode CNE21 may be electrically separated from each other. The first contact electrode CNE1 and the second contact electrode CNE21 may be surrounded by the antenna pattern ANTE and the touch electrode pattern on a plane.

[0325] Fig.31 1 is a plan layout diagram schematically showing the arrangement of one sub-pixel (eg, second sub-pixel SPX12_4) included in a first display device of a video wall display system according to yet another embodiment of the present disclosure.

[0326] refer to Fig.31 According to the first display device of the video wall display system of this embodiment, Fig.19The embodiment is different in that the antenna pattern ANTE and the touch electrode pattern are formed at the same layer as the first and second electrodes ETL1, ETL21, ETL22, and ETL23.

[0327] The antenna pattern ANTE and the touch electrode pattern may be formed simultaneously with the first and second electrodes ETL1, ETL21, ETL22, and ETL23 by the same process as the first and second electrodes ETL1, ETL21, ETL22, and ETL23. The antenna pattern ANTE and the touch electrode pattern may be electrically separated from the first and second electrodes ETL1, ETL21, ETL22, and ETL23.

[0328] Fig.32 is a cross-sectional view from a display substrate to an encapsulation layer in a first display device of a video wall display system according to yet another embodiment of the present disclosure. Fig.33 yes Fig.32 's modified example.

[0329] refer to Fig.32 According to the first display device of the video wall display system 6 of this embodiment, Fig.19 and Fig.21 The embodiment of FIG. 6 is different in that the first display device of the video wall display system 6 further includes a shielding electrode SM, and the antenna pattern ANTE and the touch electrode pattern are formed on the same layer as the shielding electrode SM.

[0330] In each subpixel (e.g., the second subpixel SPX12_5), a substrate shielding electrode can be formed on the first insulating layer 131, the first electrode ETL1, and the second electrode ETL21 to surround an aligned area of ​​each of the light emitting elements LD, and after the light emitting elements LD are aligned, the substrate shielding electrode can be patterned to form a shielding electrode SM and an antenna pattern ANTE.

[0331] As an example, the substrate shielding electrode may include Cr / CrO x CrO x 、MoO x , an external light absorbing material formed of at least one of a carbon pigment and an RGB pigment.

[0332] As an embodiment, the shield electrode SM may be disposed directly under the second contact electrode CNE21 , and the shield electrode SM may be disposed between the second electrode ETL21 and the second contact electrode CNE21 .

[0333] Although not clearly shown, the antenna pattern ANTE may be formed to surround the first and second contact electrodes CNE1 and CNE21 .

[0334] As an embodiment, the bridge pattern BE1_3 may be formed at the same layer as the second contact electrode CNE21. The bridge pattern BE1_3 may be patterned directly on the antenna pattern ANTE to cross the bank BNK. The bridge pattern BE1_3 may electrically connect the antenna patterns ANTE respectively disposed in adjacent sub-pixels.

[0335] refer to Fig.33 In the sub-pixel (e.g., the second sub-pixel SPX12_6) of the first display device in the video wall display system 6_1 according to the present embodiment, the bridge pattern BE1_4 may be formed in the same layer as the second contact electrode CNE21. The bridge pattern BE1_4 may be patterned directly on the antenna pattern ANTE to cross the bank BNK. The bridge pattern BE1_4 may electrically connect the antenna patterns ANTE respectively disposed in adjacent sub-pixels.

[0336] Fig.34 1 is a plan layout diagram schematically showing the arrangement of one sub-pixel (eg, second sub-pixel SPX12_7) included in a first display device of a video wall display system according to yet another embodiment of the present disclosure. Fig.35 is in the first display device and Fig.34 The line IV2-IV2' corresponds to a cross-sectional view from the display substrate to the encapsulation layer. Fig.36 yes Fig.34 's modified example.

[0337] refer to Fig.34 and Fig.35 According to the first display device of the video wall display system 7 of this embodiment, Fig.19 and Fig.21 The embodiment of FIG. 1 is different in that a conductive layer on which the antenna pattern ANTE is formed is separately disposed on the encapsulation layer 141 .

[0338] As an embodiment, the antenna pattern ANTE may be disposed on the encapsulation layer 141 and may be formed of a plurality of layers. For example, the antenna pattern ANTE may include a first antenna pattern layer ANTE1 and a second antenna pattern layer ANTE2 sequentially stacked.

[0339] The first antenna pattern layer ANTE1 may not overlap with the area aligned with the light emitting element LD. As an embodiment, the first antenna pattern layer ANTE1 may include a metal or a transparent electrode capable of reflecting external light. As an example, the first antenna pattern layer ANTE1 may include chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni) or an oxide or alloy thereof capable of reflecting external light, or may include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and indium tin zinc oxide (ITZO).

[0340] The second antenna pattern layer ANTE2 may include the transparent electrode material described above as an example in the first antenna pattern layer ANTE1. The second antenna pattern layer ANTE2 may include a function of improving visibility due to reflection of external light.

[0341] refer to Fig.36 In a sub-pixel (eg, the second sub-pixel SPX12_7_1), the antenna pattern ANTE may include a slit pattern SLP. The slit pattern SLP may have the functions of improving visibility and reducing noise.

[0342] In a process in which the antenna pattern ANTE is formed, the antenna pattern ANTE may be removed from a portion where the slit pattern SLP is to be formed.

[0343] Fig.37 1 is a plan layout diagram schematically showing the arrangement of one sub-pixel (eg, second sub-pixel SPX12_8) included in a first display device of a video wall display system according to yet another embodiment of the present disclosure. Fig.38 is in the first display device and Fig.37 The line V-V' corresponds to a cross-sectional view from the display substrate to the encapsulation layer.

[0344] refer to Fig.37 and Fig.38 In the first display device of the video wall display system 8 according to the present embodiment, Fig.19 and Fig.21 Compared with the embodiment of FIG. 4 , the region where the light emitting element LD is arranged may have a circular shape.

[0345] The shape between the first electrode ETL1 and the second electrode ETL21 may be circular. The second electrode ETL21 may have a circular shape, and the second electrode ETL21 may be surrounded by the first electrode ETL1. The light emitting element LD may be radially disposed with respect to the second electrode ETL21. Therefore, the light emitted from the light emitting element LD may not be focused in a specific direction, and a first display device having a uniform light output distribution may be provided. In addition, the bridge pattern BE1_5 may be formed at the same layer as the second contact electrode CNE21.

[0346] Although the partition wall is omitted in the drawings, the present disclosure is not limited thereto.

[0347] Fig.39 is a perspective view of a first display device of a video wall display system according to yet another embodiment of the present disclosure. Fig.40 yes Fig.39 Schematic cross-sectional view of a first display device shown in . Fig.41 yes Fig.40 A magnified view of area AA.

[0348] refer to Figure 39 to Figure 41 According to the video wall display system 9 of this embodiment, the first display device DV1 and Figure 1 and Fig.10 The embodiment of is different in that the first display device DV1 of the video wall display system 9 further comprises a speaker member SPC.

[0349] The speaker member SPC may be disposed adjacent to an area located in a relatively lower portion of the display substrate SUB_DA. In this embodiment, the speaker member SPC is disposed between the second protection film PF2 and the first flexible circuit board FPC1. In another embodiment, the speaker member SPC may be directly mounted on the rear surface of the display substrate SUB_DA.

[0350] The speaker member SPC is positioned adjacent to a lower portion of the display substrate SUB_DA to be prevented from being viewed from an upper portion of the display substrate SUB_DA.

[0351] The speaker member SPC can output a first vibration by generating a vibration in response to a first vibration signal. The speaker member SPC can output a first sound by vibrating the display substrate SUB_DA by the first vibration. To this end, the speaker member SPC can vibrate through a vibration layer 530 that is deformed in response to the first vibration signal. Alternatively, the speaker member SPC can vibrate by an electromagnetic force generated by causing a current according to the first vibration signal to flow to a coil surrounding a magnet. Hereinafter, the present disclosure is described based on the speaker member SPC generating a sound by the vibration of the vibration layer 530.

[0352] The speaker member SPC may include a first speaker electrode 510 , a second speaker electrode 520 , a vibration layer 530 , and a speaker base 540 .

[0353] The first speaker electrode 510 may be disposed on a first surface of the speaker base 540 , the vibration layer 530 may be disposed on the first speaker electrode 510 , and the second speaker electrode 520 may be disposed on the vibration layer 530 .

[0354] The first speaker electrode 510 and the second speaker electrode 520 may be formed of a conductive material, such as a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), an opaque metal material, a conductive polymer, a carbon nanotube (CNT), or the like.

[0355] The vibration layer 530 may be a piezoelectric actuator that is deformed according to a difference between a voltage applied to the first speaker electrode 510 and a voltage applied to the second speaker electrode 520. In this case, the vibration layer 530 may be at least one piezoelectric material such as a polyvinylidene fluoride (PVDF) film, lead zirconate titanate ceramic (PZT), and an electroactive polymer.

[0356] In this case, the vibration layer 530 contracts, relaxes, or expands according to the difference between the first driving voltage applied to the first speaker electrode 510 and the second driving voltage applied to the second speaker electrode 520. When the first driving voltage applied to the first speaker electrode 510 and the second driving voltage applied to the second speaker electrode 520 are repeated alternately with positive polarity and negative polarity, the vibration layer 530 repeats contraction and relaxation. Therefore, the speaker member SPC vibrates, and thus the first sound can be output due to the up-and-down vibration of the display substrate SUB_DA.

[0357] As an example, the speaker member SPC may reproduce the frequency bands of the middle and high ranges. For example, the speaker member SPC may reproduce the first sound having a frequency of about 4 kHz to 20 kHz. For example, the speaker member SPC may be a tweeter.

[0358] Fig.42 yes Figure 1 's modified example.

[0359] refer to Fig.42 According to the video wall display system 1_1 of the present embodiment, the arrangement shapes of the first to fourth display devices DV1 to DV4 may be irregular.

[0360] Since the first to fourth display devices DV1 to DV4 can communicate with each other through the network communication unit 270 (refer to Figure 2 ) are connected to each other, so the first display device DV1 to the fourth display device DV4 can be freely arranged.

[0361] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that the embodiments may be implemented in other specific forms without changing the technical spirit and basic features of the present disclosure. Therefore, it should be understood that the embodiments described above are illustrative and not restrictive in all aspects.

Claims

1. A display device, comprising a display area and a non-display area, wherein the display device comprises: A pixel circuit layer including a plurality of transistors; A first electrode and a second electrode are formed on the same layer on the pixel circuit layer; A light emitting element is disposed between the first electrode and the second electrode; an antenna pattern, arranged on the light emitting element; as well as a first contact electrode, electrically connecting one end of the light emitting element to the first electrode, The antenna pattern and the first contact electrode are formed in the same layer. wherein the antenna pattern includes an opening, and Wherein, the first contact electrode is arranged in the opening.

2. The display device according to claim 1, wherein: The antenna pattern and the first contact electrode are electrically separated from each other.

3. The display device according to claim 1, further comprising: The second contact electrode electrically connects the other end of the light emitting element to the second electrode.

4. The display device according to claim 3, wherein: The first contact electrode is disposed on the second contact electrode.

5. The display device according to claim 3, wherein: The antenna pattern overlaps the second contact electrode, and The display device further includes an insulating layer disposed between the antenna pattern and the second contact electrode.

6. The display device according to claim 5, further comprising: A first bridge pattern is formed on the same layer as the second contact electrode, The antenna pattern is connected to the first bridge pattern through a first contact hole formed in the insulating layer.

7. The display device according to claim 3, wherein: The first contact electrode, the second contact electrode, and the antenna pattern are disposed at the same layer and are electrically separated from each other.

8. The display device according to claim 1, wherein: The transmission / reception frequency of the antenna pattern is 28 GHz to 39 GHz.

9. The display device according to claim 1, wherein: The antenna pattern includes a transparent conductive material.

10. A video wall display system, the video wall display system comprising a plurality of display devices, in, Each of the plurality of display devices comprises: A display substrate including a display area and a non-display area; and an antenna pattern, arranged in the display area and on the display substrate, The display substrate includes in the display area: a pixel circuit layer including a plurality of transistors; a first electrode and a second electrode formed on the same layer on the pixel circuit layer; a light emitting element disposed between the first electrode and the second electrode; and a first contact electrode electrically connecting one end of the light emitting element to the first electrode. The antenna pattern and the first contact electrode are formed in the same layer. wherein the antenna pattern includes an opening, and Wherein, the first contact electrode is arranged in the opening.

11. The video wall display system according to claim 10, wherein: The plurality of display devices are connected via a wireless network.

12. The video wall display system according to claim 10, wherein: The display substrate includes a curved region.

13. The video wall display system according to claim 10, further comprising: The wireless power transmission antenna is arranged under the display substrate.

14. The video wall display system according to claim 10, further comprising: The speaker module is arranged under the display substrate.

15. The video wall display system of claim 14, wherein: The speaker module includes a first speaker electrode, a second speaker electrode, and a vibration layer disposed between the first speaker electrode and the second speaker electrode.

16. The video wall display system of claim 15, wherein: The vibration layer includes at least one of polyvinylidene fluoride, lead zirconate titanate ceramics, and electroactive polymers.

17. A video wall display system, the video wall display system comprising a plurality of display devices, in, Each of the plurality of display devices comprises: A display substrate, comprising a display area and a non-display area, wherein the display substrate comprises a first electrode, a second electrode, a plurality of transistors, a first contact electrode and a light emitting element located between the first electrode and the second electrode in the display area; an antenna pattern disposed in the display area and on the display substrate; and a network communication unit that transmits wireless signals to other display devices in the video wall display system and receives wireless signals from other display devices in the video wall display system through the antenna pattern, wherein the first electrode and the second electrode are formed in the same layer, The first contact electrode electrically connects one end of the light emitting element to the first electrode. The antenna pattern and the first contact electrode are formed in the same layer. wherein the antenna pattern includes an opening, and Wherein, the first contact electrode is arranged in the opening.

18. The video wall display system of claim 17, wherein: The light emitting element has a diameter and a length ranging from a few hundred nanometers to a few micrometers.

19. The video wall display system according to claim 17, further comprising: a control unit connected to at least one of the plurality of display devices via a wireless network, The user's instructions are input into the control unit.

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