Reset verification in memory systems

Abstract

This application is directed to reset verification in a memory system. In some examples, a memory device can perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value can be associated with a successful execution of the reset command. The memory device can transmit an indication to a host device based on determining the first value. The host device can determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device or the host device or both can be configured to verify whether the reset operation was successful.

Description

[0001] Cross-references

[0002] This patent application is a national phase application of International Patent Application No. PCT / US2020 / 060880, filed November 17, 2020, entitled “RESET VERIFICATION IN A MEMORY SYSTEM”, filed by Shaffer et al., claiming priority to U.S. Patent Application No. 17 / 097,766, filed November 13, 2020, entitled “RESET VERIFICATION IN A MEMORY SYSTEM”, and U.S. Provisional Patent Application No. 62 / 943,722, filed December 4, 2019, entitled “RESET VERIFICATION IN A MEMORY SYSTEM”, each of which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to reset verification in memory systems. Background Technology

[0004] The following text generally refers to one or more memory systems, and more specifically, to reset verification within memory systems.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0006] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, and others. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. Volatile memory devices, such as DRAM, may lose their stored state when disconnected from external power.

[0007] Some memory devices, such as memory devices containing volatile memory cells, can perform a reset operation to reset one or more logical states stored in the memory cells. Summary of the Invention

[0008] A method is described. The method includes: performing a reset operation at a memory device; setting a mode register to a first value, at least in part based on the execution of the reset operation, the first value being associated with the successful execution of the reset operation; and, after setting the mode register to the first value, transmitting an indication at least in part based on the first value to a host device.

[0009] A method is described. The method includes: issuing a reset command to a memory device; receiving, at least in part, an indication from the memory device associated with a first value stored in a mode register of the memory device based on issuing the reset command; determining, at least in part, the first value based on receiving the indication; and determining, at least in part, that the reset command has been successfully executed based on determining the first value.

[0010] Describe a device. The device includes: an interface for receiving from a host device a reset command for performing a reset operation at the device; a circuitry for detecting successful execution of the reset operation based at least in part on the receipt of the reset command; and a controller coupled to the interface and the circuitry and operable to cause the device to: generate an indication of successful execution of the reset operation based at least in part on the circuitry detecting the successful execution of the reset operation; and transmit the indication to the interface, wherein the interface transmits the indication to the host device. Attached Figure Description

[0011] Figure 1 This document describes an example of a system that supports reset verification in a memory system, based on the examples disclosed herein.

[0012] Figure 2 This document describes an example of a memory die that supports reset verification in a memory system, based on the examples disclosed herein.

[0013] Figure 3 This document describes an example of a timing diagram for resetting verification in a memory system, based on the examples disclosed herein.

[0014] Figure 4 A block diagram of a memory device supporting reset verification in a memory system according to aspects of this disclosure is shown.

[0015] Figure 5 A block diagram of a host device supporting reset verification in a memory system according to aspects of this disclosure is shown.

[0016] Figures 6 to 10 A flowchart illustrating one or more methods for resetting verification in a memory system according to the examples disclosed herein is shown. Detailed Implementation

[0017] Memory systems based on the examples disclosed herein may include memory devices and host devices coupled to the memory devices. The reliability of the memory devices in such systems may be based on the statistical probability of failure at the memory devices, and may be referred to as the time to failure (FIT), or other terms. Some applications, such as vehicle safety systems, autonomous vehicle systems, or other safety-critical systems, may have particularly high reliability constraints, or may be otherwise designed to have a particularly low probability of failure.

[0018] In some memory systems, reliability can be improved by identifying, detecting, or otherwise handling failures. For example, if a memory device experiences one hundred failures over a given period (e.g., a FIT of 100), but all errors are handled without operational failures (e.g., all errors are handled by an error correction algorithm), then the memory device can be associated with zero FIT (e.g., zero "safe FIT") or other metrics of relatively high reliability. In other words, a memory device that employs techniques to reduce the uncertainty associated with failure can have good reliability even when such failures occur, compared to a memory device that does not employ such techniques to reduce uncertainty or has relatively high uncertainty associated with failure.

[0019] In memory devices, such as those containing memory cells with a certain degree of volatility, the memory device may perform a reset operation to periodically reset one or more logical states stored in the respective memory cells. For example, the memory device may comprise one or more memory arrays of memory cells. For example, the memory device may periodically perform a reset operation to reset the logical state stored in each of the memory cells in the memory array. Without the aid of methods for verifying the reset operation, it may be necessary to assume other uncertainties regarding a given FIT loss or reliability during the reset operation. For example, the memory device may encounter an error during the reset operation, and if the error is not detected, the reset operation may be associated with a specific FIT loss.

[0020] The techniques described herein can improve the reliability or reliability rating of a memory system by enabling the memory device to verify and indicate the successful completion of a reset operation. That is, the memory device can verify and indicate (e.g., to a host device) that a reset operation has completed, or in some cases, indicate the existence of an error associated with the reset operation. For example, the memory device can transmit an indication of whether the reset operation was successful to the host device. Alternatively, the memory device can set its mode register to a given value during the reset operation, and the host device can determine whether the reset operation was successful by reading the mode register and determining whether the mode register is storing the given value. By indicating whether the reset operation was successful, the memory device can reduce the uncertainty associated with the reset operation, thus increasing the reliability or reliability rating of the memory system containing the memory device and advantageously allowing the host device or other components to perform additional operations when the reset operation is known to have been successful.

[0021] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of the memory system and the die. (See references...) Figure 3 The features of this disclosure are described in the context of the timing diagrams described. References refer to, for example, [references to, and other sources]. Figure 6-10 The device diagrams and flowcharts for resetting verification in the described memory system are provided to further illustrate and describe these and other features of this disclosure.

[0022] Figure 1 This document describes an example of a system 100 that supports reset verification in a memory system, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0023] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, networked devices, vehicle controllers, etc. Memory device 110 may be a component of the system used to store data for one or more other components of system 100.

[0024] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other instances. In some instances, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0025] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various physical package dimensions for host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0026] Memory device 110 may be operable to store data for components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of the following: write commands for write operations, read commands for read operations, reset commands for reset operations, or other commands.

[0027] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using bus 135.

[0028] Processor 125 may be operable to provide control or other functionality for at least a portion of system 100 or host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0029] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0030] Memory device 110 may include device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one bit of data. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0031] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0032] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105, or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105, or a reset command instructing memory device 110 to reset one or more logical states stored in memory device.

[0033] A local memory controller 165 (e.g., local to memory die 160) may be operable to control the operation of memory die 160. In some instances, the local memory controller 165 may be operable to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120 or processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers operable to support the operation of the described device memory controller 155 or the local memory controller 165, or both.

[0034] External memory controller 120 can be used to enable the transfer of one or more of information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0035] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to act as part of a channel.

[0036] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, information may be transmitted via channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0037] The memory array 170 of memory device 110 may include memory cells with a certain degree of volatility, and memory device 110 may perform a reset operation to reset one or more logical states stored in one or more corresponding memory cells. In some instances, the reset operation may be performed at memory device 110 after power-on. Alternatively, the reset operation may be performed at memory device 110 based on a command received from host device 105. For example, the host device may signal the reset operation by driving a reset signal to a different state (e.g., a relatively low state). For example, the memory device may begin performing a reset operation when the reset signal is in a different state (e.g., a low state) and may stop performing the reset operation when the reset signal is in another state (e.g., a relatively high state).

[0038] According to the examples disclosed herein, memory device 110 can be configured to indicate whether a reset operation was successful. That is, memory device 110 can determine (e.g., verify) whether a reset operation was successful and can indicate to host device 105 that the reset operation was successfully completed, or alternatively, an indication of an error associated with the reset operation. In some cases, if an error exists associated with the reset operation, the state of memory device 110 may be unknown (e.g., unpredictable). By indicating whether a reset operation was successful, memory device 110 can reduce the uncertainty associated with the reset operation, thereby improving the reliability or reliability rating of the system 100 including memory device 110.

[0039] In some instances, memory device 110 may determine (e.g., verify) whether a reset operation was successful and may transmit an indication of whether the reset operation was successful to host device 105. Here, memory device 110 may transmit the indication to host device 105 via multipurpose channel 115, such as CA channel 186, CK channel 188, DQ channel 190, or another channel 192, and other instances. In this example, memory device 110 may transmit the indication to host device via multipurpose channel 115 during defined unit time intervals.

[0040] Alternatively, memory device 110 may transmit the indication to host device 105 via dedicated channel 115, for example, by using reset pin 194. Reset pin 194 may be dedicated to transmitting an indication from memory device 110 to host device 105 indicating whether the reset operation was successful. In another example, the memory device may set mode register 196 to a given value during the execution of the reset operation. That is, if memory device 110 successfully completes the reset operation, then memory device 110 may program mode register 196 to a given value (e.g., a value known to both memory device 110 and host device 105). Here, host device 105 may read mode register 196 to determine whether the reset operation was successful. If the reset operation is successful, then the host device may determine (e.g., based on the performance of the read operation) that mode register 196 is storing the given value. Alternatively, if the reset operation is associated with an error, then host device 105 may determine that mode register 196 is storing a value different from the given value.

[0041] Figure 2 This document describes an example of a memory die 200 that supports reset verification in a memory system, based on the examples disclosed herein. The memory die 200 may be a reference. Figure 1 Examples of memory die 160 described. In some instances, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205, each of which may be programmable to store different logical states (e.g., programmed to one of a set of two or more possible states). For example, memory cell 205 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11).

[0042] Memory cell 205 can store charge representing a programmable state in a capacitor. A DRAM architecture can include a capacitor containing a dielectric material to store charge representing a programmable state. Other memory devices and components are also possible in other memory architectures. For example, a nonlinear dielectric material can be used. Memory cell 205 can include logic storage components, such as capacitor 230 and switching components 235. Capacitor 230 can be an example of a dielectric capacitor or a ferroelectric capacitor. Nodes of capacitor 230 can be coupled to a voltage source 240, which can be a cell board reference voltage, such as Vpl, or ground, such as Vss.

[0043] The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digital lines 215) arranged in a pattern, such as a grid pattern. Access lines may be wires coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, may be interchanged without affecting understanding or operation. Memory cells 205 may be located at the intersection of word lines 210 and digital lines 215.

[0044] Memory cell 205 can be accessed, for example, by activating or selecting one or more access lines, such as word line 210 or digital line 215. A single memory cell 205 can be accessed at its intersection point by applying a bias voltage to word line 210 and digital line 215 (e.g., applying a voltage to word line 210 or digital line 215). The intersection point of word line 210 and digital line 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of memory cell 205.

[0045] Access to memory cell 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 can receive row addresses from local memory controller 260 and activate word line 210 based on the received row addresses. Column decoder 225 can receive column addresses from local memory controller 260 and activate digital line 215 based on the received column addresses.

[0046] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating activation switch assembly 235 using word line 210. Capacitor 230 can be coupled to digital line 215 using switch assembly 235. For example, capacitor 230 can be isolated from digital line 215 when switch assembly 235 is deactivated, and can be coupled to digital line 215 when switch assembly 235 is activated.

[0047] Word line 210 may be a conductive line for electronic communication with memory cell 205 to perform access operations on memory cell 205. In some architectures, word line 210 may be coupled to the gate of switching component 235 of memory cell 205 and operable to control switching component 235 of memory cell 205. In some architectures, word line 210 may be coupled to a node of capacitor of memory cell 205, and memory cell 205 may not include a switching component.

[0048] Digital line 215 may be a wire connecting memory cell 205 and sensing component 245. In some architectures, memory cell 205 may be selectively coupled to digital line 215 during a portion of the access operation. For example, word line 210 and switching component 235 of memory cell 205 may be operable capacitor 230 and digital line 215 to couple and / or isolate memory cell 205. In some architectures, memory cell 205 may be coupled to digital line 215.

[0049] Sensing component 245 is operable to detect the state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on (e.g., using) the stored state. Sensing component 245 may include one or more sensing amplifiers to amplify or additionally transform signals generated by accessing memory cell 205. Sensing component 245 may compare the signal detected from memory cell 205 with reference 250 (e.g., reference voltage). The detected logic state of memory cell 205 may be provided as an output of sensing component 245 (e.g., to input / output component 255) and may indicate the detected logic state to another component of the memory device including memory die 200.

[0050] The local memory controller 260 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245). The local memory controller 260 can be a reference. Figure 1 Examples of the described local memory controller 165. In some instances, one or more of the row decoder 220, column decoder 225, and sensing components 245 may be located in the same location as the local memory controller 260. The local memory controller 260 may be operable to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of one or more operations. The local memory controller 260 may generate row and column address signals to activate target word line 210 and target digital line 215.

[0051] The local memory controller 260 can also generate and control various voltages or currents used during the operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may be adjusted or varied, and may differ for the various operations discussed in operating the memory die 200.

[0052] The local memory controller 260 may be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. The local memory controller 260 may also be operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 but not directly related to accessing the memory cells 205.

[0053] The local memory controller 260 is operable to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logical state. The local memory controller 260 can identify the target memory cell 205 to which the write operation will be performed. The local memory controller 260 can identify a target word line 210 and a target digital line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digital line 215 (e.g., apply a voltage to the word line 210 or the digital line 215) to access the target memory cell 205. The local memory controller 260 can apply a specific signal (e.g., a write pulse) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 230 of the memory cell 205. The pulse used as part of the write operation may contain one or more voltage levels over a duration.

[0054] The local memory controller 260 is operable to perform read operations (e.g., sensing operations) on one or more memory cells 205 of the memory die 200. During a read operation, a logical state stored on the memory cells 205 of the memory die 200 can be determined. The local memory controller 260 can identify the target memory cell 205 to which the read operation will be performed. The local memory controller 260 can identify a target word line 210 and a target digital line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digital line 215 (e.g., apply a voltage to the word line 210 or the digital line 215) to access the target memory cell 205. The target memory cell 205 can transmit a signal to a sensing component 245 in response to a bias applied to the access line. The sensing component 245 can amplify the signal. The local memory controller 260 can activate the sensing component 245 (e.g., a latching sensing component) and thus compare the signal received from the memory cell 205 with the reference 250. Based on the comparison, the sensing component 245 can determine the logic state stored in the memory cell 205.

[0055] The local memory controller 260 can be used to perform one or more reset operations on one or more memory cells 205 of the memory die 200. During a reset operation, the logical state stored in the memory cells 205 of the memory die 200 can be set to a logical value associated with the reset state. For example, the memory cells 205 of the memory die 200 can be set to the logical value '0'. Such a reset operation can be performed based on supplying initial power to the memory die 200 (e.g., energizing the memory device containing the memory die 200). In another instance, a reset operation can be performed based on receiving a command to perform a reset operation (e.g., from a host device).

[0056] The memory die 200 can be configured to indicate whether a reset operation was successful. That is, the memory die 200 can (e.g., to a host device) indicate that the reset operation was successfully completed, or alternatively, indicate an error associated with the reset operation. By indicating whether the reset operation was successful, the memory die 200 can reduce the uncertainty associated with the reset operation, thus improving the reliability or reliability rating of the memory system containing the memory die 200.

[0057] In some instances, the local memory controller 260 may initiate a reset operation at the memory die 200. After the reset operation is complete, the local memory controller 260 may transmit an indication of whether the reset operation was successful via channel 265, which may serve as a reference. Figure 1 An example of channel 115 is described. Channel 265 may be a multipurpose channel 265 (e.g., a CA channel, CK channel, DQ channel, or another channel) or a dedicated channel 265 (e.g., a channel 265 dedicated to indicating whether a reset operation was successful). In some instances, the local memory controller 260 may set mode register 296 to a given value during the execution of a reset operation. Here, the host device may read mode register 296 to determine whether the reset operation was successful. If the reset operation was successful, then mode register 296 may be storing the given value. Alternatively, if the reset operation is associated with an error, then mode register 296 may be storing a value different from the given value.

[0058] Figure 3 This document describes an example of a timing diagram 300 supporting reset verification in a memory system, based on the examples disclosed herein. Timing diagram 300 can be illustrated in reference... Figure 1 and 2 The timing of the reset operation 335 performed at the described memory device 110 or memory die 200. Timing diagram 300 may illustrate clock signal 305, power supply voltage 310, and reset signal 315.

[0059] At point 320, the memory device may be powered on. In some cases, before point 320, the memory device may be in a de-energized state or at a lower power level relative to after point 320. Here, from point 320 to point 325, the power supply voltage 310 may ramp up to or above the desired power supply voltage level. Alternatively, at point 320, the memory device may have been powered on for a period of time. Here, the power supply voltage 310 may already be at or above the desired power supply voltage level.

[0060] At 325, the memory device may initiate a reset operation 335 by maintaining the reset signal 315 in a low state (e.g., a state below a threshold). In some cases, the memory device may initiate the reset operation 335 based on executing an initialization sequence that occurs after the memory device is initially powered on. Alternatively, the memory device may initiate the reset operation 335 based on receiving a reset command from the host device. For example, the host device may drive the reset signal 315 from a first state to a second state, such as from a high state to a low state, thus initializing the reset operation 335. In some cases, the host device may drive the reset signal 315 to a low state to initiate the reset operation 335. Alternatively, the host device may drive the reset signal 315 to a low state due to noise pulses or glitches and other conditions. Here, the memory device may initiate the reset operation 335 and the host device may not be aware of the reset operation 335. If the host device drives the reset signal 315 to a higher state (e.g., after a noise pulse or glitch signal), the memory device may exit the reset operation 335 before completing the execution of the reset operation 335, thereby causing an error in the reset operation 335.

[0061] During the execution of reset operation 335, the memory device may reset at least some (if not all) of the memory cells (e.g., within a single memory array or multiple memory arrays). For example, the memory device may set a memory cell to logic state '0' during reset operation 335. Clock signal 305 may not be started during reset operation 335. For example, clock signal 305-a may be maintained at a high voltage, while clock signal 305-b may be maintained at a low voltage.

[0062] At 330, the memory device can exit the reset operation 335 by driving the reset signal 315 high. Additionally, the memory device can initialize clock signals 305-a and 305-b. The memory device can monitor one or more components or signals within the memory device to detect the completion (e.g., exit) of the reset operation 335 at 330. That is, the circuitry at the memory device can monitor the clock signal 305, the reset signal 315, or portions of the memory device (e.g., certain memory cells, access line voltages) to detect signals or signal changes associated with the completion of the reset operation 335.

[0063] For example, the circuitry may monitor clock signals 305-a, 305-b, or both. Here, the circuitry may detect one or both of the clock signals 305 that begin at 330 after the reset operation 335 has completed. The circuitry may indicate the start of the clock signals 305 (e.g., to a local controller, to a device memory controller). The memory device may determine that the reset operation 335 has completed based on the start of at least one of the clock signals 305. Therefore, the memory device may determine that no exit error occurred during the execution of the reset operation 335. Alternatively, if the circuitry does not detect the start of at least one of the clock signals 305 at 330, then the circuitry may detect that an error did indeed occur during the execution of the reset operation 335.

[0064] In another example, the circuitry may monitor a reset signal 315. Here, the circuitry may detect a transition of the reset signal 315 from a lower voltage (e.g., during the execution of reset operation 335) to a higher voltage above a threshold (e.g., after the execution of reset operation 335). The circuitry may instruct the controller of the memory device to switch the reset signal 315 from a lower voltage to a higher voltage. The controller may determine that reset operation 335 has completed based on the switch of the reset signal 315 from a lower voltage to a higher voltage. Alternatively, if the circuitry does not detect a transition of the reset signal 315 from a lower voltage to a higher voltage at 330, then the circuitry may instruct the controller not to switch the reset signal 315. Here, the controller may determine that an error occurred during the execution of reset operation 335.

[0065] In some instances, the circuitry may monitor one or more memory cells to detect when one or more memory cells are reset, thereby indicating that the reset operation 335 is complete (or nearly complete). Alternatively, the circuitry may monitor one or more access lines to determine when the reset operation 335 occurs (e.g., at a given portion of the memory device). For example, the circuitry may monitor one or more access lines associated with a set of memory cells reset at the end of the execution of the reset operation 335. Here, the circuitry may indicate to the controller of the memory device that the access line is driven to a higher voltage (e.g., associated with the reset operation 335 occurring at said set of memory cells). Thus, the controller may determine that the reset operation 335 has completed after at least some (if not all) of these memory cells have been reset. Alternatively, if the circuitry fails to detect a driven access line according to the execution of the reset operation 335, then the circuitry may indicate a failure to the controller. Here, the controller may determine that an error occurred during the execution of the reset operation 335.

[0066] If the circuitry fails to detect the completion of reset operation 335, it can indicate a failure to the host device. For example, the circuitry can set the memory device's mode register to a value associated with a reset error. In another instance, the circuitry can, for example, transmit a flag to the host device using a pin. In some cases, the pin may be a dedicated pin (e.g., for indicating whether reset operation 335 was successful). Alternatively, the pin may be a multi-purpose pin (e.g., associated with a CA channel, CK channel, DQ channel, or another channel). Thus, the memory device can indicate to the host device that the reset operation failed to exit normally. By indicating a reset operation failure to the host device, the memory device can still indicate an indeterminate state of the memory device, even if the host device is unaware of reset operation 335. For example, if the host device unintentionally (e.g., due to noise, due to glitches) drives the reset signal 315 low, the host device can still receive an erroneous indication associated with reset operation 335. This reduces the uncertainty associated with the operation of the memory device.

[0067] At 340, the memory device can confirm whether the reset operation 335 was successful via a reset confirmation. That is, between 330 and 340, the memory device can determine whether the reset operation 335 was successful, and at 340, the memory device can indicate that the reset operation 335 was successful (or an error occurred). The time between 330 and 340 can be greater than or equal to a threshold time delay. That is, the memory device can indicate whether the reset operation 335 was successful after a time greater than or equal to the threshold time delay following 330. The memory device can track the amount of time associated with a time delay (e.g., a time buffer) and indicate whether the reset operation 335 was successful after the amount of time elapsed since 330. The memory device can use a timer, or by a clock signal 305, or some other method or any combination thereof to track said amount of time.

[0068] The memory device may indicate the success of reset operation 335 based on a value (e.g., a first value) stored in the mode register indicating the success of reset operation 335. This value may be predefined or known to both the memory device and the host device. During normal operation of the memory device, the mode register may be configured to store a value (e.g., a second value). During the execution of reset operation 335 (or, in some cases, after the execution of reset operation 335), the memory device may program the mode register to the first value. Therefore, the successful completion of reset operation 335 can be indicated by storing the first value in the mode register. Alternatively, if an error occurs during the execution of reset operation 335, the mode register may store a value different from the first value (e.g., a second value). In some cases, the first value may correspond to storing a logical value '0' or, alternatively, a logical value '1' in each bit of the mode register. In some instances, the first value may correspond to the memory device setting each bit of the mode register to a logical value '1' to indicate the completion of reset operation 335. In some instances, the first logical value may be some other defined value. In some cases, if the memory detects an error associated with reset operation 335, the memory device may set the mode register to a second value (or, in some cases, maintain the mode register at the second value). Alternatively, the memory device may set the mode register to a third value indicating an error.

[0069] The mode register to be programmed to store the first value can be predefined. For example, the memory device and the host device can be preconfigured to determine that a given mode register (e.g., a third mode register (e.g., [MRx3op7]) can be programmed to store the first value immediately after the reset operation 335 is completed. In another instance, the memory device can indicate which mode register (e.g., a set of mode registers from the memory device) will be programmed to store the first value after the reset operation 335 is completed. That is, the memory device can send an indication of the mode register to the host device.

[0070] The host device can read the mode register to determine whether the reset operation 335 was successful. In some cases, the host device can periodically request (e.g., poll) the mode register or read information from the mode register by issuing read commands for the mode register according to a given rhythm (e.g., periodic, aperiodic scheduling, based on one or more conditions).

[0071] In some instances, the memory device may indicate to the host device that the reset operation 335 has completed. Here, the host device may read the mode register based on receiving the indication. To read the mode register, the host device may issue a read command for the mode register to the memory device. The memory device may then transfer the value stored in the mode register to the host device based on receiving the read command.

[0072] In some instances, the host device (or another device or component) may compare the value stored in the mode register with a second value to determine whether the value stored in the mode register is different from the second value. If the host device determines that the mode register is storing a first value (or a value different from the second value), then the host device may determine that the reset operation 335 was successful. Alternatively, if the host device determines that the mode register is storing a value different from the first value, then the host device may determine that the reset operation 335 was unsuccessful (e.g., associated with an error).

[0073] In some instances, the memory device may indicate that the reset operation 335 was successful by sending an instruction to the host device. In some cases, the memory device may program the mode register, or send the instruction, or both. For example, the memory device may instruct the host device to read the mode register. Alternatively, the memory device may instruct the host device to indicate (e.g., the value of the mode register). In some instances, the memory device may send the instruction instead of programming the mode register. Here, the instruction may indicate whether the reset operation 335 was successful or failed.

[0074] The memory device may transmit the indication after a time delay (e.g., between 330 and 340). The time delay may be defined and based on the processing speed of the memory device, or both. The memory device may transmit the indication via a channel (e.g., a pin) between the memory device and the host device. The channel may include a pin dedicated to transmitting the indication (e.g., a reset pin). In some instances, the channel may include pins that also transmit other information. For example, the pin may be a multi-purpose pin. Here, there may be a defined unit time interval during which the memory device may transmit an indication of whether the reset operation 335 was successful. For example, the unit time interval may be defined as occurring after the time delay (e.g., between 330 and 340).

[0075] At 345, the memory device may begin operation in a first operating mode (e.g., normal operating mode). For example, the memory device may begin receiving access commands from the host device and executing the access commands accordingly. That is, the memory device may perform read operations, write operations, refresh operations, or other operations (or any combination thereof) associated with typical operation of the memory device.

[0076] In some cases, one or more mode registers of the memory device may be programmed to values ​​associated with a first operating mode prior to 345. For example, if the memory device programs a mode register to a first value to indicate that a reset operation 335 has completed, then the mode register may be programmed to a different value (e.g., a second value) associated with the first operating mode before the memory device receives an access command and executes the access command according to the first operating mode. The memory device may independently determine to reprogram one or more mode registers to values ​​associated with the first operating mode. Alternatively, the memory device may receive a write command from the host device indicating a value associated with the first operating mode. The memory device may then program the mode registers to store the indicated value during the execution of the write command.

[0077] Figure 4 A block diagram 400 illustrates a memory device 405 supporting reset verification in a memory system according to an example of this disclosure. The memory device 405 may be as described in reference... Figures 1 to 3 Examples of aspects of the described memory device. Memory device 405 may include a reset manager 410, a mode register manager 415, a host command receiver 420, a send manager 425, and an error manager 430. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0078] The reset manager 410 can perform a reset operation at the memory device. In some instances, the reset manager 410 can perform a second reset operation at the memory device.

[0079] The mode register manager 415 may set the mode register to a first value based on the execution of a reset operation, the first value being associated with the successful execution of the reset operation. In some instances, the mode register manager 415 may set the mode register to a second value after issuing an instruction to the host device, the second value being associated with a second operating mode of the memory device, different from the first operating mode of the memory device associated with the execution of the reset operation. In some cases, the second operating mode of the memory device is associated with the execution of a read operation or a write operation, or both. In some cases, each bit of the first value contains the logic value '0'. Alternatively, each bit of the first value may contain the logic value '1'. In some cases, each bit of the first value corresponds to a predefined value.

[0080] The send manager 425 may send an indication based on a first value to the host device after setting the mode register to that first value. In some instances, the send manager 425 may send the first value to the host device based on receiving a read command. In some cases, the send manager 425 may send the first value stored in the mode register to the host device based on receiving a read command from a set of read commands, wherein sending the indication is based on sending the first value. In some cases, the send manager 425 may send a second indication to the host device based on detecting an error associated with a second reset operation after detecting an error.

[0081] In some instances, the transmit manager 425 may transmit the indication to the host device via a pin dedicated to transmitting an indication associated with performing a reset operation. In some cases, the amount of time between successfully performing the reset operation and transmitting the indication to the host device is greater than or equal to a time delay defined for performing the reset operation. In some cases, the indication is an indication of the completion of performing a reset operation at the memory device. In some instances, the indication includes a first value.

[0082] The host command receiver 420 can receive from the host device a command to set the mode register to a second value, wherein setting the mode register to the second value is based on receiving a command from the host device. In some instances, the host command receiver 420 can receive a read command for the mode register from the host device based on transmitting the instruction. In some cases, the host command receiver 420 can receive a set of read commands for the mode register from the host device periodically. In some instances, the transmit manager 425 can transmit a second value stored in the mode register based on receiving a read command, wherein the second value is different from the first value and indicates an error associated with a second reset operation. In some instances, the host command receiver 420 can receive from the host device a command to perform a reset operation at a memory device, wherein performing the reset operation is based on receiving the command.

[0083] Error manager 430 can detect errors associated with the second reset operation via a memory device.

[0084] Figure 5 A block diagram 500 illustrates a host device 505 supporting reset verification in a memory system according to an example disclosed herein. The host device 505 may be as described in the references... Figures 1 to 3 Examples of aspects of the described host device. Host device 505 may include command transmitter 510, receiver manager 515, value manager 520, execution command manager 525, and mode register manager 530. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0085] Command transmitter 510 may send a reset command to the memory device. In some instances, command transmitter 510 may send a read command for the mode register to the memory device based on the completion of a reset operation performed at the memory device. In some cases, command transmitter 510 may send a command to the memory device to set the mode register to a second value after determining that the reset command was executed successfully. In some cases, command transmitter 510 may send a second reset command to the memory device.

[0086] The receive manager 515 may receive an indication from the memory device associated with a first value stored in the mode register of the memory device based on issuing the reset command. In some cases, the indication includes the first value. In some instances, the receive manager 515 may receive the first value from the memory device based on issuing a read command, wherein the first value is determined based on receiving the first value from the memory device. In some cases, the receive manager 515 may receive a second indication from the memory device based on issuing a second reset command, the second indication being associated with a second value stored in the mode register of the memory device.

[0087] Value manager 520 may determine a first value based on receiving the instruction. In some instances, value manager 520 may compare the first value with a second value indicating a second operating mode of the memory device, which is different from a first operating mode of the memory device associated with executing a reset command. In some instances, value manager 520 may determine, based on the comparison, that the first value is associated with a first operating mode and is different from the second value, wherein determining that the reset command was executed successfully is based on determining that the first value and the second value are different. In some instances, value manager 520 may determine the first value based on the instruction containing the first value. In some cases, value manager 520 may determine, based on receiving a second instruction, that the second value is different from the first value, which is associated with a first operating mode of the memory device associated with executing a second reset command.

[0088] The command manager 525 can determine that the reset command was executed successfully based on determining a first value. In some instances, the command manager 525 can determine that the second reset command was not executed successfully based on determining that a second value is different from the first value.

[0089] The mode register manager 530 can determine the mode register from the mode register set based on the received instruction, wherein determining the first value is based on determining the mode register.

[0090] Figure 6 A flowchart illustrating one or more methods 600 for resetting verification in a memory system according to aspects of this disclosure is shown. Operation of method 600 may be implemented by a memory device or its components as described herein. For example, operation of method 600 may be performed by, as referenced... Figure 4 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0091] At 605, a reset operation can be performed on the memory device. The operation at 605 can be performed according to the method described herein. In some instances, it can be performed via reference. Figure 4 The described aspect of the reset manager performing the 605 operation.

[0092] At 610, the memory device may set the mode register to a first value based on the execution of a reset operation, the first value being associated with the successful execution of the reset operation. The operation at 610 can be performed according to the method described herein. In some instances, it may be provided by reference... Figure 4 The described aspect of the mode register manager performing the operation of 610.

[0093] At 615, the memory device may transmit an instruction based on the first value to the host device after setting the mode register to the first value. The operation at 615 can be performed according to the method described herein. In some instances, it may be provided by reference. Figure 4 The described launch manager performs the operations of 615.

[0094] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: performing a reset operation at a memory device; setting a mode register to a first value based on performing the reset operation, the first value being associated with successfully performing the reset operation; and, after setting the mode register to the first value, transmitting an indication based on the first value to a host device.

[0095] Some aspects of the method 600 and device described herein may additionally include operations, features, means, or instructions for: setting the mode register to a second value after the instruction is transmitted to the host device, the second value being associated with a second operating mode of the memory device, the second operating mode being different from the first operating mode of the memory device associated with performing the reset operation.

[0096] Some examples of the method 600 and device described herein may additionally include operations, features, means, or instructions for receiving from the host device a command to set the mode register to the second value, wherein setting the mode register to the second value may be based on receiving the command from the host device.

[0097] In some instances of the method 600 and device described herein, the second operating mode of the memory device may be associated with performing a read operation or a write operation or both.

[0098] Some aspects of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for: receiving a read command for the mode register from the host device based on transmitting the instruction; and transmitting the first value to the host device based on receiving the read command.

[0099] Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for: periodically receiving a set of read commands for the mode register from the host device; and transmitting the first value stored in the mode register to the host device based on receiving a read command from the set of read commands, wherein the transmission instruction may be based on transmitting the first value.

[0100] In some instances of the method 600 and device described herein, the amount of time between successfully performing the reset operation and transmitting the instruction to the host device may be greater than or equal to the time delay defined for performing the reset operation.

[0101] Some aspects of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for receiving from the host device a command to perform the reset operation at the memory device, wherein the reset operation may be performed based on receiving the command.

[0102] Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for: performing a second reset operation at the memory device; detecting an error associated with the second reset operation via the memory device; and, after detecting the error, transmitting a second indication that can be based on the detection of the error associated with the second reset operation to the host device.

[0103] Some examples of the method 600 and device described herein may additionally include operations, features, means, or instructions for: receiving a read command for the mode register from the host device based on transmitting the instruction; and transmitting a second value stored in the mode register based on receiving the read command, wherein the second value may be different from the first value and indicates the error associated with the second reset operation.

[0104] Some aspects of the method 600 and device described herein may additionally include operations, features, means, or instructions for transmitting an indication to the host device via a pin that may be dedicated to transmitting an indication associated with performing a reset operation.

[0105] In some cases of the method 600 and device described herein, each bit of the first value contains a logical value '0'; each bit of the first value contains a logical value '1'; or each bit of the first value corresponds to a predefined value.

[0106] In some instances of the method 600 and device described herein, the indication is an indication of the completion of the reset operation performed at the memory device.

[0107] In some cases of the method 600 and device described herein, the indication includes the first value.

[0108] Figure 7 A flowchart illustrating one or more methods 700 for resetting verification in a memory system according to aspects of this disclosure is shown. The operation of method 700 may be implemented by a memory device or its components as described herein. For example, it may be implemented by, as referenced... Figure 4The described memory device performs the operation of method 700. In some instances, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0109] At 705, a reset operation can be performed on the memory device. The operation at 705 can be performed according to the method described herein. In some instances, it can be performed via reference. Figure 4 The described aspect of the reset manager performing operation 705.

[0110] At 710, the memory device may set the mode register to a first value based on the execution of a reset operation, the first value being associated with the successful execution of the reset operation. The operation at 710 can be performed according to the method described herein. In some instances, it can be done via reference... Figure 4 The described aspect of the mode register manager performing the operation of 710.

[0111] At 715, the memory device may transmit an instruction based on the first value to the host device after setting the mode register to the first value. The operation of 715 can be performed according to the method described herein. In some instances, it may be provided by reference... Figure 4 The described launch manager performs the operations of 715.

[0112] At 720, after transmitting the instruction to the host device, the memory device may set the mode register to a second value, the second value being associated with a second operating mode of the memory device, different from the first operating mode of the memory device associated with performing the reset operation. The operation at 720 can be performed according to the method described herein. In some instances, it may be provided by reference... Figure 4 The described aspect of the mode register manager performing the 720 operation.

[0113] Figure 8 A flowchart illustrating one or more methods 800 for resetting verification in a supporting memory system according to aspects of this disclosure is shown. Operation of method 800 may be implemented by a host device or its components as described herein. For example, operation of method 800 may be performed by, as referenced... Figure 5 The described host device performs the function. In some instances, the host device may execute a set of instructions to control the functional elements of the host device to perform the described function. Alternatively, the host device may use dedicated hardware to perform aspects of the described function.

[0114] At 805, the host device can issue a reset command to the memory device. The operation of 805 can be performed according to the method described herein. In some instances, it can be done via reference... Figure 5 The described command transmitter performs the operations of 805.

[0115] At 810, the host device can receive an indication from the memory device associated with the first value stored in the mode register of the memory device based on the issuance of the reset command. The operation of 810 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 5 The described aspect of the receiver manager performing the operation of 810.

[0116] At point 815, the host device can determine a first value based on receiving the instruction. Operation at point 815 can be performed according to the method described herein. In some instances, it can be determined by reference. Figure 5 The described aspect of the value manager performing operation 815.

[0117] At step 820, the host device can determine that the reset command was executed successfully based on determining the first value. The operation at step 820 can be performed according to the method described herein. In some instances, it can be done via reference. Figure 5 The described aspects of the execution command manager performing the 820 operations.

[0118] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: issuing a reset command to a memory device; receiving, based on issuing the reset command, an indication associated with a first value stored in the mode register of the memory device; determining the first value based on receiving the indication; and determining, based on determining the first value, that the reset command has been successfully executed.

[0119] Some examples of the method 800 and apparatus described herein may additionally include operations, features, means, or instructions for: comparing the first value with a second value indicating a second operating mode of the memory device, the second operating mode being different from a first operating mode of the memory device associated with executing the reset command; and determining, based on the comparison, that the first value may be associated with the first operating mode and may be different from the second value, wherein determining the success of the execution of the reset command may be based on determining that the first value and the second value may be different.

[0120] Some examples of the method 800 and device described herein may additionally include operations, features, means, or instructions for issuing a command to the memory device to set the mode register to the second value after determining that the execution of the reset command was successful.

[0121] Some examples of the methods 800 and devices described herein may additionally include operations, features, means, or instructions for determining the mode register from a set of mode registers based on receiving the instruction, wherein determining the first value may be based on determining the mode register.

[0122] Some aspects of the method 800 and apparatus described herein may additionally include operations, features, means, or instructions for: issuing a read command for the mode register to the memory device based on the completion of the reset operation performed at the memory device; and receiving the first value from the memory device based on issuing the read command, wherein determining the first value may be based on receiving the first value from the memory device.

[0123] In some cases of the method 800 and apparatus described herein, the indication includes the first value, and determining the first value may be based on the indication including the first value.

[0124] Some examples of the method 800 and apparatus described herein may additionally include operations, features, means, or instructions for: issuing a second reset command to the memory device; receiving a second indication from the memory device based on issuing the second reset command, the second indication being associated with a second value stored in the mode register of the memory device; determining, based on receiving the second indication, that the second value may be different from a first value, the first value being associated with a first operating mode of the memory device, the first operating mode being associated with executing the second reset command; and determining, based on determining that the second value may be different from the first value, that the second reset command was not executed successfully.

[0125] Figure 9 A flowchart illustrating one or more methods 900 for resetting verification in a supporting memory system according to aspects of this disclosure is shown. Operation of method 900 may be implemented by a host device or its components as described herein. For example, operation of method 900 may be performed by, as referenced... Figure 5 The described host device performs the function. In some instances, the host device may execute a set of instructions to control the functional elements of the host device to perform the described function. Alternatively, the host device may use dedicated hardware to perform aspects of the described function.

[0126] At position 905, the host device may issue a reset command to the memory device. The operation at position 905 can be performed according to the method described herein. In some instances, it can be done via reference. Figure 5 The described command transmitter performs the operation of 905.

[0127] At 910, the host device can receive an indication from the memory device associated with the first value stored in the mode register of the memory device based on the issuance of the reset command. The operation at 910 can be performed according to the method described herein. In some instances, it can be performed by reference... Figure 5 The described aspect of the receiver manager performing operation 910.

[0128] At 915, the host device can determine a first value based on receiving the instruction. The operation at 915 can be performed according to the method described herein. In some instances, it can be determined by reference. Figure 5 The described aspect of the value manager performing operation 915.

[0129] At 920, the host device may compare the first value with a second value indicating a second operating mode of the memory device, different from the first operating mode of the memory device associated with executing a reset command. The operation at 920 may be performed according to the method described herein. In some instances, it may be performed by reference... Figure 5 The described aspect of the value manager performing operation 920.

[0130] At 925, the host device can determine, based on the comparison, that a first value is associated with a first operating mode and is different from a second value. Operation at 925 can be performed according to the method described herein. In some instances, it can be determined by reference... Figure 5 The described aspect of the value manager performing operation 925.

[0131] At 930, the host device can determine that the reset command was successfully executed based on determining a first value and based on determining that the first value is different from the second value. The operation at 930 can be performed according to the method described herein. In some instances, it can be done via reference. Figure 5 The described aspects of the execution command manager performing the 930 operation.

[0132] Figure 10 A flowchart illustrating one or more methods 1000 for resetting verification in a supporting memory system according to aspects of this disclosure is shown. Operation of method 1000 may be implemented by a host device or its components as described herein. For example, operation of method 1000 may be performed by, as referenced... Figure 5The described host device performs the function. In some instances, the host device may execute a set of instructions to control the functional elements of the host device to perform the described function. Alternatively, the host device may use dedicated hardware to perform aspects of the described function.

[0133] At position 1005, the memory device can perform a reset operation. The operation at position 1005 can be performed according to the method described herein. In some instances, it can be performed via reference. Figure 4 The described aspects of the reset manager performing operation 1005.

[0134] At 1010, the memory device can set the mode register to a first value based on the execution of a reset operation, the first value being associated with the successful execution of the reset operation. The operation at 1010 can be performed according to the method described herein. In some instances, it can be done via reference... Figure 4 The described aspect of the mode register manager performing operation 1010.

[0135] At point 1015, the memory device may, after setting the mode register to the first value, transmit an instruction based on the first value to the host device. Operation 1015 can be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 4 The described launch manager performs the operations of 1015.

[0136] At 1020, after transmitting the instruction to the host device, the memory device may set the mode register to a second value, the second value being associated with a second operating mode of the memory device, different from the first operating mode of the memory device associated with performing the reset operation. The operation at 1020 can be performed according to the method described herein. In some instances, it may be referenced... Figure 4 The described aspect of the mode register manager performing operation 1020.

[0137] At position 1025, the memory device can perform a second reset operation. The operation at position 1025 can be performed according to the method described herein. In some instances, it can be performed using references... Figure 4 The described aspects of the reset manager performing operation 1025.

[0138] At 1030, the memory device can detect errors associated with the second reset operation. The operation at 1030 can be performed according to the method described herein. In some instances, it can be performed using references... Figure 4 The described aspect of the error manager performing operation 1030.

[0139] At 1035, the memory device may, upon detecting the error, transmit a second indication to the host device based on the detection of the error associated with the second reset operation. The operation at 1035 can be performed according to the method described herein. In some instances, it may be provided by reference... Figure 4 The described launch manager performs the operations of 1035.

[0140] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0141] Describe a device. The device may include an interface for receiving from a host device a reset command for performing a reset operation at the device; a circuitry for detecting successful execution of the reset operation based on the received reset command; and a controller coupled to the interface and the circuitry and operable to cause the device to: generate an indication of successful execution of the reset operation based on the circuitry detecting the successful execution of the reset operation; and transmit the indication to the interface, wherein the interface transmits the indication to the host device.

[0142] In some instances, the mode register may be operable to store a first value associated with successfully performing the reset operation; or to store a second value associated with a second operating mode of the device, which may be different from the first operating mode of the device associated with performing the reset operation.

[0143] In some cases, the controller may be additionally operable to set the mode register to the first value based on performing the reset operation, wherein the indication may be based on the first value; and to set the mode register to the second value after the indication is transmitted to the host device.

[0144] In some cases, the interface includes pins dedicated to transmitting the indication from the device to the host device.

[0145] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0146] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0147] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0148] The term "isolation" refers to the relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller separates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0149] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0150] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0151] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0152] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0153] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0154] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality may also be physically located in various locations, including distributed so that portions of the functionality are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of…” or “one or more of…”) indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as “based on condition A” may be based on both condition A and condition B. In other words, as used herein, the phrase “based on” should also be interpreted as the phrase “at least partially based on”.

[0155] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for memory operations, comprising: Perform a reset operation at the memory device; At least in part, based on the execution of the reset operation, it is determined whether to set the mode register to a first value indicating successful execution of the reset operation, or a second value indicating an error associated with the execution of the reset operation; The mode register is set to the first value, at least in part based on the successful execution of the reset operation; After the mode register is set to the first value, the signal will be transmitted to the host device at least in part based on the indication of the first value; as well as After the instruction is transmitted to the host device, the mode register is set to a third value, which is associated with a second operating mode of the memory device, different from the first operating mode of the memory device associated with performing the reset operation.

2. The method according to claim 1, further comprising: The host device receives a command to set the mode register to the third value, wherein setting the mode register to the third value is based at least in part on receiving the command from the host device.

3. The method of claim 1, wherein the second operating mode of the memory device is associated with performing a read operation or a write operation or both.

4. The method of claim 1, further comprising: The host device receives a read command for the mode register based at least in part on the transmission of the instruction; and The first value is transmitted to the host device at least in part based on receiving the read command.

5. The method of claim 1, further comprising: Receives multiple read commands for the mode register from the host device periodically; and The first value stored in the mode register is transmitted to the host device at least in part based on receiving one of the plurality of read commands, wherein the transmission of the instruction is at least in part based on transmitting the first value.

6. The method of claim 1, wherein the amount of time between successfully performing the reset operation and transmitting the indication to the host device is greater than or equal to a time delay defined for performing the reset operation.

7. The method of claim 1, further comprising: The host device receives a command to perform the reset operation at the memory device, wherein the reset operation is performed at least in part based on receiving the command.

8. The method of claim 1, further comprising: A second reset operation is performed at the memory device; Errors associated with the second reset operation are detected using the memory device; and After the error is detected, a second indication will be sent to the host device based at least in part on the detection of the error associated with the second reset operation.

9. The method of claim 8, further comprising: The host device receives a read command for the mode register based at least in part on the transmission of the instruction; and The second value stored in the mode register is emitted at least in part based on the receipt of the read command, wherein the second value is different from the first value and indicates the error associated with the second reset operation.

10. The method of claim 1, further comprising: The instruction is transmitted to the host device via a pin dedicated to transmitting an instruction associated with performing a reset operation.

11. The method according to claim 1, wherein: Each bit of the first value includes the logical value '0'; Each bit of the first value includes the logical value '1'; or Each bit of the first value corresponds to a predefined value.

12. The method of claim 1, wherein the indication is an indication of the completion of the reset operation performed at the memory device.

13. The method of claim 1, wherein the indication includes the first value.

14. A method for memory operations, comprising: Send a reset command to the memory device; At least in part, the instruction associated with the mode register stored in the memory device is received from the memory device based on the issuance of the reset command; Based at least in part on receiving the instruction, determine whether the stored value is a first value indicating successful execution of the reset operation, or a second value indicating an error associated with the execution of the reset operation; The first value is compared with a third value that indicates a second operating mode of the memory device, which is different from the first operating mode of the memory device associated with executing the reset command; The first value is determined to be associated with the first operating mode and to be different from the third value, at least in part, based on the comparison. The success of the reset command is determined at least in part based on the determination that the stored value is the first value and at least in part based on the determination that the first value is different from the third value.

15. The method of claim 14, further comprising: After confirming that the reset command was executed successfully, a command to set the mode register to the third value is sent to the memory device.

16. The method of claim 14, further comprising: The mode register is determined from a plurality of mode registers based at least in part on receiving the instruction, wherein determining whether the stored value is the first value or the second value is based at least in part on determining the mode register.

17. The method of claim 14, wherein the first value indicates completion of the reset operation at the memory device, the method further comprising: A read command for the mode register is issued to the memory device, at least in part, based on the completion of the reset operation performed at the memory device. and The first value is received from the memory device at least in part based on issuing the read command, wherein determining whether the stored value is the first value or the second value is at least in part based on receiving the first value from the memory device.

18. The method of claim 14, wherein: The indication includes the first value; and Determining whether the stored value is the first value or the second value is at least in part based on the indication including the first value.

19. The method of claim 14, further comprising: Send a second reset command to the memory device; The second instruction is received from the memory device at least in part based on the issuance of the second reset command, the second instruction being associated with the second value stored in the mode register of the memory device; The second value is determined to be different from the first value, at least in part, based on receiving the second instruction, the first value being associated with the first operating mode of the memory device, the first operating mode being associated with executing the reset command; and The second reset command was determined to have failed, at least in part, based on the fact that the second value is different from the first value.

20. A device for memory operation, comprising: An interface for receiving a reset command from a host device for performing a reset operation at the device; A circuit system for detecting the successful execution of the reset operation based at least in part on receiving the reset command; The mode register is operable to: Store a first value indicating the successful execution of the reset operation; or Store a second value indicating the error associated with performing the reset operation; and A controller, coupled to the interface and the circuit system, and operable to cause the device to perform the following operations: Determine whether to set the mode register to a first value indicating successful execution of the reset operation, or a second value indicating an error associated with the execution of the reset operation; The mode register is set to the first value, at least in part based on the circuit system detecting the successful execution of the reset operation. The indication of successful execution of the reset operation is generated, at least in part, based on setting the mode register to the first value; and The instruction is transmitted to the interface, wherein the interface transmits the instruction to the host device.

21. The device of claim 20, wherein the mode register is further operable to: A third value is stored that is associated with a second operating mode of the device, which is different from the first operating mode of the device associated with performing the reset operation.

22. The device of claim 21, wherein the controller is further operable to cause the device to perform the following operations: After the instruction is transmitted to the host device, the mode register is set to the third value.

23. The device of claim 20, wherein the interface includes pins dedicated to transmitting the indication from the device to the host device.

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